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Searched defs:div1 (Results 1 – 15 of 15) sorted by relevance

/drivers/clk/uniphier/
Dclk-uniphier.h110 #define UNIPHIER_CLK_DIV2(parent, div0, div1) \ argument
114 #define UNIPHIER_CLK_DIV3(parent, div0, div1, div2) \ argument
118 #define UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3) \ argument
/drivers/clk/
Dclk-vt8500.c456 int div1, div2; in wm8750_find_pll_bits() local
504 int div1, div2; in wm8850_find_pll_bits() local
550 u32 filter, mul, div1, div2; in vtwm_pll_set_rate() local
601 u32 filter, mul, div1, div2; in vtwm_pll_round_rate() local
/drivers/clk/samsung/
Dclk-cpu.c155 unsigned long div0, div1 = 0, mux_reg; in exynos_cpuclk_pre_rate_change() local
283 unsigned long div0, div1 = 0, mux_reg; in exynos5433_cpuclk_pre_rate_change() local
Dclk-cpu.h28 unsigned long div1; member
/drivers/media/tuners/
Dmt2131.c89 u32 div1, num1, div2, num2; in mt2131_set_params() local
Dmt2060.c196 u32 div1,num1,div2,num2; in mt2060_set_params() local
/drivers/clk/imx/
Dclk-composite-8m.c54 int div1, div2; in imx8m_clk_composite_compute_dividers() local
/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dsorgf119.c124 u32 div1 = sor->asy.link == 3; in gf119_sor_clock() local
/drivers/i2c/busses/
Di2c-s3c2410.c800 unsigned int *div1, unsigned int *divs) in s3c24xx_i2c_calcdivisor()
833 unsigned int divs, div1; in s3c24xx_i2c_clockrate() local
Di2c-sprd.c340 u32 div1 = I2C_ADDR_DVD1_CALC(high, low); in sprd_i2c_set_clk() local
/drivers/spi/
Dspi-omap-uwire.c317 int div1; in uwire_setup_transfer() local
/drivers/clk/x86/
Dclk-cgu.c395 unsigned int div0, div1, exdiv; in lgm_clk_ddiv_recalc_rate() local
/drivers/media/dvb-frontends/
Dstb0899_algo.c1274 int div1, div2, rem1, rem2; in stb0899_dvbs2_get_srate() local
/drivers/comedi/drivers/
Dadl_pci9118.c533 unsigned int *div1, unsigned int *div2, in pci9118_calc_divisors()
/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.c2764 int div1 = div1_vals[i]; in icl_mg_pll_find_divisors() local
3039 u32 m1, m2_int, m2_frac, div1, div2, ref_clock; in icl_ddi_mg_pll_get_freq() local