1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "../dmub_srv.h"
27 #include "dmub_reg.h"
28 #include "dmub_dcn31.h"
29
30 #include "yellow_carp_offset.h"
31 #include "dcn/dcn_3_1_2_offset.h"
32 #include "dcn/dcn_3_1_2_sh_mask.h"
33
34 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
35 #define CTX dmub
36 #define REGS dmub->regs_dcn31
37 #define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
38
39 const struct dmub_srv_dcn31_regs dmub_srv_dcn31_regs = {
40 #define DMUB_SR(reg) REG_OFFSET_EXP(reg),
41 {
42 DMUB_DCN31_REGS()
43 DMCUB_INTERNAL_REGS()
44 },
45 #undef DMUB_SR
46
47 #define DMUB_SF(reg, field) FD_MASK(reg, field),
48 { DMUB_DCN31_FIELDS() },
49 #undef DMUB_SF
50
51 #define DMUB_SF(reg, field) FD_SHIFT(reg, field),
52 { DMUB_DCN31_FIELDS() },
53 #undef DMUB_SF
54 };
55
dmub_dcn31_get_fb_base_offset(struct dmub_srv * dmub,uint64_t * fb_base,uint64_t * fb_offset)56 static void dmub_dcn31_get_fb_base_offset(struct dmub_srv *dmub,
57 uint64_t *fb_base,
58 uint64_t *fb_offset)
59 {
60 uint32_t tmp;
61
62 if (dmub->fb_base || dmub->fb_offset) {
63 *fb_base = dmub->fb_base;
64 *fb_offset = dmub->fb_offset;
65 return;
66 }
67
68 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
69 *fb_base = (uint64_t)tmp << 24;
70
71 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
72 *fb_offset = (uint64_t)tmp << 24;
73 }
74
dmub_dcn31_translate_addr(const union dmub_addr * addr_in,uint64_t fb_base,uint64_t fb_offset,union dmub_addr * addr_out)75 static inline void dmub_dcn31_translate_addr(const union dmub_addr *addr_in,
76 uint64_t fb_base,
77 uint64_t fb_offset,
78 union dmub_addr *addr_out)
79 {
80 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
81 }
82
dmub_dcn31_reset(struct dmub_srv * dmub)83 void dmub_dcn31_reset(struct dmub_srv *dmub)
84 {
85 union dmub_gpint_data_register cmd;
86 const uint32_t timeout = 100;
87 uint32_t in_reset, scratch, i;
88
89 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
90
91 if (in_reset == 0) {
92 cmd.bits.status = 1;
93 cmd.bits.command_code = DMUB_GPINT__STOP_FW;
94 cmd.bits.param = 0;
95
96 dmub->hw_funcs.set_gpint(dmub, cmd);
97
98 /**
99 * Timeout covers both the ACK and the wait
100 * for remaining work to finish.
101 */
102
103 for (i = 0; i < timeout; ++i) {
104 if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
105 break;
106
107 udelay(1);
108 }
109
110 for (i = 0; i < timeout; ++i) {
111 scratch = dmub->hw_funcs.get_gpint_response(dmub);
112 if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
113 break;
114
115 udelay(1);
116 }
117
118 /* Force reset in case we timed out, DMCUB is likely hung. */
119 }
120
121 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);
122 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
123 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
124 REG_WRITE(DMCUB_INBOX1_RPTR, 0);
125 REG_WRITE(DMCUB_INBOX1_WPTR, 0);
126 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
127 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
128 REG_WRITE(DMCUB_SCRATCH0, 0);
129
130 /* Clear the GPINT command manually so we don't send anything during boot. */
131 cmd.all = 0;
132 dmub->hw_funcs.set_gpint(dmub, cmd);
133 }
134
dmub_dcn31_reset_release(struct dmub_srv * dmub)135 void dmub_dcn31_reset_release(struct dmub_srv *dmub)
136 {
137 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
138 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
139 REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
140 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);
141 }
142
dmub_dcn31_backdoor_load(struct dmub_srv * dmub,const struct dmub_window * cw0,const struct dmub_window * cw1)143 void dmub_dcn31_backdoor_load(struct dmub_srv *dmub,
144 const struct dmub_window *cw0,
145 const struct dmub_window *cw1)
146 {
147 union dmub_addr offset;
148 uint64_t fb_base, fb_offset;
149
150 dmub_dcn31_get_fb_base_offset(dmub, &fb_base, &fb_offset);
151
152 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
153
154 dmub_dcn31_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
155
156 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
157 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
158 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
159 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
160 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
161 DMCUB_REGION3_CW0_ENABLE, 1);
162
163 dmub_dcn31_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
164
165 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
166 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
167 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
168 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
169 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
170 DMCUB_REGION3_CW1_ENABLE, 1);
171
172 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
173 0x20);
174 }
175
dmub_dcn31_setup_windows(struct dmub_srv * dmub,const struct dmub_window * cw2,const struct dmub_window * cw3,const struct dmub_window * cw4,const struct dmub_window * cw5,const struct dmub_window * cw6)176 void dmub_dcn31_setup_windows(struct dmub_srv *dmub,
177 const struct dmub_window *cw2,
178 const struct dmub_window *cw3,
179 const struct dmub_window *cw4,
180 const struct dmub_window *cw5,
181 const struct dmub_window *cw6)
182 {
183 union dmub_addr offset;
184
185 offset = cw3->offset;
186
187 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
188 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
189 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
190 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
191 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
192 DMCUB_REGION3_CW3_ENABLE, 1);
193
194 offset = cw4->offset;
195
196 REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
197 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
198 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
199 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
200 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
201 DMCUB_REGION3_CW4_ENABLE, 1);
202
203 offset = cw5->offset;
204
205 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
206 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
207 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
208 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
209 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
210 DMCUB_REGION3_CW5_ENABLE, 1);
211
212 REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
213 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
214 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
215 DMCUB_REGION5_TOP_ADDRESS,
216 cw5->region.top - cw5->region.base - 1,
217 DMCUB_REGION5_ENABLE, 1);
218
219 offset = cw6->offset;
220
221 REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
222 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
223 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
224 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
225 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
226 DMCUB_REGION3_CW6_ENABLE, 1);
227 }
228
dmub_dcn31_setup_mailbox(struct dmub_srv * dmub,const struct dmub_region * inbox1)229 void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub,
230 const struct dmub_region *inbox1)
231 {
232 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
233 REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
234 }
235
dmub_dcn31_get_inbox1_rptr(struct dmub_srv * dmub)236 uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub)
237 {
238 return REG_READ(DMCUB_INBOX1_RPTR);
239 }
240
dmub_dcn31_set_inbox1_wptr(struct dmub_srv * dmub,uint32_t wptr_offset)241 void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
242 {
243 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
244 }
245
dmub_dcn31_setup_out_mailbox(struct dmub_srv * dmub,const struct dmub_region * outbox1)246 void dmub_dcn31_setup_out_mailbox(struct dmub_srv *dmub,
247 const struct dmub_region *outbox1)
248 {
249 REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
250 REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
251 }
252
dmub_dcn31_get_outbox1_wptr(struct dmub_srv * dmub)253 uint32_t dmub_dcn31_get_outbox1_wptr(struct dmub_srv *dmub)
254 {
255 /**
256 * outbox1 wptr register is accessed without locks (dal & dc)
257 * and to be called only by dmub_srv_stat_get_notification()
258 */
259 return REG_READ(DMCUB_OUTBOX1_WPTR);
260 }
261
dmub_dcn31_set_outbox1_rptr(struct dmub_srv * dmub,uint32_t rptr_offset)262 void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
263 {
264 /**
265 * outbox1 rptr register is accessed without locks (dal & dc)
266 * and to be called only by dmub_srv_stat_get_notification()
267 */
268 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
269 }
270
dmub_dcn31_is_hw_init(struct dmub_srv * dmub)271 bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub)
272 {
273 union dmub_fw_boot_status status;
274 uint32_t is_enable;
275
276 status.all = REG_READ(DMCUB_SCRATCH0);
277 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable);
278
279 return is_enable != 0 && status.bits.dal_fw;
280 }
281
dmub_dcn31_is_supported(struct dmub_srv * dmub)282 bool dmub_dcn31_is_supported(struct dmub_srv *dmub)
283 {
284 uint32_t supported = 0;
285
286 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
287
288 return supported;
289 }
290
dmub_dcn31_set_gpint(struct dmub_srv * dmub,union dmub_gpint_data_register reg)291 void dmub_dcn31_set_gpint(struct dmub_srv *dmub,
292 union dmub_gpint_data_register reg)
293 {
294 REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
295 }
296
dmub_dcn31_is_gpint_acked(struct dmub_srv * dmub,union dmub_gpint_data_register reg)297 bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub,
298 union dmub_gpint_data_register reg)
299 {
300 union dmub_gpint_data_register test;
301
302 reg.bits.status = 0;
303 test.all = REG_READ(DMCUB_GPINT_DATAIN1);
304
305 return test.all == reg.all;
306 }
307
dmub_dcn31_get_gpint_response(struct dmub_srv * dmub)308 uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub)
309 {
310 return REG_READ(DMCUB_SCRATCH7);
311 }
312
dmub_dcn31_get_gpint_dataout(struct dmub_srv * dmub)313 uint32_t dmub_dcn31_get_gpint_dataout(struct dmub_srv *dmub)
314 {
315 uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);
316
317 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);
318
319 REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
320 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);
321 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);
322
323 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);
324
325 return dataout;
326 }
327
dmub_dcn31_get_fw_boot_status(struct dmub_srv * dmub)328 union dmub_fw_boot_status dmub_dcn31_get_fw_boot_status(struct dmub_srv *dmub)
329 {
330 union dmub_fw_boot_status status;
331
332 status.all = REG_READ(DMCUB_SCRATCH0);
333 return status;
334 }
335
dmub_dcn31_enable_dmub_boot_options(struct dmub_srv * dmub,const struct dmub_srv_hw_params * params)336 void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
337 {
338 union dmub_fw_boot_options boot_options = {0};
339
340 boot_options.bits.z10_disable = params->disable_z10;
341
342 REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
343 }
344
dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv * dmub,bool skip)345 void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
346 {
347 union dmub_fw_boot_options boot_options;
348 boot_options.all = REG_READ(DMCUB_SCRATCH14);
349 boot_options.bits.skip_phy_init_panel_sequence = skip;
350 REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
351 }
352
dmub_dcn31_setup_outbox0(struct dmub_srv * dmub,const struct dmub_region * outbox0)353 void dmub_dcn31_setup_outbox0(struct dmub_srv *dmub,
354 const struct dmub_region *outbox0)
355 {
356 REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
357
358 REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
359 }
360
dmub_dcn31_get_outbox0_wptr(struct dmub_srv * dmub)361 uint32_t dmub_dcn31_get_outbox0_wptr(struct dmub_srv *dmub)
362 {
363 return REG_READ(DMCUB_OUTBOX0_WPTR);
364 }
365
dmub_dcn31_set_outbox0_rptr(struct dmub_srv * dmub,uint32_t rptr_offset)366 void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
367 {
368 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
369 }
370
dmub_dcn31_get_current_time(struct dmub_srv * dmub)371 uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub)
372 {
373 return REG_READ(DMCUB_TIMER_CURRENT);
374 }
375
dmub_dcn31_get_diagnostic_data(struct dmub_srv * dmub,struct dmub_diagnostic_data * diag_data)376 void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
377 {
378 uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;
379 uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
380
381 if (!dmub || !diag_data)
382 return;
383
384 memset(diag_data, 0, sizeof(*diag_data));
385
386 diag_data->dmcub_version = dmub->fw_version;
387
388 diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0);
389 diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1);
390 diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2);
391 diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3);
392 diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4);
393 diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5);
394 diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6);
395 diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7);
396 diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8);
397 diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9);
398 diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10);
399 diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11);
400 diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12);
401 diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13);
402 diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14);
403 diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15);
404
405 diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
406 diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
407 diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
408
409 diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
410 diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
411 diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
412
413 diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
414 diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
415 diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
416
417 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
418 diag_data->is_dmcub_enabled = is_dmub_enabled;
419
420 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
421 diag_data->is_dmcub_soft_reset = is_soft_reset;
422
423 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
424 diag_data->is_dmcub_secure_reset = is_sec_reset;
425
426 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
427 diag_data->is_traceport_en = is_traceport_enabled;
428
429 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
430 diag_data->is_cw0_enabled = is_cw0_enabled;
431
432 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
433 diag_data->is_cw6_enabled = is_cw6_enabled;
434 }
435