1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /*
3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
4 */
5
6 #include "ena_com.h"
7
8 /*****************************************************************************/
9 /*****************************************************************************/
10
11 /* Timeout in micro-sec */
12 #define ADMIN_CMD_TIMEOUT_US (3000000)
13
14 #define ENA_ASYNC_QUEUE_DEPTH 16
15 #define ENA_ADMIN_QUEUE_DEPTH 32
16
17
18 #define ENA_CTRL_MAJOR 0
19 #define ENA_CTRL_MINOR 0
20 #define ENA_CTRL_SUB_MINOR 1
21
22 #define MIN_ENA_CTRL_VER \
23 (((ENA_CTRL_MAJOR) << \
24 (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
25 ((ENA_CTRL_MINOR) << \
26 (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
27 (ENA_CTRL_SUB_MINOR))
28
29 #define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x)))
30 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32))
31
32 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF
33
34 #define ENA_COM_BOUNCE_BUFFER_CNTRL_CNT 4
35
36 #define ENA_REGS_ADMIN_INTR_MASK 1
37
38 #define ENA_MAX_BACKOFF_DELAY_EXP 16U
39
40 #define ENA_MIN_ADMIN_POLL_US 100
41
42 #define ENA_MAX_ADMIN_POLL_US 5000
43
44 /*****************************************************************************/
45 /*****************************************************************************/
46 /*****************************************************************************/
47
48 enum ena_cmd_status {
49 ENA_CMD_SUBMITTED,
50 ENA_CMD_COMPLETED,
51 /* Abort - canceled by the driver */
52 ENA_CMD_ABORTED,
53 };
54
55 struct ena_comp_ctx {
56 struct completion wait_event;
57 struct ena_admin_acq_entry *user_cqe;
58 u32 comp_size;
59 enum ena_cmd_status status;
60 /* status from the device */
61 u8 comp_status;
62 u8 cmd_opcode;
63 bool occupied;
64 };
65
66 struct ena_com_stats_ctx {
67 struct ena_admin_aq_get_stats_cmd get_cmd;
68 struct ena_admin_acq_get_stats_resp get_resp;
69 };
70
ena_com_mem_addr_set(struct ena_com_dev * ena_dev,struct ena_common_mem_addr * ena_addr,dma_addr_t addr)71 static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev,
72 struct ena_common_mem_addr *ena_addr,
73 dma_addr_t addr)
74 {
75 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) {
76 netdev_err(ena_dev->net_device,
77 "DMA address has more bits that the device supports\n");
78 return -EINVAL;
79 }
80
81 ena_addr->mem_addr_low = lower_32_bits(addr);
82 ena_addr->mem_addr_high = (u16)upper_32_bits(addr);
83
84 return 0;
85 }
86
ena_com_admin_init_sq(struct ena_com_admin_queue * admin_queue)87 static int ena_com_admin_init_sq(struct ena_com_admin_queue *admin_queue)
88 {
89 struct ena_com_dev *ena_dev = admin_queue->ena_dev;
90 struct ena_com_admin_sq *sq = &admin_queue->sq;
91 u16 size = ADMIN_SQ_SIZE(admin_queue->q_depth);
92
93 sq->entries = dma_alloc_coherent(admin_queue->q_dmadev, size,
94 &sq->dma_addr, GFP_KERNEL);
95
96 if (!sq->entries) {
97 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
98 return -ENOMEM;
99 }
100
101 sq->head = 0;
102 sq->tail = 0;
103 sq->phase = 1;
104
105 sq->db_addr = NULL;
106
107 return 0;
108 }
109
ena_com_admin_init_cq(struct ena_com_admin_queue * admin_queue)110 static int ena_com_admin_init_cq(struct ena_com_admin_queue *admin_queue)
111 {
112 struct ena_com_dev *ena_dev = admin_queue->ena_dev;
113 struct ena_com_admin_cq *cq = &admin_queue->cq;
114 u16 size = ADMIN_CQ_SIZE(admin_queue->q_depth);
115
116 cq->entries = dma_alloc_coherent(admin_queue->q_dmadev, size,
117 &cq->dma_addr, GFP_KERNEL);
118
119 if (!cq->entries) {
120 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
121 return -ENOMEM;
122 }
123
124 cq->head = 0;
125 cq->phase = 1;
126
127 return 0;
128 }
129
ena_com_admin_init_aenq(struct ena_com_dev * ena_dev,struct ena_aenq_handlers * aenq_handlers)130 static int ena_com_admin_init_aenq(struct ena_com_dev *ena_dev,
131 struct ena_aenq_handlers *aenq_handlers)
132 {
133 struct ena_com_aenq *aenq = &ena_dev->aenq;
134 u32 addr_low, addr_high, aenq_caps;
135 u16 size;
136
137 ena_dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH;
138 size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH);
139 aenq->entries = dma_alloc_coherent(ena_dev->dmadev, size,
140 &aenq->dma_addr, GFP_KERNEL);
141
142 if (!aenq->entries) {
143 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
144 return -ENOMEM;
145 }
146
147 aenq->head = aenq->q_depth;
148 aenq->phase = 1;
149
150 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
151 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
152
153 writel(addr_low, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);
154 writel(addr_high, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);
155
156 aenq_caps = 0;
157 aenq_caps |= ena_dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
158 aenq_caps |= (sizeof(struct ena_admin_aenq_entry)
159 << ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
160 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
161 writel(aenq_caps, ena_dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);
162
163 if (unlikely(!aenq_handlers)) {
164 netdev_err(ena_dev->net_device,
165 "AENQ handlers pointer is NULL\n");
166 return -EINVAL;
167 }
168
169 aenq->aenq_handlers = aenq_handlers;
170
171 return 0;
172 }
173
comp_ctxt_release(struct ena_com_admin_queue * queue,struct ena_comp_ctx * comp_ctx)174 static void comp_ctxt_release(struct ena_com_admin_queue *queue,
175 struct ena_comp_ctx *comp_ctx)
176 {
177 comp_ctx->occupied = false;
178 atomic_dec(&queue->outstanding_cmds);
179 }
180
get_comp_ctxt(struct ena_com_admin_queue * admin_queue,u16 command_id,bool capture)181 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *admin_queue,
182 u16 command_id, bool capture)
183 {
184 if (unlikely(command_id >= admin_queue->q_depth)) {
185 netdev_err(admin_queue->ena_dev->net_device,
186 "Command id is larger than the queue size. cmd_id: %u queue size %d\n",
187 command_id, admin_queue->q_depth);
188 return NULL;
189 }
190
191 if (unlikely(!admin_queue->comp_ctx)) {
192 netdev_err(admin_queue->ena_dev->net_device,
193 "Completion context is NULL\n");
194 return NULL;
195 }
196
197 if (unlikely(admin_queue->comp_ctx[command_id].occupied && capture)) {
198 netdev_err(admin_queue->ena_dev->net_device,
199 "Completion context is occupied\n");
200 return NULL;
201 }
202
203 if (capture) {
204 atomic_inc(&admin_queue->outstanding_cmds);
205 admin_queue->comp_ctx[command_id].occupied = true;
206 }
207
208 return &admin_queue->comp_ctx[command_id];
209 }
210
__ena_com_submit_admin_cmd(struct ena_com_admin_queue * admin_queue,struct ena_admin_aq_entry * cmd,size_t cmd_size_in_bytes,struct ena_admin_acq_entry * comp,size_t comp_size_in_bytes)211 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
212 struct ena_admin_aq_entry *cmd,
213 size_t cmd_size_in_bytes,
214 struct ena_admin_acq_entry *comp,
215 size_t comp_size_in_bytes)
216 {
217 struct ena_comp_ctx *comp_ctx;
218 u16 tail_masked, cmd_id;
219 u16 queue_size_mask;
220 u16 cnt;
221
222 queue_size_mask = admin_queue->q_depth - 1;
223
224 tail_masked = admin_queue->sq.tail & queue_size_mask;
225
226 /* In case of queue FULL */
227 cnt = (u16)atomic_read(&admin_queue->outstanding_cmds);
228 if (cnt >= admin_queue->q_depth) {
229 netdev_dbg(admin_queue->ena_dev->net_device,
230 "Admin queue is full.\n");
231 admin_queue->stats.out_of_space++;
232 return ERR_PTR(-ENOSPC);
233 }
234
235 cmd_id = admin_queue->curr_cmd_id;
236
237 cmd->aq_common_descriptor.flags |= admin_queue->sq.phase &
238 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
239
240 cmd->aq_common_descriptor.command_id |= cmd_id &
241 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
242
243 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true);
244 if (unlikely(!comp_ctx))
245 return ERR_PTR(-EINVAL);
246
247 comp_ctx->status = ENA_CMD_SUBMITTED;
248 comp_ctx->comp_size = (u32)comp_size_in_bytes;
249 comp_ctx->user_cqe = comp;
250 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
251
252 reinit_completion(&comp_ctx->wait_event);
253
254 memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes);
255
256 admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) &
257 queue_size_mask;
258
259 admin_queue->sq.tail++;
260 admin_queue->stats.submitted_cmd++;
261
262 if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0))
263 admin_queue->sq.phase = !admin_queue->sq.phase;
264
265 writel(admin_queue->sq.tail, admin_queue->sq.db_addr);
266
267 return comp_ctx;
268 }
269
ena_com_init_comp_ctxt(struct ena_com_admin_queue * admin_queue)270 static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *admin_queue)
271 {
272 struct ena_com_dev *ena_dev = admin_queue->ena_dev;
273 size_t size = admin_queue->q_depth * sizeof(struct ena_comp_ctx);
274 struct ena_comp_ctx *comp_ctx;
275 u16 i;
276
277 admin_queue->comp_ctx =
278 devm_kzalloc(admin_queue->q_dmadev, size, GFP_KERNEL);
279 if (unlikely(!admin_queue->comp_ctx)) {
280 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
281 return -ENOMEM;
282 }
283
284 for (i = 0; i < admin_queue->q_depth; i++) {
285 comp_ctx = get_comp_ctxt(admin_queue, i, false);
286 if (comp_ctx)
287 init_completion(&comp_ctx->wait_event);
288 }
289
290 return 0;
291 }
292
ena_com_submit_admin_cmd(struct ena_com_admin_queue * admin_queue,struct ena_admin_aq_entry * cmd,size_t cmd_size_in_bytes,struct ena_admin_acq_entry * comp,size_t comp_size_in_bytes)293 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue,
294 struct ena_admin_aq_entry *cmd,
295 size_t cmd_size_in_bytes,
296 struct ena_admin_acq_entry *comp,
297 size_t comp_size_in_bytes)
298 {
299 unsigned long flags = 0;
300 struct ena_comp_ctx *comp_ctx;
301
302 spin_lock_irqsave(&admin_queue->q_lock, flags);
303 if (unlikely(!admin_queue->running_state)) {
304 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
305 return ERR_PTR(-ENODEV);
306 }
307 comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd,
308 cmd_size_in_bytes,
309 comp,
310 comp_size_in_bytes);
311 if (IS_ERR(comp_ctx))
312 admin_queue->running_state = false;
313 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
314
315 return comp_ctx;
316 }
317
ena_com_init_io_sq(struct ena_com_dev * ena_dev,struct ena_com_create_io_ctx * ctx,struct ena_com_io_sq * io_sq)318 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,
319 struct ena_com_create_io_ctx *ctx,
320 struct ena_com_io_sq *io_sq)
321 {
322 size_t size;
323 int dev_node = 0;
324
325 memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr));
326
327 io_sq->dma_addr_bits = (u8)ena_dev->dma_addr_bits;
328 io_sq->desc_entry_size =
329 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
330 sizeof(struct ena_eth_io_tx_desc) :
331 sizeof(struct ena_eth_io_rx_desc);
332
333 size = io_sq->desc_entry_size * io_sq->q_depth;
334
335 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
336 dev_node = dev_to_node(ena_dev->dmadev);
337 set_dev_node(ena_dev->dmadev, ctx->numa_node);
338 io_sq->desc_addr.virt_addr =
339 dma_alloc_coherent(ena_dev->dmadev, size,
340 &io_sq->desc_addr.phys_addr,
341 GFP_KERNEL);
342 set_dev_node(ena_dev->dmadev, dev_node);
343 if (!io_sq->desc_addr.virt_addr) {
344 io_sq->desc_addr.virt_addr =
345 dma_alloc_coherent(ena_dev->dmadev, size,
346 &io_sq->desc_addr.phys_addr,
347 GFP_KERNEL);
348 }
349
350 if (!io_sq->desc_addr.virt_addr) {
351 netdev_err(ena_dev->net_device,
352 "Memory allocation failed\n");
353 return -ENOMEM;
354 }
355 }
356
357 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
358 /* Allocate bounce buffers */
359 io_sq->bounce_buf_ctrl.buffer_size =
360 ena_dev->llq_info.desc_list_entry_size;
361 io_sq->bounce_buf_ctrl.buffers_num =
362 ENA_COM_BOUNCE_BUFFER_CNTRL_CNT;
363 io_sq->bounce_buf_ctrl.next_to_use = 0;
364
365 size = io_sq->bounce_buf_ctrl.buffer_size *
366 io_sq->bounce_buf_ctrl.buffers_num;
367
368 dev_node = dev_to_node(ena_dev->dmadev);
369 set_dev_node(ena_dev->dmadev, ctx->numa_node);
370 io_sq->bounce_buf_ctrl.base_buffer =
371 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
372 set_dev_node(ena_dev->dmadev, dev_node);
373 if (!io_sq->bounce_buf_ctrl.base_buffer)
374 io_sq->bounce_buf_ctrl.base_buffer =
375 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL);
376
377 if (!io_sq->bounce_buf_ctrl.base_buffer) {
378 netdev_err(ena_dev->net_device,
379 "Bounce buffer memory allocation failed\n");
380 return -ENOMEM;
381 }
382
383 memcpy(&io_sq->llq_info, &ena_dev->llq_info,
384 sizeof(io_sq->llq_info));
385
386 /* Initiate the first bounce buffer */
387 io_sq->llq_buf_ctrl.curr_bounce_buf =
388 ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl);
389 memset(io_sq->llq_buf_ctrl.curr_bounce_buf,
390 0x0, io_sq->llq_info.desc_list_entry_size);
391 io_sq->llq_buf_ctrl.descs_left_in_line =
392 io_sq->llq_info.descs_num_before_header;
393 io_sq->disable_meta_caching =
394 io_sq->llq_info.disable_meta_caching;
395
396 if (io_sq->llq_info.max_entries_in_tx_burst > 0)
397 io_sq->entries_in_tx_burst_left =
398 io_sq->llq_info.max_entries_in_tx_burst;
399 }
400
401 io_sq->tail = 0;
402 io_sq->next_to_comp = 0;
403 io_sq->phase = 1;
404
405 return 0;
406 }
407
ena_com_init_io_cq(struct ena_com_dev * ena_dev,struct ena_com_create_io_ctx * ctx,struct ena_com_io_cq * io_cq)408 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
409 struct ena_com_create_io_ctx *ctx,
410 struct ena_com_io_cq *io_cq)
411 {
412 size_t size;
413 int prev_node = 0;
414
415 memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr));
416
417 /* Use the basic completion descriptor for Rx */
418 io_cq->cdesc_entry_size_in_bytes =
419 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ?
420 sizeof(struct ena_eth_io_tx_cdesc) :
421 sizeof(struct ena_eth_io_rx_cdesc_base);
422
423 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
424
425 prev_node = dev_to_node(ena_dev->dmadev);
426 set_dev_node(ena_dev->dmadev, ctx->numa_node);
427 io_cq->cdesc_addr.virt_addr =
428 dma_alloc_coherent(ena_dev->dmadev, size,
429 &io_cq->cdesc_addr.phys_addr, GFP_KERNEL);
430 set_dev_node(ena_dev->dmadev, prev_node);
431 if (!io_cq->cdesc_addr.virt_addr) {
432 io_cq->cdesc_addr.virt_addr =
433 dma_alloc_coherent(ena_dev->dmadev, size,
434 &io_cq->cdesc_addr.phys_addr,
435 GFP_KERNEL);
436 }
437
438 if (!io_cq->cdesc_addr.virt_addr) {
439 netdev_err(ena_dev->net_device, "Memory allocation failed\n");
440 return -ENOMEM;
441 }
442
443 io_cq->phase = 1;
444 io_cq->head = 0;
445
446 return 0;
447 }
448
ena_com_handle_single_admin_completion(struct ena_com_admin_queue * admin_queue,struct ena_admin_acq_entry * cqe)449 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue,
450 struct ena_admin_acq_entry *cqe)
451 {
452 struct ena_comp_ctx *comp_ctx;
453 u16 cmd_id;
454
455 cmd_id = cqe->acq_common_descriptor.command &
456 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
457
458 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false);
459 if (unlikely(!comp_ctx)) {
460 netdev_err(admin_queue->ena_dev->net_device,
461 "comp_ctx is NULL. Changing the admin queue running state\n");
462 admin_queue->running_state = false;
463 return;
464 }
465
466 comp_ctx->status = ENA_CMD_COMPLETED;
467 comp_ctx->comp_status = cqe->acq_common_descriptor.status;
468
469 if (comp_ctx->user_cqe)
470 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size);
471
472 if (!admin_queue->polling)
473 complete(&comp_ctx->wait_event);
474 }
475
ena_com_handle_admin_completion(struct ena_com_admin_queue * admin_queue)476 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue)
477 {
478 struct ena_admin_acq_entry *cqe = NULL;
479 u16 comp_num = 0;
480 u16 head_masked;
481 u8 phase;
482
483 head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1);
484 phase = admin_queue->cq.phase;
485
486 cqe = &admin_queue->cq.entries[head_masked];
487
488 /* Go over all the completions */
489 while ((READ_ONCE(cqe->acq_common_descriptor.flags) &
490 ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
491 /* Do not read the rest of the completion entry before the
492 * phase bit was validated
493 */
494 dma_rmb();
495 ena_com_handle_single_admin_completion(admin_queue, cqe);
496
497 head_masked++;
498 comp_num++;
499 if (unlikely(head_masked == admin_queue->q_depth)) {
500 head_masked = 0;
501 phase = !phase;
502 }
503
504 cqe = &admin_queue->cq.entries[head_masked];
505 }
506
507 admin_queue->cq.head += comp_num;
508 admin_queue->cq.phase = phase;
509 admin_queue->sq.head += comp_num;
510 admin_queue->stats.completed_cmd += comp_num;
511 }
512
ena_com_comp_status_to_errno(struct ena_com_admin_queue * admin_queue,u8 comp_status)513 static int ena_com_comp_status_to_errno(struct ena_com_admin_queue *admin_queue,
514 u8 comp_status)
515 {
516 if (unlikely(comp_status != 0))
517 netdev_err(admin_queue->ena_dev->net_device,
518 "Admin command failed[%u]\n", comp_status);
519
520 switch (comp_status) {
521 case ENA_ADMIN_SUCCESS:
522 return 0;
523 case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
524 return -ENOMEM;
525 case ENA_ADMIN_UNSUPPORTED_OPCODE:
526 return -EOPNOTSUPP;
527 case ENA_ADMIN_BAD_OPCODE:
528 case ENA_ADMIN_MALFORMED_REQUEST:
529 case ENA_ADMIN_ILLEGAL_PARAMETER:
530 case ENA_ADMIN_UNKNOWN_ERROR:
531 return -EINVAL;
532 case ENA_ADMIN_RESOURCE_BUSY:
533 return -EAGAIN;
534 }
535
536 return -EINVAL;
537 }
538
ena_delay_exponential_backoff_us(u32 exp,u32 delay_us)539 static void ena_delay_exponential_backoff_us(u32 exp, u32 delay_us)
540 {
541 exp = min_t(u32, exp, ENA_MAX_BACKOFF_DELAY_EXP);
542 delay_us = max_t(u32, ENA_MIN_ADMIN_POLL_US, delay_us);
543 delay_us = min_t(u32, delay_us * (1U << exp), ENA_MAX_ADMIN_POLL_US);
544 usleep_range(delay_us, 2 * delay_us);
545 }
546
ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx * comp_ctx,struct ena_com_admin_queue * admin_queue)547 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx,
548 struct ena_com_admin_queue *admin_queue)
549 {
550 unsigned long flags = 0;
551 unsigned long timeout;
552 int ret;
553 u32 exp = 0;
554
555 timeout = jiffies + usecs_to_jiffies(admin_queue->completion_timeout);
556
557 while (1) {
558 spin_lock_irqsave(&admin_queue->q_lock, flags);
559 ena_com_handle_admin_completion(admin_queue);
560 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
561
562 if (comp_ctx->status != ENA_CMD_SUBMITTED)
563 break;
564
565 if (time_is_before_jiffies(timeout)) {
566 netdev_err(admin_queue->ena_dev->net_device,
567 "Wait for completion (polling) timeout\n");
568 /* ENA didn't have any completion */
569 spin_lock_irqsave(&admin_queue->q_lock, flags);
570 admin_queue->stats.no_completion++;
571 admin_queue->running_state = false;
572 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
573
574 ret = -ETIME;
575 goto err;
576 }
577
578 ena_delay_exponential_backoff_us(exp++,
579 admin_queue->ena_dev->ena_min_poll_delay_us);
580 }
581
582 if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) {
583 netdev_err(admin_queue->ena_dev->net_device,
584 "Command was aborted\n");
585 spin_lock_irqsave(&admin_queue->q_lock, flags);
586 admin_queue->stats.aborted_cmd++;
587 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
588 ret = -ENODEV;
589 goto err;
590 }
591
592 WARN(comp_ctx->status != ENA_CMD_COMPLETED, "Invalid comp status %d\n",
593 comp_ctx->status);
594
595 ret = ena_com_comp_status_to_errno(admin_queue, comp_ctx->comp_status);
596 err:
597 comp_ctxt_release(admin_queue, comp_ctx);
598 return ret;
599 }
600
601 /*
602 * Set the LLQ configurations of the firmware
603 *
604 * The driver provides only the enabled feature values to the device,
605 * which in turn, checks if they are supported.
606 */
ena_com_set_llq(struct ena_com_dev * ena_dev)607 static int ena_com_set_llq(struct ena_com_dev *ena_dev)
608 {
609 struct ena_com_admin_queue *admin_queue;
610 struct ena_admin_set_feat_cmd cmd;
611 struct ena_admin_set_feat_resp resp;
612 struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
613 int ret;
614
615 memset(&cmd, 0x0, sizeof(cmd));
616 admin_queue = &ena_dev->admin_queue;
617
618 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
619 cmd.feat_common.feature_id = ENA_ADMIN_LLQ;
620
621 cmd.u.llq.header_location_ctrl_enabled = llq_info->header_location_ctrl;
622 cmd.u.llq.entry_size_ctrl_enabled = llq_info->desc_list_entry_size_ctrl;
623 cmd.u.llq.desc_num_before_header_enabled = llq_info->descs_num_before_header;
624 cmd.u.llq.descriptors_stride_ctrl_enabled = llq_info->desc_stride_ctrl;
625
626 cmd.u.llq.accel_mode.u.set.enabled_flags =
627 BIT(ENA_ADMIN_DISABLE_META_CACHING) |
628 BIT(ENA_ADMIN_LIMIT_TX_BURST);
629
630 ret = ena_com_execute_admin_command(admin_queue,
631 (struct ena_admin_aq_entry *)&cmd,
632 sizeof(cmd),
633 (struct ena_admin_acq_entry *)&resp,
634 sizeof(resp));
635
636 if (unlikely(ret))
637 netdev_err(ena_dev->net_device,
638 "Failed to set LLQ configurations: %d\n", ret);
639
640 return ret;
641 }
642
ena_com_config_llq_info(struct ena_com_dev * ena_dev,struct ena_admin_feature_llq_desc * llq_features,struct ena_llq_configurations * llq_default_cfg)643 static int ena_com_config_llq_info(struct ena_com_dev *ena_dev,
644 struct ena_admin_feature_llq_desc *llq_features,
645 struct ena_llq_configurations *llq_default_cfg)
646 {
647 struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
648 struct ena_admin_accel_mode_get llq_accel_mode_get;
649 u16 supported_feat;
650 int rc;
651
652 memset(llq_info, 0, sizeof(*llq_info));
653
654 supported_feat = llq_features->header_location_ctrl_supported;
655
656 if (likely(supported_feat & llq_default_cfg->llq_header_location)) {
657 llq_info->header_location_ctrl =
658 llq_default_cfg->llq_header_location;
659 } else {
660 netdev_err(ena_dev->net_device,
661 "Invalid header location control, supported: 0x%x\n",
662 supported_feat);
663 return -EINVAL;
664 }
665
666 if (likely(llq_info->header_location_ctrl == ENA_ADMIN_INLINE_HEADER)) {
667 supported_feat = llq_features->descriptors_stride_ctrl_supported;
668 if (likely(supported_feat & llq_default_cfg->llq_stride_ctrl)) {
669 llq_info->desc_stride_ctrl = llq_default_cfg->llq_stride_ctrl;
670 } else {
671 if (supported_feat & ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) {
672 llq_info->desc_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY;
673 } else if (supported_feat & ENA_ADMIN_SINGLE_DESC_PER_ENTRY) {
674 llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY;
675 } else {
676 netdev_err(ena_dev->net_device,
677 "Invalid desc_stride_ctrl, supported: 0x%x\n",
678 supported_feat);
679 return -EINVAL;
680 }
681
682 netdev_err(ena_dev->net_device,
683 "Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
684 llq_default_cfg->llq_stride_ctrl,
685 supported_feat, llq_info->desc_stride_ctrl);
686 }
687 } else {
688 llq_info->desc_stride_ctrl = 0;
689 }
690
691 supported_feat = llq_features->entry_size_ctrl_supported;
692 if (likely(supported_feat & llq_default_cfg->llq_ring_entry_size)) {
693 llq_info->desc_list_entry_size_ctrl = llq_default_cfg->llq_ring_entry_size;
694 llq_info->desc_list_entry_size = llq_default_cfg->llq_ring_entry_size_value;
695 } else {
696 if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_128B) {
697 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_128B;
698 llq_info->desc_list_entry_size = 128;
699 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_192B) {
700 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_192B;
701 llq_info->desc_list_entry_size = 192;
702 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_256B) {
703 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_256B;
704 llq_info->desc_list_entry_size = 256;
705 } else {
706 netdev_err(ena_dev->net_device,
707 "Invalid entry_size_ctrl, supported: 0x%x\n",
708 supported_feat);
709 return -EINVAL;
710 }
711
712 netdev_err(ena_dev->net_device,
713 "Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
714 llq_default_cfg->llq_ring_entry_size, supported_feat,
715 llq_info->desc_list_entry_size);
716 }
717 if (unlikely(llq_info->desc_list_entry_size & 0x7)) {
718 /* The desc list entry size should be whole multiply of 8
719 * This requirement comes from __iowrite64_copy()
720 */
721 netdev_err(ena_dev->net_device, "Illegal entry size %d\n",
722 llq_info->desc_list_entry_size);
723 return -EINVAL;
724 }
725
726 if (llq_info->desc_stride_ctrl == ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY)
727 llq_info->descs_per_entry = llq_info->desc_list_entry_size /
728 sizeof(struct ena_eth_io_tx_desc);
729 else
730 llq_info->descs_per_entry = 1;
731
732 supported_feat = llq_features->desc_num_before_header_supported;
733 if (likely(supported_feat & llq_default_cfg->llq_num_decs_before_header)) {
734 llq_info->descs_num_before_header = llq_default_cfg->llq_num_decs_before_header;
735 } else {
736 if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2) {
737 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2;
738 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1) {
739 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1;
740 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4) {
741 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4;
742 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8) {
743 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8;
744 } else {
745 netdev_err(ena_dev->net_device,
746 "Invalid descs_num_before_header, supported: 0x%x\n",
747 supported_feat);
748 return -EINVAL;
749 }
750
751 netdev_err(ena_dev->net_device,
752 "Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n",
753 llq_default_cfg->llq_num_decs_before_header,
754 supported_feat, llq_info->descs_num_before_header);
755 }
756 /* Check for accelerated queue supported */
757 llq_accel_mode_get = llq_features->accel_mode.u.get;
758
759 llq_info->disable_meta_caching =
760 !!(llq_accel_mode_get.supported_flags &
761 BIT(ENA_ADMIN_DISABLE_META_CACHING));
762
763 if (llq_accel_mode_get.supported_flags & BIT(ENA_ADMIN_LIMIT_TX_BURST))
764 llq_info->max_entries_in_tx_burst =
765 llq_accel_mode_get.max_tx_burst_size /
766 llq_default_cfg->llq_ring_entry_size_value;
767
768 rc = ena_com_set_llq(ena_dev);
769 if (rc)
770 netdev_err(ena_dev->net_device,
771 "Cannot set LLQ configuration: %d\n", rc);
772
773 return rc;
774 }
775
ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx * comp_ctx,struct ena_com_admin_queue * admin_queue)776 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx,
777 struct ena_com_admin_queue *admin_queue)
778 {
779 unsigned long flags = 0;
780 int ret;
781
782 wait_for_completion_timeout(&comp_ctx->wait_event,
783 usecs_to_jiffies(
784 admin_queue->completion_timeout));
785
786 /* In case the command wasn't completed find out the root cause.
787 * There might be 2 kinds of errors
788 * 1) No completion (timeout reached)
789 * 2) There is completion but the device didn't get any msi-x interrupt.
790 */
791 if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) {
792 spin_lock_irqsave(&admin_queue->q_lock, flags);
793 ena_com_handle_admin_completion(admin_queue);
794 admin_queue->stats.no_completion++;
795 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
796
797 if (comp_ctx->status == ENA_CMD_COMPLETED) {
798 netdev_err(admin_queue->ena_dev->net_device,
799 "The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d), autopolling mode is %s\n",
800 comp_ctx->cmd_opcode,
801 admin_queue->auto_polling ? "ON" : "OFF");
802 /* Check if fallback to polling is enabled */
803 if (admin_queue->auto_polling)
804 admin_queue->polling = true;
805 } else {
806 netdev_err(admin_queue->ena_dev->net_device,
807 "The ena device didn't send a completion for the admin cmd %d status %d\n",
808 comp_ctx->cmd_opcode, comp_ctx->status);
809 }
810 /* Check if shifted to polling mode.
811 * This will happen if there is a completion without an interrupt
812 * and autopolling mode is enabled. Continuing normal execution in such case
813 */
814 if (!admin_queue->polling) {
815 admin_queue->running_state = false;
816 ret = -ETIME;
817 goto err;
818 }
819 }
820
821 ret = ena_com_comp_status_to_errno(admin_queue, comp_ctx->comp_status);
822 err:
823 comp_ctxt_release(admin_queue, comp_ctx);
824 return ret;
825 }
826
827 /* This method read the hardware device register through posting writes
828 * and waiting for response
829 * On timeout the function will return ENA_MMIO_READ_TIMEOUT
830 */
ena_com_reg_bar_read32(struct ena_com_dev * ena_dev,u16 offset)831 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset)
832 {
833 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
834 volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp =
835 mmio_read->read_resp;
836 u32 mmio_read_reg, ret, i;
837 unsigned long flags = 0;
838 u32 timeout = mmio_read->reg_read_to;
839
840 might_sleep();
841
842 if (timeout == 0)
843 timeout = ENA_REG_READ_TIMEOUT;
844
845 /* If readless is disabled, perform regular read */
846 if (!mmio_read->readless_supported)
847 return readl(ena_dev->reg_bar + offset);
848
849 spin_lock_irqsave(&mmio_read->lock, flags);
850 mmio_read->seq_num++;
851
852 read_resp->req_id = mmio_read->seq_num + 0xDEAD;
853 mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
854 ENA_REGS_MMIO_REG_READ_REG_OFF_MASK;
855 mmio_read_reg |= mmio_read->seq_num &
856 ENA_REGS_MMIO_REG_READ_REQ_ID_MASK;
857
858 writel(mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);
859
860 for (i = 0; i < timeout; i++) {
861 if (READ_ONCE(read_resp->req_id) == mmio_read->seq_num)
862 break;
863
864 udelay(1);
865 }
866
867 if (unlikely(i == timeout)) {
868 netdev_err(ena_dev->net_device,
869 "Reading reg failed for timeout. expected: req id[%u] offset[%u] actual: req id[%u] offset[%u]\n",
870 mmio_read->seq_num, offset, read_resp->req_id,
871 read_resp->reg_off);
872 ret = ENA_MMIO_READ_TIMEOUT;
873 goto err;
874 }
875
876 if (read_resp->reg_off != offset) {
877 netdev_err(ena_dev->net_device,
878 "Read failure: wrong offset provided\n");
879 ret = ENA_MMIO_READ_TIMEOUT;
880 } else {
881 ret = read_resp->reg_val;
882 }
883 err:
884 spin_unlock_irqrestore(&mmio_read->lock, flags);
885
886 return ret;
887 }
888
889 /* There are two types to wait for completion.
890 * Polling mode - wait until the completion is available.
891 * Async mode - wait on wait queue until the completion is ready
892 * (or the timeout expired).
893 * It is expected that the IRQ called ena_com_handle_admin_completion
894 * to mark the completions.
895 */
ena_com_wait_and_process_admin_cq(struct ena_comp_ctx * comp_ctx,struct ena_com_admin_queue * admin_queue)896 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx,
897 struct ena_com_admin_queue *admin_queue)
898 {
899 if (admin_queue->polling)
900 return ena_com_wait_and_process_admin_cq_polling(comp_ctx,
901 admin_queue);
902
903 return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx,
904 admin_queue);
905 }
906
ena_com_destroy_io_sq(struct ena_com_dev * ena_dev,struct ena_com_io_sq * io_sq)907 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev,
908 struct ena_com_io_sq *io_sq)
909 {
910 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
911 struct ena_admin_aq_destroy_sq_cmd destroy_cmd;
912 struct ena_admin_acq_destroy_sq_resp_desc destroy_resp;
913 u8 direction;
914 int ret;
915
916 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
917
918 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
919 direction = ENA_ADMIN_SQ_DIRECTION_TX;
920 else
921 direction = ENA_ADMIN_SQ_DIRECTION_RX;
922
923 destroy_cmd.sq.sq_identity |= (direction <<
924 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) &
925 ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
926
927 destroy_cmd.sq.sq_idx = io_sq->idx;
928 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ;
929
930 ret = ena_com_execute_admin_command(admin_queue,
931 (struct ena_admin_aq_entry *)&destroy_cmd,
932 sizeof(destroy_cmd),
933 (struct ena_admin_acq_entry *)&destroy_resp,
934 sizeof(destroy_resp));
935
936 if (unlikely(ret && (ret != -ENODEV)))
937 netdev_err(ena_dev->net_device,
938 "Failed to destroy io sq error: %d\n", ret);
939
940 return ret;
941 }
942
ena_com_io_queue_free(struct ena_com_dev * ena_dev,struct ena_com_io_sq * io_sq,struct ena_com_io_cq * io_cq)943 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev,
944 struct ena_com_io_sq *io_sq,
945 struct ena_com_io_cq *io_cq)
946 {
947 size_t size;
948
949 if (io_cq->cdesc_addr.virt_addr) {
950 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
951
952 dma_free_coherent(ena_dev->dmadev, size,
953 io_cq->cdesc_addr.virt_addr,
954 io_cq->cdesc_addr.phys_addr);
955
956 io_cq->cdesc_addr.virt_addr = NULL;
957 }
958
959 if (io_sq->desc_addr.virt_addr) {
960 size = io_sq->desc_entry_size * io_sq->q_depth;
961
962 dma_free_coherent(ena_dev->dmadev, size,
963 io_sq->desc_addr.virt_addr,
964 io_sq->desc_addr.phys_addr);
965
966 io_sq->desc_addr.virt_addr = NULL;
967 }
968
969 if (io_sq->bounce_buf_ctrl.base_buffer) {
970 devm_kfree(ena_dev->dmadev, io_sq->bounce_buf_ctrl.base_buffer);
971 io_sq->bounce_buf_ctrl.base_buffer = NULL;
972 }
973 }
974
wait_for_reset_state(struct ena_com_dev * ena_dev,u32 timeout,u16 exp_state)975 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout,
976 u16 exp_state)
977 {
978 u32 val, exp = 0;
979 unsigned long timeout_stamp;
980
981 /* Convert timeout from resolution of 100ms to us resolution. */
982 timeout_stamp = jiffies + usecs_to_jiffies(100 * 1000 * timeout);
983
984 while (1) {
985 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
986
987 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) {
988 netdev_err(ena_dev->net_device,
989 "Reg read timeout occurred\n");
990 return -ETIME;
991 }
992
993 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
994 exp_state)
995 return 0;
996
997 if (time_is_before_jiffies(timeout_stamp))
998 return -ETIME;
999
1000 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us);
1001 }
1002 }
1003
ena_com_check_supported_feature_id(struct ena_com_dev * ena_dev,enum ena_admin_aq_feature_id feature_id)1004 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev,
1005 enum ena_admin_aq_feature_id feature_id)
1006 {
1007 u32 feature_mask = 1 << feature_id;
1008
1009 /* Device attributes is always supported */
1010 if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) &&
1011 !(ena_dev->supported_features & feature_mask))
1012 return false;
1013
1014 return true;
1015 }
1016
ena_com_get_feature_ex(struct ena_com_dev * ena_dev,struct ena_admin_get_feat_resp * get_resp,enum ena_admin_aq_feature_id feature_id,dma_addr_t control_buf_dma_addr,u32 control_buff_size,u8 feature_ver)1017 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev,
1018 struct ena_admin_get_feat_resp *get_resp,
1019 enum ena_admin_aq_feature_id feature_id,
1020 dma_addr_t control_buf_dma_addr,
1021 u32 control_buff_size,
1022 u8 feature_ver)
1023 {
1024 struct ena_com_admin_queue *admin_queue;
1025 struct ena_admin_get_feat_cmd get_cmd;
1026 int ret;
1027
1028 if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) {
1029 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n",
1030 feature_id);
1031 return -EOPNOTSUPP;
1032 }
1033
1034 memset(&get_cmd, 0x0, sizeof(get_cmd));
1035 admin_queue = &ena_dev->admin_queue;
1036
1037 get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE;
1038
1039 if (control_buff_size)
1040 get_cmd.aq_common_descriptor.flags =
1041 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1042 else
1043 get_cmd.aq_common_descriptor.flags = 0;
1044
1045 ret = ena_com_mem_addr_set(ena_dev,
1046 &get_cmd.control_buffer.address,
1047 control_buf_dma_addr);
1048 if (unlikely(ret)) {
1049 netdev_err(ena_dev->net_device, "Memory address set failed\n");
1050 return ret;
1051 }
1052
1053 get_cmd.control_buffer.length = control_buff_size;
1054 get_cmd.feat_common.feature_version = feature_ver;
1055 get_cmd.feat_common.feature_id = feature_id;
1056
1057 ret = ena_com_execute_admin_command(admin_queue,
1058 (struct ena_admin_aq_entry *)
1059 &get_cmd,
1060 sizeof(get_cmd),
1061 (struct ena_admin_acq_entry *)
1062 get_resp,
1063 sizeof(*get_resp));
1064
1065 if (unlikely(ret))
1066 netdev_err(ena_dev->net_device,
1067 "Failed to submit get_feature command %d error: %d\n",
1068 feature_id, ret);
1069
1070 return ret;
1071 }
1072
ena_com_get_feature(struct ena_com_dev * ena_dev,struct ena_admin_get_feat_resp * get_resp,enum ena_admin_aq_feature_id feature_id,u8 feature_ver)1073 static int ena_com_get_feature(struct ena_com_dev *ena_dev,
1074 struct ena_admin_get_feat_resp *get_resp,
1075 enum ena_admin_aq_feature_id feature_id,
1076 u8 feature_ver)
1077 {
1078 return ena_com_get_feature_ex(ena_dev,
1079 get_resp,
1080 feature_id,
1081 0,
1082 0,
1083 feature_ver);
1084 }
1085
ena_com_get_current_hash_function(struct ena_com_dev * ena_dev)1086 int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev)
1087 {
1088 return ena_dev->rss.hash_func;
1089 }
1090
ena_com_hash_key_fill_default_key(struct ena_com_dev * ena_dev)1091 static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev)
1092 {
1093 struct ena_admin_feature_rss_flow_hash_control *hash_key =
1094 (ena_dev->rss).hash_key;
1095
1096 netdev_rss_key_fill(&hash_key->key, sizeof(hash_key->key));
1097 /* The key buffer is stored in the device in an array of
1098 * uint32 elements.
1099 */
1100 hash_key->key_parts = ENA_ADMIN_RSS_KEY_PARTS;
1101 }
1102
ena_com_hash_key_allocate(struct ena_com_dev * ena_dev)1103 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev)
1104 {
1105 struct ena_rss *rss = &ena_dev->rss;
1106
1107 if (!ena_com_check_supported_feature_id(ena_dev,
1108 ENA_ADMIN_RSS_HASH_FUNCTION))
1109 return -EOPNOTSUPP;
1110
1111 rss->hash_key =
1112 dma_alloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_key),
1113 &rss->hash_key_dma_addr, GFP_KERNEL);
1114
1115 if (unlikely(!rss->hash_key))
1116 return -ENOMEM;
1117
1118 return 0;
1119 }
1120
ena_com_hash_key_destroy(struct ena_com_dev * ena_dev)1121 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev)
1122 {
1123 struct ena_rss *rss = &ena_dev->rss;
1124
1125 if (rss->hash_key)
1126 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_key),
1127 rss->hash_key, rss->hash_key_dma_addr);
1128 rss->hash_key = NULL;
1129 }
1130
ena_com_hash_ctrl_init(struct ena_com_dev * ena_dev)1131 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev)
1132 {
1133 struct ena_rss *rss = &ena_dev->rss;
1134
1135 rss->hash_ctrl =
1136 dma_alloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl),
1137 &rss->hash_ctrl_dma_addr, GFP_KERNEL);
1138
1139 if (unlikely(!rss->hash_ctrl))
1140 return -ENOMEM;
1141
1142 return 0;
1143 }
1144
ena_com_hash_ctrl_destroy(struct ena_com_dev * ena_dev)1145 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev)
1146 {
1147 struct ena_rss *rss = &ena_dev->rss;
1148
1149 if (rss->hash_ctrl)
1150 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl),
1151 rss->hash_ctrl, rss->hash_ctrl_dma_addr);
1152 rss->hash_ctrl = NULL;
1153 }
1154
ena_com_indirect_table_allocate(struct ena_com_dev * ena_dev,u16 log_size)1155 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev,
1156 u16 log_size)
1157 {
1158 struct ena_rss *rss = &ena_dev->rss;
1159 struct ena_admin_get_feat_resp get_resp;
1160 size_t tbl_size;
1161 int ret;
1162
1163 ret = ena_com_get_feature(ena_dev, &get_resp,
1164 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG, 0);
1165 if (unlikely(ret))
1166 return ret;
1167
1168 if ((get_resp.u.ind_table.min_size > log_size) ||
1169 (get_resp.u.ind_table.max_size < log_size)) {
1170 netdev_err(ena_dev->net_device,
1171 "Indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n",
1172 1 << log_size, 1 << get_resp.u.ind_table.min_size,
1173 1 << get_resp.u.ind_table.max_size);
1174 return -EINVAL;
1175 }
1176
1177 tbl_size = (1ULL << log_size) *
1178 sizeof(struct ena_admin_rss_ind_table_entry);
1179
1180 rss->rss_ind_tbl =
1181 dma_alloc_coherent(ena_dev->dmadev, tbl_size,
1182 &rss->rss_ind_tbl_dma_addr, GFP_KERNEL);
1183 if (unlikely(!rss->rss_ind_tbl))
1184 goto mem_err1;
1185
1186 tbl_size = (1ULL << log_size) * sizeof(u16);
1187 rss->host_rss_ind_tbl =
1188 devm_kzalloc(ena_dev->dmadev, tbl_size, GFP_KERNEL);
1189 if (unlikely(!rss->host_rss_ind_tbl))
1190 goto mem_err2;
1191
1192 rss->tbl_log_size = log_size;
1193
1194 return 0;
1195
1196 mem_err2:
1197 tbl_size = (1ULL << log_size) *
1198 sizeof(struct ena_admin_rss_ind_table_entry);
1199
1200 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl,
1201 rss->rss_ind_tbl_dma_addr);
1202 rss->rss_ind_tbl = NULL;
1203 mem_err1:
1204 rss->tbl_log_size = 0;
1205 return -ENOMEM;
1206 }
1207
ena_com_indirect_table_destroy(struct ena_com_dev * ena_dev)1208 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev)
1209 {
1210 struct ena_rss *rss = &ena_dev->rss;
1211 size_t tbl_size = (1ULL << rss->tbl_log_size) *
1212 sizeof(struct ena_admin_rss_ind_table_entry);
1213
1214 if (rss->rss_ind_tbl)
1215 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl,
1216 rss->rss_ind_tbl_dma_addr);
1217 rss->rss_ind_tbl = NULL;
1218
1219 if (rss->host_rss_ind_tbl)
1220 devm_kfree(ena_dev->dmadev, rss->host_rss_ind_tbl);
1221 rss->host_rss_ind_tbl = NULL;
1222 }
1223
ena_com_create_io_sq(struct ena_com_dev * ena_dev,struct ena_com_io_sq * io_sq,u16 cq_idx)1224 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev,
1225 struct ena_com_io_sq *io_sq, u16 cq_idx)
1226 {
1227 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1228 struct ena_admin_aq_create_sq_cmd create_cmd;
1229 struct ena_admin_acq_create_sq_resp_desc cmd_completion;
1230 u8 direction;
1231 int ret;
1232
1233 memset(&create_cmd, 0x0, sizeof(create_cmd));
1234
1235 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ;
1236
1237 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1238 direction = ENA_ADMIN_SQ_DIRECTION_TX;
1239 else
1240 direction = ENA_ADMIN_SQ_DIRECTION_RX;
1241
1242 create_cmd.sq_identity |= (direction <<
1243 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) &
1244 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1245
1246 create_cmd.sq_caps_2 |= io_sq->mem_queue_type &
1247 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1248
1249 create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC <<
1250 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) &
1251 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1252
1253 create_cmd.sq_caps_3 |=
1254 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1255
1256 create_cmd.cq_idx = cq_idx;
1257 create_cmd.sq_depth = io_sq->q_depth;
1258
1259 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) {
1260 ret = ena_com_mem_addr_set(ena_dev,
1261 &create_cmd.sq_ba,
1262 io_sq->desc_addr.phys_addr);
1263 if (unlikely(ret)) {
1264 netdev_err(ena_dev->net_device,
1265 "Memory address set failed\n");
1266 return ret;
1267 }
1268 }
1269
1270 ret = ena_com_execute_admin_command(admin_queue,
1271 (struct ena_admin_aq_entry *)&create_cmd,
1272 sizeof(create_cmd),
1273 (struct ena_admin_acq_entry *)&cmd_completion,
1274 sizeof(cmd_completion));
1275 if (unlikely(ret)) {
1276 netdev_err(ena_dev->net_device,
1277 "Failed to create IO SQ. error: %d\n", ret);
1278 return ret;
1279 }
1280
1281 io_sq->idx = cmd_completion.sq_idx;
1282
1283 io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1284 (uintptr_t)cmd_completion.sq_doorbell_offset);
1285
1286 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1287 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar
1288 + cmd_completion.llq_headers_offset);
1289
1290 io_sq->desc_addr.pbuf_dev_addr =
1291 (u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
1292 cmd_completion.llq_descriptors_offset);
1293 }
1294
1295 netdev_dbg(ena_dev->net_device, "Created sq[%u], depth[%u]\n",
1296 io_sq->idx, io_sq->q_depth);
1297
1298 return ret;
1299 }
1300
ena_com_ind_tbl_convert_to_device(struct ena_com_dev * ena_dev)1301 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev)
1302 {
1303 struct ena_rss *rss = &ena_dev->rss;
1304 struct ena_com_io_sq *io_sq;
1305 u16 qid;
1306 int i;
1307
1308 for (i = 0; i < 1 << rss->tbl_log_size; i++) {
1309 qid = rss->host_rss_ind_tbl[i];
1310 if (qid >= ENA_TOTAL_NUM_QUEUES)
1311 return -EINVAL;
1312
1313 io_sq = &ena_dev->io_sq_queues[qid];
1314
1315 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX)
1316 return -EINVAL;
1317
1318 rss->rss_ind_tbl[i].cq_idx = io_sq->idx;
1319 }
1320
1321 return 0;
1322 }
1323
ena_com_update_intr_delay_resolution(struct ena_com_dev * ena_dev,u16 intr_delay_resolution)1324 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev,
1325 u16 intr_delay_resolution)
1326 {
1327 u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution;
1328
1329 if (unlikely(!intr_delay_resolution)) {
1330 netdev_err(ena_dev->net_device,
1331 "Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n");
1332 intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION;
1333 }
1334
1335 /* update Rx */
1336 ena_dev->intr_moder_rx_interval =
1337 ena_dev->intr_moder_rx_interval *
1338 prev_intr_delay_resolution /
1339 intr_delay_resolution;
1340
1341 /* update Tx */
1342 ena_dev->intr_moder_tx_interval =
1343 ena_dev->intr_moder_tx_interval *
1344 prev_intr_delay_resolution /
1345 intr_delay_resolution;
1346
1347 ena_dev->intr_delay_resolution = intr_delay_resolution;
1348 }
1349
1350 /*****************************************************************************/
1351 /******************************* API ******************************/
1352 /*****************************************************************************/
1353
ena_com_execute_admin_command(struct ena_com_admin_queue * admin_queue,struct ena_admin_aq_entry * cmd,size_t cmd_size,struct ena_admin_acq_entry * comp,size_t comp_size)1354 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
1355 struct ena_admin_aq_entry *cmd,
1356 size_t cmd_size,
1357 struct ena_admin_acq_entry *comp,
1358 size_t comp_size)
1359 {
1360 struct ena_comp_ctx *comp_ctx;
1361 int ret;
1362
1363 comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size,
1364 comp, comp_size);
1365 if (IS_ERR(comp_ctx)) {
1366 ret = PTR_ERR(comp_ctx);
1367 if (ret == -ENODEV)
1368 netdev_dbg(admin_queue->ena_dev->net_device,
1369 "Failed to submit command [%d]\n", ret);
1370 else
1371 netdev_err(admin_queue->ena_dev->net_device,
1372 "Failed to submit command [%d]\n", ret);
1373
1374 return ret;
1375 }
1376
1377 ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue);
1378 if (unlikely(ret)) {
1379 if (admin_queue->running_state)
1380 netdev_err(admin_queue->ena_dev->net_device,
1381 "Failed to process command. ret = %d\n", ret);
1382 else
1383 netdev_dbg(admin_queue->ena_dev->net_device,
1384 "Failed to process command. ret = %d\n", ret);
1385 }
1386 return ret;
1387 }
1388
ena_com_create_io_cq(struct ena_com_dev * ena_dev,struct ena_com_io_cq * io_cq)1389 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
1390 struct ena_com_io_cq *io_cq)
1391 {
1392 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1393 struct ena_admin_aq_create_cq_cmd create_cmd;
1394 struct ena_admin_acq_create_cq_resp_desc cmd_completion;
1395 int ret;
1396
1397 memset(&create_cmd, 0x0, sizeof(create_cmd));
1398
1399 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ;
1400
1401 create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) &
1402 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1403 create_cmd.cq_caps_1 |=
1404 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1405
1406 create_cmd.msix_vector = io_cq->msix_vector;
1407 create_cmd.cq_depth = io_cq->q_depth;
1408
1409 ret = ena_com_mem_addr_set(ena_dev,
1410 &create_cmd.cq_ba,
1411 io_cq->cdesc_addr.phys_addr);
1412 if (unlikely(ret)) {
1413 netdev_err(ena_dev->net_device, "Memory address set failed\n");
1414 return ret;
1415 }
1416
1417 ret = ena_com_execute_admin_command(admin_queue,
1418 (struct ena_admin_aq_entry *)&create_cmd,
1419 sizeof(create_cmd),
1420 (struct ena_admin_acq_entry *)&cmd_completion,
1421 sizeof(cmd_completion));
1422 if (unlikely(ret)) {
1423 netdev_err(ena_dev->net_device,
1424 "Failed to create IO CQ. error: %d\n", ret);
1425 return ret;
1426 }
1427
1428 io_cq->idx = cmd_completion.cq_idx;
1429
1430 io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1431 cmd_completion.cq_interrupt_unmask_register_offset);
1432
1433 if (cmd_completion.cq_head_db_register_offset)
1434 io_cq->cq_head_db_reg =
1435 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1436 cmd_completion.cq_head_db_register_offset);
1437
1438 if (cmd_completion.numa_node_register_offset)
1439 io_cq->numa_node_cfg_reg =
1440 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1441 cmd_completion.numa_node_register_offset);
1442
1443 netdev_dbg(ena_dev->net_device, "Created cq[%u], depth[%u]\n",
1444 io_cq->idx, io_cq->q_depth);
1445
1446 return ret;
1447 }
1448
ena_com_get_io_handlers(struct ena_com_dev * ena_dev,u16 qid,struct ena_com_io_sq ** io_sq,struct ena_com_io_cq ** io_cq)1449 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
1450 struct ena_com_io_sq **io_sq,
1451 struct ena_com_io_cq **io_cq)
1452 {
1453 if (qid >= ENA_TOTAL_NUM_QUEUES) {
1454 netdev_err(ena_dev->net_device,
1455 "Invalid queue number %d but the max is %d\n", qid,
1456 ENA_TOTAL_NUM_QUEUES);
1457 return -EINVAL;
1458 }
1459
1460 *io_sq = &ena_dev->io_sq_queues[qid];
1461 *io_cq = &ena_dev->io_cq_queues[qid];
1462
1463 return 0;
1464 }
1465
ena_com_abort_admin_commands(struct ena_com_dev * ena_dev)1466 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev)
1467 {
1468 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1469 struct ena_comp_ctx *comp_ctx;
1470 u16 i;
1471
1472 if (!admin_queue->comp_ctx)
1473 return;
1474
1475 for (i = 0; i < admin_queue->q_depth; i++) {
1476 comp_ctx = get_comp_ctxt(admin_queue, i, false);
1477 if (unlikely(!comp_ctx))
1478 break;
1479
1480 comp_ctx->status = ENA_CMD_ABORTED;
1481
1482 complete(&comp_ctx->wait_event);
1483 }
1484 }
1485
ena_com_wait_for_abort_completion(struct ena_com_dev * ena_dev)1486 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev)
1487 {
1488 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1489 unsigned long flags = 0;
1490 u32 exp = 0;
1491
1492 spin_lock_irqsave(&admin_queue->q_lock, flags);
1493 while (atomic_read(&admin_queue->outstanding_cmds) != 0) {
1494 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1495 ena_delay_exponential_backoff_us(exp++,
1496 ena_dev->ena_min_poll_delay_us);
1497 spin_lock_irqsave(&admin_queue->q_lock, flags);
1498 }
1499 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1500 }
1501
ena_com_destroy_io_cq(struct ena_com_dev * ena_dev,struct ena_com_io_cq * io_cq)1502 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
1503 struct ena_com_io_cq *io_cq)
1504 {
1505 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1506 struct ena_admin_aq_destroy_cq_cmd destroy_cmd;
1507 struct ena_admin_acq_destroy_cq_resp_desc destroy_resp;
1508 int ret;
1509
1510 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd));
1511
1512 destroy_cmd.cq_idx = io_cq->idx;
1513 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ;
1514
1515 ret = ena_com_execute_admin_command(admin_queue,
1516 (struct ena_admin_aq_entry *)&destroy_cmd,
1517 sizeof(destroy_cmd),
1518 (struct ena_admin_acq_entry *)&destroy_resp,
1519 sizeof(destroy_resp));
1520
1521 if (unlikely(ret && (ret != -ENODEV)))
1522 netdev_err(ena_dev->net_device,
1523 "Failed to destroy IO CQ. error: %d\n", ret);
1524
1525 return ret;
1526 }
1527
ena_com_get_admin_running_state(struct ena_com_dev * ena_dev)1528 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev)
1529 {
1530 return ena_dev->admin_queue.running_state;
1531 }
1532
ena_com_set_admin_running_state(struct ena_com_dev * ena_dev,bool state)1533 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state)
1534 {
1535 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1536 unsigned long flags = 0;
1537
1538 spin_lock_irqsave(&admin_queue->q_lock, flags);
1539 ena_dev->admin_queue.running_state = state;
1540 spin_unlock_irqrestore(&admin_queue->q_lock, flags);
1541 }
1542
ena_com_admin_aenq_enable(struct ena_com_dev * ena_dev)1543 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev)
1544 {
1545 u16 depth = ena_dev->aenq.q_depth;
1546
1547 WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n");
1548
1549 /* Init head_db to mark that all entries in the queue
1550 * are initially available
1551 */
1552 writel(depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
1553 }
1554
ena_com_set_aenq_config(struct ena_com_dev * ena_dev,u32 groups_flag)1555 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)
1556 {
1557 struct ena_com_admin_queue *admin_queue;
1558 struct ena_admin_set_feat_cmd cmd;
1559 struct ena_admin_set_feat_resp resp;
1560 struct ena_admin_get_feat_resp get_resp;
1561 int ret;
1562
1563 ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0);
1564 if (ret) {
1565 dev_info(ena_dev->dmadev, "Can't get aenq configuration\n");
1566 return ret;
1567 }
1568
1569 if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) {
1570 netdev_warn(ena_dev->net_device,
1571 "Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n",
1572 get_resp.u.aenq.supported_groups, groups_flag);
1573 return -EOPNOTSUPP;
1574 }
1575
1576 memset(&cmd, 0x0, sizeof(cmd));
1577 admin_queue = &ena_dev->admin_queue;
1578
1579 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
1580 cmd.aq_common_descriptor.flags = 0;
1581 cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG;
1582 cmd.u.aenq.enabled_groups = groups_flag;
1583
1584 ret = ena_com_execute_admin_command(admin_queue,
1585 (struct ena_admin_aq_entry *)&cmd,
1586 sizeof(cmd),
1587 (struct ena_admin_acq_entry *)&resp,
1588 sizeof(resp));
1589
1590 if (unlikely(ret))
1591 netdev_err(ena_dev->net_device,
1592 "Failed to config AENQ ret: %d\n", ret);
1593
1594 return ret;
1595 }
1596
ena_com_get_dma_width(struct ena_com_dev * ena_dev)1597 int ena_com_get_dma_width(struct ena_com_dev *ena_dev)
1598 {
1599 u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
1600 u32 width;
1601
1602 if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) {
1603 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n");
1604 return -ETIME;
1605 }
1606
1607 width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1608 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1609
1610 netdev_dbg(ena_dev->net_device, "ENA dma width: %d\n", width);
1611
1612 if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) {
1613 netdev_err(ena_dev->net_device, "DMA width illegal value: %d\n",
1614 width);
1615 return -EINVAL;
1616 }
1617
1618 ena_dev->dma_addr_bits = width;
1619
1620 return width;
1621 }
1622
ena_com_validate_version(struct ena_com_dev * ena_dev)1623 int ena_com_validate_version(struct ena_com_dev *ena_dev)
1624 {
1625 u32 ver;
1626 u32 ctrl_ver;
1627 u32 ctrl_ver_masked;
1628
1629 /* Make sure the ENA version and the controller version are at least
1630 * as the driver expects
1631 */
1632 ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF);
1633 ctrl_ver = ena_com_reg_bar_read32(ena_dev,
1634 ENA_REGS_CONTROLLER_VERSION_OFF);
1635
1636 if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) ||
1637 (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) {
1638 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n");
1639 return -ETIME;
1640 }
1641
1642 dev_info(ena_dev->dmadev, "ENA device version: %d.%d\n",
1643 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >>
1644 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT,
1645 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK);
1646
1647 dev_info(ena_dev->dmadev,
1648 "ENA controller version: %d.%d.%d implementation version %d\n",
1649 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) >>
1650 ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
1651 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) >>
1652 ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
1653 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
1654 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
1655 ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
1656
1657 ctrl_ver_masked =
1658 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
1659 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
1660 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
1661
1662 /* Validate the ctrl version without the implementation ID */
1663 if (ctrl_ver_masked < MIN_ENA_CTRL_VER) {
1664 netdev_err(ena_dev->net_device,
1665 "ENA ctrl version is lower than the minimal ctrl version the driver supports\n");
1666 return -1;
1667 }
1668
1669 return 0;
1670 }
1671
1672 static void
ena_com_free_ena_admin_queue_comp_ctx(struct ena_com_dev * ena_dev,struct ena_com_admin_queue * admin_queue)1673 ena_com_free_ena_admin_queue_comp_ctx(struct ena_com_dev *ena_dev,
1674 struct ena_com_admin_queue *admin_queue)
1675
1676 {
1677 if (!admin_queue->comp_ctx)
1678 return;
1679
1680 devm_kfree(ena_dev->dmadev, admin_queue->comp_ctx);
1681
1682 admin_queue->comp_ctx = NULL;
1683 }
1684
ena_com_admin_destroy(struct ena_com_dev * ena_dev)1685 void ena_com_admin_destroy(struct ena_com_dev *ena_dev)
1686 {
1687 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1688 struct ena_com_admin_cq *cq = &admin_queue->cq;
1689 struct ena_com_admin_sq *sq = &admin_queue->sq;
1690 struct ena_com_aenq *aenq = &ena_dev->aenq;
1691 u16 size;
1692
1693 ena_com_free_ena_admin_queue_comp_ctx(ena_dev, admin_queue);
1694
1695 size = ADMIN_SQ_SIZE(admin_queue->q_depth);
1696 if (sq->entries)
1697 dma_free_coherent(ena_dev->dmadev, size, sq->entries,
1698 sq->dma_addr);
1699 sq->entries = NULL;
1700
1701 size = ADMIN_CQ_SIZE(admin_queue->q_depth);
1702 if (cq->entries)
1703 dma_free_coherent(ena_dev->dmadev, size, cq->entries,
1704 cq->dma_addr);
1705 cq->entries = NULL;
1706
1707 size = ADMIN_AENQ_SIZE(aenq->q_depth);
1708 if (ena_dev->aenq.entries)
1709 dma_free_coherent(ena_dev->dmadev, size, aenq->entries,
1710 aenq->dma_addr);
1711 aenq->entries = NULL;
1712 }
1713
ena_com_set_admin_polling_mode(struct ena_com_dev * ena_dev,bool polling)1714 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling)
1715 {
1716 u32 mask_value = 0;
1717
1718 if (polling)
1719 mask_value = ENA_REGS_ADMIN_INTR_MASK;
1720
1721 writel(mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);
1722 ena_dev->admin_queue.polling = polling;
1723 }
1724
ena_com_set_admin_auto_polling_mode(struct ena_com_dev * ena_dev,bool polling)1725 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev,
1726 bool polling)
1727 {
1728 ena_dev->admin_queue.auto_polling = polling;
1729 }
1730
ena_com_mmio_reg_read_request_init(struct ena_com_dev * ena_dev)1731 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev)
1732 {
1733 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1734
1735 spin_lock_init(&mmio_read->lock);
1736 mmio_read->read_resp =
1737 dma_alloc_coherent(ena_dev->dmadev,
1738 sizeof(*mmio_read->read_resp),
1739 &mmio_read->read_resp_dma_addr, GFP_KERNEL);
1740 if (unlikely(!mmio_read->read_resp))
1741 goto err;
1742
1743 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
1744
1745 mmio_read->read_resp->req_id = 0x0;
1746 mmio_read->seq_num = 0x0;
1747 mmio_read->readless_supported = true;
1748
1749 return 0;
1750
1751 err:
1752
1753 return -ENOMEM;
1754 }
1755
ena_com_set_mmio_read_mode(struct ena_com_dev * ena_dev,bool readless_supported)1756 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported)
1757 {
1758 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1759
1760 mmio_read->readless_supported = readless_supported;
1761 }
1762
ena_com_mmio_reg_read_request_destroy(struct ena_com_dev * ena_dev)1763 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev)
1764 {
1765 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1766
1767 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1768 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1769
1770 dma_free_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp),
1771 mmio_read->read_resp, mmio_read->read_resp_dma_addr);
1772
1773 mmio_read->read_resp = NULL;
1774 }
1775
ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev * ena_dev)1776 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev)
1777 {
1778 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
1779 u32 addr_low, addr_high;
1780
1781 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr);
1782 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr);
1783
1784 writel(addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);
1785 writel(addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);
1786 }
1787
ena_com_admin_init(struct ena_com_dev * ena_dev,struct ena_aenq_handlers * aenq_handlers)1788 int ena_com_admin_init(struct ena_com_dev *ena_dev,
1789 struct ena_aenq_handlers *aenq_handlers)
1790 {
1791 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
1792 u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high;
1793 int ret;
1794
1795 dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
1796
1797 if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) {
1798 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n");
1799 return -ETIME;
1800 }
1801
1802 if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) {
1803 netdev_err(ena_dev->net_device,
1804 "Device isn't ready, abort com init\n");
1805 return -ENODEV;
1806 }
1807
1808 admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH;
1809
1810 admin_queue->q_dmadev = ena_dev->dmadev;
1811 admin_queue->polling = false;
1812 admin_queue->curr_cmd_id = 0;
1813
1814 atomic_set(&admin_queue->outstanding_cmds, 0);
1815
1816 spin_lock_init(&admin_queue->q_lock);
1817
1818 ret = ena_com_init_comp_ctxt(admin_queue);
1819 if (ret)
1820 goto error;
1821
1822 ret = ena_com_admin_init_sq(admin_queue);
1823 if (ret)
1824 goto error;
1825
1826 ret = ena_com_admin_init_cq(admin_queue);
1827 if (ret)
1828 goto error;
1829
1830 admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
1831 ENA_REGS_AQ_DB_OFF);
1832
1833 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr);
1834 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr);
1835
1836 writel(addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);
1837 writel(addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);
1838
1839 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr);
1840 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr);
1841
1842 writel(addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);
1843 writel(addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);
1844
1845 aq_caps = 0;
1846 aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
1847 aq_caps |= (sizeof(struct ena_admin_aq_entry) <<
1848 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
1849 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
1850
1851 acq_caps = 0;
1852 acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
1853 acq_caps |= (sizeof(struct ena_admin_acq_entry) <<
1854 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
1855 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
1856
1857 writel(aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);
1858 writel(acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);
1859 ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers);
1860 if (ret)
1861 goto error;
1862
1863 admin_queue->ena_dev = ena_dev;
1864 admin_queue->running_state = true;
1865
1866 return 0;
1867 error:
1868 ena_com_admin_destroy(ena_dev);
1869
1870 return ret;
1871 }
1872
ena_com_create_io_queue(struct ena_com_dev * ena_dev,struct ena_com_create_io_ctx * ctx)1873 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
1874 struct ena_com_create_io_ctx *ctx)
1875 {
1876 struct ena_com_io_sq *io_sq;
1877 struct ena_com_io_cq *io_cq;
1878 int ret;
1879
1880 if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) {
1881 netdev_err(ena_dev->net_device,
1882 "Qid (%d) is bigger than max num of queues (%d)\n",
1883 ctx->qid, ENA_TOTAL_NUM_QUEUES);
1884 return -EINVAL;
1885 }
1886
1887 io_sq = &ena_dev->io_sq_queues[ctx->qid];
1888 io_cq = &ena_dev->io_cq_queues[ctx->qid];
1889
1890 memset(io_sq, 0x0, sizeof(*io_sq));
1891 memset(io_cq, 0x0, sizeof(*io_cq));
1892
1893 /* Init CQ */
1894 io_cq->q_depth = ctx->queue_size;
1895 io_cq->direction = ctx->direction;
1896 io_cq->qid = ctx->qid;
1897
1898 io_cq->msix_vector = ctx->msix_vector;
1899
1900 io_sq->q_depth = ctx->queue_size;
1901 io_sq->direction = ctx->direction;
1902 io_sq->qid = ctx->qid;
1903
1904 io_sq->mem_queue_type = ctx->mem_queue_type;
1905
1906 if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX)
1907 /* header length is limited to 8 bits */
1908 io_sq->tx_max_header_size =
1909 min_t(u32, ena_dev->tx_max_header_size, SZ_256);
1910
1911 ret = ena_com_init_io_sq(ena_dev, ctx, io_sq);
1912 if (ret)
1913 goto error;
1914 ret = ena_com_init_io_cq(ena_dev, ctx, io_cq);
1915 if (ret)
1916 goto error;
1917
1918 ret = ena_com_create_io_cq(ena_dev, io_cq);
1919 if (ret)
1920 goto error;
1921
1922 ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx);
1923 if (ret)
1924 goto destroy_io_cq;
1925
1926 return 0;
1927
1928 destroy_io_cq:
1929 ena_com_destroy_io_cq(ena_dev, io_cq);
1930 error:
1931 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1932 return ret;
1933 }
1934
ena_com_destroy_io_queue(struct ena_com_dev * ena_dev,u16 qid)1935 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)
1936 {
1937 struct ena_com_io_sq *io_sq;
1938 struct ena_com_io_cq *io_cq;
1939
1940 if (qid >= ENA_TOTAL_NUM_QUEUES) {
1941 netdev_err(ena_dev->net_device,
1942 "Qid (%d) is bigger than max num of queues (%d)\n",
1943 qid, ENA_TOTAL_NUM_QUEUES);
1944 return;
1945 }
1946
1947 io_sq = &ena_dev->io_sq_queues[qid];
1948 io_cq = &ena_dev->io_cq_queues[qid];
1949
1950 ena_com_destroy_io_sq(ena_dev, io_sq);
1951 ena_com_destroy_io_cq(ena_dev, io_cq);
1952
1953 ena_com_io_queue_free(ena_dev, io_sq, io_cq);
1954 }
1955
ena_com_get_link_params(struct ena_com_dev * ena_dev,struct ena_admin_get_feat_resp * resp)1956 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
1957 struct ena_admin_get_feat_resp *resp)
1958 {
1959 return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0);
1960 }
1961
ena_com_get_dev_attr_feat(struct ena_com_dev * ena_dev,struct ena_com_dev_get_features_ctx * get_feat_ctx)1962 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
1963 struct ena_com_dev_get_features_ctx *get_feat_ctx)
1964 {
1965 struct ena_admin_get_feat_resp get_resp;
1966 int rc;
1967
1968 rc = ena_com_get_feature(ena_dev, &get_resp,
1969 ENA_ADMIN_DEVICE_ATTRIBUTES, 0);
1970 if (rc)
1971 return rc;
1972
1973 memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr,
1974 sizeof(get_resp.u.dev_attr));
1975
1976 ena_dev->supported_features = get_resp.u.dev_attr.supported_features;
1977
1978 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) {
1979 rc = ena_com_get_feature(ena_dev, &get_resp,
1980 ENA_ADMIN_MAX_QUEUES_EXT,
1981 ENA_FEATURE_MAX_QUEUE_EXT_VER);
1982 if (rc)
1983 return rc;
1984
1985 if (get_resp.u.max_queue_ext.version !=
1986 ENA_FEATURE_MAX_QUEUE_EXT_VER)
1987 return -EINVAL;
1988
1989 memcpy(&get_feat_ctx->max_queue_ext, &get_resp.u.max_queue_ext,
1990 sizeof(get_resp.u.max_queue_ext));
1991 ena_dev->tx_max_header_size =
1992 get_resp.u.max_queue_ext.max_queue_ext.max_tx_header_size;
1993 } else {
1994 rc = ena_com_get_feature(ena_dev, &get_resp,
1995 ENA_ADMIN_MAX_QUEUES_NUM, 0);
1996 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue,
1997 sizeof(get_resp.u.max_queue));
1998 ena_dev->tx_max_header_size =
1999 get_resp.u.max_queue.max_header_size;
2000
2001 if (rc)
2002 return rc;
2003 }
2004
2005 rc = ena_com_get_feature(ena_dev, &get_resp,
2006 ENA_ADMIN_AENQ_CONFIG, 0);
2007 if (rc)
2008 return rc;
2009
2010 memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq,
2011 sizeof(get_resp.u.aenq));
2012
2013 rc = ena_com_get_feature(ena_dev, &get_resp,
2014 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
2015 if (rc)
2016 return rc;
2017
2018 memcpy(&get_feat_ctx->offload, &get_resp.u.offload,
2019 sizeof(get_resp.u.offload));
2020
2021 /* Driver hints isn't mandatory admin command. So in case the
2022 * command isn't supported set driver hints to 0
2023 */
2024 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS, 0);
2025
2026 if (!rc)
2027 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints,
2028 sizeof(get_resp.u.hw_hints));
2029 else if (rc == -EOPNOTSUPP)
2030 memset(&get_feat_ctx->hw_hints, 0x0,
2031 sizeof(get_feat_ctx->hw_hints));
2032 else
2033 return rc;
2034
2035 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ, 0);
2036 if (!rc)
2037 memcpy(&get_feat_ctx->llq, &get_resp.u.llq,
2038 sizeof(get_resp.u.llq));
2039 else if (rc == -EOPNOTSUPP)
2040 memset(&get_feat_ctx->llq, 0x0, sizeof(get_feat_ctx->llq));
2041 else
2042 return rc;
2043
2044 return 0;
2045 }
2046
ena_com_admin_q_comp_intr_handler(struct ena_com_dev * ena_dev)2047 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev)
2048 {
2049 ena_com_handle_admin_completion(&ena_dev->admin_queue);
2050 }
2051
2052 /* ena_handle_specific_aenq_event:
2053 * return the handler that is relevant to the specific event group
2054 */
ena_com_get_specific_aenq_cb(struct ena_com_dev * ena_dev,u16 group)2055 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *ena_dev,
2056 u16 group)
2057 {
2058 struct ena_aenq_handlers *aenq_handlers = ena_dev->aenq.aenq_handlers;
2059
2060 if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group])
2061 return aenq_handlers->handlers[group];
2062
2063 return aenq_handlers->unimplemented_handler;
2064 }
2065
2066 /* ena_aenq_intr_handler:
2067 * handles the aenq incoming events.
2068 * pop events from the queue and apply the specific handler
2069 */
ena_com_aenq_intr_handler(struct ena_com_dev * ena_dev,void * data)2070 void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data)
2071 {
2072 struct ena_admin_aenq_entry *aenq_e;
2073 struct ena_admin_aenq_common_desc *aenq_common;
2074 struct ena_com_aenq *aenq = &ena_dev->aenq;
2075 u64 timestamp;
2076 ena_aenq_handler handler_cb;
2077 u16 masked_head, processed = 0;
2078 u8 phase;
2079
2080 masked_head = aenq->head & (aenq->q_depth - 1);
2081 phase = aenq->phase;
2082 aenq_e = &aenq->entries[masked_head]; /* Get first entry */
2083 aenq_common = &aenq_e->aenq_common_desc;
2084
2085 /* Go over all the events */
2086 while ((READ_ONCE(aenq_common->flags) &
2087 ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
2088 /* Make sure the phase bit (ownership) is as expected before
2089 * reading the rest of the descriptor.
2090 */
2091 dma_rmb();
2092
2093 timestamp = (u64)aenq_common->timestamp_low |
2094 ((u64)aenq_common->timestamp_high << 32);
2095
2096 netdev_dbg(ena_dev->net_device,
2097 "AENQ! Group[%x] Syndrome[%x] timestamp: [%llus]\n",
2098 aenq_common->group, aenq_common->syndrome, timestamp);
2099
2100 /* Handle specific event*/
2101 handler_cb = ena_com_get_specific_aenq_cb(ena_dev,
2102 aenq_common->group);
2103 handler_cb(data, aenq_e); /* call the actual event handler*/
2104
2105 /* Get next event entry */
2106 masked_head++;
2107 processed++;
2108
2109 if (unlikely(masked_head == aenq->q_depth)) {
2110 masked_head = 0;
2111 phase = !phase;
2112 }
2113 aenq_e = &aenq->entries[masked_head];
2114 aenq_common = &aenq_e->aenq_common_desc;
2115 }
2116
2117 aenq->head += processed;
2118 aenq->phase = phase;
2119
2120 /* Don't update aenq doorbell if there weren't any processed events */
2121 if (!processed)
2122 return;
2123
2124 /* write the aenq doorbell after all AENQ descriptors were read */
2125 mb();
2126 writel_relaxed((u32)aenq->head,
2127 ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);
2128 }
2129
ena_com_dev_reset(struct ena_com_dev * ena_dev,enum ena_regs_reset_reason_types reset_reason)2130 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
2131 enum ena_regs_reset_reason_types reset_reason)
2132 {
2133 u32 stat, timeout, cap, reset_val;
2134 int rc;
2135
2136 stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF);
2137 cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF);
2138
2139 if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) ||
2140 (cap == ENA_MMIO_READ_TIMEOUT))) {
2141 netdev_err(ena_dev->net_device, "Reg read32 timeout occurred\n");
2142 return -ETIME;
2143 }
2144
2145 if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) {
2146 netdev_err(ena_dev->net_device,
2147 "Device isn't ready, can't reset device\n");
2148 return -EINVAL;
2149 }
2150
2151 timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
2152 ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
2153 if (timeout == 0) {
2154 netdev_err(ena_dev->net_device, "Invalid timeout value\n");
2155 return -EINVAL;
2156 }
2157
2158 /* start reset */
2159 reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK;
2160 reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
2161 ENA_REGS_DEV_CTL_RESET_REASON_MASK;
2162 writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2163
2164 /* Write again the MMIO read request address */
2165 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev);
2166
2167 rc = wait_for_reset_state(ena_dev, timeout,
2168 ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
2169 if (rc != 0) {
2170 netdev_err(ena_dev->net_device,
2171 "Reset indication didn't turn on\n");
2172 return rc;
2173 }
2174
2175 /* reset done */
2176 writel(0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);
2177 rc = wait_for_reset_state(ena_dev, timeout, 0);
2178 if (rc != 0) {
2179 netdev_err(ena_dev->net_device,
2180 "Reset indication didn't turn off\n");
2181 return rc;
2182 }
2183
2184 timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
2185 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
2186 if (timeout)
2187 /* the resolution of timeout reg is 100ms */
2188 ena_dev->admin_queue.completion_timeout = timeout * 100000;
2189 else
2190 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US;
2191
2192 return 0;
2193 }
2194
ena_get_dev_stats(struct ena_com_dev * ena_dev,struct ena_com_stats_ctx * ctx,enum ena_admin_get_stats_type type)2195 static int ena_get_dev_stats(struct ena_com_dev *ena_dev,
2196 struct ena_com_stats_ctx *ctx,
2197 enum ena_admin_get_stats_type type)
2198 {
2199 struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd;
2200 struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp;
2201 struct ena_com_admin_queue *admin_queue;
2202 int ret;
2203
2204 admin_queue = &ena_dev->admin_queue;
2205
2206 get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS;
2207 get_cmd->aq_common_descriptor.flags = 0;
2208 get_cmd->type = type;
2209
2210 ret = ena_com_execute_admin_command(admin_queue,
2211 (struct ena_admin_aq_entry *)get_cmd,
2212 sizeof(*get_cmd),
2213 (struct ena_admin_acq_entry *)get_resp,
2214 sizeof(*get_resp));
2215
2216 if (unlikely(ret))
2217 netdev_err(ena_dev->net_device,
2218 "Failed to get stats. error: %d\n", ret);
2219
2220 return ret;
2221 }
2222
ena_com_get_eni_stats(struct ena_com_dev * ena_dev,struct ena_admin_eni_stats * stats)2223 int ena_com_get_eni_stats(struct ena_com_dev *ena_dev,
2224 struct ena_admin_eni_stats *stats)
2225 {
2226 struct ena_com_stats_ctx ctx;
2227 int ret;
2228
2229 memset(&ctx, 0x0, sizeof(ctx));
2230 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_ENI);
2231 if (likely(ret == 0))
2232 memcpy(stats, &ctx.get_resp.u.eni_stats,
2233 sizeof(ctx.get_resp.u.eni_stats));
2234
2235 return ret;
2236 }
2237
ena_com_get_dev_basic_stats(struct ena_com_dev * ena_dev,struct ena_admin_basic_stats * stats)2238 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
2239 struct ena_admin_basic_stats *stats)
2240 {
2241 struct ena_com_stats_ctx ctx;
2242 int ret;
2243
2244 memset(&ctx, 0x0, sizeof(ctx));
2245 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC);
2246 if (likely(ret == 0))
2247 memcpy(stats, &ctx.get_resp.u.basic_stats,
2248 sizeof(ctx.get_resp.u.basic_stats));
2249
2250 return ret;
2251 }
2252
ena_com_set_dev_mtu(struct ena_com_dev * ena_dev,u32 mtu)2253 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, u32 mtu)
2254 {
2255 struct ena_com_admin_queue *admin_queue;
2256 struct ena_admin_set_feat_cmd cmd;
2257 struct ena_admin_set_feat_resp resp;
2258 int ret;
2259
2260 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) {
2261 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n",
2262 ENA_ADMIN_MTU);
2263 return -EOPNOTSUPP;
2264 }
2265
2266 memset(&cmd, 0x0, sizeof(cmd));
2267 admin_queue = &ena_dev->admin_queue;
2268
2269 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2270 cmd.aq_common_descriptor.flags = 0;
2271 cmd.feat_common.feature_id = ENA_ADMIN_MTU;
2272 cmd.u.mtu.mtu = mtu;
2273
2274 ret = ena_com_execute_admin_command(admin_queue,
2275 (struct ena_admin_aq_entry *)&cmd,
2276 sizeof(cmd),
2277 (struct ena_admin_acq_entry *)&resp,
2278 sizeof(resp));
2279
2280 if (unlikely(ret))
2281 netdev_err(ena_dev->net_device,
2282 "Failed to set mtu %d. error: %d\n", mtu, ret);
2283
2284 return ret;
2285 }
2286
ena_com_get_offload_settings(struct ena_com_dev * ena_dev,struct ena_admin_feature_offload_desc * offload)2287 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
2288 struct ena_admin_feature_offload_desc *offload)
2289 {
2290 int ret;
2291 struct ena_admin_get_feat_resp resp;
2292
2293 ret = ena_com_get_feature(ena_dev, &resp,
2294 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0);
2295 if (unlikely(ret)) {
2296 netdev_err(ena_dev->net_device,
2297 "Failed to get offload capabilities %d\n", ret);
2298 return ret;
2299 }
2300
2301 memcpy(offload, &resp.u.offload, sizeof(resp.u.offload));
2302
2303 return 0;
2304 }
2305
ena_com_set_hash_function(struct ena_com_dev * ena_dev)2306 int ena_com_set_hash_function(struct ena_com_dev *ena_dev)
2307 {
2308 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2309 struct ena_rss *rss = &ena_dev->rss;
2310 struct ena_admin_set_feat_cmd cmd;
2311 struct ena_admin_set_feat_resp resp;
2312 struct ena_admin_get_feat_resp get_resp;
2313 int ret;
2314
2315 if (!ena_com_check_supported_feature_id(ena_dev,
2316 ENA_ADMIN_RSS_HASH_FUNCTION)) {
2317 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n",
2318 ENA_ADMIN_RSS_HASH_FUNCTION);
2319 return -EOPNOTSUPP;
2320 }
2321
2322 /* Validate hash function is supported */
2323 ret = ena_com_get_feature(ena_dev, &get_resp,
2324 ENA_ADMIN_RSS_HASH_FUNCTION, 0);
2325 if (unlikely(ret))
2326 return ret;
2327
2328 if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) {
2329 netdev_err(ena_dev->net_device,
2330 "Func hash %d isn't supported by device, abort\n",
2331 rss->hash_func);
2332 return -EOPNOTSUPP;
2333 }
2334
2335 memset(&cmd, 0x0, sizeof(cmd));
2336
2337 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2338 cmd.aq_common_descriptor.flags =
2339 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2340 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION;
2341 cmd.u.flow_hash_func.init_val = rss->hash_init_val;
2342 cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func;
2343
2344 ret = ena_com_mem_addr_set(ena_dev,
2345 &cmd.control_buffer.address,
2346 rss->hash_key_dma_addr);
2347 if (unlikely(ret)) {
2348 netdev_err(ena_dev->net_device, "Memory address set failed\n");
2349 return ret;
2350 }
2351
2352 cmd.control_buffer.length = sizeof(*rss->hash_key);
2353
2354 ret = ena_com_execute_admin_command(admin_queue,
2355 (struct ena_admin_aq_entry *)&cmd,
2356 sizeof(cmd),
2357 (struct ena_admin_acq_entry *)&resp,
2358 sizeof(resp));
2359 if (unlikely(ret)) {
2360 netdev_err(ena_dev->net_device,
2361 "Failed to set hash function %d. error: %d\n",
2362 rss->hash_func, ret);
2363 return -EINVAL;
2364 }
2365
2366 return 0;
2367 }
2368
ena_com_fill_hash_function(struct ena_com_dev * ena_dev,enum ena_admin_hash_functions func,const u8 * key,u16 key_len,u32 init_val)2369 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
2370 enum ena_admin_hash_functions func,
2371 const u8 *key, u16 key_len, u32 init_val)
2372 {
2373 struct ena_admin_feature_rss_flow_hash_control *hash_key;
2374 struct ena_admin_get_feat_resp get_resp;
2375 enum ena_admin_hash_functions old_func;
2376 struct ena_rss *rss = &ena_dev->rss;
2377 int rc;
2378
2379 hash_key = rss->hash_key;
2380
2381 /* Make sure size is a mult of DWs */
2382 if (unlikely(key_len & 0x3))
2383 return -EINVAL;
2384
2385 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2386 ENA_ADMIN_RSS_HASH_FUNCTION,
2387 rss->hash_key_dma_addr,
2388 sizeof(*rss->hash_key), 0);
2389 if (unlikely(rc))
2390 return rc;
2391
2392 if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) {
2393 netdev_err(ena_dev->net_device,
2394 "Flow hash function %d isn't supported\n", func);
2395 return -EOPNOTSUPP;
2396 }
2397
2398 if ((func == ENA_ADMIN_TOEPLITZ) && key) {
2399 if (key_len != sizeof(hash_key->key)) {
2400 netdev_err(ena_dev->net_device,
2401 "key len (%u) doesn't equal the supported size (%zu)\n",
2402 key_len, sizeof(hash_key->key));
2403 return -EINVAL;
2404 }
2405 memcpy(hash_key->key, key, key_len);
2406 hash_key->key_parts = key_len / sizeof(hash_key->key[0]);
2407 }
2408
2409 rss->hash_init_val = init_val;
2410 old_func = rss->hash_func;
2411 rss->hash_func = func;
2412 rc = ena_com_set_hash_function(ena_dev);
2413
2414 /* Restore the old function */
2415 if (unlikely(rc))
2416 rss->hash_func = old_func;
2417
2418 return rc;
2419 }
2420
ena_com_get_hash_function(struct ena_com_dev * ena_dev,enum ena_admin_hash_functions * func)2421 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
2422 enum ena_admin_hash_functions *func)
2423 {
2424 struct ena_rss *rss = &ena_dev->rss;
2425 struct ena_admin_get_feat_resp get_resp;
2426 int rc;
2427
2428 if (unlikely(!func))
2429 return -EINVAL;
2430
2431 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2432 ENA_ADMIN_RSS_HASH_FUNCTION,
2433 rss->hash_key_dma_addr,
2434 sizeof(*rss->hash_key), 0);
2435 if (unlikely(rc))
2436 return rc;
2437
2438 /* ffs() returns 1 in case the lsb is set */
2439 rss->hash_func = ffs(get_resp.u.flow_hash_func.selected_func);
2440 if (rss->hash_func)
2441 rss->hash_func--;
2442
2443 *func = rss->hash_func;
2444
2445 return 0;
2446 }
2447
ena_com_get_hash_key(struct ena_com_dev * ena_dev,u8 * key)2448 int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key)
2449 {
2450 struct ena_admin_feature_rss_flow_hash_control *hash_key =
2451 ena_dev->rss.hash_key;
2452
2453 if (key)
2454 memcpy(key, hash_key->key,
2455 (size_t)(hash_key->key_parts) * sizeof(hash_key->key[0]));
2456
2457 return 0;
2458 }
2459
ena_com_get_hash_ctrl(struct ena_com_dev * ena_dev,enum ena_admin_flow_hash_proto proto,u16 * fields)2460 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
2461 enum ena_admin_flow_hash_proto proto,
2462 u16 *fields)
2463 {
2464 struct ena_rss *rss = &ena_dev->rss;
2465 struct ena_admin_get_feat_resp get_resp;
2466 int rc;
2467
2468 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2469 ENA_ADMIN_RSS_HASH_INPUT,
2470 rss->hash_ctrl_dma_addr,
2471 sizeof(*rss->hash_ctrl), 0);
2472 if (unlikely(rc))
2473 return rc;
2474
2475 if (fields)
2476 *fields = rss->hash_ctrl->selected_fields[proto].fields;
2477
2478 return 0;
2479 }
2480
ena_com_set_hash_ctrl(struct ena_com_dev * ena_dev)2481 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev)
2482 {
2483 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2484 struct ena_rss *rss = &ena_dev->rss;
2485 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2486 struct ena_admin_set_feat_cmd cmd;
2487 struct ena_admin_set_feat_resp resp;
2488 int ret;
2489
2490 if (!ena_com_check_supported_feature_id(ena_dev,
2491 ENA_ADMIN_RSS_HASH_INPUT)) {
2492 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n",
2493 ENA_ADMIN_RSS_HASH_INPUT);
2494 return -EOPNOTSUPP;
2495 }
2496
2497 memset(&cmd, 0x0, sizeof(cmd));
2498
2499 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2500 cmd.aq_common_descriptor.flags =
2501 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2502 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT;
2503 cmd.u.flow_hash_input.enabled_input_sort =
2504 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK |
2505 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
2506
2507 ret = ena_com_mem_addr_set(ena_dev,
2508 &cmd.control_buffer.address,
2509 rss->hash_ctrl_dma_addr);
2510 if (unlikely(ret)) {
2511 netdev_err(ena_dev->net_device, "Memory address set failed\n");
2512 return ret;
2513 }
2514 cmd.control_buffer.length = sizeof(*hash_ctrl);
2515
2516 ret = ena_com_execute_admin_command(admin_queue,
2517 (struct ena_admin_aq_entry *)&cmd,
2518 sizeof(cmd),
2519 (struct ena_admin_acq_entry *)&resp,
2520 sizeof(resp));
2521 if (unlikely(ret))
2522 netdev_err(ena_dev->net_device,
2523 "Failed to set hash input. error: %d\n", ret);
2524
2525 return ret;
2526 }
2527
ena_com_set_default_hash_ctrl(struct ena_com_dev * ena_dev)2528 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev)
2529 {
2530 struct ena_rss *rss = &ena_dev->rss;
2531 struct ena_admin_feature_rss_hash_control *hash_ctrl =
2532 rss->hash_ctrl;
2533 u16 available_fields = 0;
2534 int rc, i;
2535
2536 /* Get the supported hash input */
2537 rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2538 if (unlikely(rc))
2539 return rc;
2540
2541 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields =
2542 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2543 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2544
2545 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields =
2546 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2547 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2548
2549 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields =
2550 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2551 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2552
2553 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields =
2554 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA |
2555 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP;
2556
2557 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields =
2558 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2559
2560 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields =
2561 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2562
2563 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields =
2564 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA;
2565
2566 hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields =
2567 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA;
2568
2569 for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) {
2570 available_fields = hash_ctrl->selected_fields[i].fields &
2571 hash_ctrl->supported_fields[i].fields;
2572 if (available_fields != hash_ctrl->selected_fields[i].fields) {
2573 netdev_err(ena_dev->net_device,
2574 "Hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n",
2575 i, hash_ctrl->supported_fields[i].fields,
2576 hash_ctrl->selected_fields[i].fields);
2577 return -EOPNOTSUPP;
2578 }
2579 }
2580
2581 rc = ena_com_set_hash_ctrl(ena_dev);
2582
2583 /* In case of failure, restore the old hash ctrl */
2584 if (unlikely(rc))
2585 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2586
2587 return rc;
2588 }
2589
ena_com_fill_hash_ctrl(struct ena_com_dev * ena_dev,enum ena_admin_flow_hash_proto proto,u16 hash_fields)2590 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
2591 enum ena_admin_flow_hash_proto proto,
2592 u16 hash_fields)
2593 {
2594 struct ena_rss *rss = &ena_dev->rss;
2595 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl;
2596 u16 supported_fields;
2597 int rc;
2598
2599 if (proto >= ENA_ADMIN_RSS_PROTO_NUM) {
2600 netdev_err(ena_dev->net_device, "Invalid proto num (%u)\n",
2601 proto);
2602 return -EINVAL;
2603 }
2604
2605 /* Get the ctrl table */
2606 rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL);
2607 if (unlikely(rc))
2608 return rc;
2609
2610 /* Make sure all the fields are supported */
2611 supported_fields = hash_ctrl->supported_fields[proto].fields;
2612 if ((hash_fields & supported_fields) != hash_fields) {
2613 netdev_err(ena_dev->net_device,
2614 "Proto %d doesn't support the required fields %x. supports only: %x\n",
2615 proto, hash_fields, supported_fields);
2616 }
2617
2618 hash_ctrl->selected_fields[proto].fields = hash_fields;
2619
2620 rc = ena_com_set_hash_ctrl(ena_dev);
2621
2622 /* In case of failure, restore the old hash ctrl */
2623 if (unlikely(rc))
2624 ena_com_get_hash_ctrl(ena_dev, 0, NULL);
2625
2626 return 0;
2627 }
2628
ena_com_indirect_table_fill_entry(struct ena_com_dev * ena_dev,u16 entry_idx,u16 entry_value)2629 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
2630 u16 entry_idx, u16 entry_value)
2631 {
2632 struct ena_rss *rss = &ena_dev->rss;
2633
2634 if (unlikely(entry_idx >= (1 << rss->tbl_log_size)))
2635 return -EINVAL;
2636
2637 if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES)))
2638 return -EINVAL;
2639
2640 rss->host_rss_ind_tbl[entry_idx] = entry_value;
2641
2642 return 0;
2643 }
2644
ena_com_indirect_table_set(struct ena_com_dev * ena_dev)2645 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev)
2646 {
2647 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue;
2648 struct ena_rss *rss = &ena_dev->rss;
2649 struct ena_admin_set_feat_cmd cmd;
2650 struct ena_admin_set_feat_resp resp;
2651 int ret;
2652
2653 if (!ena_com_check_supported_feature_id(
2654 ena_dev, ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG)) {
2655 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n",
2656 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG);
2657 return -EOPNOTSUPP;
2658 }
2659
2660 ret = ena_com_ind_tbl_convert_to_device(ena_dev);
2661 if (ret) {
2662 netdev_err(ena_dev->net_device,
2663 "Failed to convert host indirection table to device table\n");
2664 return ret;
2665 }
2666
2667 memset(&cmd, 0x0, sizeof(cmd));
2668
2669 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2670 cmd.aq_common_descriptor.flags =
2671 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
2672 cmd.feat_common.feature_id = ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG;
2673 cmd.u.ind_table.size = rss->tbl_log_size;
2674 cmd.u.ind_table.inline_index = 0xFFFFFFFF;
2675
2676 ret = ena_com_mem_addr_set(ena_dev,
2677 &cmd.control_buffer.address,
2678 rss->rss_ind_tbl_dma_addr);
2679 if (unlikely(ret)) {
2680 netdev_err(ena_dev->net_device, "Memory address set failed\n");
2681 return ret;
2682 }
2683
2684 cmd.control_buffer.length = (1ULL << rss->tbl_log_size) *
2685 sizeof(struct ena_admin_rss_ind_table_entry);
2686
2687 ret = ena_com_execute_admin_command(admin_queue,
2688 (struct ena_admin_aq_entry *)&cmd,
2689 sizeof(cmd),
2690 (struct ena_admin_acq_entry *)&resp,
2691 sizeof(resp));
2692
2693 if (unlikely(ret))
2694 netdev_err(ena_dev->net_device,
2695 "Failed to set indirect table. error: %d\n", ret);
2696
2697 return ret;
2698 }
2699
ena_com_indirect_table_get(struct ena_com_dev * ena_dev,u32 * ind_tbl)2700 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl)
2701 {
2702 struct ena_rss *rss = &ena_dev->rss;
2703 struct ena_admin_get_feat_resp get_resp;
2704 u32 tbl_size;
2705 int i, rc;
2706
2707 tbl_size = (1ULL << rss->tbl_log_size) *
2708 sizeof(struct ena_admin_rss_ind_table_entry);
2709
2710 rc = ena_com_get_feature_ex(ena_dev, &get_resp,
2711 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG,
2712 rss->rss_ind_tbl_dma_addr,
2713 tbl_size, 0);
2714 if (unlikely(rc))
2715 return rc;
2716
2717 if (!ind_tbl)
2718 return 0;
2719
2720 for (i = 0; i < (1 << rss->tbl_log_size); i++)
2721 ind_tbl[i] = rss->host_rss_ind_tbl[i];
2722
2723 return 0;
2724 }
2725
ena_com_rss_init(struct ena_com_dev * ena_dev,u16 indr_tbl_log_size)2726 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size)
2727 {
2728 int rc;
2729
2730 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2731
2732 rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size);
2733 if (unlikely(rc))
2734 goto err_indr_tbl;
2735
2736 /* The following function might return unsupported in case the
2737 * device doesn't support setting the key / hash function. We can safely
2738 * ignore this error and have indirection table support only.
2739 */
2740 rc = ena_com_hash_key_allocate(ena_dev);
2741 if (likely(!rc))
2742 ena_com_hash_key_fill_default_key(ena_dev);
2743 else if (rc != -EOPNOTSUPP)
2744 goto err_hash_key;
2745
2746 rc = ena_com_hash_ctrl_init(ena_dev);
2747 if (unlikely(rc))
2748 goto err_hash_ctrl;
2749
2750 return 0;
2751
2752 err_hash_ctrl:
2753 ena_com_hash_key_destroy(ena_dev);
2754 err_hash_key:
2755 ena_com_indirect_table_destroy(ena_dev);
2756 err_indr_tbl:
2757
2758 return rc;
2759 }
2760
ena_com_rss_destroy(struct ena_com_dev * ena_dev)2761 void ena_com_rss_destroy(struct ena_com_dev *ena_dev)
2762 {
2763 ena_com_indirect_table_destroy(ena_dev);
2764 ena_com_hash_key_destroy(ena_dev);
2765 ena_com_hash_ctrl_destroy(ena_dev);
2766
2767 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss));
2768 }
2769
ena_com_allocate_host_info(struct ena_com_dev * ena_dev)2770 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev)
2771 {
2772 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2773
2774 host_attr->host_info =
2775 dma_alloc_coherent(ena_dev->dmadev, SZ_4K,
2776 &host_attr->host_info_dma_addr, GFP_KERNEL);
2777 if (unlikely(!host_attr->host_info))
2778 return -ENOMEM;
2779
2780 host_attr->host_info->ena_spec_version = ((ENA_COMMON_SPEC_VERSION_MAJOR <<
2781 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) |
2782 (ENA_COMMON_SPEC_VERSION_MINOR));
2783
2784 return 0;
2785 }
2786
ena_com_allocate_debug_area(struct ena_com_dev * ena_dev,u32 debug_area_size)2787 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
2788 u32 debug_area_size)
2789 {
2790 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2791
2792 host_attr->debug_area_virt_addr =
2793 dma_alloc_coherent(ena_dev->dmadev, debug_area_size,
2794 &host_attr->debug_area_dma_addr, GFP_KERNEL);
2795 if (unlikely(!host_attr->debug_area_virt_addr)) {
2796 host_attr->debug_area_size = 0;
2797 return -ENOMEM;
2798 }
2799
2800 host_attr->debug_area_size = debug_area_size;
2801
2802 return 0;
2803 }
2804
ena_com_delete_host_info(struct ena_com_dev * ena_dev)2805 void ena_com_delete_host_info(struct ena_com_dev *ena_dev)
2806 {
2807 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2808
2809 if (host_attr->host_info) {
2810 dma_free_coherent(ena_dev->dmadev, SZ_4K, host_attr->host_info,
2811 host_attr->host_info_dma_addr);
2812 host_attr->host_info = NULL;
2813 }
2814 }
2815
ena_com_delete_debug_area(struct ena_com_dev * ena_dev)2816 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev)
2817 {
2818 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2819
2820 if (host_attr->debug_area_virt_addr) {
2821 dma_free_coherent(ena_dev->dmadev, host_attr->debug_area_size,
2822 host_attr->debug_area_virt_addr,
2823 host_attr->debug_area_dma_addr);
2824 host_attr->debug_area_virt_addr = NULL;
2825 }
2826 }
2827
ena_com_set_host_attributes(struct ena_com_dev * ena_dev)2828 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev)
2829 {
2830 struct ena_host_attribute *host_attr = &ena_dev->host_attr;
2831 struct ena_com_admin_queue *admin_queue;
2832 struct ena_admin_set_feat_cmd cmd;
2833 struct ena_admin_set_feat_resp resp;
2834
2835 int ret;
2836
2837 /* Host attribute config is called before ena_com_get_dev_attr_feat
2838 * so ena_com can't check if the feature is supported.
2839 */
2840
2841 memset(&cmd, 0x0, sizeof(cmd));
2842 admin_queue = &ena_dev->admin_queue;
2843
2844 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE;
2845 cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG;
2846
2847 ret = ena_com_mem_addr_set(ena_dev,
2848 &cmd.u.host_attr.debug_ba,
2849 host_attr->debug_area_dma_addr);
2850 if (unlikely(ret)) {
2851 netdev_err(ena_dev->net_device, "Memory address set failed\n");
2852 return ret;
2853 }
2854
2855 ret = ena_com_mem_addr_set(ena_dev,
2856 &cmd.u.host_attr.os_info_ba,
2857 host_attr->host_info_dma_addr);
2858 if (unlikely(ret)) {
2859 netdev_err(ena_dev->net_device, "Memory address set failed\n");
2860 return ret;
2861 }
2862
2863 cmd.u.host_attr.debug_area_size = host_attr->debug_area_size;
2864
2865 ret = ena_com_execute_admin_command(admin_queue,
2866 (struct ena_admin_aq_entry *)&cmd,
2867 sizeof(cmd),
2868 (struct ena_admin_acq_entry *)&resp,
2869 sizeof(resp));
2870
2871 if (unlikely(ret))
2872 netdev_err(ena_dev->net_device,
2873 "Failed to set host attributes: %d\n", ret);
2874
2875 return ret;
2876 }
2877
2878 /* Interrupt moderation */
ena_com_interrupt_moderation_supported(struct ena_com_dev * ena_dev)2879 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev)
2880 {
2881 return ena_com_check_supported_feature_id(ena_dev,
2882 ENA_ADMIN_INTERRUPT_MODERATION);
2883 }
2884
ena_com_update_nonadaptive_moderation_interval(struct ena_com_dev * ena_dev,u32 coalesce_usecs,u32 intr_delay_resolution,u32 * intr_moder_interval)2885 static int ena_com_update_nonadaptive_moderation_interval(struct ena_com_dev *ena_dev,
2886 u32 coalesce_usecs,
2887 u32 intr_delay_resolution,
2888 u32 *intr_moder_interval)
2889 {
2890 if (!intr_delay_resolution) {
2891 netdev_err(ena_dev->net_device,
2892 "Illegal interrupt delay granularity value\n");
2893 return -EFAULT;
2894 }
2895
2896 *intr_moder_interval = coalesce_usecs / intr_delay_resolution;
2897
2898 return 0;
2899 }
2900
ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev * ena_dev,u32 tx_coalesce_usecs)2901 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
2902 u32 tx_coalesce_usecs)
2903 {
2904 return ena_com_update_nonadaptive_moderation_interval(ena_dev,
2905 tx_coalesce_usecs,
2906 ena_dev->intr_delay_resolution,
2907 &ena_dev->intr_moder_tx_interval);
2908 }
2909
ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev * ena_dev,u32 rx_coalesce_usecs)2910 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
2911 u32 rx_coalesce_usecs)
2912 {
2913 return ena_com_update_nonadaptive_moderation_interval(ena_dev,
2914 rx_coalesce_usecs,
2915 ena_dev->intr_delay_resolution,
2916 &ena_dev->intr_moder_rx_interval);
2917 }
2918
ena_com_init_interrupt_moderation(struct ena_com_dev * ena_dev)2919 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev)
2920 {
2921 struct ena_admin_get_feat_resp get_resp;
2922 u16 delay_resolution;
2923 int rc;
2924
2925 rc = ena_com_get_feature(ena_dev, &get_resp,
2926 ENA_ADMIN_INTERRUPT_MODERATION, 0);
2927
2928 if (rc) {
2929 if (rc == -EOPNOTSUPP) {
2930 netdev_dbg(ena_dev->net_device,
2931 "Feature %d isn't supported\n",
2932 ENA_ADMIN_INTERRUPT_MODERATION);
2933 rc = 0;
2934 } else {
2935 netdev_err(ena_dev->net_device,
2936 "Failed to get interrupt moderation admin cmd. rc: %d\n",
2937 rc);
2938 }
2939
2940 /* no moderation supported, disable adaptive support */
2941 ena_com_disable_adaptive_moderation(ena_dev);
2942 return rc;
2943 }
2944
2945 /* if moderation is supported by device we set adaptive moderation */
2946 delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution;
2947 ena_com_update_intr_delay_resolution(ena_dev, delay_resolution);
2948
2949 /* Disable adaptive moderation by default - can be enabled later */
2950 ena_com_disable_adaptive_moderation(ena_dev);
2951
2952 return 0;
2953 }
2954
ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev * ena_dev)2955 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev)
2956 {
2957 return ena_dev->intr_moder_tx_interval;
2958 }
2959
ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev * ena_dev)2960 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev)
2961 {
2962 return ena_dev->intr_moder_rx_interval;
2963 }
2964
ena_com_config_dev_mode(struct ena_com_dev * ena_dev,struct ena_admin_feature_llq_desc * llq_features,struct ena_llq_configurations * llq_default_cfg)2965 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
2966 struct ena_admin_feature_llq_desc *llq_features,
2967 struct ena_llq_configurations *llq_default_cfg)
2968 {
2969 struct ena_com_llq_info *llq_info = &ena_dev->llq_info;
2970 int rc;
2971
2972 if (!llq_features->max_llq_num) {
2973 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
2974 return 0;
2975 }
2976
2977 rc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg);
2978 if (rc)
2979 return rc;
2980
2981 ena_dev->tx_max_header_size = llq_info->desc_list_entry_size -
2982 (llq_info->descs_num_before_header * sizeof(struct ena_eth_io_tx_desc));
2983
2984 if (unlikely(ena_dev->tx_max_header_size == 0)) {
2985 netdev_err(ena_dev->net_device,
2986 "The size of the LLQ entry is smaller than needed\n");
2987 return -EINVAL;
2988 }
2989
2990 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
2991
2992 return 0;
2993 }
2994