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1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  *  and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include <linux/delay.h>
27 
28 #include "dc_bios_types.h"
29 #include "dcn10_stream_encoder.h"
30 #include "reg_helper.h"
31 #include "hw_shared.h"
32 
33 #define DC_LOGGER \
34 		enc1->base.ctx->logger
35 
36 
37 #define REG(reg)\
38 	(enc1->regs->reg)
39 
40 #undef FN
41 #define FN(reg_name, field_name) \
42 	enc1->se_shift->field_name, enc1->se_mask->field_name
43 
44 #define VBI_LINE_0 0
45 #define DP_BLANK_MAX_RETRY 20
46 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
47 
48 
49 enum {
50 	DP_MST_UPDATE_MAX_RETRY = 50
51 };
52 
53 #define CTX \
54 	enc1->base.ctx
55 
enc1_update_generic_info_packet(struct dcn10_stream_encoder * enc1,uint32_t packet_index,const struct dc_info_packet * info_packet)56 void enc1_update_generic_info_packet(
57 	struct dcn10_stream_encoder *enc1,
58 	uint32_t packet_index,
59 	const struct dc_info_packet *info_packet)
60 {
61 	uint32_t regval;
62 	/* TODOFPGA Figure out a proper number for max_retries polling for lock
63 	 * use 50 for now.
64 	 */
65 	uint32_t max_retries = 50;
66 
67 	/*we need turn on clock before programming AFMT block*/
68 	REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
69 
70 	if (packet_index >= 8)
71 		ASSERT(0);
72 
73 	/* poll dig_update_lock is not locked -> asic internal signal
74 	 * assume otg master lock will unlock it
75 	 */
76 /*		REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
77 			0, 10, max_retries);*/
78 
79 	/* check if HW reading GSP memory */
80 	REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
81 			0, 10, max_retries);
82 
83 	/* HW does is not reading GSP memory not reading too long ->
84 	 * something wrong. clear GPS memory access and notify?
85 	 * hw SW is writing to GSP memory
86 	 */
87 	REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
88 
89 	/* choose which generic packet to use */
90 	regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
91 	REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
92 			AFMT_GENERIC_INDEX, packet_index);
93 
94 	/* write generic packet header
95 	 * (4th byte is for GENERIC0 only)
96 	 */
97 	REG_SET_4(AFMT_GENERIC_HDR, 0,
98 			AFMT_GENERIC_HB0, info_packet->hb0,
99 			AFMT_GENERIC_HB1, info_packet->hb1,
100 			AFMT_GENERIC_HB2, info_packet->hb2,
101 			AFMT_GENERIC_HB3, info_packet->hb3);
102 
103 	/* write generic packet contents
104 	 * (we never use last 4 bytes)
105 	 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
106 	 */
107 	{
108 		const uint32_t *content =
109 			(const uint32_t *) &info_packet->sb[0];
110 
111 		REG_WRITE(AFMT_GENERIC_0, *content++);
112 		REG_WRITE(AFMT_GENERIC_1, *content++);
113 		REG_WRITE(AFMT_GENERIC_2, *content++);
114 		REG_WRITE(AFMT_GENERIC_3, *content++);
115 		REG_WRITE(AFMT_GENERIC_4, *content++);
116 		REG_WRITE(AFMT_GENERIC_5, *content++);
117 		REG_WRITE(AFMT_GENERIC_6, *content++);
118 		REG_WRITE(AFMT_GENERIC_7, *content);
119 	}
120 
121 	switch (packet_index) {
122 	case 0:
123 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
124 				AFMT_GENERIC0_IMMEDIATE_UPDATE, 1);
125 		break;
126 	case 1:
127 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
128 				AFMT_GENERIC1_IMMEDIATE_UPDATE, 1);
129 		break;
130 	case 2:
131 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
132 				AFMT_GENERIC2_IMMEDIATE_UPDATE, 1);
133 		break;
134 	case 3:
135 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
136 				AFMT_GENERIC3_IMMEDIATE_UPDATE, 1);
137 		break;
138 	case 4:
139 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
140 				AFMT_GENERIC4_IMMEDIATE_UPDATE, 1);
141 		break;
142 	case 5:
143 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
144 				AFMT_GENERIC5_IMMEDIATE_UPDATE, 1);
145 		break;
146 	case 6:
147 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
148 				AFMT_GENERIC6_IMMEDIATE_UPDATE, 1);
149 		break;
150 	case 7:
151 		REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
152 				AFMT_GENERIC7_IMMEDIATE_UPDATE, 1);
153 		break;
154 	default:
155 		break;
156 	}
157 }
158 
enc1_update_hdmi_info_packet(struct dcn10_stream_encoder * enc1,uint32_t packet_index,const struct dc_info_packet * info_packet)159 static void enc1_update_hdmi_info_packet(
160 	struct dcn10_stream_encoder *enc1,
161 	uint32_t packet_index,
162 	const struct dc_info_packet *info_packet)
163 {
164 	uint32_t cont, send, line;
165 
166 	if (info_packet->valid) {
167 		enc1_update_generic_info_packet(
168 			enc1,
169 			packet_index,
170 			info_packet);
171 
172 		/* enable transmission of packet(s) -
173 		 * packet transmission begins on the next frame
174 		 */
175 		cont = 1;
176 		/* send packet(s) every frame */
177 		send = 1;
178 		/* select line number to send packets on */
179 		line = 2;
180 	} else {
181 		cont = 0;
182 		send = 0;
183 		line = 0;
184 	}
185 
186 	/* choose which generic packet control to use */
187 	switch (packet_index) {
188 	case 0:
189 		REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
190 				HDMI_GENERIC0_CONT, cont,
191 				HDMI_GENERIC0_SEND, send,
192 				HDMI_GENERIC0_LINE, line);
193 		break;
194 	case 1:
195 		REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
196 				HDMI_GENERIC1_CONT, cont,
197 				HDMI_GENERIC1_SEND, send,
198 				HDMI_GENERIC1_LINE, line);
199 		break;
200 	case 2:
201 		REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
202 				HDMI_GENERIC0_CONT, cont,
203 				HDMI_GENERIC0_SEND, send,
204 				HDMI_GENERIC0_LINE, line);
205 		break;
206 	case 3:
207 		REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
208 				HDMI_GENERIC1_CONT, cont,
209 				HDMI_GENERIC1_SEND, send,
210 				HDMI_GENERIC1_LINE, line);
211 		break;
212 	case 4:
213 		REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
214 				HDMI_GENERIC0_CONT, cont,
215 				HDMI_GENERIC0_SEND, send,
216 				HDMI_GENERIC0_LINE, line);
217 		break;
218 	case 5:
219 		REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
220 				HDMI_GENERIC1_CONT, cont,
221 				HDMI_GENERIC1_SEND, send,
222 				HDMI_GENERIC1_LINE, line);
223 		break;
224 	case 6:
225 		REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
226 				HDMI_GENERIC0_CONT, cont,
227 				HDMI_GENERIC0_SEND, send,
228 				HDMI_GENERIC0_LINE, line);
229 		break;
230 	case 7:
231 		REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
232 				HDMI_GENERIC1_CONT, cont,
233 				HDMI_GENERIC1_SEND, send,
234 				HDMI_GENERIC1_LINE, line);
235 		break;
236 	default:
237 		/* invalid HW packet index */
238 		DC_LOG_WARNING(
239 			"Invalid HW packet index: %s()\n",
240 			__func__);
241 		return;
242 	}
243 }
244 
245 /* setup stream encoder in dp mode */
enc1_stream_encoder_dp_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,enum dc_color_space output_color_space,bool use_vsc_sdp_for_colorimetry,uint32_t enable_sdp_splitting)246 void enc1_stream_encoder_dp_set_stream_attribute(
247 	struct stream_encoder *enc,
248 	struct dc_crtc_timing *crtc_timing,
249 	enum dc_color_space output_color_space,
250 	bool use_vsc_sdp_for_colorimetry,
251 	uint32_t enable_sdp_splitting)
252 {
253 	uint32_t h_active_start;
254 	uint32_t v_active_start;
255 	uint32_t misc0 = 0;
256 	uint32_t misc1 = 0;
257 	uint32_t h_blank;
258 	uint32_t h_back_porch;
259 	uint8_t synchronous_clock = 0; /* asynchronous mode */
260 	uint8_t colorimetry_bpc;
261 	uint8_t dynamic_range_rgb = 0; /*full range*/
262 	uint8_t dynamic_range_ycbcr = 1; /*bt709*/
263 	uint8_t dp_pixel_encoding = 0;
264 	uint8_t dp_component_depth = 0;
265 
266 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
267 	struct dc_crtc_timing hw_crtc_timing = *crtc_timing;
268 
269 	if (hw_crtc_timing.flags.INTERLACE) {
270 		/*the input timing is in VESA spec format with Interlace flag =1*/
271 		hw_crtc_timing.v_total /= 2;
272 		hw_crtc_timing.v_border_top /= 2;
273 		hw_crtc_timing.v_addressable /= 2;
274 		hw_crtc_timing.v_border_bottom /= 2;
275 		hw_crtc_timing.v_front_porch /= 2;
276 		hw_crtc_timing.v_sync_width /= 2;
277 	}
278 
279 
280 	/* set pixel encoding */
281 	switch (hw_crtc_timing.pixel_encoding) {
282 	case PIXEL_ENCODING_YCBCR422:
283 		dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422;
284 		break;
285 	case PIXEL_ENCODING_YCBCR444:
286 		dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444;
287 
288 		if (hw_crtc_timing.flags.Y_ONLY)
289 			if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666)
290 				/* HW testing only, no use case yet.
291 				 * Color depth of Y-only could be
292 				 * 8, 10, 12, 16 bits
293 				 */
294 				dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_Y_ONLY;
295 
296 		/* Note: DP_MSA_MISC1 bit 7 is the indicator
297 		 * of Y-only mode.
298 		 * This bit is set in HW if register
299 		 * DP_PIXEL_ENCODING is programmed to 0x4
300 		 */
301 		break;
302 	case PIXEL_ENCODING_YCBCR420:
303 		dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420;
304 		break;
305 	default:
306 		dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444;
307 		break;
308 	}
309 
310 	misc1 = REG_READ(DP_MSA_MISC);
311 	/* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used.
312 	 * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the
313 	 * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7,
314 	 * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care").
315 	 */
316 	if (use_vsc_sdp_for_colorimetry)
317 		misc1 = misc1 | 0x40;
318 	else
319 		misc1 = misc1 & ~0x40;
320 
321 	/* set color depth */
322 	switch (hw_crtc_timing.display_color_depth) {
323 	case COLOR_DEPTH_666:
324 		dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
325 		break;
326 	case COLOR_DEPTH_888:
327 		dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC;
328 		break;
329 	case COLOR_DEPTH_101010:
330 		dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC;
331 		break;
332 	case COLOR_DEPTH_121212:
333 		dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_12BPC;
334 		break;
335 	case COLOR_DEPTH_161616:
336 		dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_16BPC;
337 		break;
338 	default:
339 		dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC;
340 		break;
341 	}
342 
343 	/* Set DP pixel encoding and component depth */
344 	REG_UPDATE_2(DP_PIXEL_FORMAT,
345 			DP_PIXEL_ENCODING, dp_pixel_encoding,
346 			DP_COMPONENT_DEPTH, dp_component_depth);
347 
348 	/* set dynamic range and YCbCr range */
349 
350 	switch (hw_crtc_timing.display_color_depth) {
351 	case COLOR_DEPTH_666:
352 		colorimetry_bpc = 0;
353 		break;
354 	case COLOR_DEPTH_888:
355 		colorimetry_bpc = 1;
356 		break;
357 	case COLOR_DEPTH_101010:
358 		colorimetry_bpc = 2;
359 		break;
360 	case COLOR_DEPTH_121212:
361 		colorimetry_bpc = 3;
362 		break;
363 	default:
364 		colorimetry_bpc = 0;
365 		break;
366 	}
367 
368 	misc0 = misc0 | synchronous_clock;
369 	misc0 = colorimetry_bpc << 5;
370 
371 	switch (output_color_space) {
372 	case COLOR_SPACE_SRGB:
373 		misc1 = misc1 & ~0x80; /* bit7 = 0*/
374 		dynamic_range_rgb = 0; /*full range*/
375 		break;
376 	case COLOR_SPACE_SRGB_LIMITED:
377 		misc0 = misc0 | 0x8; /* bit3=1 */
378 		misc1 = misc1 & ~0x80; /* bit7 = 0*/
379 		dynamic_range_rgb = 1; /*limited range*/
380 		break;
381 	case COLOR_SPACE_YCBCR601:
382 	case COLOR_SPACE_YCBCR601_LIMITED:
383 		misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
384 		misc1 = misc1 & ~0x80; /* bit7 = 0*/
385 		dynamic_range_ycbcr = 0; /*bt601*/
386 		if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
387 			misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
388 		else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
389 			misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
390 		break;
391 	case COLOR_SPACE_YCBCR709:
392 	case COLOR_SPACE_YCBCR709_LIMITED:
393 		misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
394 		misc1 = misc1 & ~0x80; /* bit7 = 0*/
395 		dynamic_range_ycbcr = 1; /*bt709*/
396 		if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
397 			misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
398 		else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444)
399 			misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
400 		break;
401 	case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
402 		dynamic_range_rgb = 1; /*limited range*/
403 		break;
404 	case COLOR_SPACE_2020_RGB_FULLRANGE:
405 	case COLOR_SPACE_2020_YCBCR:
406 	case COLOR_SPACE_XR_RGB:
407 	case COLOR_SPACE_MSREF_SCRGB:
408 	case COLOR_SPACE_ADOBERGB:
409 	case COLOR_SPACE_DCIP3:
410 	case COLOR_SPACE_XV_YCC_709:
411 	case COLOR_SPACE_XV_YCC_601:
412 	case COLOR_SPACE_DISPLAYNATIVE:
413 	case COLOR_SPACE_DOLBYVISION:
414 	case COLOR_SPACE_APPCTRL:
415 	case COLOR_SPACE_CUSTOMPOINTS:
416 	case COLOR_SPACE_UNKNOWN:
417 	case COLOR_SPACE_YCBCR709_BLACK:
418 		/* do nothing */
419 		break;
420 	}
421 
422 	REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
423 	REG_WRITE(DP_MSA_MISC, misc1);   /* MSA_MISC1 */
424 
425 	/* dcn new register
426 	 * dc_crtc_timing is vesa dmt struct. data from edid
427 	 */
428 	REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
429 			DP_MSA_HTOTAL, hw_crtc_timing.h_total,
430 			DP_MSA_VTOTAL, hw_crtc_timing.v_total);
431 
432 	/* calculate from vesa timing parameters
433 	 * h_active_start related to leading edge of sync
434 	 */
435 
436 	h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left -
437 			hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right;
438 
439 	h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
440 			hw_crtc_timing.h_sync_width;
441 
442 	/* start at beginning of left border */
443 	h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
444 
445 
446 	v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top -
447 			hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom -
448 			hw_crtc_timing.v_front_porch;
449 
450 
451 	/* start at beginning of left border */
452 	REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
453 		DP_MSA_HSTART, h_active_start,
454 		DP_MSA_VSTART, v_active_start);
455 
456 	REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
457 			DP_MSA_HSYNCWIDTH,
458 			hw_crtc_timing.h_sync_width,
459 			DP_MSA_HSYNCPOLARITY,
460 			!hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY,
461 			DP_MSA_VSYNCWIDTH,
462 			hw_crtc_timing.v_sync_width,
463 			DP_MSA_VSYNCPOLARITY,
464 			!hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY);
465 
466 	/* HWDITH include border or overscan */
467 	REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
468 		DP_MSA_HWIDTH, hw_crtc_timing.h_border_left +
469 		hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right,
470 		DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top +
471 		hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom);
472 }
473 
enc1_stream_encoder_set_stream_attribute_helper(struct dcn10_stream_encoder * enc1,struct dc_crtc_timing * crtc_timing)474 void enc1_stream_encoder_set_stream_attribute_helper(
475 		struct dcn10_stream_encoder *enc1,
476 		struct dc_crtc_timing *crtc_timing)
477 {
478 	switch (crtc_timing->pixel_encoding) {
479 	case PIXEL_ENCODING_YCBCR422:
480 		REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
481 		break;
482 	default:
483 		REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
484 		break;
485 	}
486 	REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
487 }
488 
489 /* setup stream encoder in hdmi mode */
enc1_stream_encoder_hdmi_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,int actual_pix_clk_khz,bool enable_audio)490 void enc1_stream_encoder_hdmi_set_stream_attribute(
491 	struct stream_encoder *enc,
492 	struct dc_crtc_timing *crtc_timing,
493 	int actual_pix_clk_khz,
494 	bool enable_audio)
495 {
496 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
497 	struct bp_encoder_control cntl = {0};
498 
499 	cntl.action = ENCODER_CONTROL_SETUP;
500 	cntl.engine_id = enc1->base.id;
501 	cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
502 	cntl.enable_dp_audio = enable_audio;
503 	cntl.pixel_clock = actual_pix_clk_khz;
504 	cntl.lanes_number = LANE_COUNT_FOUR;
505 
506 	if (enc1->base.bp->funcs->encoder_control(
507 			enc1->base.bp, &cntl) != BP_RESULT_OK)
508 		return;
509 
510 	enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
511 
512 	/* setup HDMI engine */
513 	REG_UPDATE_6(HDMI_CONTROL,
514 		HDMI_PACKET_GEN_VERSION, 1,
515 		HDMI_KEEPOUT_MODE, 1,
516 		HDMI_DEEP_COLOR_ENABLE, 0,
517 		HDMI_DATA_SCRAMBLE_EN, 0,
518 		HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,
519 		HDMI_CLOCK_CHANNEL_RATE, 0);
520 
521 
522 	switch (crtc_timing->display_color_depth) {
523 	case COLOR_DEPTH_888:
524 		REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
525 		DC_LOG_DEBUG("HDMI source set to 24BPP deep color depth\n");
526 		break;
527 	case COLOR_DEPTH_101010:
528 		if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
529 			REG_UPDATE_2(HDMI_CONTROL,
530 					HDMI_DEEP_COLOR_DEPTH, 1,
531 					HDMI_DEEP_COLOR_ENABLE, 0);
532 			DC_LOG_DEBUG("HDMI source 30BPP deep color depth"  \
533 				"disabled for YCBCR422 pixel encoding\n");
534 		} else {
535 			REG_UPDATE_2(HDMI_CONTROL,
536 					HDMI_DEEP_COLOR_DEPTH, 1,
537 					HDMI_DEEP_COLOR_ENABLE, 1);
538 			DC_LOG_DEBUG("HDMI source 30BPP deep color depth"  \
539 				"enabled for YCBCR422 non-pixel encoding\n");
540 			}
541 		break;
542 	case COLOR_DEPTH_121212:
543 		if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
544 			REG_UPDATE_2(HDMI_CONTROL,
545 					HDMI_DEEP_COLOR_DEPTH, 2,
546 					HDMI_DEEP_COLOR_ENABLE, 0);
547 			DC_LOG_DEBUG("HDMI source 36BPP deep color depth"  \
548 				"disabled for YCBCR422 pixel encoding\n");
549 		} else {
550 			REG_UPDATE_2(HDMI_CONTROL,
551 					HDMI_DEEP_COLOR_DEPTH, 2,
552 					HDMI_DEEP_COLOR_ENABLE, 1);
553 			DC_LOG_DEBUG("HDMI source 36BPP deep color depth"  \
554 				"enabled for non-pixel YCBCR422 encoding\n");
555 			}
556 		break;
557 	case COLOR_DEPTH_161616:
558 		REG_UPDATE_2(HDMI_CONTROL,
559 				HDMI_DEEP_COLOR_DEPTH, 3,
560 				HDMI_DEEP_COLOR_ENABLE, 1);
561 		DC_LOG_DEBUG("HDMI source deep color depth enabled in"  \
562 				"reserved mode\n");
563 		break;
564 	default:
565 		break;
566 	}
567 
568 	if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
569 		/* enable HDMI data scrambler
570 		 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
571 		 * Clock channel frequency is 1/4 of character rate.
572 		 */
573 		REG_UPDATE_2(HDMI_CONTROL,
574 			HDMI_DATA_SCRAMBLE_EN, 1,
575 			HDMI_CLOCK_CHANNEL_RATE, 1);
576 	} else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
577 
578 		/* TODO: New feature for DCE11, still need to implement */
579 
580 		/* enable HDMI data scrambler
581 		 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
582 		 * Clock channel frequency is the same
583 		 * as character rate
584 		 */
585 		REG_UPDATE_2(HDMI_CONTROL,
586 			HDMI_DATA_SCRAMBLE_EN, 1,
587 			HDMI_CLOCK_CHANNEL_RATE, 0);
588 	}
589 
590 
591 	REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
592 		HDMI_GC_CONT, 1,
593 		HDMI_GC_SEND, 1,
594 		HDMI_NULL_SEND, 1);
595 
596 	/* following belongs to audio */
597 	REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
598 
599 	REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
600 
601 	REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
602 				VBI_LINE_0 + 2);
603 
604 	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
605 }
606 
607 /* setup stream encoder in dvi mode */
enc1_stream_encoder_dvi_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,bool is_dual_link)608 void enc1_stream_encoder_dvi_set_stream_attribute(
609 	struct stream_encoder *enc,
610 	struct dc_crtc_timing *crtc_timing,
611 	bool is_dual_link)
612 {
613 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
614 	struct bp_encoder_control cntl = {0};
615 
616 	cntl.action = ENCODER_CONTROL_SETUP;
617 	cntl.engine_id = enc1->base.id;
618 	cntl.signal = is_dual_link ?
619 			SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
620 	cntl.enable_dp_audio = false;
621 	cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
622 	cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
623 
624 	if (enc1->base.bp->funcs->encoder_control(
625 			enc1->base.bp, &cntl) != BP_RESULT_OK)
626 		return;
627 
628 	ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
629 	ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
630 	enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
631 }
632 
enc1_stream_encoder_set_throttled_vcp_size(struct stream_encoder * enc,struct fixed31_32 avg_time_slots_per_mtp)633 void enc1_stream_encoder_set_throttled_vcp_size(
634 	struct stream_encoder *enc,
635 	struct fixed31_32 avg_time_slots_per_mtp)
636 {
637 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
638 	uint32_t x = dc_fixpt_floor(
639 		avg_time_slots_per_mtp);
640 	uint32_t y = dc_fixpt_ceil(
641 		dc_fixpt_shl(
642 			dc_fixpt_sub_int(
643 				avg_time_slots_per_mtp,
644 				x),
645 			26));
646 
647 	REG_SET_2(DP_MSE_RATE_CNTL, 0,
648 		DP_MSE_RATE_X, x,
649 		DP_MSE_RATE_Y, y);
650 
651 	/* wait for update to be completed on the link */
652 	/* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
653 	/* is reset to 0 (not pending) */
654 	REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
655 			0,
656 			10, DP_MST_UPDATE_MAX_RETRY);
657 }
658 
enc1_stream_encoder_update_hdmi_info_packets(struct stream_encoder * enc,const struct encoder_info_frame * info_frame)659 static void enc1_stream_encoder_update_hdmi_info_packets(
660 	struct stream_encoder *enc,
661 	const struct encoder_info_frame *info_frame)
662 {
663 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
664 
665 	/* for bring up, disable dp double  TODO */
666 	REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
667 
668 	enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
669 	enc1_update_hdmi_info_packet(enc1, 1, &info_frame->vendor);
670 	enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
671 	enc1_update_hdmi_info_packet(enc1, 3, &info_frame->spd);
672 	enc1_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd);
673 }
674 
enc1_stream_encoder_stop_hdmi_info_packets(struct stream_encoder * enc)675 static void enc1_stream_encoder_stop_hdmi_info_packets(
676 	struct stream_encoder *enc)
677 {
678 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
679 
680 	/* stop generic packets 0 & 1 on HDMI */
681 	REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
682 		HDMI_GENERIC1_CONT, 0,
683 		HDMI_GENERIC1_LINE, 0,
684 		HDMI_GENERIC1_SEND, 0,
685 		HDMI_GENERIC0_CONT, 0,
686 		HDMI_GENERIC0_LINE, 0,
687 		HDMI_GENERIC0_SEND, 0);
688 
689 	/* stop generic packets 2 & 3 on HDMI */
690 	REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
691 		HDMI_GENERIC0_CONT, 0,
692 		HDMI_GENERIC0_LINE, 0,
693 		HDMI_GENERIC0_SEND, 0,
694 		HDMI_GENERIC1_CONT, 0,
695 		HDMI_GENERIC1_LINE, 0,
696 		HDMI_GENERIC1_SEND, 0);
697 
698 	/* stop generic packets 2 & 3 on HDMI */
699 	REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
700 		HDMI_GENERIC0_CONT, 0,
701 		HDMI_GENERIC0_LINE, 0,
702 		HDMI_GENERIC0_SEND, 0,
703 		HDMI_GENERIC1_CONT, 0,
704 		HDMI_GENERIC1_LINE, 0,
705 		HDMI_GENERIC1_SEND, 0);
706 
707 	REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
708 		HDMI_GENERIC0_CONT, 0,
709 		HDMI_GENERIC0_LINE, 0,
710 		HDMI_GENERIC0_SEND, 0,
711 		HDMI_GENERIC1_CONT, 0,
712 		HDMI_GENERIC1_LINE, 0,
713 		HDMI_GENERIC1_SEND, 0);
714 }
715 
enc1_stream_encoder_update_dp_info_packets(struct stream_encoder * enc,const struct encoder_info_frame * info_frame)716 void enc1_stream_encoder_update_dp_info_packets(
717 	struct stream_encoder *enc,
718 	const struct encoder_info_frame *info_frame)
719 {
720 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
721 	uint32_t value = 0;
722 
723 	if (info_frame->vsc.valid)
724 		enc1_update_generic_info_packet(
725 					enc1,
726 					0,  /* packetIndex */
727 					&info_frame->vsc);
728 
729 	if (info_frame->spd.valid)
730 		enc1_update_generic_info_packet(
731 				enc1,
732 				2,  /* packetIndex */
733 				&info_frame->spd);
734 
735 	if (info_frame->hdrsmd.valid)
736 		enc1_update_generic_info_packet(
737 				enc1,
738 				3,  /* packetIndex */
739 				&info_frame->hdrsmd);
740 
741 	/* packetIndex 4 is used for send immediate sdp message, and please
742 	 * use other packetIndex (such as 5,6) for other info packet
743 	 */
744 
745 	/* enable/disable transmission of packet(s).
746 	 * If enabled, packet transmission begins on the next frame
747 	 */
748 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
749 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
750 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
751 
752 	/* This bit is the master enable bit.
753 	 * When enabling secondary stream engine,
754 	 * this master bit must also be set.
755 	 * This register shared with audio info frame.
756 	 * Therefore we need to enable master bit
757 	 * if at least on of the fields is not 0
758 	 */
759 	value = REG_READ(DP_SEC_CNTL);
760 	if (value)
761 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
762 }
763 
enc1_stream_encoder_send_immediate_sdp_message(struct stream_encoder * enc,const uint8_t * custom_sdp_message,unsigned int sdp_message_size)764 void enc1_stream_encoder_send_immediate_sdp_message(
765 	struct stream_encoder *enc,
766 	const uint8_t *custom_sdp_message,
767 	unsigned int sdp_message_size)
768 {
769 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
770 	uint32_t value = 0;
771 
772 	/* TODOFPGA Figure out a proper number for max_retries polling for lock
773 	 * use 50 for now.
774 	 */
775 	uint32_t max_retries = 50;
776 
777 	/* check if GSP4 is transmitted */
778 	REG_WAIT(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING,
779 		0, 10, max_retries);
780 
781 	/* disable GSP4 transmitting */
782 	REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 0);
783 
784 	/* transmit GSP4 at the earliest time in a frame */
785 	REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, 1);
786 
787 	/*we need turn on clock before programming AFMT block*/
788 	REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
789 
790 	/* check if HW reading GSP memory */
791 	REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
792 			0, 10, max_retries);
793 
794 	/* HW does is not reading GSP memory not reading too long ->
795 	 * something wrong. clear GPS memory access and notify?
796 	 * hw SW is writing to GSP memory
797 	 */
798 	REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
799 
800 	/* use generic packet 4 for immediate sdp message */
801 	REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
802 			AFMT_GENERIC_INDEX, 4);
803 
804 	/* write generic packet header
805 	 * (4th byte is for GENERIC0 only)
806 	 */
807 	REG_SET_4(AFMT_GENERIC_HDR, 0,
808 			AFMT_GENERIC_HB0, custom_sdp_message[0],
809 			AFMT_GENERIC_HB1, custom_sdp_message[1],
810 			AFMT_GENERIC_HB2, custom_sdp_message[2],
811 			AFMT_GENERIC_HB3, custom_sdp_message[3]);
812 
813 	/* write generic packet contents
814 	 * (we never use last 4 bytes)
815 	 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers
816 	 */
817 	{
818 		const uint32_t *content =
819 			(const uint32_t *) &custom_sdp_message[4];
820 
821 		REG_WRITE(AFMT_GENERIC_0, *content++);
822 		REG_WRITE(AFMT_GENERIC_1, *content++);
823 		REG_WRITE(AFMT_GENERIC_2, *content++);
824 		REG_WRITE(AFMT_GENERIC_3, *content++);
825 		REG_WRITE(AFMT_GENERIC_4, *content++);
826 		REG_WRITE(AFMT_GENERIC_5, *content++);
827 		REG_WRITE(AFMT_GENERIC_6, *content++);
828 		REG_WRITE(AFMT_GENERIC_7, *content);
829 	}
830 
831 	/* check whether GENERIC4 registers double buffer update in immediate mode
832 	 * is pending
833 	 */
834 	REG_WAIT(AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING,
835 			0, 10, max_retries);
836 
837 	/* atomically update double-buffered GENERIC4 registers in immediate mode
838 	 * (update immediately)
839 	 */
840 	REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
841 			AFMT_GENERIC4_IMMEDIATE_UPDATE, 1);
842 
843 	/* enable GSP4 transmitting */
844 	REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP4_SEND, 1);
845 
846 	/* This bit is the master enable bit.
847 	 * When enabling secondary stream engine,
848 	 * this master bit must also be set.
849 	 * This register shared with audio info frame.
850 	 * Therefore we need to enable master bit
851 	 * if at least on of the fields is not 0
852 	 */
853 	value = REG_READ(DP_SEC_CNTL);
854 	if (value)
855 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
856 }
857 
enc1_stream_encoder_stop_dp_info_packets(struct stream_encoder * enc)858 void enc1_stream_encoder_stop_dp_info_packets(
859 	struct stream_encoder *enc)
860 {
861 	/* stop generic packets on DP */
862 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
863 	uint32_t value = 0;
864 
865 	REG_SET_10(DP_SEC_CNTL, 0,
866 		DP_SEC_GSP0_ENABLE, 0,
867 		DP_SEC_GSP1_ENABLE, 0,
868 		DP_SEC_GSP2_ENABLE, 0,
869 		DP_SEC_GSP3_ENABLE, 0,
870 		DP_SEC_GSP4_ENABLE, 0,
871 		DP_SEC_GSP5_ENABLE, 0,
872 		DP_SEC_GSP6_ENABLE, 0,
873 		DP_SEC_GSP7_ENABLE, 0,
874 		DP_SEC_MPG_ENABLE, 0,
875 		DP_SEC_STREAM_ENABLE, 0);
876 
877 	/* this register shared with audio info frame.
878 	 * therefore we need to keep master enabled
879 	 * if at least one of the fields is not 0 */
880 	value = REG_READ(DP_SEC_CNTL);
881 	if (value)
882 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
883 
884 }
885 
enc1_stream_encoder_dp_blank(struct stream_encoder * enc)886 void enc1_stream_encoder_dp_blank(
887 	struct stream_encoder *enc)
888 {
889 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
890 	uint32_t  reg1 = 0;
891 	uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
892 
893 	/* Note: For CZ, we are changing driver default to disable
894 	 * stream deferred to next VBLANK. If results are positive, we
895 	 * will make the same change to all DCE versions. There are a
896 	 * handful of panels that cannot handle disable stream at
897 	 * HBLANK and will result in a white line flash across the
898 	 * screen on stream disable.
899 	 */
900 	REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);
901 	if ((reg1 & 0x1) == 0)
902 		/*stream not enabled*/
903 		return;
904 	/* Specify the video stream disable point
905 	 * (2 = start of the next vertical blank)
906 	 */
907 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
908 	/* Larger delay to wait until VBLANK - use max retry of
909 	 * 10us*10200=102ms. This covers 100.0ms of minimum 10 Hz mode +
910 	 * a little more because we may not trust delay accuracy.
911 	 */
912 	max_retries = DP_BLANK_MAX_RETRY * 501;
913 
914 	/* disable DP stream */
915 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
916 
917 	/* the encoder stops sending the video stream
918 	 * at the start of the vertical blanking.
919 	 * Poll for DP_VID_STREAM_STATUS == 0
920 	 */
921 
922 	REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
923 			0,
924 			10, max_retries);
925 
926 	/* Tell the DP encoder to ignore timing from CRTC, must be done after
927 	 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
928 	 * complete, stream status will be stuck in video stream enabled state,
929 	 * i.e. DP_VID_STREAM_STATUS stuck at 1.
930 	 */
931 
932 	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
933 }
934 
935 /* output video stream to link encoder */
enc1_stream_encoder_dp_unblank(struct stream_encoder * enc,const struct encoder_unblank_param * param)936 void enc1_stream_encoder_dp_unblank(
937 	struct stream_encoder *enc,
938 	const struct encoder_unblank_param *param)
939 {
940 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
941 
942 	if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
943 		uint32_t n_vid = 0x8000;
944 		uint32_t m_vid;
945 		uint32_t n_multiply = 0;
946 		uint64_t m_vid_l = n_vid;
947 
948 		/* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
949 		if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
950 			/*this param->pixel_clk_khz is half of 444 rate for 420 already*/
951 			n_multiply = 1;
952 		}
953 		/* M / N = Fstream / Flink
954 		 * m_vid / n_vid = pixel rate / link rate
955 		 */
956 
957 		m_vid_l *= param->timing.pix_clk_100hz / 10;
958 		m_vid_l = div_u64(m_vid_l,
959 			param->link_settings.link_rate
960 				* LINK_RATE_REF_FREQ_IN_KHZ);
961 
962 		m_vid = (uint32_t) m_vid_l;
963 
964 		/* enable auto measurement */
965 
966 		REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
967 
968 		/* auto measurement need 1 full 0x8000 symbol cycle to kick in,
969 		 * therefore program initial value for Mvid and Nvid
970 		 */
971 
972 		REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
973 
974 		REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
975 
976 		REG_UPDATE_2(DP_VID_TIMING,
977 				DP_VID_M_N_GEN_EN, 1,
978 				DP_VID_N_MUL, n_multiply);
979 	}
980 
981 	/* set DIG_START to 0x1 to resync FIFO */
982 
983 	REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
984 
985 	/* switch DP encoder to CRTC data */
986 
987 	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
988 
989 	/* wait 100us for DIG/DP logic to prime
990 	 * (i.e. a few video lines)
991 	 */
992 	udelay(100);
993 
994 	/* the hardware would start sending video at the start of the next DP
995 	 * frame (i.e. rising edge of the vblank).
996 	 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
997 	 * register has no effect on enable transition! HW always guarantees
998 	 * VID_STREAM enable at start of next frame, and this is not
999 	 * programmable
1000 	 */
1001 
1002 	REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
1003 }
1004 
enc1_stream_encoder_set_avmute(struct stream_encoder * enc,bool enable)1005 void enc1_stream_encoder_set_avmute(
1006 	struct stream_encoder *enc,
1007 	bool enable)
1008 {
1009 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1010 	unsigned int value = enable ? 1 : 0;
1011 
1012 	REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
1013 }
1014 
enc1_reset_hdmi_stream_attribute(struct stream_encoder * enc)1015 void enc1_reset_hdmi_stream_attribute(
1016 	struct stream_encoder *enc)
1017 {
1018 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1019 
1020 	REG_UPDATE_5(HDMI_CONTROL,
1021 		HDMI_PACKET_GEN_VERSION, 1,
1022 		HDMI_KEEPOUT_MODE, 1,
1023 		HDMI_DEEP_COLOR_ENABLE, 0,
1024 		HDMI_DATA_SCRAMBLE_EN, 0,
1025 		HDMI_CLOCK_CHANNEL_RATE, 0);
1026 }
1027 
1028 
1029 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
1030 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
1031 
1032 #include "include/audio_types.h"
1033 
1034 
1035 /* 25.2MHz/1.001*/
1036 /* 25.2MHz/1.001*/
1037 /* 25.2MHz*/
1038 /* 27MHz */
1039 /* 27MHz*1.001*/
1040 /* 27MHz*1.001*/
1041 /* 54MHz*/
1042 /* 54MHz*1.001*/
1043 /* 74.25MHz/1.001*/
1044 /* 74.25MHz*/
1045 /* 148.5MHz/1.001*/
1046 /* 148.5MHz*/
1047 
1048 static const struct audio_clock_info audio_clock_info_table[16] = {
1049 	{2517, 4576, 28125, 7007, 31250, 6864, 28125},
1050 	{2518, 4576, 28125, 7007, 31250, 6864, 28125},
1051 	{2520, 4096, 25200, 6272, 28000, 6144, 25200},
1052 	{2700, 4096, 27000, 6272, 30000, 6144, 27000},
1053 	{2702, 4096, 27027, 6272, 30030, 6144, 27027},
1054 	{2703, 4096, 27027, 6272, 30030, 6144, 27027},
1055 	{5400, 4096, 54000, 6272, 60000, 6144, 54000},
1056 	{5405, 4096, 54054, 6272, 60060, 6144, 54054},
1057 	{7417, 11648, 210937, 17836, 234375, 11648, 140625},
1058 	{7425, 4096, 74250, 6272, 82500, 6144, 74250},
1059 	{14835, 11648, 421875, 8918, 234375, 5824, 140625},
1060 	{14850, 4096, 148500, 6272, 165000, 6144, 148500},
1061 	{29670, 5824, 421875, 4459, 234375, 5824, 281250},
1062 	{29700, 3072, 222750, 4704, 247500, 5120, 247500},
1063 	{59340, 5824, 843750, 8918, 937500, 5824, 562500},
1064 	{59400, 3072, 445500, 9408, 990000, 6144, 594000}
1065 };
1066 
1067 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1068 	{2517,  9152,  84375,  7007,  48875,  9152,  56250},
1069 	{2518,  9152,  84375,  7007,  48875,  9152,  56250},
1070 	{2520,  4096,  37800,  6272,  42000,  6144,  37800},
1071 	{2700,  4096,  40500,  6272,  45000,  6144,  40500},
1072 	{2702,  8192,  81081,  6272,  45045,  8192,  54054},
1073 	{2703,  8192,  81081,  6272,  45045,  8192,  54054},
1074 	{5400,  4096,  81000,  6272,  90000,  6144,  81000},
1075 	{5405,  4096,  81081,  6272,  90090,  6144,  81081},
1076 	{7417, 11648, 316406, 17836, 351562, 11648, 210937},
1077 	{7425, 4096, 111375,  6272, 123750,  6144, 111375},
1078 	{14835, 11648, 632812, 17836, 703125, 11648, 421875},
1079 	{14850, 4096, 222750,  6272, 247500,  6144, 222750},
1080 	{29670, 5824, 632812,  8918, 703125,  5824, 421875},
1081 	{29700, 4096, 445500,  4704, 371250,  5120, 371250}
1082 };
1083 
1084 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1085 	{2517,  4576,  56250,  7007,  62500,  6864,  56250},
1086 	{2518,  4576,  56250,  7007,  62500,  6864,  56250},
1087 	{2520,  4096,  50400,  6272,  56000,  6144,  50400},
1088 	{2700,  4096,  54000,  6272,  60000,  6144,  54000},
1089 	{2702,  4096,  54054,  6267,  60060,  8192,  54054},
1090 	{2703,  4096,  54054,  6272,  60060,  8192,  54054},
1091 	{5400,  4096, 108000,  6272, 120000,  6144, 108000},
1092 	{5405,  4096, 108108,  6272, 120120,  6144, 108108},
1093 	{7417, 11648, 421875, 17836, 468750, 11648, 281250},
1094 	{7425,  4096, 148500,  6272, 165000,  6144, 148500},
1095 	{14835, 11648, 843750,  8918, 468750, 11648, 281250},
1096 	{14850, 4096, 297000,  6272, 330000,  6144, 297000},
1097 	{29670, 5824, 843750,  4459, 468750,  5824, 562500},
1098 	{29700, 3072, 445500,  4704, 495000,  5120, 495000}
1099 
1100 
1101 };
1102 
speakers_to_channels(struct audio_speaker_flags speaker_flags)1103 static union audio_cea_channels speakers_to_channels(
1104 	struct audio_speaker_flags speaker_flags)
1105 {
1106 	union audio_cea_channels cea_channels = {0};
1107 
1108 	/* these are one to one */
1109 	cea_channels.channels.FL = speaker_flags.FL_FR;
1110 	cea_channels.channels.FR = speaker_flags.FL_FR;
1111 	cea_channels.channels.LFE = speaker_flags.LFE;
1112 	cea_channels.channels.FC = speaker_flags.FC;
1113 
1114 	/* if Rear Left and Right exist move RC speaker to channel 7
1115 	 * otherwise to channel 5
1116 	 */
1117 	if (speaker_flags.RL_RR) {
1118 		cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1119 		cea_channels.channels.RR = speaker_flags.RL_RR;
1120 		cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1121 	} else {
1122 		cea_channels.channels.RL_RC = speaker_flags.RC;
1123 	}
1124 
1125 	/* FRONT Left Right Center and REAR Left Right Center are exclusive */
1126 	if (speaker_flags.FLC_FRC) {
1127 		cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1128 		cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1129 	} else {
1130 		cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1131 		cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1132 	}
1133 
1134 	return cea_channels;
1135 }
1136 
get_audio_clock_info(enum dc_color_depth color_depth,uint32_t crtc_pixel_clock_100Hz,uint32_t actual_pixel_clock_100Hz,struct audio_clock_info * audio_clock_info)1137 void get_audio_clock_info(
1138 	enum dc_color_depth color_depth,
1139 	uint32_t crtc_pixel_clock_100Hz,
1140 	uint32_t actual_pixel_clock_100Hz,
1141 	struct audio_clock_info *audio_clock_info)
1142 {
1143 	const struct audio_clock_info *clock_info;
1144 	uint32_t index;
1145 	uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100;
1146 	uint32_t audio_array_size;
1147 
1148 	switch (color_depth) {
1149 	case COLOR_DEPTH_161616:
1150 		clock_info = audio_clock_info_table_48bpc;
1151 		audio_array_size = ARRAY_SIZE(
1152 				audio_clock_info_table_48bpc);
1153 		break;
1154 	case COLOR_DEPTH_121212:
1155 		clock_info = audio_clock_info_table_36bpc;
1156 		audio_array_size = ARRAY_SIZE(
1157 				audio_clock_info_table_36bpc);
1158 		break;
1159 	default:
1160 		clock_info = audio_clock_info_table;
1161 		audio_array_size = ARRAY_SIZE(
1162 				audio_clock_info_table);
1163 		break;
1164 	}
1165 
1166 	if (clock_info != NULL) {
1167 		/* search for exact pixel clock in table */
1168 		for (index = 0; index < audio_array_size; index++) {
1169 			if (clock_info[index].pixel_clock_in_10khz >
1170 				crtc_pixel_clock_in_10khz)
1171 				break;  /* not match */
1172 			else if (clock_info[index].pixel_clock_in_10khz ==
1173 					crtc_pixel_clock_in_10khz) {
1174 				/* match found */
1175 				*audio_clock_info = clock_info[index];
1176 				return;
1177 			}
1178 		}
1179 	}
1180 
1181 	/* not found */
1182 	if (actual_pixel_clock_100Hz == 0)
1183 		actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz;
1184 
1185 	/* See HDMI spec  the table entry under
1186 	 *  pixel clock of "Other". */
1187 	audio_clock_info->pixel_clock_in_10khz =
1188 			actual_pixel_clock_100Hz / 100;
1189 	audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10;
1190 	audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10;
1191 	audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10;
1192 
1193 	audio_clock_info->n_32khz = 4096;
1194 	audio_clock_info->n_44khz = 6272;
1195 	audio_clock_info->n_48khz = 6144;
1196 }
1197 
enc1_se_audio_setup(struct stream_encoder * enc,unsigned int az_inst,struct audio_info * audio_info)1198 static void enc1_se_audio_setup(
1199 	struct stream_encoder *enc,
1200 	unsigned int az_inst,
1201 	struct audio_info *audio_info)
1202 {
1203 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1204 
1205 	uint32_t channels = 0;
1206 
1207 	ASSERT(audio_info);
1208 	if (audio_info == NULL)
1209 		/* This should not happen.it does so we don't get BSOD*/
1210 		return;
1211 
1212 	channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1213 
1214 	/* setup the audio stream source select (audio -> dig mapping) */
1215 	REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1216 
1217 	/* Channel allocation */
1218 	REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1219 }
1220 
enc1_se_setup_hdmi_audio(struct stream_encoder * enc,const struct audio_crtc_info * crtc_info)1221 static void enc1_se_setup_hdmi_audio(
1222 	struct stream_encoder *enc,
1223 	const struct audio_crtc_info *crtc_info)
1224 {
1225 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1226 
1227 	struct audio_clock_info audio_clock_info = {0};
1228 
1229 	/* HDMI_AUDIO_PACKET_CONTROL */
1230 	REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,
1231 			HDMI_AUDIO_DELAY_EN, 1);
1232 
1233 	/* AFMT_AUDIO_PACKET_CONTROL */
1234 	REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1235 
1236 	/* AFMT_AUDIO_PACKET_CONTROL2 */
1237 	REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1238 			AFMT_AUDIO_LAYOUT_OVRD, 0,
1239 			AFMT_60958_OSF_OVRD, 0);
1240 
1241 	/* HDMI_ACR_PACKET_CONTROL */
1242 	REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1243 			HDMI_ACR_AUTO_SEND, 1,
1244 			HDMI_ACR_SOURCE, 0,
1245 			HDMI_ACR_AUDIO_PRIORITY, 0);
1246 
1247 	/* Program audio clock sample/regeneration parameters */
1248 	get_audio_clock_info(crtc_info->color_depth,
1249 			     crtc_info->requested_pixel_clock_100Hz,
1250 			     crtc_info->calculated_pixel_clock_100Hz,
1251 			     &audio_clock_info);
1252 	DC_LOG_HW_AUDIO(
1253 			"\n%s:Input::requested_pixel_clock_100Hz = %d"	\
1254 			"calculated_pixel_clock_100Hz = %d \n", __func__,	\
1255 			crtc_info->requested_pixel_clock_100Hz,		\
1256 			crtc_info->calculated_pixel_clock_100Hz);
1257 
1258 	/* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1259 	REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1260 
1261 	/* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1262 	REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1263 
1264 	/* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1265 	REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1266 
1267 	/* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1268 	REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1269 
1270 	/* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1271 	REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1272 
1273 	/* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1274 	REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1275 
1276 	/* Video driver cannot know in advance which sample rate will
1277 	 * be used by HD Audio driver
1278 	 * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1279 	 * programmed below in interruppt callback
1280 	 */
1281 
1282 	/* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1283 	 * AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK
1284 	 */
1285 	REG_UPDATE_2(AFMT_60958_0,
1286 			AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1287 			AFMT_60958_CS_CLOCK_ACCURACY, 0);
1288 
1289 	/* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1290 	REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1291 
1292 	/* AFMT_60958_2 now keep this settings until
1293 	 * Programming guide comes out
1294 	 */
1295 	REG_UPDATE_6(AFMT_60958_2,
1296 			AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1297 			AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1298 			AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1299 			AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1300 			AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1301 			AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1302 }
1303 
enc1_se_setup_dp_audio(struct stream_encoder * enc)1304 static void enc1_se_setup_dp_audio(
1305 	struct stream_encoder *enc)
1306 {
1307 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1308 
1309 	/* --- DP Audio packet configurations --- */
1310 
1311 	/* ATP Configuration */
1312 	REG_SET(DP_SEC_AUD_N, 0,
1313 			DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1314 
1315 	/* Async/auto-calc timestamp mode */
1316 	REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1317 			DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1318 
1319 	/* --- The following are the registers
1320 	 *  copied from the SetupHDMI ---
1321 	 */
1322 
1323 	/* AFMT_AUDIO_PACKET_CONTROL */
1324 	REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1325 
1326 	/* AFMT_AUDIO_PACKET_CONTROL2 */
1327 	/* Program the ATP and AIP next */
1328 	REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1329 			AFMT_AUDIO_LAYOUT_OVRD, 0,
1330 			AFMT_60958_OSF_OVRD, 0);
1331 
1332 	/* AFMT_INFOFRAME_CONTROL0 */
1333 	REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1334 
1335 	/* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1336 	REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1337 }
1338 
enc1_se_enable_audio_clock(struct stream_encoder * enc,bool enable)1339 void enc1_se_enable_audio_clock(
1340 	struct stream_encoder *enc,
1341 	bool enable)
1342 {
1343 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1344 
1345 	if (REG(AFMT_CNTL) == 0)
1346 		return;   /* DCE8/10 does not have this register */
1347 
1348 	REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1349 
1350 	/* wait for AFMT clock to turn on,
1351 	 * expectation: this should complete in 1-2 reads
1352 	 *
1353 	 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1354 	 *
1355 	 * TODO: wait for clock_on does not work well. May need HW
1356 	 * program sequence. But audio seems work normally even without wait
1357 	 * for clock_on status change
1358 	 */
1359 }
1360 
enc1_se_enable_dp_audio(struct stream_encoder * enc)1361 void enc1_se_enable_dp_audio(
1362 	struct stream_encoder *enc)
1363 {
1364 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1365 
1366 	/* Enable Audio packets */
1367 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1368 
1369 	/* Program the ATP and AIP next */
1370 	REG_UPDATE_2(DP_SEC_CNTL,
1371 			DP_SEC_ATP_ENABLE, 1,
1372 			DP_SEC_AIP_ENABLE, 1);
1373 
1374 	/* Program STREAM_ENABLE after all the other enables. */
1375 	REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1376 }
1377 
enc1_se_disable_dp_audio(struct stream_encoder * enc)1378 static void enc1_se_disable_dp_audio(
1379 	struct stream_encoder *enc)
1380 {
1381 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1382 	uint32_t value = 0;
1383 
1384 	/* Disable Audio packets */
1385 	REG_UPDATE_5(DP_SEC_CNTL,
1386 			DP_SEC_ASP_ENABLE, 0,
1387 			DP_SEC_ATP_ENABLE, 0,
1388 			DP_SEC_AIP_ENABLE, 0,
1389 			DP_SEC_ACM_ENABLE, 0,
1390 			DP_SEC_STREAM_ENABLE, 0);
1391 
1392 	/* This register shared with encoder info frame. Therefore we need to
1393 	 * keep master enabled if at least on of the fields is not 0
1394 	 */
1395 	value = REG_READ(DP_SEC_CNTL);
1396 	if (value != 0)
1397 		REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1398 
1399 }
1400 
enc1_se_audio_mute_control(struct stream_encoder * enc,bool mute)1401 void enc1_se_audio_mute_control(
1402 	struct stream_encoder *enc,
1403 	bool mute)
1404 {
1405 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1406 
1407 	REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1408 }
1409 
enc1_se_dp_audio_setup(struct stream_encoder * enc,unsigned int az_inst,struct audio_info * info)1410 void enc1_se_dp_audio_setup(
1411 	struct stream_encoder *enc,
1412 	unsigned int az_inst,
1413 	struct audio_info *info)
1414 {
1415 	enc1_se_audio_setup(enc, az_inst, info);
1416 }
1417 
enc1_se_dp_audio_enable(struct stream_encoder * enc)1418 void enc1_se_dp_audio_enable(
1419 	struct stream_encoder *enc)
1420 {
1421 	enc1_se_enable_audio_clock(enc, true);
1422 	enc1_se_setup_dp_audio(enc);
1423 	enc1_se_enable_dp_audio(enc);
1424 }
1425 
enc1_se_dp_audio_disable(struct stream_encoder * enc)1426 void enc1_se_dp_audio_disable(
1427 	struct stream_encoder *enc)
1428 {
1429 	enc1_se_disable_dp_audio(enc);
1430 	enc1_se_enable_audio_clock(enc, false);
1431 }
1432 
enc1_se_hdmi_audio_setup(struct stream_encoder * enc,unsigned int az_inst,struct audio_info * info,struct audio_crtc_info * audio_crtc_info)1433 void enc1_se_hdmi_audio_setup(
1434 	struct stream_encoder *enc,
1435 	unsigned int az_inst,
1436 	struct audio_info *info,
1437 	struct audio_crtc_info *audio_crtc_info)
1438 {
1439 	enc1_se_enable_audio_clock(enc, true);
1440 	enc1_se_setup_hdmi_audio(enc, audio_crtc_info);
1441 	enc1_se_audio_setup(enc, az_inst, info);
1442 }
1443 
enc1_se_hdmi_audio_disable(struct stream_encoder * enc)1444 void enc1_se_hdmi_audio_disable(
1445 	struct stream_encoder *enc)
1446 {
1447 	enc1_se_enable_audio_clock(enc, false);
1448 }
1449 
1450 
enc1_setup_stereo_sync(struct stream_encoder * enc,int tg_inst,bool enable)1451 void enc1_setup_stereo_sync(
1452 	struct stream_encoder *enc,
1453 	int tg_inst, bool enable)
1454 {
1455 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1456 	REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1457 	REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1458 }
1459 
enc1_dig_connect_to_otg(struct stream_encoder * enc,int tg_inst)1460 void enc1_dig_connect_to_otg(
1461 	struct stream_encoder *enc,
1462 	int tg_inst)
1463 {
1464 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1465 
1466 	REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst);
1467 }
1468 
enc1_dig_source_otg(struct stream_encoder * enc)1469 unsigned int enc1_dig_source_otg(
1470 	struct stream_encoder *enc)
1471 {
1472 	uint32_t tg_inst = 0;
1473 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1474 
1475 	REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst);
1476 
1477 	return tg_inst;
1478 }
1479 
enc1_stream_encoder_dp_get_pixel_format(struct stream_encoder * enc,enum dc_pixel_encoding * encoding,enum dc_color_depth * depth)1480 bool enc1_stream_encoder_dp_get_pixel_format(
1481 	struct stream_encoder *enc,
1482 	enum dc_pixel_encoding *encoding,
1483 	enum dc_color_depth *depth)
1484 {
1485 	uint32_t hw_encoding = 0;
1486 	uint32_t hw_depth = 0;
1487 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
1488 
1489 	if (enc == NULL ||
1490 		encoding == NULL ||
1491 		depth == NULL)
1492 		return false;
1493 
1494 	REG_GET_2(DP_PIXEL_FORMAT,
1495 		DP_PIXEL_ENCODING, &hw_encoding,
1496 		DP_COMPONENT_DEPTH, &hw_depth);
1497 
1498 	switch (hw_depth) {
1499 	case DP_COMPONENT_PIXEL_DEPTH_6BPC:
1500 		*depth = COLOR_DEPTH_666;
1501 		break;
1502 	case DP_COMPONENT_PIXEL_DEPTH_8BPC:
1503 		*depth = COLOR_DEPTH_888;
1504 		break;
1505 	case DP_COMPONENT_PIXEL_DEPTH_10BPC:
1506 		*depth = COLOR_DEPTH_101010;
1507 		break;
1508 	case DP_COMPONENT_PIXEL_DEPTH_12BPC:
1509 		*depth = COLOR_DEPTH_121212;
1510 		break;
1511 	case DP_COMPONENT_PIXEL_DEPTH_16BPC:
1512 		*depth = COLOR_DEPTH_161616;
1513 		break;
1514 	default:
1515 		*depth = COLOR_DEPTH_UNDEFINED;
1516 		break;
1517 	}
1518 
1519 	switch (hw_encoding) {
1520 	case DP_PIXEL_ENCODING_TYPE_RGB444:
1521 		*encoding = PIXEL_ENCODING_RGB;
1522 		break;
1523 	case DP_PIXEL_ENCODING_TYPE_YCBCR422:
1524 		*encoding = PIXEL_ENCODING_YCBCR422;
1525 		break;
1526 	case DP_PIXEL_ENCODING_TYPE_YCBCR444:
1527 	case DP_PIXEL_ENCODING_TYPE_Y_ONLY:
1528 		*encoding = PIXEL_ENCODING_YCBCR444;
1529 		break;
1530 	case DP_PIXEL_ENCODING_TYPE_YCBCR420:
1531 		*encoding = PIXEL_ENCODING_YCBCR420;
1532 		break;
1533 	default:
1534 		*encoding = PIXEL_ENCODING_UNDEFINED;
1535 		break;
1536 	}
1537 	return true;
1538 }
1539 
1540 static const struct stream_encoder_funcs dcn10_str_enc_funcs = {
1541 	.dp_set_stream_attribute =
1542 		enc1_stream_encoder_dp_set_stream_attribute,
1543 	.hdmi_set_stream_attribute =
1544 		enc1_stream_encoder_hdmi_set_stream_attribute,
1545 	.dvi_set_stream_attribute =
1546 		enc1_stream_encoder_dvi_set_stream_attribute,
1547 	.set_throttled_vcp_size =
1548 		enc1_stream_encoder_set_throttled_vcp_size,
1549 	.update_hdmi_info_packets =
1550 		enc1_stream_encoder_update_hdmi_info_packets,
1551 	.stop_hdmi_info_packets =
1552 		enc1_stream_encoder_stop_hdmi_info_packets,
1553 	.update_dp_info_packets =
1554 		enc1_stream_encoder_update_dp_info_packets,
1555 	.send_immediate_sdp_message =
1556 		enc1_stream_encoder_send_immediate_sdp_message,
1557 	.stop_dp_info_packets =
1558 		enc1_stream_encoder_stop_dp_info_packets,
1559 	.dp_blank =
1560 		enc1_stream_encoder_dp_blank,
1561 	.dp_unblank =
1562 		enc1_stream_encoder_dp_unblank,
1563 	.audio_mute_control = enc1_se_audio_mute_control,
1564 
1565 	.dp_audio_setup = enc1_se_dp_audio_setup,
1566 	.dp_audio_enable = enc1_se_dp_audio_enable,
1567 	.dp_audio_disable = enc1_se_dp_audio_disable,
1568 
1569 	.hdmi_audio_setup = enc1_se_hdmi_audio_setup,
1570 	.hdmi_audio_disable = enc1_se_hdmi_audio_disable,
1571 	.setup_stereo_sync  = enc1_setup_stereo_sync,
1572 	.set_avmute = enc1_stream_encoder_set_avmute,
1573 	.dig_connect_to_otg  = enc1_dig_connect_to_otg,
1574 	.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
1575 	.dig_source_otg = enc1_dig_source_otg,
1576 
1577 	.dp_get_pixel_format  = enc1_stream_encoder_dp_get_pixel_format,
1578 };
1579 
dcn10_stream_encoder_construct(struct dcn10_stream_encoder * enc1,struct dc_context * ctx,struct dc_bios * bp,enum engine_id eng_id,const struct dcn10_stream_enc_registers * regs,const struct dcn10_stream_encoder_shift * se_shift,const struct dcn10_stream_encoder_mask * se_mask)1580 void dcn10_stream_encoder_construct(
1581 	struct dcn10_stream_encoder *enc1,
1582 	struct dc_context *ctx,
1583 	struct dc_bios *bp,
1584 	enum engine_id eng_id,
1585 	const struct dcn10_stream_enc_registers *regs,
1586 	const struct dcn10_stream_encoder_shift *se_shift,
1587 	const struct dcn10_stream_encoder_mask *se_mask)
1588 {
1589 	enc1->base.funcs = &dcn10_str_enc_funcs;
1590 	enc1->base.ctx = ctx;
1591 	enc1->base.id = eng_id;
1592 	enc1->base.bp = bp;
1593 	enc1->regs = regs;
1594 	enc1->se_shift = se_shift;
1595 	enc1->se_mask = se_mask;
1596 	enc1->base.stream_enc_inst = eng_id - ENGINE_ID_DIGA;
1597 }
1598 
1599