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1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3  * Copyright (C) 2018-2021 Intel Corporation
4  */
5 #include <linux/firmware.h>
6 #include "iwl-drv.h"
7 #include "iwl-trans.h"
8 #include "iwl-dbg-tlv.h"
9 #include "fw/dbg.h"
10 #include "fw/runtime.h"
11 
12 /**
13  * enum iwl_dbg_tlv_type - debug TLV types
14  * @IWL_DBG_TLV_TYPE_DEBUG_INFO: debug info TLV
15  * @IWL_DBG_TLV_TYPE_BUF_ALLOC: buffer allocation TLV
16  * @IWL_DBG_TLV_TYPE_HCMD: host command TLV
17  * @IWL_DBG_TLV_TYPE_REGION: region TLV
18  * @IWL_DBG_TLV_TYPE_TRIGGER: trigger TLV
19  * @IWL_DBG_TLV_TYPE_NUM: number of debug TLVs
20  */
21 enum iwl_dbg_tlv_type {
22 	IWL_DBG_TLV_TYPE_DEBUG_INFO =
23 		IWL_UCODE_TLV_TYPE_DEBUG_INFO - IWL_UCODE_TLV_DEBUG_BASE,
24 	IWL_DBG_TLV_TYPE_BUF_ALLOC,
25 	IWL_DBG_TLV_TYPE_HCMD,
26 	IWL_DBG_TLV_TYPE_REGION,
27 	IWL_DBG_TLV_TYPE_TRIGGER,
28 	IWL_DBG_TLV_TYPE_NUM,
29 };
30 
31 /**
32  * struct iwl_dbg_tlv_ver_data -  debug TLV version struct
33  * @min_ver: min version supported
34  * @max_ver: max version supported
35  */
36 struct iwl_dbg_tlv_ver_data {
37 	int min_ver;
38 	int max_ver;
39 };
40 
41 /**
42  * struct iwl_dbg_tlv_timer_node - timer node struct
43  * @list: list of &struct iwl_dbg_tlv_timer_node
44  * @timer: timer
45  * @fwrt: &struct iwl_fw_runtime
46  * @tlv: TLV attach to the timer node
47  */
48 struct iwl_dbg_tlv_timer_node {
49 	struct list_head list;
50 	struct timer_list timer;
51 	struct iwl_fw_runtime *fwrt;
52 	struct iwl_ucode_tlv *tlv;
53 };
54 
55 static const struct iwl_dbg_tlv_ver_data
56 dbg_ver_table[IWL_DBG_TLV_TYPE_NUM] = {
57 	[IWL_DBG_TLV_TYPE_DEBUG_INFO]	= {.min_ver = 1, .max_ver = 1,},
58 	[IWL_DBG_TLV_TYPE_BUF_ALLOC]	= {.min_ver = 1, .max_ver = 1,},
59 	[IWL_DBG_TLV_TYPE_HCMD]		= {.min_ver = 1, .max_ver = 1,},
60 	[IWL_DBG_TLV_TYPE_REGION]	= {.min_ver = 1, .max_ver = 2,},
61 	[IWL_DBG_TLV_TYPE_TRIGGER]	= {.min_ver = 1, .max_ver = 1,},
62 };
63 
iwl_dbg_tlv_add(const struct iwl_ucode_tlv * tlv,struct list_head * list)64 static int iwl_dbg_tlv_add(const struct iwl_ucode_tlv *tlv,
65 			   struct list_head *list)
66 {
67 	u32 len = le32_to_cpu(tlv->length);
68 	struct iwl_dbg_tlv_node *node;
69 
70 	node = kzalloc(sizeof(*node) + len, GFP_KERNEL);
71 	if (!node)
72 		return -ENOMEM;
73 
74 	memcpy(&node->tlv, tlv, sizeof(node->tlv) + len);
75 	list_add_tail(&node->list, list);
76 
77 	return 0;
78 }
79 
iwl_dbg_tlv_ver_support(const struct iwl_ucode_tlv * tlv)80 static bool iwl_dbg_tlv_ver_support(const struct iwl_ucode_tlv *tlv)
81 {
82 	const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0];
83 	u32 type = le32_to_cpu(tlv->type);
84 	u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE;
85 	u32 ver = le32_to_cpu(hdr->version);
86 
87 	if (ver < dbg_ver_table[tlv_idx].min_ver ||
88 	    ver > dbg_ver_table[tlv_idx].max_ver)
89 		return false;
90 
91 	return true;
92 }
93 
iwl_dbg_tlv_alloc_debug_info(struct iwl_trans * trans,const struct iwl_ucode_tlv * tlv)94 static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans,
95 					const struct iwl_ucode_tlv *tlv)
96 {
97 	const struct iwl_fw_ini_debug_info_tlv *debug_info = (const void *)tlv->data;
98 
99 	if (le32_to_cpu(tlv->length) != sizeof(*debug_info))
100 		return -EINVAL;
101 
102 	IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n",
103 		     debug_info->debug_cfg_name);
104 
105 	return iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list);
106 }
107 
iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans * trans,const struct iwl_ucode_tlv * tlv)108 static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans,
109 				       const struct iwl_ucode_tlv *tlv)
110 {
111 	const struct iwl_fw_ini_allocation_tlv *alloc = (const void *)tlv->data;
112 	u32 buf_location;
113 	u32 alloc_id;
114 
115 	if (le32_to_cpu(tlv->length) != sizeof(*alloc))
116 		return -EINVAL;
117 
118 	buf_location = le32_to_cpu(alloc->buf_location);
119 	alloc_id = le32_to_cpu(alloc->alloc_id);
120 
121 	if (buf_location == IWL_FW_INI_LOCATION_INVALID ||
122 	    buf_location >= IWL_FW_INI_LOCATION_NUM)
123 		goto err;
124 
125 	if (alloc_id == IWL_FW_INI_ALLOCATION_INVALID ||
126 	    alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
127 		goto err;
128 
129 	if (buf_location == IWL_FW_INI_LOCATION_NPK_PATH &&
130 	    alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1)
131 		goto err;
132 
133 	if (buf_location == IWL_FW_INI_LOCATION_SRAM_PATH &&
134 	    alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1)
135 		goto err;
136 
137 	if (buf_location == IWL_FW_INI_LOCATION_DRAM_PATH &&
138 	    alloc->req_size == 0) {
139 		IWL_ERR(trans, "WRT: Invalid DRAM buffer allocation requested size (0)\n");
140 		return -EINVAL;
141 	}
142 
143 	trans->dbg.fw_mon_cfg[alloc_id] = *alloc;
144 
145 	return 0;
146 err:
147 	IWL_ERR(trans,
148 		"WRT: Invalid allocation id %u and/or location id %u for allocation TLV\n",
149 		alloc_id, buf_location);
150 	return -EINVAL;
151 }
152 
iwl_dbg_tlv_alloc_hcmd(struct iwl_trans * trans,const struct iwl_ucode_tlv * tlv)153 static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans,
154 				  const struct iwl_ucode_tlv *tlv)
155 {
156 	const struct iwl_fw_ini_hcmd_tlv *hcmd = (const void *)tlv->data;
157 	u32 tp = le32_to_cpu(hcmd->time_point);
158 
159 	if (le32_to_cpu(tlv->length) <= sizeof(*hcmd))
160 		return -EINVAL;
161 
162 	/* Host commands can not be sent in early time point since the FW
163 	 * is not ready
164 	 */
165 	if (tp == IWL_FW_INI_TIME_POINT_INVALID ||
166 	    tp >= IWL_FW_INI_TIME_POINT_NUM ||
167 	    tp == IWL_FW_INI_TIME_POINT_EARLY) {
168 		IWL_ERR(trans,
169 			"WRT: Invalid time point %u for host command TLV\n",
170 			tp);
171 		return -EINVAL;
172 	}
173 
174 	return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list);
175 }
176 
iwl_dbg_tlv_alloc_region(struct iwl_trans * trans,const struct iwl_ucode_tlv * tlv)177 static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans,
178 				    const struct iwl_ucode_tlv *tlv)
179 {
180 	const struct iwl_fw_ini_region_tlv *reg = (const void *)tlv->data;
181 	struct iwl_ucode_tlv **active_reg;
182 	u32 id = le32_to_cpu(reg->id);
183 	u32 type = le32_to_cpu(reg->type);
184 	u32 tlv_len = sizeof(*tlv) + le32_to_cpu(tlv->length);
185 
186 	/*
187 	 * The higher part of the ID in version 2 is irrelevant for
188 	 * us, so mask it out.
189 	 */
190 	if (le32_to_cpu(reg->hdr.version) == 2)
191 		id &= IWL_FW_INI_REGION_V2_MASK;
192 
193 	if (le32_to_cpu(tlv->length) < sizeof(*reg))
194 		return -EINVAL;
195 
196 	/* for safe use of a string from FW, limit it to IWL_FW_INI_MAX_NAME */
197 	IWL_DEBUG_FW(trans, "WRT: parsing region: %.*s\n",
198 		     IWL_FW_INI_MAX_NAME, reg->name);
199 
200 	if (id >= IWL_FW_INI_MAX_REGION_ID) {
201 		IWL_ERR(trans, "WRT: Invalid region id %u\n", id);
202 		return -EINVAL;
203 	}
204 
205 	if (type <= IWL_FW_INI_REGION_INVALID ||
206 	    type >= IWL_FW_INI_REGION_NUM) {
207 		IWL_ERR(trans, "WRT: Invalid region type %u\n", type);
208 		return -EINVAL;
209 	}
210 
211 	if (type == IWL_FW_INI_REGION_PCI_IOSF_CONFIG &&
212 	    !trans->ops->read_config32) {
213 		IWL_ERR(trans, "WRT: Unsupported region type %u\n", type);
214 		return -EOPNOTSUPP;
215 	}
216 
217 	active_reg = &trans->dbg.active_regions[id];
218 	if (*active_reg) {
219 		IWL_WARN(trans, "WRT: Overriding region id %u\n", id);
220 
221 		kfree(*active_reg);
222 	}
223 
224 	*active_reg = kmemdup(tlv, tlv_len, GFP_KERNEL);
225 	if (!*active_reg)
226 		return -ENOMEM;
227 
228 	IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type);
229 
230 	return 0;
231 }
232 
iwl_dbg_tlv_alloc_trigger(struct iwl_trans * trans,const struct iwl_ucode_tlv * tlv)233 static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans,
234 				     const struct iwl_ucode_tlv *tlv)
235 {
236 	const struct iwl_fw_ini_trigger_tlv *trig = (const void *)tlv->data;
237 	struct iwl_fw_ini_trigger_tlv *dup_trig;
238 	u32 tp = le32_to_cpu(trig->time_point);
239 	struct iwl_ucode_tlv *dup = NULL;
240 	int ret;
241 
242 	if (le32_to_cpu(tlv->length) < sizeof(*trig))
243 		return -EINVAL;
244 
245 	if (tp <= IWL_FW_INI_TIME_POINT_INVALID ||
246 	    tp >= IWL_FW_INI_TIME_POINT_NUM) {
247 		IWL_ERR(trans,
248 			"WRT: Invalid time point %u for trigger TLV\n",
249 			tp);
250 		return -EINVAL;
251 	}
252 
253 	if (!le32_to_cpu(trig->occurrences)) {
254 		dup = kmemdup(tlv, sizeof(*tlv) + le32_to_cpu(tlv->length),
255 				GFP_KERNEL);
256 		if (!dup)
257 			return -ENOMEM;
258 		dup_trig = (void *)dup->data;
259 		dup_trig->occurrences = cpu_to_le32(-1);
260 		tlv = dup;
261 	}
262 
263 	ret = iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list);
264 	kfree(dup);
265 
266 	return ret;
267 }
268 
269 static int (*dbg_tlv_alloc[])(struct iwl_trans *trans,
270 			      const struct iwl_ucode_tlv *tlv) = {
271 	[IWL_DBG_TLV_TYPE_DEBUG_INFO]	= iwl_dbg_tlv_alloc_debug_info,
272 	[IWL_DBG_TLV_TYPE_BUF_ALLOC]	= iwl_dbg_tlv_alloc_buf_alloc,
273 	[IWL_DBG_TLV_TYPE_HCMD]		= iwl_dbg_tlv_alloc_hcmd,
274 	[IWL_DBG_TLV_TYPE_REGION]	= iwl_dbg_tlv_alloc_region,
275 	[IWL_DBG_TLV_TYPE_TRIGGER]	= iwl_dbg_tlv_alloc_trigger,
276 };
277 
iwl_dbg_tlv_alloc(struct iwl_trans * trans,const struct iwl_ucode_tlv * tlv,bool ext)278 void iwl_dbg_tlv_alloc(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv,
279 		       bool ext)
280 {
281 	const struct iwl_fw_ini_header *hdr = (const void *)&tlv->data[0];
282 	u32 type = le32_to_cpu(tlv->type);
283 	u32 tlv_idx = type - IWL_UCODE_TLV_DEBUG_BASE;
284 	u32 domain = le32_to_cpu(hdr->domain);
285 	enum iwl_ini_cfg_state *cfg_state = ext ?
286 		&trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg;
287 	int ret;
288 
289 	if (domain != IWL_FW_INI_DOMAIN_ALWAYS_ON &&
290 	    !(domain & trans->dbg.domains_bitmap)) {
291 		IWL_DEBUG_FW(trans,
292 			     "WRT: Skipping TLV with disabled domain 0x%0x (0x%0x)\n",
293 			     domain, trans->dbg.domains_bitmap);
294 		return;
295 	}
296 
297 	if (tlv_idx >= ARRAY_SIZE(dbg_tlv_alloc) || !dbg_tlv_alloc[tlv_idx]) {
298 		IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type);
299 		goto out_err;
300 	}
301 
302 	if (!iwl_dbg_tlv_ver_support(tlv)) {
303 		IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type,
304 			le32_to_cpu(hdr->version));
305 		goto out_err;
306 	}
307 
308 	ret = dbg_tlv_alloc[tlv_idx](trans, tlv);
309 	if (ret) {
310 		IWL_ERR(trans,
311 			"WRT: Failed to allocate TLV 0x%x, ret %d, (ext=%d)\n",
312 			type, ret, ext);
313 		goto out_err;
314 	}
315 
316 	if (*cfg_state == IWL_INI_CFG_STATE_NOT_LOADED)
317 		*cfg_state = IWL_INI_CFG_STATE_LOADED;
318 
319 	return;
320 
321 out_err:
322 	*cfg_state = IWL_INI_CFG_STATE_CORRUPTED;
323 }
324 
iwl_dbg_tlv_del_timers(struct iwl_trans * trans)325 void iwl_dbg_tlv_del_timers(struct iwl_trans *trans)
326 {
327 	struct list_head *timer_list = &trans->dbg.periodic_trig_list;
328 	struct iwl_dbg_tlv_timer_node *node, *tmp;
329 
330 	list_for_each_entry_safe(node, tmp, timer_list, list) {
331 		del_timer_sync(&node->timer);
332 		list_del(&node->list);
333 		kfree(node);
334 	}
335 }
336 IWL_EXPORT_SYMBOL(iwl_dbg_tlv_del_timers);
337 
iwl_dbg_tlv_fragments_free(struct iwl_trans * trans,enum iwl_fw_ini_allocation_id alloc_id)338 static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans,
339 				       enum iwl_fw_ini_allocation_id alloc_id)
340 {
341 	struct iwl_fw_mon *fw_mon;
342 	int i;
343 
344 	if (alloc_id <= IWL_FW_INI_ALLOCATION_INVALID ||
345 	    alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
346 		return;
347 
348 	fw_mon = &trans->dbg.fw_mon_ini[alloc_id];
349 
350 	for (i = 0; i < fw_mon->num_frags; i++) {
351 		struct iwl_dram_data *frag = &fw_mon->frags[i];
352 
353 		dma_free_coherent(trans->dev, frag->size, frag->block,
354 				  frag->physical);
355 
356 		frag->physical = 0;
357 		frag->block = NULL;
358 		frag->size = 0;
359 	}
360 
361 	kfree(fw_mon->frags);
362 	fw_mon->frags = NULL;
363 	fw_mon->num_frags = 0;
364 }
365 
iwl_dbg_tlv_free(struct iwl_trans * trans)366 void iwl_dbg_tlv_free(struct iwl_trans *trans)
367 {
368 	struct iwl_dbg_tlv_node *tlv_node, *tlv_node_tmp;
369 	int i;
370 
371 	iwl_dbg_tlv_del_timers(trans);
372 
373 	for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) {
374 		struct iwl_ucode_tlv **active_reg =
375 			&trans->dbg.active_regions[i];
376 
377 		kfree(*active_reg);
378 		*active_reg = NULL;
379 	}
380 
381 	list_for_each_entry_safe(tlv_node, tlv_node_tmp,
382 				 &trans->dbg.debug_info_tlv_list, list) {
383 		list_del(&tlv_node->list);
384 		kfree(tlv_node);
385 	}
386 
387 	for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
388 		struct iwl_dbg_tlv_time_point_data *tp =
389 			&trans->dbg.time_point[i];
390 
391 		list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->trig_list,
392 					 list) {
393 			list_del(&tlv_node->list);
394 			kfree(tlv_node);
395 		}
396 
397 		list_for_each_entry_safe(tlv_node, tlv_node_tmp, &tp->hcmd_list,
398 					 list) {
399 			list_del(&tlv_node->list);
400 			kfree(tlv_node);
401 		}
402 
403 		list_for_each_entry_safe(tlv_node, tlv_node_tmp,
404 					 &tp->active_trig_list, list) {
405 			list_del(&tlv_node->list);
406 			kfree(tlv_node);
407 		}
408 	}
409 
410 	for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++)
411 		iwl_dbg_tlv_fragments_free(trans, i);
412 }
413 
iwl_dbg_tlv_parse_bin(struct iwl_trans * trans,const u8 * data,size_t len)414 static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data,
415 				 size_t len)
416 {
417 	const struct iwl_ucode_tlv *tlv;
418 	u32 tlv_len;
419 
420 	while (len >= sizeof(*tlv)) {
421 		len -= sizeof(*tlv);
422 		tlv = (void *)data;
423 
424 		tlv_len = le32_to_cpu(tlv->length);
425 
426 		if (len < tlv_len) {
427 			IWL_ERR(trans, "invalid TLV len: %zd/%u\n",
428 				len, tlv_len);
429 			return -EINVAL;
430 		}
431 		len -= ALIGN(tlv_len, 4);
432 		data += sizeof(*tlv) + ALIGN(tlv_len, 4);
433 
434 		iwl_dbg_tlv_alloc(trans, tlv, true);
435 	}
436 
437 	return 0;
438 }
439 
iwl_dbg_tlv_load_bin(struct device * dev,struct iwl_trans * trans)440 void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans)
441 {
442 	const struct firmware *fw;
443 	const char *yoyo_bin = "iwl-debug-yoyo.bin";
444 	int res;
445 
446 	if (!iwlwifi_mod_params.enable_ini ||
447 	    trans->trans_cfg->device_family <= IWL_DEVICE_FAMILY_9000)
448 		return;
449 
450 	res = firmware_request_nowarn(&fw, yoyo_bin, dev);
451 	IWL_DEBUG_FW(trans, "%s %s\n", res ? "didn't load" : "loaded", yoyo_bin);
452 
453 	if (res)
454 		return;
455 
456 	iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size);
457 
458 	release_firmware(fw);
459 }
460 
iwl_dbg_tlv_init(struct iwl_trans * trans)461 void iwl_dbg_tlv_init(struct iwl_trans *trans)
462 {
463 	int i;
464 
465 	INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list);
466 	INIT_LIST_HEAD(&trans->dbg.periodic_trig_list);
467 
468 	for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
469 		struct iwl_dbg_tlv_time_point_data *tp =
470 			&trans->dbg.time_point[i];
471 
472 		INIT_LIST_HEAD(&tp->trig_list);
473 		INIT_LIST_HEAD(&tp->hcmd_list);
474 		INIT_LIST_HEAD(&tp->active_trig_list);
475 	}
476 }
477 
iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime * fwrt,struct iwl_dram_data * frag,u32 pages)478 static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt,
479 				      struct iwl_dram_data *frag, u32 pages)
480 {
481 	void *block = NULL;
482 	dma_addr_t physical;
483 
484 	if (!frag || frag->size || !pages)
485 		return -EIO;
486 
487 	/*
488 	 * We try to allocate as many pages as we can, starting with
489 	 * the requested amount and going down until we can allocate
490 	 * something.  Because of DIV_ROUND_UP(), pages will never go
491 	 * down to 0 and stop the loop, so stop when pages reaches 1,
492 	 * which is too small anyway.
493 	 */
494 	while (pages > 1) {
495 		block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE,
496 					   &physical,
497 					   GFP_KERNEL | __GFP_NOWARN);
498 		if (block)
499 			break;
500 
501 		IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n",
502 			 pages * PAGE_SIZE);
503 
504 		pages = DIV_ROUND_UP(pages, 2);
505 	}
506 
507 	if (!block)
508 		return -ENOMEM;
509 
510 	frag->physical = physical;
511 	frag->block = block;
512 	frag->size = pages * PAGE_SIZE;
513 
514 	return pages;
515 }
516 
iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime * fwrt,enum iwl_fw_ini_allocation_id alloc_id)517 static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt,
518 				       enum iwl_fw_ini_allocation_id alloc_id)
519 {
520 	struct iwl_fw_mon *fw_mon;
521 	struct iwl_fw_ini_allocation_tlv *fw_mon_cfg;
522 	u32 num_frags, remain_pages, frag_pages;
523 	int i;
524 
525 	if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID ||
526 	    alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
527 		return -EIO;
528 
529 	fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id];
530 	fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
531 
532 	if (fw_mon->num_frags ||
533 	    fw_mon_cfg->buf_location !=
534 	    cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH))
535 		return 0;
536 
537 	num_frags = le32_to_cpu(fw_mon_cfg->max_frags_num);
538 	if (!fw_has_capa(&fwrt->fw->ucode_capa,
539 			 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP)) {
540 		if (alloc_id != IWL_FW_INI_ALLOCATION_ID_DBGC1)
541 			return -EIO;
542 		num_frags = 1;
543 	}
544 
545 	remain_pages = DIV_ROUND_UP(le32_to_cpu(fw_mon_cfg->req_size),
546 				    PAGE_SIZE);
547 	num_frags = min_t(u32, num_frags, BUF_ALLOC_MAX_NUM_FRAGS);
548 	num_frags = min_t(u32, num_frags, remain_pages);
549 	frag_pages = DIV_ROUND_UP(remain_pages, num_frags);
550 
551 	fw_mon->frags = kcalloc(num_frags, sizeof(*fw_mon->frags), GFP_KERNEL);
552 	if (!fw_mon->frags)
553 		return -ENOMEM;
554 
555 	for (i = 0; i < num_frags; i++) {
556 		int pages = min_t(u32, frag_pages, remain_pages);
557 
558 		IWL_DEBUG_FW(fwrt,
559 			     "WRT: Allocating DRAM buffer (alloc_id=%u, fragment=%u, size=0x%lx)\n",
560 			     alloc_id, i, pages * PAGE_SIZE);
561 
562 		pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i],
563 						   pages);
564 		if (pages < 0) {
565 			u32 alloc_size = le32_to_cpu(fw_mon_cfg->req_size) -
566 				(remain_pages * PAGE_SIZE);
567 
568 			if (alloc_size < le32_to_cpu(fw_mon_cfg->min_size)) {
569 				iwl_dbg_tlv_fragments_free(fwrt->trans,
570 							   alloc_id);
571 				return pages;
572 			}
573 			break;
574 		}
575 
576 		remain_pages -= pages;
577 		fw_mon->num_frags++;
578 	}
579 
580 	return 0;
581 }
582 
iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime * fwrt,enum iwl_fw_ini_allocation_id alloc_id)583 static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt,
584 				    enum iwl_fw_ini_allocation_id alloc_id)
585 {
586 	struct iwl_fw_mon *fw_mon;
587 	u32 remain_frags, num_commands;
588 	int i, fw_mon_idx = 0;
589 
590 	if (!fw_has_capa(&fwrt->fw->ucode_capa,
591 			 IWL_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP))
592 		return 0;
593 
594 	if (alloc_id < IWL_FW_INI_ALLOCATION_INVALID ||
595 	    alloc_id >= IWL_FW_INI_ALLOCATION_NUM)
596 		return -EIO;
597 
598 	if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
599 	    IWL_FW_INI_LOCATION_DRAM_PATH)
600 		return 0;
601 
602 	fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
603 
604 	/* the first fragment of DBGC1 is given to the FW via register
605 	 * or context info
606 	 */
607 	if (alloc_id == IWL_FW_INI_ALLOCATION_ID_DBGC1)
608 		fw_mon_idx++;
609 
610 	remain_frags = fw_mon->num_frags - fw_mon_idx;
611 	if (!remain_frags)
612 		return 0;
613 
614 	num_commands = DIV_ROUND_UP(remain_frags, BUF_ALLOC_MAX_NUM_FRAGS);
615 
616 	IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n",
617 		     alloc_id);
618 
619 	for (i = 0; i < num_commands; i++) {
620 		u32 num_frags = min_t(u32, remain_frags,
621 				      BUF_ALLOC_MAX_NUM_FRAGS);
622 		struct iwl_buf_alloc_cmd data = {
623 			.alloc_id = cpu_to_le32(alloc_id),
624 			.num_frags = cpu_to_le32(num_frags),
625 			.buf_location =
626 				cpu_to_le32(IWL_FW_INI_LOCATION_DRAM_PATH),
627 		};
628 		struct iwl_host_cmd hcmd = {
629 			.id = WIDE_ID(DEBUG_GROUP, BUFFER_ALLOCATION),
630 			.data[0] = &data,
631 			.len[0] = sizeof(data),
632 			.flags = CMD_SEND_IN_RFKILL,
633 		};
634 		int ret, j;
635 
636 		for (j = 0; j < num_frags; j++) {
637 			struct iwl_buf_alloc_frag *frag = &data.frags[j];
638 			struct iwl_dram_data *fw_mon_frag =
639 				&fw_mon->frags[fw_mon_idx++];
640 
641 			frag->addr = cpu_to_le64(fw_mon_frag->physical);
642 			frag->size = cpu_to_le32(fw_mon_frag->size);
643 		}
644 		ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
645 		if (ret)
646 			return ret;
647 
648 		remain_frags -= num_frags;
649 	}
650 
651 	return 0;
652 }
653 
iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime * fwrt)654 static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt)
655 {
656 	int ret, i;
657 
658 	for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) {
659 		ret = iwl_dbg_tlv_apply_buffer(fwrt, i);
660 		if (ret)
661 			IWL_WARN(fwrt,
662 				 "WRT: Failed to apply DRAM buffer for allocation id %d, ret=%d\n",
663 				 i, ret);
664 	}
665 }
666 
iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime * fwrt,struct list_head * hcmd_list)667 static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt,
668 				   struct list_head *hcmd_list)
669 {
670 	struct iwl_dbg_tlv_node *node;
671 
672 	list_for_each_entry(node, hcmd_list, list) {
673 		struct iwl_fw_ini_hcmd_tlv *hcmd = (void *)node->tlv.data;
674 		struct iwl_fw_ini_hcmd *hcmd_data = &hcmd->hcmd;
675 		u16 hcmd_len = le32_to_cpu(node->tlv.length) - sizeof(*hcmd);
676 		struct iwl_host_cmd cmd = {
677 			.id = WIDE_ID(hcmd_data->group, hcmd_data->id),
678 			.len = { hcmd_len, },
679 			.data = { hcmd_data->data, },
680 		};
681 
682 		iwl_trans_send_cmd(fwrt->trans, &cmd);
683 	}
684 }
685 
iwl_dbg_tlv_periodic_trig_handler(struct timer_list * t)686 static void iwl_dbg_tlv_periodic_trig_handler(struct timer_list *t)
687 {
688 	struct iwl_dbg_tlv_timer_node *timer_node =
689 		from_timer(timer_node, t, timer);
690 	struct iwl_fwrt_dump_data dump_data = {
691 		.trig = (void *)timer_node->tlv->data,
692 	};
693 	int ret;
694 
695 	ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data, false);
696 	if (!ret || ret == -EBUSY) {
697 		u32 occur = le32_to_cpu(dump_data.trig->occurrences);
698 		u32 collect_interval = le32_to_cpu(dump_data.trig->data[0]);
699 
700 		if (!occur)
701 			return;
702 
703 		mod_timer(t, jiffies + msecs_to_jiffies(collect_interval));
704 	}
705 }
706 
iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime * fwrt)707 static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt)
708 {
709 	struct iwl_dbg_tlv_node *node;
710 	struct list_head *trig_list =
711 		&fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list;
712 
713 	list_for_each_entry(node, trig_list, list) {
714 		struct iwl_fw_ini_trigger_tlv *trig = (void *)node->tlv.data;
715 		struct iwl_dbg_tlv_timer_node *timer_node;
716 		u32 occur = le32_to_cpu(trig->occurrences), collect_interval;
717 		u32 min_interval = 100;
718 
719 		if (!occur)
720 			continue;
721 
722 		/* make sure there is at least one dword of data for the
723 		 * interval value
724 		 */
725 		if (le32_to_cpu(node->tlv.length) <
726 		    sizeof(*trig) + sizeof(__le32)) {
727 			IWL_ERR(fwrt,
728 				"WRT: Invalid periodic trigger data was not given\n");
729 			continue;
730 		}
731 
732 		if (le32_to_cpu(trig->data[0]) < min_interval) {
733 			IWL_WARN(fwrt,
734 				 "WRT: Override min interval from %u to %u msec\n",
735 				 le32_to_cpu(trig->data[0]), min_interval);
736 			trig->data[0] = cpu_to_le32(min_interval);
737 		}
738 
739 		collect_interval = le32_to_cpu(trig->data[0]);
740 
741 		timer_node = kzalloc(sizeof(*timer_node), GFP_KERNEL);
742 		if (!timer_node) {
743 			IWL_ERR(fwrt,
744 				"WRT: Failed to allocate periodic trigger\n");
745 			continue;
746 		}
747 
748 		timer_node->fwrt = fwrt;
749 		timer_node->tlv = &node->tlv;
750 		timer_setup(&timer_node->timer,
751 			    iwl_dbg_tlv_periodic_trig_handler, 0);
752 
753 		list_add_tail(&timer_node->list,
754 			      &fwrt->trans->dbg.periodic_trig_list);
755 
756 		IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n");
757 
758 		mod_timer(&timer_node->timer,
759 			  jiffies + msecs_to_jiffies(collect_interval));
760 	}
761 }
762 
is_trig_data_contained(const struct iwl_ucode_tlv * new,const struct iwl_ucode_tlv * old)763 static bool is_trig_data_contained(const struct iwl_ucode_tlv *new,
764 				   const struct iwl_ucode_tlv *old)
765 {
766 	const struct iwl_fw_ini_trigger_tlv *new_trig = (const void *)new->data;
767 	const struct iwl_fw_ini_trigger_tlv *old_trig = (const void *)old->data;
768 	const __le32 *new_data = new_trig->data, *old_data = old_trig->data;
769 	u32 new_dwords_num = iwl_tlv_array_len(new, new_trig, data);
770 	u32 old_dwords_num = iwl_tlv_array_len(old, old_trig, data);
771 	int i, j;
772 
773 	for (i = 0; i < new_dwords_num; i++) {
774 		bool match = false;
775 
776 		for (j = 0; j < old_dwords_num; j++) {
777 			if (new_data[i] == old_data[j]) {
778 				match = true;
779 				break;
780 			}
781 		}
782 		if (!match)
783 			return false;
784 	}
785 
786 	return true;
787 }
788 
iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime * fwrt,struct iwl_ucode_tlv * trig_tlv,struct iwl_dbg_tlv_node * node)789 static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt,
790 					  struct iwl_ucode_tlv *trig_tlv,
791 					  struct iwl_dbg_tlv_node *node)
792 {
793 	struct iwl_ucode_tlv *node_tlv = &node->tlv;
794 	struct iwl_fw_ini_trigger_tlv *node_trig = (void *)node_tlv->data;
795 	struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data;
796 	u32 policy = le32_to_cpu(trig->apply_policy);
797 	u32 size = le32_to_cpu(trig_tlv->length);
798 	u32 trig_data_len = size - sizeof(*trig);
799 	u32 offset = 0;
800 
801 	if (!(policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_DATA)) {
802 		u32 data_len = le32_to_cpu(node_tlv->length) -
803 			sizeof(*node_trig);
804 
805 		IWL_DEBUG_FW(fwrt,
806 			     "WRT: Appending trigger data (time point %u)\n",
807 			     le32_to_cpu(trig->time_point));
808 
809 		offset += data_len;
810 		size += data_len;
811 	} else {
812 		IWL_DEBUG_FW(fwrt,
813 			     "WRT: Overriding trigger data (time point %u)\n",
814 			     le32_to_cpu(trig->time_point));
815 	}
816 
817 	if (size != le32_to_cpu(node_tlv->length)) {
818 		struct list_head *prev = node->list.prev;
819 		struct iwl_dbg_tlv_node *tmp;
820 
821 		list_del(&node->list);
822 
823 		tmp = krealloc(node, sizeof(*node) + size, GFP_KERNEL);
824 		if (!tmp) {
825 			IWL_WARN(fwrt,
826 				 "WRT: No memory to override trigger (time point %u)\n",
827 				 le32_to_cpu(trig->time_point));
828 
829 			list_add(&node->list, prev);
830 
831 			return -ENOMEM;
832 		}
833 
834 		list_add(&tmp->list, prev);
835 		node_tlv = &tmp->tlv;
836 		node_trig = (void *)node_tlv->data;
837 	}
838 
839 	memcpy((u8 *)node_trig->data + offset, trig->data, trig_data_len);
840 	node_tlv->length = cpu_to_le32(size);
841 
842 	if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_CFG) {
843 		IWL_DEBUG_FW(fwrt,
844 			     "WRT: Overriding trigger configuration (time point %u)\n",
845 			     le32_to_cpu(trig->time_point));
846 
847 		/* the first 11 dwords are configuration related */
848 		memcpy(node_trig, trig, sizeof(__le32) * 11);
849 	}
850 
851 	if (policy & IWL_FW_INI_APPLY_POLICY_OVERRIDE_REGIONS) {
852 		IWL_DEBUG_FW(fwrt,
853 			     "WRT: Overriding trigger regions (time point %u)\n",
854 			     le32_to_cpu(trig->time_point));
855 
856 		node_trig->regions_mask = trig->regions_mask;
857 	} else {
858 		IWL_DEBUG_FW(fwrt,
859 			     "WRT: Appending trigger regions (time point %u)\n",
860 			     le32_to_cpu(trig->time_point));
861 
862 		node_trig->regions_mask |= trig->regions_mask;
863 	}
864 
865 	return 0;
866 }
867 
868 static int
iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime * fwrt,struct list_head * trig_list,struct iwl_ucode_tlv * trig_tlv)869 iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt,
870 			       struct list_head *trig_list,
871 			       struct iwl_ucode_tlv *trig_tlv)
872 {
873 	struct iwl_fw_ini_trigger_tlv *trig = (void *)trig_tlv->data;
874 	struct iwl_dbg_tlv_node *node, *match = NULL;
875 	u32 policy = le32_to_cpu(trig->apply_policy);
876 
877 	list_for_each_entry(node, trig_list, list) {
878 		if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_TIME_POINT))
879 			break;
880 
881 		if (!(policy & IWL_FW_INI_APPLY_POLICY_MATCH_DATA) ||
882 		    is_trig_data_contained(trig_tlv, &node->tlv)) {
883 			match = node;
884 			break;
885 		}
886 	}
887 
888 	if (!match) {
889 		IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n",
890 			     le32_to_cpu(trig->time_point));
891 		return iwl_dbg_tlv_add(trig_tlv, trig_list);
892 	}
893 
894 	return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match);
895 }
896 
897 static void
iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime * fwrt,struct iwl_dbg_tlv_time_point_data * tp)898 iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt,
899 				 struct iwl_dbg_tlv_time_point_data *tp)
900 {
901 	struct iwl_dbg_tlv_node *node;
902 	struct list_head *trig_list = &tp->trig_list;
903 	struct list_head *active_trig_list = &tp->active_trig_list;
904 
905 	list_for_each_entry(node, trig_list, list) {
906 		struct iwl_ucode_tlv *tlv = &node->tlv;
907 
908 		iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv);
909 	}
910 }
911 
iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data,union iwl_dbg_tlv_tp_data * tp_data,u32 trig_data)912 static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt,
913 				     struct iwl_fwrt_dump_data *dump_data,
914 				     union iwl_dbg_tlv_tp_data *tp_data,
915 				     u32 trig_data)
916 {
917 	struct iwl_rx_packet *pkt = tp_data->fw_pkt;
918 	struct iwl_cmd_header *wanted_hdr = (void *)&trig_data;
919 
920 	if (pkt && (pkt->hdr.cmd == wanted_hdr->cmd &&
921 		    pkt->hdr.group_id == wanted_hdr->group_id)) {
922 		struct iwl_rx_packet *fw_pkt =
923 			kmemdup(pkt,
924 				sizeof(*pkt) + iwl_rx_packet_payload_len(pkt),
925 				GFP_ATOMIC);
926 
927 		if (!fw_pkt)
928 			return false;
929 
930 		dump_data->fw_pkt = fw_pkt;
931 
932 		return true;
933 	}
934 
935 	return false;
936 }
937 
938 static int
iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime * fwrt,bool sync,struct list_head * active_trig_list,union iwl_dbg_tlv_tp_data * tp_data,bool (* data_check)(struct iwl_fw_runtime * fwrt,struct iwl_fwrt_dump_data * dump_data,union iwl_dbg_tlv_tp_data * tp_data,u32 trig_data))939 iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt, bool sync,
940 		       struct list_head *active_trig_list,
941 		       union iwl_dbg_tlv_tp_data *tp_data,
942 		       bool (*data_check)(struct iwl_fw_runtime *fwrt,
943 					  struct iwl_fwrt_dump_data *dump_data,
944 					  union iwl_dbg_tlv_tp_data *tp_data,
945 					  u32 trig_data))
946 {
947 	struct iwl_dbg_tlv_node *node;
948 
949 	list_for_each_entry(node, active_trig_list, list) {
950 		struct iwl_fwrt_dump_data dump_data = {
951 			.trig = (void *)node->tlv.data,
952 		};
953 		u32 num_data = iwl_tlv_array_len(&node->tlv, dump_data.trig,
954 						 data);
955 		int ret, i;
956 
957 		if (!num_data) {
958 			ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync);
959 			if (ret)
960 				return ret;
961 		}
962 
963 		for (i = 0; i < num_data; i++) {
964 			if (!data_check ||
965 			    data_check(fwrt, &dump_data, tp_data,
966 				       le32_to_cpu(dump_data.trig->data[i]))) {
967 				ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync);
968 				if (ret)
969 					return ret;
970 
971 				break;
972 			}
973 		}
974 	}
975 
976 	return 0;
977 }
978 
iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime * fwrt)979 static void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt)
980 {
981 	enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest;
982 	int ret, i;
983 	u32 failed_alloc = 0;
984 
985 	if (*ini_dest != IWL_FW_INI_LOCATION_INVALID)
986 		return;
987 
988 	IWL_DEBUG_FW(fwrt,
989 		     "WRT: Generating active triggers list, domain 0x%x\n",
990 		     fwrt->trans->dbg.domains_bitmap);
991 
992 	for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) {
993 		struct iwl_dbg_tlv_time_point_data *tp =
994 			&fwrt->trans->dbg.time_point[i];
995 
996 		iwl_dbg_tlv_gen_active_trig_list(fwrt, tp);
997 	}
998 
999 	*ini_dest = IWL_FW_INI_LOCATION_INVALID;
1000 	for (i = 0; i < IWL_FW_INI_ALLOCATION_NUM; i++) {
1001 		struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
1002 			&fwrt->trans->dbg.fw_mon_cfg[i];
1003 		u32 dest = le32_to_cpu(fw_mon_cfg->buf_location);
1004 
1005 		if (dest == IWL_FW_INI_LOCATION_INVALID)
1006 			continue;
1007 
1008 		if (*ini_dest == IWL_FW_INI_LOCATION_INVALID)
1009 			*ini_dest = dest;
1010 
1011 		if (dest != *ini_dest)
1012 			continue;
1013 
1014 		ret = iwl_dbg_tlv_alloc_fragments(fwrt, i);
1015 
1016 		if (ret) {
1017 			IWL_WARN(fwrt,
1018 				 "WRT: Failed to allocate DRAM buffer for allocation id %d, ret=%d\n",
1019 				 i, ret);
1020 			failed_alloc |= BIT(i);
1021 		}
1022 	}
1023 
1024 	if (!failed_alloc)
1025 		return;
1026 
1027 	for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions) && failed_alloc; i++) {
1028 		struct iwl_fw_ini_region_tlv *reg;
1029 		struct iwl_ucode_tlv **active_reg =
1030 			&fwrt->trans->dbg.active_regions[i];
1031 		u32 reg_type;
1032 
1033 		if (!*active_reg)
1034 			continue;
1035 
1036 		reg = (void *)(*active_reg)->data;
1037 		reg_type = le32_to_cpu(reg->type);
1038 
1039 		if (reg_type != IWL_FW_INI_REGION_DRAM_BUFFER ||
1040 		    !(BIT(le32_to_cpu(reg->dram_alloc_id)) & failed_alloc))
1041 			continue;
1042 
1043 		IWL_DEBUG_FW(fwrt,
1044 			     "WRT: removing allocation id %d from region id %d\n",
1045 			     le32_to_cpu(reg->dram_alloc_id), i);
1046 
1047 		failed_alloc &= ~le32_to_cpu(reg->dram_alloc_id);
1048 		fwrt->trans->dbg.unsupported_region_msk |= BIT(i);
1049 
1050 		kfree(*active_reg);
1051 		*active_reg = NULL;
1052 	}
1053 }
1054 
_iwl_dbg_tlv_time_point(struct iwl_fw_runtime * fwrt,enum iwl_fw_ini_time_point tp_id,union iwl_dbg_tlv_tp_data * tp_data,bool sync)1055 void _iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt,
1056 			     enum iwl_fw_ini_time_point tp_id,
1057 			     union iwl_dbg_tlv_tp_data *tp_data,
1058 			     bool sync)
1059 {
1060 	struct list_head *hcmd_list, *trig_list;
1061 
1062 	if (!iwl_trans_dbg_ini_valid(fwrt->trans) ||
1063 	    tp_id == IWL_FW_INI_TIME_POINT_INVALID ||
1064 	    tp_id >= IWL_FW_INI_TIME_POINT_NUM)
1065 		return;
1066 
1067 	hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list;
1068 	trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list;
1069 
1070 	switch (tp_id) {
1071 	case IWL_FW_INI_TIME_POINT_EARLY:
1072 		iwl_dbg_tlv_init_cfg(fwrt);
1073 		iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL);
1074 		break;
1075 	case IWL_FW_INI_TIME_POINT_AFTER_ALIVE:
1076 		iwl_dbg_tlv_apply_buffers(fwrt);
1077 		iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1078 		iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL);
1079 		break;
1080 	case IWL_FW_INI_TIME_POINT_PERIODIC:
1081 		iwl_dbg_tlv_set_periodic_trigs(fwrt);
1082 		iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1083 		break;
1084 	case IWL_FW_INI_TIME_POINT_FW_RSP_OR_NOTIF:
1085 	case IWL_FW_INI_TIME_POINT_MISSED_BEACONS:
1086 	case IWL_FW_INI_TIME_POINT_FW_DHC_NOTIFICATION:
1087 		iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1088 		iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data,
1089 				       iwl_dbg_tlv_check_fw_pkt);
1090 		break;
1091 	default:
1092 		iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1093 		iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL);
1094 		break;
1095 	}
1096 }
1097 IWL_EXPORT_SYMBOL(_iwl_dbg_tlv_time_point);
1098