1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright © 2014 Intel Corporation
4 */
5
6 #ifndef __GEN8_ENGINE_CS_H__
7 #define __GEN8_ENGINE_CS_H__
8
9 #include <linux/string.h>
10 #include <linux/types.h>
11
12 #include "i915_gem.h" /* GEM_BUG_ON */
13
14 #include "intel_gpu_commands.h"
15
16 struct i915_request;
17
18 int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode);
19 int gen11_emit_flush_rcs(struct i915_request *rq, u32 mode);
20 int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode);
21
22 int gen8_emit_flush_xcs(struct i915_request *rq, u32 mode);
23 int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode);
24
25 int gen8_emit_init_breadcrumb(struct i915_request *rq);
26
27 int gen8_emit_bb_start_noarb(struct i915_request *rq,
28 u64 offset, u32 len,
29 const unsigned int flags);
30 int gen8_emit_bb_start(struct i915_request *rq,
31 u64 offset, u32 len,
32 const unsigned int flags);
33
34 u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
35 u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
36
37 u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
38 u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
39 u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
40
41 static inline u32 *
__gen8_emit_pipe_control(u32 * batch,u32 flags0,u32 flags1,u32 offset)42 __gen8_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset)
43 {
44 memset(batch, 0, 6 * sizeof(u32));
45
46 batch[0] = GFX_OP_PIPE_CONTROL(6) | flags0;
47 batch[1] = flags1;
48 batch[2] = offset;
49
50 return batch + 6;
51 }
52
gen8_emit_pipe_control(u32 * batch,u32 flags,u32 offset)53 static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset)
54 {
55 return __gen8_emit_pipe_control(batch, 0, flags, offset);
56 }
57
gen12_emit_pipe_control(u32 * batch,u32 flags0,u32 flags1,u32 offset)58 static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset)
59 {
60 return __gen8_emit_pipe_control(batch, flags0, flags1, offset);
61 }
62
63 static inline u32 *
__gen8_emit_write_rcs(u32 * cs,u32 value,u32 offset,u32 flags0,u32 flags1)64 __gen8_emit_write_rcs(u32 *cs, u32 value, u32 offset, u32 flags0, u32 flags1)
65 {
66 *cs++ = GFX_OP_PIPE_CONTROL(6) | flags0;
67 *cs++ = flags1 | PIPE_CONTROL_QW_WRITE;
68 *cs++ = offset;
69 *cs++ = 0;
70 *cs++ = value;
71 *cs++ = 0; /* We're thrashing one extra dword. */
72
73 return cs;
74 }
75
76 static inline u32*
gen8_emit_ggtt_write_rcs(u32 * cs,u32 value,u32 gtt_offset,u32 flags)77 gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
78 {
79 /* We're using qword write, offset should be aligned to 8 bytes. */
80 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
81
82 return __gen8_emit_write_rcs(cs,
83 value,
84 gtt_offset,
85 0,
86 flags | PIPE_CONTROL_GLOBAL_GTT_IVB);
87 }
88
89 static inline u32*
gen12_emit_ggtt_write_rcs(u32 * cs,u32 value,u32 gtt_offset,u32 flags0,u32 flags1)90 gen12_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags0, u32 flags1)
91 {
92 /* We're using qword write, offset should be aligned to 8 bytes. */
93 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
94
95 return __gen8_emit_write_rcs(cs,
96 value,
97 gtt_offset,
98 flags0,
99 flags1 | PIPE_CONTROL_GLOBAL_GTT_IVB);
100 }
101
102 static inline u32 *
__gen8_emit_flush_dw(u32 * cs,u32 value,u32 gtt_offset,u32 flags)103 __gen8_emit_flush_dw(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
104 {
105 *cs++ = (MI_FLUSH_DW + 1) | flags;
106 *cs++ = gtt_offset;
107 *cs++ = 0;
108 *cs++ = value;
109
110 return cs;
111 }
112
113 static inline u32 *
gen8_emit_ggtt_write(u32 * cs,u32 value,u32 gtt_offset,u32 flags)114 gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags)
115 {
116 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
117 GEM_BUG_ON(gtt_offset & (1 << 5));
118 /* Offset should be aligned to 8 bytes for both (QW/DW) write types */
119 GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));
120
121 return __gen8_emit_flush_dw(cs,
122 value,
123 gtt_offset | MI_FLUSH_DW_USE_GTT,
124 flags | MI_FLUSH_DW_OP_STOREDW);
125 }
126
127 #endif /* __GEN8_ENGINE_CS_H__ */
128