1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
3
4 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */
5 #define __DISABLE_TRACE_MMIO__
6
7 #include <linux/acpi.h>
8 #include <linux/clk.h>
9 #include <linux/slab.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/io.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_platform.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/platform_device.h>
17 #include <linux/qcom-geni-se.h>
18
19 /**
20 * DOC: Overview
21 *
22 * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced
23 * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper
24 * controller. QUP Wrapper is designed to support various serial bus protocols
25 * like UART, SPI, I2C, I3C, etc.
26 */
27
28 /**
29 * DOC: Hardware description
30 *
31 * GENI based QUP is a highly-flexible and programmable module for supporting
32 * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single
33 * QUP module can provide upto 8 serial interfaces, using its internal
34 * serial engines. The actual configuration is determined by the target
35 * platform configuration. The protocol supported by each interface is
36 * determined by the firmware loaded to the serial engine. Each SE consists
37 * of a DMA Engine and GENI sub modules which enable serial engines to
38 * support FIFO and DMA modes of operation.
39 *
40 *
41 * +-----------------------------------------+
42 * |QUP Wrapper |
43 * | +----------------------------+ |
44 * --QUP & SE Clocks--> | Serial Engine N | +-IO------>
45 * | | ... | | Interface
46 * <---Clock Perf.----+ +----+-----------------------+ | |
47 * State Interface | | Serial Engine 1 | | |
48 * | | | | |
49 * | | | | |
50 * <--------AHB-------> | | | |
51 * | | +----+ |
52 * | | | |
53 * | | | |
54 * <------SE IRQ------+ +----------------------------+ |
55 * | |
56 * +-----------------------------------------+
57 *
58 * Figure 1: GENI based QUP Wrapper
59 *
60 * The GENI submodules include primary and secondary sequencers which are
61 * used to drive TX & RX operations. On serial interfaces that operate using
62 * master-slave model, primary sequencer drives both TX & RX operations. On
63 * serial interfaces that operate using peer-to-peer model, primary sequencer
64 * drives TX operation and secondary sequencer drives RX operation.
65 */
66
67 /**
68 * DOC: Software description
69 *
70 * GENI SE Wrapper driver is structured into 2 parts:
71 *
72 * geni_wrapper represents QUP Wrapper controller. This part of the driver
73 * manages QUP Wrapper information such as hardware version, clock
74 * performance table that is common to all the internal serial engines.
75 *
76 * geni_se represents serial engine. This part of the driver manages serial
77 * engine information such as clocks, containing QUP Wrapper, etc. This part
78 * of driver also supports operations (eg. initialize the concerned serial
79 * engine, select between FIFO and DMA mode of operation etc.) that are
80 * common to all the serial engines and are independent of serial interfaces.
81 */
82
83 #define MAX_CLK_PERF_LEVEL 32
84 #define NUM_AHB_CLKS 2
85
86 /**
87 * struct geni_wrapper - Data structure to represent the QUP Wrapper Core
88 * @dev: Device pointer of the QUP wrapper core
89 * @base: Base address of this instance of QUP wrapper core
90 * @ahb_clks: Handle to the primary & secondary AHB clocks
91 * @to_core: Core ICC path
92 */
93 struct geni_wrapper {
94 struct device *dev;
95 void __iomem *base;
96 struct clk_bulk_data ahb_clks[NUM_AHB_CLKS];
97 };
98
99 static const char * const icc_path_names[] = {"qup-core", "qup-config",
100 "qup-memory"};
101
102 #define QUP_HW_VER_REG 0x4
103
104 /* Common SE registers */
105 #define GENI_INIT_CFG_REVISION 0x0
106 #define GENI_S_INIT_CFG_REVISION 0x4
107 #define GENI_OUTPUT_CTRL 0x24
108 #define GENI_CGC_CTRL 0x28
109 #define GENI_CLK_CTRL_RO 0x60
110 #define GENI_FW_S_REVISION_RO 0x6c
111 #define SE_GENI_BYTE_GRAN 0x254
112 #define SE_GENI_TX_PACKING_CFG0 0x260
113 #define SE_GENI_TX_PACKING_CFG1 0x264
114 #define SE_GENI_RX_PACKING_CFG0 0x284
115 #define SE_GENI_RX_PACKING_CFG1 0x288
116 #define SE_GENI_M_GP_LENGTH 0x910
117 #define SE_GENI_S_GP_LENGTH 0x914
118 #define SE_DMA_TX_PTR_L 0xc30
119 #define SE_DMA_TX_PTR_H 0xc34
120 #define SE_DMA_TX_ATTR 0xc38
121 #define SE_DMA_TX_LEN 0xc3c
122 #define SE_DMA_TX_IRQ_EN 0xc48
123 #define SE_DMA_TX_IRQ_EN_SET 0xc4c
124 #define SE_DMA_TX_IRQ_EN_CLR 0xc50
125 #define SE_DMA_TX_LEN_IN 0xc54
126 #define SE_DMA_TX_MAX_BURST 0xc5c
127 #define SE_DMA_RX_PTR_L 0xd30
128 #define SE_DMA_RX_PTR_H 0xd34
129 #define SE_DMA_RX_ATTR 0xd38
130 #define SE_DMA_RX_LEN 0xd3c
131 #define SE_DMA_RX_IRQ_EN 0xd48
132 #define SE_DMA_RX_IRQ_EN_SET 0xd4c
133 #define SE_DMA_RX_IRQ_EN_CLR 0xd50
134 #define SE_DMA_RX_LEN_IN 0xd54
135 #define SE_DMA_RX_MAX_BURST 0xd5c
136 #define SE_DMA_RX_FLUSH 0xd60
137 #define SE_GSI_EVENT_EN 0xe18
138 #define SE_IRQ_EN 0xe1c
139 #define SE_DMA_GENERAL_CFG 0xe30
140
141 /* GENI_OUTPUT_CTRL fields */
142 #define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0)
143
144 /* GENI_CGC_CTRL fields */
145 #define CFG_AHB_CLK_CGC_ON BIT(0)
146 #define CFG_AHB_WR_ACLK_CGC_ON BIT(1)
147 #define DATA_AHB_CLK_CGC_ON BIT(2)
148 #define SCLK_CGC_ON BIT(3)
149 #define TX_CLK_CGC_ON BIT(4)
150 #define RX_CLK_CGC_ON BIT(5)
151 #define EXT_CLK_CGC_ON BIT(6)
152 #define PROG_RAM_HCLK_OFF BIT(8)
153 #define PROG_RAM_SCLK_OFF BIT(9)
154 #define DEFAULT_CGC_EN GENMASK(6, 0)
155
156 /* SE_GSI_EVENT_EN fields */
157 #define DMA_RX_EVENT_EN BIT(0)
158 #define DMA_TX_EVENT_EN BIT(1)
159 #define GENI_M_EVENT_EN BIT(2)
160 #define GENI_S_EVENT_EN BIT(3)
161
162 /* SE_IRQ_EN fields */
163 #define DMA_RX_IRQ_EN BIT(0)
164 #define DMA_TX_IRQ_EN BIT(1)
165 #define GENI_M_IRQ_EN BIT(2)
166 #define GENI_S_IRQ_EN BIT(3)
167
168 /* SE_DMA_GENERAL_CFG */
169 #define DMA_RX_CLK_CGC_ON BIT(0)
170 #define DMA_TX_CLK_CGC_ON BIT(1)
171 #define DMA_AHB_SLV_CFG_ON BIT(2)
172 #define AHB_SEC_SLV_CLK_CGC_ON BIT(3)
173 #define DUMMY_RX_NON_BUFFERABLE BIT(4)
174 #define RX_DMA_ZERO_PADDING_EN BIT(5)
175 #define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6)
176 #define RX_DMA_IRQ_DELAY_SHFT 6
177
178 /**
179 * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version
180 * @se: Pointer to the corresponding serial engine.
181 *
182 * Return: Hardware Version of the wrapper.
183 */
geni_se_get_qup_hw_version(struct geni_se * se)184 u32 geni_se_get_qup_hw_version(struct geni_se *se)
185 {
186 struct geni_wrapper *wrapper = se->wrapper;
187
188 return readl_relaxed(wrapper->base + QUP_HW_VER_REG);
189 }
190 EXPORT_SYMBOL(geni_se_get_qup_hw_version);
191
geni_se_io_set_mode(void __iomem * base)192 static void geni_se_io_set_mode(void __iomem *base)
193 {
194 u32 val;
195
196 val = readl_relaxed(base + SE_IRQ_EN);
197 val |= GENI_M_IRQ_EN | GENI_S_IRQ_EN;
198 val |= DMA_TX_IRQ_EN | DMA_RX_IRQ_EN;
199 writel_relaxed(val, base + SE_IRQ_EN);
200
201 val = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
202 val &= ~GENI_DMA_MODE_EN;
203 writel_relaxed(val, base + SE_GENI_DMA_MODE_EN);
204
205 writel_relaxed(0, base + SE_GSI_EVENT_EN);
206 }
207
geni_se_io_init(void __iomem * base)208 static void geni_se_io_init(void __iomem *base)
209 {
210 u32 val;
211
212 val = readl_relaxed(base + GENI_CGC_CTRL);
213 val |= DEFAULT_CGC_EN;
214 writel_relaxed(val, base + GENI_CGC_CTRL);
215
216 val = readl_relaxed(base + SE_DMA_GENERAL_CFG);
217 val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON;
218 val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON;
219 writel_relaxed(val, base + SE_DMA_GENERAL_CFG);
220
221 writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL);
222 writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG);
223 }
224
geni_se_irq_clear(struct geni_se * se)225 static void geni_se_irq_clear(struct geni_se *se)
226 {
227 writel_relaxed(0, se->base + SE_GSI_EVENT_EN);
228 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);
229 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);
230 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);
231 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);
232 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);
233 }
234
235 /**
236 * geni_se_init() - Initialize the GENI serial engine
237 * @se: Pointer to the concerned serial engine.
238 * @rx_wm: Receive watermark, in units of FIFO words.
239 * @rx_rfr: Ready-for-receive watermark, in units of FIFO words.
240 *
241 * This function is used to initialize the GENI serial engine, configure
242 * receive watermark and ready-for-receive watermarks.
243 */
geni_se_init(struct geni_se * se,u32 rx_wm,u32 rx_rfr)244 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr)
245 {
246 u32 val;
247
248 geni_se_irq_clear(se);
249 geni_se_io_init(se->base);
250 geni_se_io_set_mode(se->base);
251
252 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG);
253 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG);
254
255 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
256 val |= M_COMMON_GENI_M_IRQ_EN;
257 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
258
259 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
260 val |= S_COMMON_GENI_S_IRQ_EN;
261 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
262 }
263 EXPORT_SYMBOL(geni_se_init);
264
geni_se_select_fifo_mode(struct geni_se * se)265 static void geni_se_select_fifo_mode(struct geni_se *se)
266 {
267 u32 proto = geni_se_read_proto(se);
268 u32 val, val_old;
269
270 geni_se_irq_clear(se);
271
272 /*
273 * The RX path for the UART is asynchronous and so needs more
274 * complex logic for enabling / disabling its interrupts.
275 *
276 * Specific notes:
277 * - The done and TX-related interrupts are managed manually.
278 * - We don't RX from the main sequencer (we use the secondary) so
279 * we don't need the RX-related interrupts enabled in the main
280 * sequencer for UART.
281 */
282 if (proto != GENI_SE_UART) {
283 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
284 val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN;
285 val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
286 if (val != val_old)
287 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
288
289 val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
290 val |= S_CMD_DONE_EN;
291 if (val != val_old)
292 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
293 }
294
295 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
296 val &= ~GENI_DMA_MODE_EN;
297 if (val != val_old)
298 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
299 }
300
geni_se_select_dma_mode(struct geni_se * se)301 static void geni_se_select_dma_mode(struct geni_se *se)
302 {
303 u32 proto = geni_se_read_proto(se);
304 u32 val, val_old;
305
306 geni_se_irq_clear(se);
307
308 if (proto != GENI_SE_UART) {
309 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
310 val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
311 val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
312 if (val != val_old)
313 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
314
315 val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
316 val &= ~S_CMD_DONE_EN;
317 if (val != val_old)
318 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
319 }
320
321 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
322 val |= GENI_DMA_MODE_EN;
323 if (val != val_old)
324 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
325 }
326
geni_se_select_gpi_mode(struct geni_se * se)327 static void geni_se_select_gpi_mode(struct geni_se *se)
328 {
329 u32 val;
330
331 geni_se_irq_clear(se);
332
333 writel(0, se->base + SE_IRQ_EN);
334
335 val = readl(se->base + SE_GENI_S_IRQ_EN);
336 val &= ~S_CMD_DONE_EN;
337 writel(val, se->base + SE_GENI_S_IRQ_EN);
338
339 val = readl(se->base + SE_GENI_M_IRQ_EN);
340 val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN |
341 M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
342 writel(val, se->base + SE_GENI_M_IRQ_EN);
343
344 writel(GENI_DMA_MODE_EN, se->base + SE_GENI_DMA_MODE_EN);
345
346 val = readl(se->base + SE_GSI_EVENT_EN);
347 val |= (DMA_RX_EVENT_EN | DMA_TX_EVENT_EN | GENI_M_EVENT_EN | GENI_S_EVENT_EN);
348 writel(val, se->base + SE_GSI_EVENT_EN);
349 }
350
351 /**
352 * geni_se_select_mode() - Select the serial engine transfer mode
353 * @se: Pointer to the concerned serial engine.
354 * @mode: Transfer mode to be selected.
355 */
geni_se_select_mode(struct geni_se * se,enum geni_se_xfer_mode mode)356 void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode)
357 {
358 WARN_ON(mode != GENI_SE_FIFO && mode != GENI_SE_DMA && mode != GENI_GPI_DMA);
359
360 switch (mode) {
361 case GENI_SE_FIFO:
362 geni_se_select_fifo_mode(se);
363 break;
364 case GENI_SE_DMA:
365 geni_se_select_dma_mode(se);
366 break;
367 case GENI_GPI_DMA:
368 geni_se_select_gpi_mode(se);
369 break;
370 case GENI_SE_INVALID:
371 default:
372 break;
373 }
374 }
375 EXPORT_SYMBOL(geni_se_select_mode);
376
377 /**
378 * DOC: Overview
379 *
380 * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist
381 * of up to 4 operations, each operation represented by 4 configuration vectors
382 * of 10 bits programmed in GENI_TX_PACKING_CFG0 and GENI_TX_PACKING_CFG1 for
383 * TX FIFO and in GENI_RX_PACKING_CFG0 and GENI_RX_PACKING_CFG1 for RX FIFO.
384 * Refer to below examples for detailed bit-field description.
385 *
386 * Example 1: word_size = 7, packing_mode = 4 x 8, msb_to_lsb = 1
387 *
388 * +-----------+-------+-------+-------+-------+
389 * | | vec_0 | vec_1 | vec_2 | vec_3 |
390 * +-----------+-------+-------+-------+-------+
391 * | start | 0x6 | 0xe | 0x16 | 0x1e |
392 * | direction | 1 | 1 | 1 | 1 |
393 * | length | 6 | 6 | 6 | 6 |
394 * | stop | 0 | 0 | 0 | 1 |
395 * +-----------+-------+-------+-------+-------+
396 *
397 * Example 2: word_size = 15, packing_mode = 2 x 16, msb_to_lsb = 0
398 *
399 * +-----------+-------+-------+-------+-------+
400 * | | vec_0 | vec_1 | vec_2 | vec_3 |
401 * +-----------+-------+-------+-------+-------+
402 * | start | 0x0 | 0x8 | 0x10 | 0x18 |
403 * | direction | 0 | 0 | 0 | 0 |
404 * | length | 7 | 6 | 7 | 6 |
405 * | stop | 0 | 0 | 0 | 1 |
406 * +-----------+-------+-------+-------+-------+
407 *
408 * Example 3: word_size = 23, packing_mode = 1 x 32, msb_to_lsb = 1
409 *
410 * +-----------+-------+-------+-------+-------+
411 * | | vec_0 | vec_1 | vec_2 | vec_3 |
412 * +-----------+-------+-------+-------+-------+
413 * | start | 0x16 | 0xe | 0x6 | 0x0 |
414 * | direction | 1 | 1 | 1 | 1 |
415 * | length | 7 | 7 | 6 | 0 |
416 * | stop | 0 | 0 | 1 | 0 |
417 * +-----------+-------+-------+-------+-------+
418 *
419 */
420
421 #define NUM_PACKING_VECTORS 4
422 #define PACKING_START_SHIFT 5
423 #define PACKING_DIR_SHIFT 4
424 #define PACKING_LEN_SHIFT 1
425 #define PACKING_STOP_BIT BIT(0)
426 #define PACKING_VECTOR_SHIFT 10
427 /**
428 * geni_se_config_packing() - Packing configuration of the serial engine
429 * @se: Pointer to the concerned serial engine
430 * @bpw: Bits of data per transfer word.
431 * @pack_words: Number of words per fifo element.
432 * @msb_to_lsb: Transfer from MSB to LSB or vice-versa.
433 * @tx_cfg: Flag to configure the TX Packing.
434 * @rx_cfg: Flag to configure the RX Packing.
435 *
436 * This function is used to configure the packing rules for the current
437 * transfer.
438 */
geni_se_config_packing(struct geni_se * se,int bpw,int pack_words,bool msb_to_lsb,bool tx_cfg,bool rx_cfg)439 void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,
440 bool msb_to_lsb, bool tx_cfg, bool rx_cfg)
441 {
442 u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0};
443 int len;
444 int temp_bpw = bpw;
445 int idx_start = msb_to_lsb ? bpw - 1 : 0;
446 int idx = idx_start;
447 int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE;
448 int ceil_bpw = ALIGN(bpw, BITS_PER_BYTE);
449 int iter = (ceil_bpw * pack_words) / BITS_PER_BYTE;
450 int i;
451
452 if (iter <= 0 || iter > NUM_PACKING_VECTORS)
453 return;
454
455 for (i = 0; i < iter; i++) {
456 len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1;
457 cfg[i] = idx << PACKING_START_SHIFT;
458 cfg[i] |= msb_to_lsb << PACKING_DIR_SHIFT;
459 cfg[i] |= len << PACKING_LEN_SHIFT;
460
461 if (temp_bpw <= BITS_PER_BYTE) {
462 idx = ((i + 1) * BITS_PER_BYTE) + idx_start;
463 temp_bpw = bpw;
464 } else {
465 idx = idx + idx_delta;
466 temp_bpw = temp_bpw - BITS_PER_BYTE;
467 }
468 }
469 cfg[iter - 1] |= PACKING_STOP_BIT;
470 cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT);
471 cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT);
472
473 if (tx_cfg) {
474 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0);
475 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1);
476 }
477 if (rx_cfg) {
478 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0);
479 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1);
480 }
481
482 /*
483 * Number of protocol words in each FIFO entry
484 * 0 - 4x8, four words in each entry, max word size of 8 bits
485 * 1 - 2x16, two words in each entry, max word size of 16 bits
486 * 2 - 1x32, one word in each entry, max word size of 32 bits
487 * 3 - undefined
488 */
489 if (pack_words || bpw == 32)
490 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN);
491 }
492 EXPORT_SYMBOL(geni_se_config_packing);
493
geni_se_clks_off(struct geni_se * se)494 static void geni_se_clks_off(struct geni_se *se)
495 {
496 struct geni_wrapper *wrapper = se->wrapper;
497
498 clk_disable_unprepare(se->clk);
499 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks),
500 wrapper->ahb_clks);
501 }
502
503 /**
504 * geni_se_resources_off() - Turn off resources associated with the serial
505 * engine
506 * @se: Pointer to the concerned serial engine.
507 *
508 * Return: 0 on success, standard Linux error codes on failure/error.
509 */
geni_se_resources_off(struct geni_se * se)510 int geni_se_resources_off(struct geni_se *se)
511 {
512 int ret;
513
514 if (has_acpi_companion(se->dev))
515 return 0;
516
517 ret = pinctrl_pm_select_sleep_state(se->dev);
518 if (ret)
519 return ret;
520
521 geni_se_clks_off(se);
522 return 0;
523 }
524 EXPORT_SYMBOL(geni_se_resources_off);
525
geni_se_clks_on(struct geni_se * se)526 static int geni_se_clks_on(struct geni_se *se)
527 {
528 int ret;
529 struct geni_wrapper *wrapper = se->wrapper;
530
531 ret = clk_bulk_prepare_enable(ARRAY_SIZE(wrapper->ahb_clks),
532 wrapper->ahb_clks);
533 if (ret)
534 return ret;
535
536 ret = clk_prepare_enable(se->clk);
537 if (ret)
538 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks),
539 wrapper->ahb_clks);
540 return ret;
541 }
542
543 /**
544 * geni_se_resources_on() - Turn on resources associated with the serial
545 * engine
546 * @se: Pointer to the concerned serial engine.
547 *
548 * Return: 0 on success, standard Linux error codes on failure/error.
549 */
geni_se_resources_on(struct geni_se * se)550 int geni_se_resources_on(struct geni_se *se)
551 {
552 int ret;
553
554 if (has_acpi_companion(se->dev))
555 return 0;
556
557 ret = geni_se_clks_on(se);
558 if (ret)
559 return ret;
560
561 ret = pinctrl_pm_select_default_state(se->dev);
562 if (ret)
563 geni_se_clks_off(se);
564
565 return ret;
566 }
567 EXPORT_SYMBOL(geni_se_resources_on);
568
569 /**
570 * geni_se_clk_tbl_get() - Get the clock table to program DFS
571 * @se: Pointer to the concerned serial engine.
572 * @tbl: Table in which the output is returned.
573 *
574 * This function is called by the protocol drivers to determine the different
575 * clock frequencies supported by serial engine core clock. The protocol
576 * drivers use the output to determine the clock frequency index to be
577 * programmed into DFS.
578 *
579 * Return: number of valid performance levels in the table on success,
580 * standard Linux error codes on failure.
581 */
geni_se_clk_tbl_get(struct geni_se * se,unsigned long ** tbl)582 int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl)
583 {
584 long freq = 0;
585 int i;
586
587 if (se->clk_perf_tbl) {
588 *tbl = se->clk_perf_tbl;
589 return se->num_clk_levels;
590 }
591
592 se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL,
593 sizeof(*se->clk_perf_tbl),
594 GFP_KERNEL);
595 if (!se->clk_perf_tbl)
596 return -ENOMEM;
597
598 for (i = 0; i < MAX_CLK_PERF_LEVEL; i++) {
599 freq = clk_round_rate(se->clk, freq + 1);
600 if (freq <= 0 || freq == se->clk_perf_tbl[i - 1])
601 break;
602 se->clk_perf_tbl[i] = freq;
603 }
604 se->num_clk_levels = i;
605 *tbl = se->clk_perf_tbl;
606 return se->num_clk_levels;
607 }
608 EXPORT_SYMBOL(geni_se_clk_tbl_get);
609
610 /**
611 * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency
612 * @se: Pointer to the concerned serial engine.
613 * @req_freq: Requested clock frequency.
614 * @index: Index of the resultant frequency in the table.
615 * @res_freq: Resultant frequency of the source clock.
616 * @exact: Flag to indicate exact multiple requirement of the requested
617 * frequency.
618 *
619 * This function is called by the protocol drivers to determine the best match
620 * of the requested frequency as provided by the serial engine clock in order
621 * to meet the performance requirements.
622 *
623 * If we return success:
624 * - if @exact is true then @res_freq / <an_integer> == @req_freq
625 * - if @exact is false then @res_freq / <an_integer> <= @req_freq
626 *
627 * Return: 0 on success, standard Linux error codes on failure.
628 */
geni_se_clk_freq_match(struct geni_se * se,unsigned long req_freq,unsigned int * index,unsigned long * res_freq,bool exact)629 int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,
630 unsigned int *index, unsigned long *res_freq,
631 bool exact)
632 {
633 unsigned long *tbl;
634 int num_clk_levels;
635 int i;
636 unsigned long best_delta;
637 unsigned long new_delta;
638 unsigned int divider;
639
640 num_clk_levels = geni_se_clk_tbl_get(se, &tbl);
641 if (num_clk_levels < 0)
642 return num_clk_levels;
643
644 if (num_clk_levels == 0)
645 return -EINVAL;
646
647 best_delta = ULONG_MAX;
648 for (i = 0; i < num_clk_levels; i++) {
649 divider = DIV_ROUND_UP(tbl[i], req_freq);
650 new_delta = req_freq - tbl[i] / divider;
651 if (new_delta < best_delta) {
652 /* We have a new best! */
653 *index = i;
654 *res_freq = tbl[i];
655
656 /* If the new best is exact then we're done */
657 if (new_delta == 0)
658 return 0;
659
660 /* Record how close we got */
661 best_delta = new_delta;
662 }
663 }
664
665 if (exact)
666 return -EINVAL;
667
668 return 0;
669 }
670 EXPORT_SYMBOL(geni_se_clk_freq_match);
671
672 #define GENI_SE_DMA_DONE_EN BIT(0)
673 #define GENI_SE_DMA_EOT_EN BIT(1)
674 #define GENI_SE_DMA_AHB_ERR_EN BIT(2)
675 #define GENI_SE_DMA_EOT_BUF BIT(0)
676 /**
677 * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer
678 * @se: Pointer to the concerned serial engine.
679 * @buf: Pointer to the TX buffer.
680 * @len: Length of the TX buffer.
681 * @iova: Pointer to store the mapped DMA address.
682 *
683 * This function is used to prepare the buffers for DMA TX.
684 *
685 * Return: 0 on success, standard Linux error codes on failure.
686 */
geni_se_tx_dma_prep(struct geni_se * se,void * buf,size_t len,dma_addr_t * iova)687 int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,
688 dma_addr_t *iova)
689 {
690 struct geni_wrapper *wrapper = se->wrapper;
691 u32 val;
692
693 if (!wrapper)
694 return -EINVAL;
695
696 *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE);
697 if (dma_mapping_error(wrapper->dev, *iova))
698 return -EIO;
699
700 val = GENI_SE_DMA_DONE_EN;
701 val |= GENI_SE_DMA_EOT_EN;
702 val |= GENI_SE_DMA_AHB_ERR_EN;
703 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET);
704 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L);
705 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H);
706 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR);
707 writel(len, se->base + SE_DMA_TX_LEN);
708 return 0;
709 }
710 EXPORT_SYMBOL(geni_se_tx_dma_prep);
711
712 /**
713 * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer
714 * @se: Pointer to the concerned serial engine.
715 * @buf: Pointer to the RX buffer.
716 * @len: Length of the RX buffer.
717 * @iova: Pointer to store the mapped DMA address.
718 *
719 * This function is used to prepare the buffers for DMA RX.
720 *
721 * Return: 0 on success, standard Linux error codes on failure.
722 */
geni_se_rx_dma_prep(struct geni_se * se,void * buf,size_t len,dma_addr_t * iova)723 int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
724 dma_addr_t *iova)
725 {
726 struct geni_wrapper *wrapper = se->wrapper;
727 u32 val;
728
729 if (!wrapper)
730 return -EINVAL;
731
732 *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE);
733 if (dma_mapping_error(wrapper->dev, *iova))
734 return -EIO;
735
736 val = GENI_SE_DMA_DONE_EN;
737 val |= GENI_SE_DMA_EOT_EN;
738 val |= GENI_SE_DMA_AHB_ERR_EN;
739 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET);
740 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L);
741 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H);
742 /* RX does not have EOT buffer type bit. So just reset RX_ATTR */
743 writel_relaxed(0, se->base + SE_DMA_RX_ATTR);
744 writel(len, se->base + SE_DMA_RX_LEN);
745 return 0;
746 }
747 EXPORT_SYMBOL(geni_se_rx_dma_prep);
748
749 /**
750 * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer
751 * @se: Pointer to the concerned serial engine.
752 * @iova: DMA address of the TX buffer.
753 * @len: Length of the TX buffer.
754 *
755 * This function is used to unprepare the DMA buffers after DMA TX.
756 */
geni_se_tx_dma_unprep(struct geni_se * se,dma_addr_t iova,size_t len)757 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
758 {
759 struct geni_wrapper *wrapper = se->wrapper;
760
761 if (!dma_mapping_error(wrapper->dev, iova))
762 dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE);
763 }
764 EXPORT_SYMBOL(geni_se_tx_dma_unprep);
765
766 /**
767 * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer
768 * @se: Pointer to the concerned serial engine.
769 * @iova: DMA address of the RX buffer.
770 * @len: Length of the RX buffer.
771 *
772 * This function is used to unprepare the DMA buffers after DMA RX.
773 */
geni_se_rx_dma_unprep(struct geni_se * se,dma_addr_t iova,size_t len)774 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
775 {
776 struct geni_wrapper *wrapper = se->wrapper;
777
778 if (!dma_mapping_error(wrapper->dev, iova))
779 dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE);
780 }
781 EXPORT_SYMBOL(geni_se_rx_dma_unprep);
782
geni_icc_get(struct geni_se * se,const char * icc_ddr)783 int geni_icc_get(struct geni_se *se, const char *icc_ddr)
784 {
785 int i, err;
786 const char *icc_names[] = {"qup-core", "qup-config", icc_ddr};
787
788 if (has_acpi_companion(se->dev))
789 return 0;
790
791 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
792 if (!icc_names[i])
793 continue;
794
795 se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]);
796 if (IS_ERR(se->icc_paths[i].path))
797 goto err;
798 }
799
800 return 0;
801
802 err:
803 err = PTR_ERR(se->icc_paths[i].path);
804 if (err != -EPROBE_DEFER)
805 dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n",
806 icc_names[i], err);
807 return err;
808
809 }
810 EXPORT_SYMBOL(geni_icc_get);
811
geni_icc_set_bw(struct geni_se * se)812 int geni_icc_set_bw(struct geni_se *se)
813 {
814 int i, ret;
815
816 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
817 ret = icc_set_bw(se->icc_paths[i].path,
818 se->icc_paths[i].avg_bw, se->icc_paths[i].avg_bw);
819 if (ret) {
820 dev_err_ratelimited(se->dev, "ICC BW voting failed on path '%s': %d\n",
821 icc_path_names[i], ret);
822 return ret;
823 }
824 }
825
826 return 0;
827 }
828 EXPORT_SYMBOL(geni_icc_set_bw);
829
geni_icc_set_tag(struct geni_se * se,u32 tag)830 void geni_icc_set_tag(struct geni_se *se, u32 tag)
831 {
832 int i;
833
834 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++)
835 icc_set_tag(se->icc_paths[i].path, tag);
836 }
837 EXPORT_SYMBOL(geni_icc_set_tag);
838
839 /* To do: Replace this by icc_bulk_enable once it's implemented in ICC core */
geni_icc_enable(struct geni_se * se)840 int geni_icc_enable(struct geni_se *se)
841 {
842 int i, ret;
843
844 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
845 ret = icc_enable(se->icc_paths[i].path);
846 if (ret) {
847 dev_err_ratelimited(se->dev, "ICC enable failed on path '%s': %d\n",
848 icc_path_names[i], ret);
849 return ret;
850 }
851 }
852
853 return 0;
854 }
855 EXPORT_SYMBOL(geni_icc_enable);
856
geni_icc_disable(struct geni_se * se)857 int geni_icc_disable(struct geni_se *se)
858 {
859 int i, ret;
860
861 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
862 ret = icc_disable(se->icc_paths[i].path);
863 if (ret) {
864 dev_err_ratelimited(se->dev, "ICC disable failed on path '%s': %d\n",
865 icc_path_names[i], ret);
866 return ret;
867 }
868 }
869
870 return 0;
871 }
872 EXPORT_SYMBOL(geni_icc_disable);
873
geni_se_probe(struct platform_device * pdev)874 static int geni_se_probe(struct platform_device *pdev)
875 {
876 struct device *dev = &pdev->dev;
877 struct resource *res;
878 struct geni_wrapper *wrapper;
879 int ret;
880
881 wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL);
882 if (!wrapper)
883 return -ENOMEM;
884
885 wrapper->dev = dev;
886 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
887 wrapper->base = devm_ioremap_resource(dev, res);
888 if (IS_ERR(wrapper->base))
889 return PTR_ERR(wrapper->base);
890
891 if (!has_acpi_companion(&pdev->dev)) {
892 wrapper->ahb_clks[0].id = "m-ahb";
893 wrapper->ahb_clks[1].id = "s-ahb";
894 ret = devm_clk_bulk_get(dev, NUM_AHB_CLKS, wrapper->ahb_clks);
895 if (ret) {
896 dev_err(dev, "Err getting AHB clks %d\n", ret);
897 return ret;
898 }
899 }
900
901 dev_set_drvdata(dev, wrapper);
902 dev_dbg(dev, "GENI SE Driver probed\n");
903 return devm_of_platform_populate(dev);
904 }
905
906 static const struct of_device_id geni_se_dt_match[] = {
907 { .compatible = "qcom,geni-se-qup", },
908 {}
909 };
910 MODULE_DEVICE_TABLE(of, geni_se_dt_match);
911
912 static struct platform_driver geni_se_driver = {
913 .driver = {
914 .name = "geni_se_qup",
915 .of_match_table = geni_se_dt_match,
916 },
917 .probe = geni_se_probe,
918 };
919 module_platform_driver(geni_se_driver);
920
921 MODULE_DESCRIPTION("GENI Serial Engine Driver");
922 MODULE_LICENSE("GPL v2");
923