1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/kvm/reset.c
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9 */
10
11 #include <linux/errno.h>
12 #include <linux/kernel.h>
13 #include <linux/kvm_host.h>
14 #include <linux/kvm.h>
15 #include <linux/hw_breakpoint.h>
16 #include <linux/slab.h>
17 #include <linux/string.h>
18 #include <linux/types.h>
19
20 #include <kvm/arm_arch_timer.h>
21
22 #include <asm/cpufeature.h>
23 #include <asm/cputype.h>
24 #include <asm/fpsimd.h>
25 #include <asm/ptrace.h>
26 #include <asm/kvm_arm.h>
27 #include <asm/kvm_asm.h>
28 #include <asm/kvm_emulate.h>
29 #include <asm/kvm_mmu.h>
30 #include <asm/virt.h>
31
32 /* Maximum phys_shift supported for any VM on this host */
33 static u32 kvm_ipa_limit;
34
35 unsigned int kvm_sve_max_vl;
36
kvm_arm_init_sve(void)37 int kvm_arm_init_sve(void)
38 {
39 if (system_supports_sve()) {
40 kvm_sve_max_vl = sve_max_virtualisable_vl;
41
42 /*
43 * The get_sve_reg()/set_sve_reg() ioctl interface will need
44 * to be extended with multiple register slice support in
45 * order to support vector lengths greater than
46 * SVE_VL_ARCH_MAX:
47 */
48 if (WARN_ON(kvm_sve_max_vl > SVE_VL_ARCH_MAX))
49 kvm_sve_max_vl = SVE_VL_ARCH_MAX;
50
51 /*
52 * Don't even try to make use of vector lengths that
53 * aren't available on all CPUs, for now:
54 */
55 if (kvm_sve_max_vl < sve_max_vl)
56 pr_warn("KVM: SVE vector length for guests limited to %u bytes\n",
57 kvm_sve_max_vl);
58 }
59
60 return 0;
61 }
62
kvm_vcpu_enable_sve(struct kvm_vcpu * vcpu)63 static int kvm_vcpu_enable_sve(struct kvm_vcpu *vcpu)
64 {
65 if (!system_supports_sve())
66 return -EINVAL;
67
68 vcpu->arch.sve_max_vl = kvm_sve_max_vl;
69
70 /*
71 * Userspace can still customize the vector lengths by writing
72 * KVM_REG_ARM64_SVE_VLS. Allocation is deferred until
73 * kvm_arm_vcpu_finalize(), which freezes the configuration.
74 */
75 vcpu->arch.flags |= KVM_ARM64_GUEST_HAS_SVE;
76
77 return 0;
78 }
79
80 /*
81 * Finalize vcpu's maximum SVE vector length, allocating
82 * vcpu->arch.sve_state as necessary.
83 */
kvm_vcpu_finalize_sve(struct kvm_vcpu * vcpu)84 static int kvm_vcpu_finalize_sve(struct kvm_vcpu *vcpu)
85 {
86 void *buf;
87 unsigned int vl;
88 size_t reg_sz;
89 int ret;
90
91 vl = vcpu->arch.sve_max_vl;
92
93 /*
94 * Responsibility for these properties is shared between
95 * kvm_arm_init_sve(), kvm_vcpu_enable_sve() and
96 * set_sve_vls(). Double-check here just to be sure:
97 */
98 if (WARN_ON(!sve_vl_valid(vl) || vl > sve_max_virtualisable_vl ||
99 vl > SVE_VL_ARCH_MAX))
100 return -EIO;
101
102 reg_sz = vcpu_sve_state_size(vcpu);
103 buf = kzalloc(reg_sz, GFP_KERNEL_ACCOUNT);
104 if (!buf)
105 return -ENOMEM;
106
107 ret = kvm_share_hyp(buf, buf + reg_sz);
108 if (ret) {
109 kfree(buf);
110 return ret;
111 }
112
113 vcpu->arch.sve_state = buf;
114 vcpu->arch.flags |= KVM_ARM64_VCPU_SVE_FINALIZED;
115 return 0;
116 }
117
kvm_arm_vcpu_finalize(struct kvm_vcpu * vcpu,int feature)118 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature)
119 {
120 switch (feature) {
121 case KVM_ARM_VCPU_SVE:
122 if (!vcpu_has_sve(vcpu))
123 return -EINVAL;
124
125 if (kvm_arm_vcpu_sve_finalized(vcpu))
126 return -EPERM;
127
128 return kvm_vcpu_finalize_sve(vcpu);
129 }
130
131 return -EINVAL;
132 }
133
kvm_arm_vcpu_is_finalized(struct kvm_vcpu * vcpu)134 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu)
135 {
136 if (vcpu_has_sve(vcpu) && !kvm_arm_vcpu_sve_finalized(vcpu))
137 return false;
138
139 return true;
140 }
141
kvm_arm_vcpu_destroy(struct kvm_vcpu * vcpu)142 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu)
143 {
144 void *sve_state = vcpu->arch.sve_state;
145
146 kvm_vcpu_unshare_task_fp(vcpu);
147 kvm_unshare_hyp(vcpu, vcpu + 1);
148 if (sve_state)
149 kvm_unshare_hyp(sve_state, sve_state + vcpu_sve_state_size(vcpu));
150 kfree(sve_state);
151 }
152
kvm_vcpu_reset_sve(struct kvm_vcpu * vcpu)153 static void kvm_vcpu_reset_sve(struct kvm_vcpu *vcpu)
154 {
155 if (vcpu_has_sve(vcpu))
156 memset(vcpu->arch.sve_state, 0, vcpu_sve_state_size(vcpu));
157 }
158
vcpu_allowed_register_width(struct kvm_vcpu * vcpu)159 static bool vcpu_allowed_register_width(struct kvm_vcpu *vcpu)
160 {
161 struct kvm_vcpu *tmp;
162 bool is32bit;
163 int i;
164
165 is32bit = vcpu_has_feature(vcpu, KVM_ARM_VCPU_EL1_32BIT);
166 if (!cpus_have_const_cap(ARM64_HAS_32BIT_EL1) && is32bit)
167 return false;
168
169 /* MTE is incompatible with AArch32 */
170 if (kvm_has_mte(vcpu->kvm) && is32bit)
171 return false;
172
173 /* Check that the vcpus are either all 32bit or all 64bit */
174 kvm_for_each_vcpu(i, tmp, vcpu->kvm) {
175 if (vcpu_has_feature(tmp, KVM_ARM_VCPU_EL1_32BIT) != is32bit)
176 return false;
177 }
178
179 return true;
180 }
181
182 /**
183 * kvm_reset_vcpu - sets core registers and sys_regs to reset value
184 * @vcpu: The VCPU pointer
185 *
186 * This function sets the registers on the virtual CPU struct to their
187 * architecturally defined reset values, except for registers whose reset is
188 * deferred until kvm_arm_vcpu_finalize().
189 *
190 * Note: This function can be called from two paths: The KVM_ARM_VCPU_INIT
191 * ioctl or as part of handling a request issued by another VCPU in the PSCI
192 * handling code. In the first case, the VCPU will not be loaded, and in the
193 * second case the VCPU will be loaded. Because this function operates purely
194 * on the memory-backed values of system registers, we want to do a full put if
195 * we were loaded (handling a request) and load the values back at the end of
196 * the function. Otherwise we leave the state alone. In both cases, we
197 * disable preemption around the vcpu reset as we would otherwise race with
198 * preempt notifiers which also call put/load.
199 */
kvm_reset_vcpu(struct kvm_vcpu * vcpu)200 int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
201 {
202 struct vcpu_reset_state reset_state;
203 int ret;
204 bool loaded;
205 u32 pstate;
206
207 mutex_lock(&vcpu->kvm->lock);
208 reset_state = vcpu->arch.reset_state;
209 WRITE_ONCE(vcpu->arch.reset_state.reset, false);
210 mutex_unlock(&vcpu->kvm->lock);
211
212 /* Reset PMU outside of the non-preemptible section */
213 kvm_pmu_vcpu_reset(vcpu);
214
215 preempt_disable();
216 loaded = (vcpu->cpu != -1);
217 if (loaded)
218 kvm_arch_vcpu_put(vcpu);
219
220 if (!kvm_arm_vcpu_sve_finalized(vcpu)) {
221 if (test_bit(KVM_ARM_VCPU_SVE, vcpu->arch.features)) {
222 ret = kvm_vcpu_enable_sve(vcpu);
223 if (ret)
224 goto out;
225 }
226 } else {
227 kvm_vcpu_reset_sve(vcpu);
228 }
229
230 if (test_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, vcpu->arch.features) ||
231 test_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, vcpu->arch.features)) {
232 if (kvm_vcpu_enable_ptrauth(vcpu)) {
233 ret = -EINVAL;
234 goto out;
235 }
236 }
237
238 if (!vcpu_allowed_register_width(vcpu)) {
239 ret = -EINVAL;
240 goto out;
241 }
242
243 switch (vcpu->arch.target) {
244 default:
245 if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) {
246 pstate = VCPU_RESET_PSTATE_SVC;
247 } else {
248 pstate = VCPU_RESET_PSTATE_EL1;
249 }
250
251 if (kvm_vcpu_has_pmu(vcpu) && !kvm_arm_support_pmu_v3()) {
252 ret = -EINVAL;
253 goto out;
254 }
255 break;
256 }
257
258 /* Reset core registers */
259 memset(vcpu_gp_regs(vcpu), 0, sizeof(*vcpu_gp_regs(vcpu)));
260 memset(&vcpu->arch.ctxt.fp_regs, 0, sizeof(vcpu->arch.ctxt.fp_regs));
261 vcpu->arch.ctxt.spsr_abt = 0;
262 vcpu->arch.ctxt.spsr_und = 0;
263 vcpu->arch.ctxt.spsr_irq = 0;
264 vcpu->arch.ctxt.spsr_fiq = 0;
265 vcpu_gp_regs(vcpu)->pstate = pstate;
266
267 /* Reset system registers */
268 kvm_reset_sys_regs(vcpu);
269
270 /*
271 * Additional reset state handling that PSCI may have imposed on us.
272 * Must be done after all the sys_reg reset.
273 */
274 if (reset_state.reset) {
275 unsigned long target_pc = reset_state.pc;
276
277 /* Gracefully handle Thumb2 entry point */
278 if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) {
279 target_pc &= ~1UL;
280 vcpu_set_thumb(vcpu);
281 }
282
283 /* Propagate caller endianness */
284 if (reset_state.be)
285 kvm_vcpu_set_be(vcpu);
286
287 *vcpu_pc(vcpu) = target_pc;
288 vcpu_set_reg(vcpu, 0, reset_state.r0);
289 }
290
291 /* Reset timer */
292 ret = kvm_timer_vcpu_reset(vcpu);
293 out:
294 if (loaded)
295 kvm_arch_vcpu_load(vcpu, smp_processor_id());
296 preempt_enable();
297 return ret;
298 }
299
get_kvm_ipa_limit(void)300 u32 get_kvm_ipa_limit(void)
301 {
302 return kvm_ipa_limit;
303 }
304
kvm_set_ipa_limit(void)305 int kvm_set_ipa_limit(void)
306 {
307 unsigned int parange;
308 u64 mmfr0;
309
310 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
311 parange = cpuid_feature_extract_unsigned_field(mmfr0,
312 ID_AA64MMFR0_PARANGE_SHIFT);
313 /*
314 * IPA size beyond 48 bits could not be supported
315 * on either 4K or 16K page size. Hence let's cap
316 * it to 48 bits, in case it's reported as larger
317 * on the system.
318 */
319 if (PAGE_SIZE != SZ_64K)
320 parange = min(parange, (unsigned int)ID_AA64MMFR0_PARANGE_48);
321
322 /*
323 * Check with ARMv8.5-GTG that our PAGE_SIZE is supported at
324 * Stage-2. If not, things will stop very quickly.
325 */
326 switch (cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_TGRAN_2_SHIFT)) {
327 case ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE:
328 kvm_err("PAGE_SIZE not supported at Stage-2, giving up\n");
329 return -EINVAL;
330 case ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT:
331 kvm_debug("PAGE_SIZE supported at Stage-2 (default)\n");
332 break;
333 case ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN ... ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX:
334 kvm_debug("PAGE_SIZE supported at Stage-2 (advertised)\n");
335 break;
336 default:
337 kvm_err("Unsupported value for TGRAN_2, giving up\n");
338 return -EINVAL;
339 }
340
341 kvm_ipa_limit = id_aa64mmfr0_parange_to_phys_shift(parange);
342 kvm_info("IPA Size Limit: %d bits%s\n", kvm_ipa_limit,
343 ((kvm_ipa_limit < KVM_PHYS_SHIFT) ?
344 " (Reduced IPA size, limited VM/VMM compatibility)" : ""));
345
346 return 0;
347 }
348