1 // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
2 /*
3 * Copyright(c) 2015 - 2020 Intel Corporation.
4 */
5
6 #include <linux/pci.h>
7 #include <linux/netdevice.h>
8 #include <linux/vmalloc.h>
9 #include <linux/delay.h>
10 #include <linux/xarray.h>
11 #include <linux/module.h>
12 #include <linux/printk.h>
13 #include <linux/hrtimer.h>
14 #include <linux/bitmap.h>
15 #include <linux/numa.h>
16 #include <rdma/rdma_vt.h>
17
18 #include "hfi.h"
19 #include "device.h"
20 #include "common.h"
21 #include "trace.h"
22 #include "mad.h"
23 #include "sdma.h"
24 #include "debugfs.h"
25 #include "verbs.h"
26 #include "aspm.h"
27 #include "affinity.h"
28 #include "vnic.h"
29 #include "exp_rcv.h"
30 #include "netdev.h"
31
32 #undef pr_fmt
33 #define pr_fmt(fmt) DRIVER_NAME ": " fmt
34
35 /*
36 * min buffers we want to have per context, after driver
37 */
38 #define HFI1_MIN_USER_CTXT_BUFCNT 7
39
40 #define HFI1_MIN_EAGER_BUFFER_SIZE (4 * 1024) /* 4KB */
41 #define HFI1_MAX_EAGER_BUFFER_SIZE (256 * 1024) /* 256KB */
42
43 #define NUM_IB_PORTS 1
44
45 /*
46 * Number of user receive contexts we are configured to use (to allow for more
47 * pio buffers per ctxt, etc.) Zero means use one user context per CPU.
48 */
49 int num_user_contexts = -1;
50 module_param_named(num_user_contexts, num_user_contexts, int, 0444);
51 MODULE_PARM_DESC(
52 num_user_contexts, "Set max number of user contexts to use (default: -1 will use the real (non-HT) CPU count)");
53
54 uint krcvqs[RXE_NUM_DATA_VL];
55 int krcvqsset;
56 module_param_array(krcvqs, uint, &krcvqsset, S_IRUGO);
57 MODULE_PARM_DESC(krcvqs, "Array of the number of non-control kernel receive queues by VL");
58
59 /* computed based on above array */
60 unsigned long n_krcvqs;
61
62 static unsigned hfi1_rcvarr_split = 25;
63 module_param_named(rcvarr_split, hfi1_rcvarr_split, uint, S_IRUGO);
64 MODULE_PARM_DESC(rcvarr_split, "Percent of context's RcvArray entries used for Eager buffers");
65
66 static uint eager_buffer_size = (8 << 20); /* 8MB */
67 module_param(eager_buffer_size, uint, S_IRUGO);
68 MODULE_PARM_DESC(eager_buffer_size, "Size of the eager buffers, default: 8MB");
69
70 static uint rcvhdrcnt = 2048; /* 2x the max eager buffer count */
71 module_param_named(rcvhdrcnt, rcvhdrcnt, uint, S_IRUGO);
72 MODULE_PARM_DESC(rcvhdrcnt, "Receive header queue count (default 2048)");
73
74 static uint hfi1_hdrq_entsize = 32;
75 module_param_named(hdrq_entsize, hfi1_hdrq_entsize, uint, 0444);
76 MODULE_PARM_DESC(hdrq_entsize, "Size of header queue entries: 2 - 8B, 16 - 64B, 32 - 128B (default)");
77
78 unsigned int user_credit_return_threshold = 33; /* default is 33% */
79 module_param(user_credit_return_threshold, uint, S_IRUGO);
80 MODULE_PARM_DESC(user_credit_return_threshold, "Credit return threshold for user send contexts, return when unreturned credits passes this many blocks (in percent of allocated blocks, 0 is off)");
81
82 DEFINE_XARRAY_FLAGS(hfi1_dev_table, XA_FLAGS_ALLOC | XA_FLAGS_LOCK_IRQ);
83
hfi1_create_kctxt(struct hfi1_devdata * dd,struct hfi1_pportdata * ppd)84 static int hfi1_create_kctxt(struct hfi1_devdata *dd,
85 struct hfi1_pportdata *ppd)
86 {
87 struct hfi1_ctxtdata *rcd;
88 int ret;
89
90 /* Control context has to be always 0 */
91 BUILD_BUG_ON(HFI1_CTRL_CTXT != 0);
92
93 ret = hfi1_create_ctxtdata(ppd, dd->node, &rcd);
94 if (ret < 0) {
95 dd_dev_err(dd, "Kernel receive context allocation failed\n");
96 return ret;
97 }
98
99 /*
100 * Set up the kernel context flags here and now because they use
101 * default values for all receive side memories. User contexts will
102 * be handled as they are created.
103 */
104 rcd->flags = HFI1_CAP_KGET(MULTI_PKT_EGR) |
105 HFI1_CAP_KGET(NODROP_RHQ_FULL) |
106 HFI1_CAP_KGET(NODROP_EGR_FULL) |
107 HFI1_CAP_KGET(DMA_RTAIL);
108
109 /* Control context must use DMA_RTAIL */
110 if (rcd->ctxt == HFI1_CTRL_CTXT)
111 rcd->flags |= HFI1_CAP_DMA_RTAIL;
112 rcd->fast_handler = get_dma_rtail_setting(rcd) ?
113 handle_receive_interrupt_dma_rtail :
114 handle_receive_interrupt_nodma_rtail;
115
116 hfi1_set_seq_cnt(rcd, 1);
117
118 rcd->sc = sc_alloc(dd, SC_ACK, rcd->rcvhdrqentsize, dd->node);
119 if (!rcd->sc) {
120 dd_dev_err(dd, "Kernel send context allocation failed\n");
121 return -ENOMEM;
122 }
123 hfi1_init_ctxt(rcd->sc);
124
125 return 0;
126 }
127
128 /*
129 * Create the receive context array and one or more kernel contexts
130 */
hfi1_create_kctxts(struct hfi1_devdata * dd)131 int hfi1_create_kctxts(struct hfi1_devdata *dd)
132 {
133 u16 i;
134 int ret;
135
136 dd->rcd = kcalloc_node(dd->num_rcv_contexts, sizeof(*dd->rcd),
137 GFP_KERNEL, dd->node);
138 if (!dd->rcd)
139 return -ENOMEM;
140
141 for (i = 0; i < dd->first_dyn_alloc_ctxt; ++i) {
142 ret = hfi1_create_kctxt(dd, dd->pport);
143 if (ret)
144 goto bail;
145 }
146
147 return 0;
148 bail:
149 for (i = 0; dd->rcd && i < dd->first_dyn_alloc_ctxt; ++i)
150 hfi1_free_ctxt(dd->rcd[i]);
151
152 /* All the contexts should be freed, free the array */
153 kfree(dd->rcd);
154 dd->rcd = NULL;
155 return ret;
156 }
157
158 /*
159 * Helper routines for the receive context reference count (rcd and uctxt).
160 */
hfi1_rcd_init(struct hfi1_ctxtdata * rcd)161 static void hfi1_rcd_init(struct hfi1_ctxtdata *rcd)
162 {
163 kref_init(&rcd->kref);
164 }
165
166 /**
167 * hfi1_rcd_free - When reference is zero clean up.
168 * @kref: pointer to an initialized rcd data structure
169 *
170 */
hfi1_rcd_free(struct kref * kref)171 static void hfi1_rcd_free(struct kref *kref)
172 {
173 unsigned long flags;
174 struct hfi1_ctxtdata *rcd =
175 container_of(kref, struct hfi1_ctxtdata, kref);
176
177 spin_lock_irqsave(&rcd->dd->uctxt_lock, flags);
178 rcd->dd->rcd[rcd->ctxt] = NULL;
179 spin_unlock_irqrestore(&rcd->dd->uctxt_lock, flags);
180
181 hfi1_free_ctxtdata(rcd->dd, rcd);
182
183 kfree(rcd);
184 }
185
186 /**
187 * hfi1_rcd_put - decrement reference for rcd
188 * @rcd: pointer to an initialized rcd data structure
189 *
190 * Use this to put a reference after the init.
191 */
hfi1_rcd_put(struct hfi1_ctxtdata * rcd)192 int hfi1_rcd_put(struct hfi1_ctxtdata *rcd)
193 {
194 if (rcd)
195 return kref_put(&rcd->kref, hfi1_rcd_free);
196
197 return 0;
198 }
199
200 /**
201 * hfi1_rcd_get - increment reference for rcd
202 * @rcd: pointer to an initialized rcd data structure
203 *
204 * Use this to get a reference after the init.
205 *
206 * Return : reflect kref_get_unless_zero(), which returns non-zero on
207 * increment, otherwise 0.
208 */
hfi1_rcd_get(struct hfi1_ctxtdata * rcd)209 int hfi1_rcd_get(struct hfi1_ctxtdata *rcd)
210 {
211 return kref_get_unless_zero(&rcd->kref);
212 }
213
214 /**
215 * allocate_rcd_index - allocate an rcd index from the rcd array
216 * @dd: pointer to a valid devdata structure
217 * @rcd: rcd data structure to assign
218 * @index: pointer to index that is allocated
219 *
220 * Find an empty index in the rcd array, and assign the given rcd to it.
221 * If the array is full, we are EBUSY.
222 *
223 */
allocate_rcd_index(struct hfi1_devdata * dd,struct hfi1_ctxtdata * rcd,u16 * index)224 static int allocate_rcd_index(struct hfi1_devdata *dd,
225 struct hfi1_ctxtdata *rcd, u16 *index)
226 {
227 unsigned long flags;
228 u16 ctxt;
229
230 spin_lock_irqsave(&dd->uctxt_lock, flags);
231 for (ctxt = 0; ctxt < dd->num_rcv_contexts; ctxt++)
232 if (!dd->rcd[ctxt])
233 break;
234
235 if (ctxt < dd->num_rcv_contexts) {
236 rcd->ctxt = ctxt;
237 dd->rcd[ctxt] = rcd;
238 hfi1_rcd_init(rcd);
239 }
240 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
241
242 if (ctxt >= dd->num_rcv_contexts)
243 return -EBUSY;
244
245 *index = ctxt;
246
247 return 0;
248 }
249
250 /**
251 * hfi1_rcd_get_by_index_safe - validate the ctxt index before accessing the
252 * array
253 * @dd: pointer to a valid devdata structure
254 * @ctxt: the index of an possilbe rcd
255 *
256 * This is a wrapper for hfi1_rcd_get_by_index() to validate that the given
257 * ctxt index is valid.
258 *
259 * The caller is responsible for making the _put().
260 *
261 */
hfi1_rcd_get_by_index_safe(struct hfi1_devdata * dd,u16 ctxt)262 struct hfi1_ctxtdata *hfi1_rcd_get_by_index_safe(struct hfi1_devdata *dd,
263 u16 ctxt)
264 {
265 if (ctxt < dd->num_rcv_contexts)
266 return hfi1_rcd_get_by_index(dd, ctxt);
267
268 return NULL;
269 }
270
271 /**
272 * hfi1_rcd_get_by_index - get by index
273 * @dd: pointer to a valid devdata structure
274 * @ctxt: the index of an possilbe rcd
275 *
276 * We need to protect access to the rcd array. If access is needed to
277 * one or more index, get the protecting spinlock and then increment the
278 * kref.
279 *
280 * The caller is responsible for making the _put().
281 *
282 */
hfi1_rcd_get_by_index(struct hfi1_devdata * dd,u16 ctxt)283 struct hfi1_ctxtdata *hfi1_rcd_get_by_index(struct hfi1_devdata *dd, u16 ctxt)
284 {
285 unsigned long flags;
286 struct hfi1_ctxtdata *rcd = NULL;
287
288 spin_lock_irqsave(&dd->uctxt_lock, flags);
289 if (dd->rcd[ctxt]) {
290 rcd = dd->rcd[ctxt];
291 if (!hfi1_rcd_get(rcd))
292 rcd = NULL;
293 }
294 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
295
296 return rcd;
297 }
298
299 /*
300 * Common code for user and kernel context create and setup.
301 * NOTE: the initial kref is done here (hf1_rcd_init()).
302 */
hfi1_create_ctxtdata(struct hfi1_pportdata * ppd,int numa,struct hfi1_ctxtdata ** context)303 int hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, int numa,
304 struct hfi1_ctxtdata **context)
305 {
306 struct hfi1_devdata *dd = ppd->dd;
307 struct hfi1_ctxtdata *rcd;
308 unsigned kctxt_ngroups = 0;
309 u32 base;
310
311 if (dd->rcv_entries.nctxt_extra >
312 dd->num_rcv_contexts - dd->first_dyn_alloc_ctxt)
313 kctxt_ngroups = (dd->rcv_entries.nctxt_extra -
314 (dd->num_rcv_contexts - dd->first_dyn_alloc_ctxt));
315 rcd = kzalloc_node(sizeof(*rcd), GFP_KERNEL, numa);
316 if (rcd) {
317 u32 rcvtids, max_entries;
318 u16 ctxt;
319 int ret;
320
321 ret = allocate_rcd_index(dd, rcd, &ctxt);
322 if (ret) {
323 *context = NULL;
324 kfree(rcd);
325 return ret;
326 }
327
328 INIT_LIST_HEAD(&rcd->qp_wait_list);
329 hfi1_exp_tid_group_init(rcd);
330 rcd->ppd = ppd;
331 rcd->dd = dd;
332 rcd->numa_id = numa;
333 rcd->rcv_array_groups = dd->rcv_entries.ngroups;
334 rcd->rhf_rcv_function_map = normal_rhf_rcv_functions;
335 rcd->slow_handler = handle_receive_interrupt;
336 rcd->do_interrupt = rcd->slow_handler;
337 rcd->msix_intr = CCE_NUM_MSIX_VECTORS;
338
339 mutex_init(&rcd->exp_mutex);
340 spin_lock_init(&rcd->exp_lock);
341 INIT_LIST_HEAD(&rcd->flow_queue.queue_head);
342 INIT_LIST_HEAD(&rcd->rarr_queue.queue_head);
343
344 hfi1_cdbg(PROC, "setting up context %u\n", rcd->ctxt);
345
346 /*
347 * Calculate the context's RcvArray entry starting point.
348 * We do this here because we have to take into account all
349 * the RcvArray entries that previous context would have
350 * taken and we have to account for any extra groups assigned
351 * to the static (kernel) or dynamic (vnic/user) contexts.
352 */
353 if (ctxt < dd->first_dyn_alloc_ctxt) {
354 if (ctxt < kctxt_ngroups) {
355 base = ctxt * (dd->rcv_entries.ngroups + 1);
356 rcd->rcv_array_groups++;
357 } else {
358 base = kctxt_ngroups +
359 (ctxt * dd->rcv_entries.ngroups);
360 }
361 } else {
362 u16 ct = ctxt - dd->first_dyn_alloc_ctxt;
363
364 base = ((dd->n_krcv_queues * dd->rcv_entries.ngroups) +
365 kctxt_ngroups);
366 if (ct < dd->rcv_entries.nctxt_extra) {
367 base += ct * (dd->rcv_entries.ngroups + 1);
368 rcd->rcv_array_groups++;
369 } else {
370 base += dd->rcv_entries.nctxt_extra +
371 (ct * dd->rcv_entries.ngroups);
372 }
373 }
374 rcd->eager_base = base * dd->rcv_entries.group_size;
375
376 rcd->rcvhdrq_cnt = rcvhdrcnt;
377 rcd->rcvhdrqentsize = hfi1_hdrq_entsize;
378 rcd->rhf_offset =
379 rcd->rcvhdrqentsize - sizeof(u64) / sizeof(u32);
380 /*
381 * Simple Eager buffer allocation: we have already pre-allocated
382 * the number of RcvArray entry groups. Each ctxtdata structure
383 * holds the number of groups for that context.
384 *
385 * To follow CSR requirements and maintain cacheline alignment,
386 * make sure all sizes and bases are multiples of group_size.
387 *
388 * The expected entry count is what is left after assigning
389 * eager.
390 */
391 max_entries = rcd->rcv_array_groups *
392 dd->rcv_entries.group_size;
393 rcvtids = ((max_entries * hfi1_rcvarr_split) / 100);
394 rcd->egrbufs.count = round_down(rcvtids,
395 dd->rcv_entries.group_size);
396 if (rcd->egrbufs.count > MAX_EAGER_ENTRIES) {
397 dd_dev_err(dd, "ctxt%u: requested too many RcvArray entries.\n",
398 rcd->ctxt);
399 rcd->egrbufs.count = MAX_EAGER_ENTRIES;
400 }
401 hfi1_cdbg(PROC,
402 "ctxt%u: max Eager buffer RcvArray entries: %u\n",
403 rcd->ctxt, rcd->egrbufs.count);
404
405 /*
406 * Allocate array that will hold the eager buffer accounting
407 * data.
408 * This will allocate the maximum possible buffer count based
409 * on the value of the RcvArray split parameter.
410 * The resulting value will be rounded down to the closest
411 * multiple of dd->rcv_entries.group_size.
412 */
413 rcd->egrbufs.buffers =
414 kcalloc_node(rcd->egrbufs.count,
415 sizeof(*rcd->egrbufs.buffers),
416 GFP_KERNEL, numa);
417 if (!rcd->egrbufs.buffers)
418 goto bail;
419 rcd->egrbufs.rcvtids =
420 kcalloc_node(rcd->egrbufs.count,
421 sizeof(*rcd->egrbufs.rcvtids),
422 GFP_KERNEL, numa);
423 if (!rcd->egrbufs.rcvtids)
424 goto bail;
425 rcd->egrbufs.size = eager_buffer_size;
426 /*
427 * The size of the buffers programmed into the RcvArray
428 * entries needs to be big enough to handle the highest
429 * MTU supported.
430 */
431 if (rcd->egrbufs.size < hfi1_max_mtu) {
432 rcd->egrbufs.size = __roundup_pow_of_two(hfi1_max_mtu);
433 hfi1_cdbg(PROC,
434 "ctxt%u: eager bufs size too small. Adjusting to %u\n",
435 rcd->ctxt, rcd->egrbufs.size);
436 }
437 rcd->egrbufs.rcvtid_size = HFI1_MAX_EAGER_BUFFER_SIZE;
438
439 /* Applicable only for statically created kernel contexts */
440 if (ctxt < dd->first_dyn_alloc_ctxt) {
441 rcd->opstats = kzalloc_node(sizeof(*rcd->opstats),
442 GFP_KERNEL, numa);
443 if (!rcd->opstats)
444 goto bail;
445
446 /* Initialize TID flow generations for the context */
447 hfi1_kern_init_ctxt_generations(rcd);
448 }
449
450 *context = rcd;
451 return 0;
452 }
453
454 bail:
455 *context = NULL;
456 hfi1_free_ctxt(rcd);
457 return -ENOMEM;
458 }
459
460 /**
461 * hfi1_free_ctxt - free context
462 * @rcd: pointer to an initialized rcd data structure
463 *
464 * This wrapper is the free function that matches hfi1_create_ctxtdata().
465 * When a context is done being used (kernel or user), this function is called
466 * for the "final" put to match the kref init from hf1i_create_ctxtdata().
467 * Other users of the context do a get/put sequence to make sure that the
468 * structure isn't removed while in use.
469 */
hfi1_free_ctxt(struct hfi1_ctxtdata * rcd)470 void hfi1_free_ctxt(struct hfi1_ctxtdata *rcd)
471 {
472 hfi1_rcd_put(rcd);
473 }
474
475 /*
476 * Select the largest ccti value over all SLs to determine the intra-
477 * packet gap for the link.
478 *
479 * called with cca_timer_lock held (to protect access to cca_timer
480 * array), and rcu_read_lock() (to protect access to cc_state).
481 */
set_link_ipg(struct hfi1_pportdata * ppd)482 void set_link_ipg(struct hfi1_pportdata *ppd)
483 {
484 struct hfi1_devdata *dd = ppd->dd;
485 struct cc_state *cc_state;
486 int i;
487 u16 cce, ccti_limit, max_ccti = 0;
488 u16 shift, mult;
489 u64 src;
490 u32 current_egress_rate; /* Mbits /sec */
491 u64 max_pkt_time;
492 /*
493 * max_pkt_time is the maximum packet egress time in units
494 * of the fabric clock period 1/(805 MHz).
495 */
496
497 cc_state = get_cc_state(ppd);
498
499 if (!cc_state)
500 /*
501 * This should _never_ happen - rcu_read_lock() is held,
502 * and set_link_ipg() should not be called if cc_state
503 * is NULL.
504 */
505 return;
506
507 for (i = 0; i < OPA_MAX_SLS; i++) {
508 u16 ccti = ppd->cca_timer[i].ccti;
509
510 if (ccti > max_ccti)
511 max_ccti = ccti;
512 }
513
514 ccti_limit = cc_state->cct.ccti_limit;
515 if (max_ccti > ccti_limit)
516 max_ccti = ccti_limit;
517
518 cce = cc_state->cct.entries[max_ccti].entry;
519 shift = (cce & 0xc000) >> 14;
520 mult = (cce & 0x3fff);
521
522 current_egress_rate = active_egress_rate(ppd);
523
524 max_pkt_time = egress_cycles(ppd->ibmaxlen, current_egress_rate);
525
526 src = (max_pkt_time >> shift) * mult;
527
528 src &= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SMASK;
529 src <<= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SHIFT;
530
531 write_csr(dd, SEND_STATIC_RATE_CONTROL, src);
532 }
533
cca_timer_fn(struct hrtimer * t)534 static enum hrtimer_restart cca_timer_fn(struct hrtimer *t)
535 {
536 struct cca_timer *cca_timer;
537 struct hfi1_pportdata *ppd;
538 int sl;
539 u16 ccti_timer, ccti_min;
540 struct cc_state *cc_state;
541 unsigned long flags;
542 enum hrtimer_restart ret = HRTIMER_NORESTART;
543
544 cca_timer = container_of(t, struct cca_timer, hrtimer);
545 ppd = cca_timer->ppd;
546 sl = cca_timer->sl;
547
548 rcu_read_lock();
549
550 cc_state = get_cc_state(ppd);
551
552 if (!cc_state) {
553 rcu_read_unlock();
554 return HRTIMER_NORESTART;
555 }
556
557 /*
558 * 1) decrement ccti for SL
559 * 2) calculate IPG for link (set_link_ipg())
560 * 3) restart timer, unless ccti is at min value
561 */
562
563 ccti_min = cc_state->cong_setting.entries[sl].ccti_min;
564 ccti_timer = cc_state->cong_setting.entries[sl].ccti_timer;
565
566 spin_lock_irqsave(&ppd->cca_timer_lock, flags);
567
568 if (cca_timer->ccti > ccti_min) {
569 cca_timer->ccti--;
570 set_link_ipg(ppd);
571 }
572
573 if (cca_timer->ccti > ccti_min) {
574 unsigned long nsec = 1024 * ccti_timer;
575 /* ccti_timer is in units of 1.024 usec */
576 hrtimer_forward_now(t, ns_to_ktime(nsec));
577 ret = HRTIMER_RESTART;
578 }
579
580 spin_unlock_irqrestore(&ppd->cca_timer_lock, flags);
581 rcu_read_unlock();
582 return ret;
583 }
584
585 /*
586 * Common code for initializing the physical port structure.
587 */
hfi1_init_pportdata(struct pci_dev * pdev,struct hfi1_pportdata * ppd,struct hfi1_devdata * dd,u8 hw_pidx,u32 port)588 void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd,
589 struct hfi1_devdata *dd, u8 hw_pidx, u32 port)
590 {
591 int i;
592 uint default_pkey_idx;
593 struct cc_state *cc_state;
594
595 ppd->dd = dd;
596 ppd->hw_pidx = hw_pidx;
597 ppd->port = port; /* IB port number, not index */
598 ppd->prev_link_width = LINK_WIDTH_DEFAULT;
599 /*
600 * There are C_VL_COUNT number of PortVLXmitWait counters.
601 * Adding 1 to C_VL_COUNT to include the PortXmitWait counter.
602 */
603 for (i = 0; i < C_VL_COUNT + 1; i++) {
604 ppd->port_vl_xmit_wait_last[i] = 0;
605 ppd->vl_xmit_flit_cnt[i] = 0;
606 }
607
608 default_pkey_idx = 1;
609
610 ppd->pkeys[default_pkey_idx] = DEFAULT_P_KEY;
611 ppd->part_enforce |= HFI1_PART_ENFORCE_IN;
612 ppd->pkeys[0] = 0x8001;
613
614 INIT_WORK(&ppd->link_vc_work, handle_verify_cap);
615 INIT_WORK(&ppd->link_up_work, handle_link_up);
616 INIT_WORK(&ppd->link_down_work, handle_link_down);
617 INIT_WORK(&ppd->freeze_work, handle_freeze);
618 INIT_WORK(&ppd->link_downgrade_work, handle_link_downgrade);
619 INIT_WORK(&ppd->sma_message_work, handle_sma_message);
620 INIT_WORK(&ppd->link_bounce_work, handle_link_bounce);
621 INIT_DELAYED_WORK(&ppd->start_link_work, handle_start_link);
622 INIT_WORK(&ppd->linkstate_active_work, receive_interrupt_work);
623 INIT_WORK(&ppd->qsfp_info.qsfp_work, qsfp_event);
624
625 mutex_init(&ppd->hls_lock);
626 spin_lock_init(&ppd->qsfp_info.qsfp_lock);
627
628 ppd->qsfp_info.ppd = ppd;
629 ppd->sm_trap_qp = 0x0;
630 ppd->sa_qp = 0x1;
631
632 ppd->hfi1_wq = NULL;
633
634 spin_lock_init(&ppd->cca_timer_lock);
635
636 for (i = 0; i < OPA_MAX_SLS; i++) {
637 hrtimer_init(&ppd->cca_timer[i].hrtimer, CLOCK_MONOTONIC,
638 HRTIMER_MODE_REL);
639 ppd->cca_timer[i].ppd = ppd;
640 ppd->cca_timer[i].sl = i;
641 ppd->cca_timer[i].ccti = 0;
642 ppd->cca_timer[i].hrtimer.function = cca_timer_fn;
643 }
644
645 ppd->cc_max_table_entries = IB_CC_TABLE_CAP_DEFAULT;
646
647 spin_lock_init(&ppd->cc_state_lock);
648 spin_lock_init(&ppd->cc_log_lock);
649 cc_state = kzalloc(sizeof(*cc_state), GFP_KERNEL);
650 RCU_INIT_POINTER(ppd->cc_state, cc_state);
651 if (!cc_state)
652 goto bail;
653 return;
654
655 bail:
656 dd_dev_err(dd, "Congestion Control Agent disabled for port %d\n", port);
657 }
658
659 /*
660 * Do initialization for device that is only needed on
661 * first detect, not on resets.
662 */
loadtime_init(struct hfi1_devdata * dd)663 static int loadtime_init(struct hfi1_devdata *dd)
664 {
665 return 0;
666 }
667
668 /**
669 * init_after_reset - re-initialize after a reset
670 * @dd: the hfi1_ib device
671 *
672 * sanity check at least some of the values after reset, and
673 * ensure no receive or transmit (explicitly, in case reset
674 * failed
675 */
init_after_reset(struct hfi1_devdata * dd)676 static int init_after_reset(struct hfi1_devdata *dd)
677 {
678 int i;
679 struct hfi1_ctxtdata *rcd;
680 /*
681 * Ensure chip does no sends or receives, tail updates, or
682 * pioavail updates while we re-initialize. This is mostly
683 * for the driver data structures, not chip registers.
684 */
685 for (i = 0; i < dd->num_rcv_contexts; i++) {
686 rcd = hfi1_rcd_get_by_index(dd, i);
687 hfi1_rcvctrl(dd, HFI1_RCVCTRL_CTXT_DIS |
688 HFI1_RCVCTRL_INTRAVAIL_DIS |
689 HFI1_RCVCTRL_TAILUPD_DIS, rcd);
690 hfi1_rcd_put(rcd);
691 }
692 pio_send_control(dd, PSC_GLOBAL_DISABLE);
693 for (i = 0; i < dd->num_send_contexts; i++)
694 sc_disable(dd->send_contexts[i].sc);
695
696 return 0;
697 }
698
enable_chip(struct hfi1_devdata * dd)699 static void enable_chip(struct hfi1_devdata *dd)
700 {
701 struct hfi1_ctxtdata *rcd;
702 u32 rcvmask;
703 u16 i;
704
705 /* enable PIO send */
706 pio_send_control(dd, PSC_GLOBAL_ENABLE);
707
708 /*
709 * Enable kernel ctxts' receive and receive interrupt.
710 * Other ctxts done as user opens and initializes them.
711 */
712 for (i = 0; i < dd->first_dyn_alloc_ctxt; ++i) {
713 rcd = hfi1_rcd_get_by_index(dd, i);
714 if (!rcd)
715 continue;
716 rcvmask = HFI1_RCVCTRL_CTXT_ENB | HFI1_RCVCTRL_INTRAVAIL_ENB;
717 rcvmask |= HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL) ?
718 HFI1_RCVCTRL_TAILUPD_ENB : HFI1_RCVCTRL_TAILUPD_DIS;
719 if (!HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR))
720 rcvmask |= HFI1_RCVCTRL_ONE_PKT_EGR_ENB;
721 if (HFI1_CAP_KGET_MASK(rcd->flags, NODROP_RHQ_FULL))
722 rcvmask |= HFI1_RCVCTRL_NO_RHQ_DROP_ENB;
723 if (HFI1_CAP_KGET_MASK(rcd->flags, NODROP_EGR_FULL))
724 rcvmask |= HFI1_RCVCTRL_NO_EGR_DROP_ENB;
725 if (HFI1_CAP_IS_KSET(TID_RDMA))
726 rcvmask |= HFI1_RCVCTRL_TIDFLOW_ENB;
727 hfi1_rcvctrl(dd, rcvmask, rcd);
728 sc_enable(rcd->sc);
729 hfi1_rcd_put(rcd);
730 }
731 }
732
733 /**
734 * create_workqueues - create per port workqueues
735 * @dd: the hfi1_ib device
736 */
create_workqueues(struct hfi1_devdata * dd)737 static int create_workqueues(struct hfi1_devdata *dd)
738 {
739 int pidx;
740 struct hfi1_pportdata *ppd;
741
742 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
743 ppd = dd->pport + pidx;
744 if (!ppd->hfi1_wq) {
745 ppd->hfi1_wq =
746 alloc_workqueue(
747 "hfi%d_%d",
748 WQ_SYSFS | WQ_HIGHPRI | WQ_CPU_INTENSIVE |
749 WQ_MEM_RECLAIM,
750 HFI1_MAX_ACTIVE_WORKQUEUE_ENTRIES,
751 dd->unit, pidx);
752 if (!ppd->hfi1_wq)
753 goto wq_error;
754 }
755 if (!ppd->link_wq) {
756 /*
757 * Make the link workqueue single-threaded to enforce
758 * serialization.
759 */
760 ppd->link_wq =
761 alloc_workqueue(
762 "hfi_link_%d_%d",
763 WQ_SYSFS | WQ_MEM_RECLAIM | WQ_UNBOUND,
764 1, /* max_active */
765 dd->unit, pidx);
766 if (!ppd->link_wq)
767 goto wq_error;
768 }
769 }
770 return 0;
771 wq_error:
772 pr_err("alloc_workqueue failed for port %d\n", pidx + 1);
773 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
774 ppd = dd->pport + pidx;
775 if (ppd->hfi1_wq) {
776 destroy_workqueue(ppd->hfi1_wq);
777 ppd->hfi1_wq = NULL;
778 }
779 if (ppd->link_wq) {
780 destroy_workqueue(ppd->link_wq);
781 ppd->link_wq = NULL;
782 }
783 }
784 return -ENOMEM;
785 }
786
787 /**
788 * destroy_workqueues - destroy per port workqueues
789 * @dd: the hfi1_ib device
790 */
destroy_workqueues(struct hfi1_devdata * dd)791 static void destroy_workqueues(struct hfi1_devdata *dd)
792 {
793 int pidx;
794 struct hfi1_pportdata *ppd;
795
796 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
797 ppd = dd->pport + pidx;
798
799 if (ppd->hfi1_wq) {
800 destroy_workqueue(ppd->hfi1_wq);
801 ppd->hfi1_wq = NULL;
802 }
803 if (ppd->link_wq) {
804 destroy_workqueue(ppd->link_wq);
805 ppd->link_wq = NULL;
806 }
807 }
808 }
809
810 /**
811 * enable_general_intr() - Enable the IRQs that will be handled by the
812 * general interrupt handler.
813 * @dd: valid devdata
814 *
815 */
enable_general_intr(struct hfi1_devdata * dd)816 static void enable_general_intr(struct hfi1_devdata *dd)
817 {
818 set_intr_bits(dd, CCE_ERR_INT, MISC_ERR_INT, true);
819 set_intr_bits(dd, PIO_ERR_INT, TXE_ERR_INT, true);
820 set_intr_bits(dd, IS_SENDCTXT_ERR_START, IS_SENDCTXT_ERR_END, true);
821 set_intr_bits(dd, PBC_INT, GPIO_ASSERT_INT, true);
822 set_intr_bits(dd, TCRIT_INT, TCRIT_INT, true);
823 set_intr_bits(dd, IS_DC_START, IS_DC_END, true);
824 set_intr_bits(dd, IS_SENDCREDIT_START, IS_SENDCREDIT_END, true);
825 }
826
827 /**
828 * hfi1_init - do the actual initialization sequence on the chip
829 * @dd: the hfi1_ib device
830 * @reinit: re-initializing, so don't allocate new memory
831 *
832 * Do the actual initialization sequence on the chip. This is done
833 * both from the init routine called from the PCI infrastructure, and
834 * when we reset the chip, or detect that it was reset internally,
835 * or it's administratively re-enabled.
836 *
837 * Memory allocation here and in called routines is only done in
838 * the first case (reinit == 0). We have to be careful, because even
839 * without memory allocation, we need to re-write all the chip registers
840 * TIDs, etc. after the reset or enable has completed.
841 */
hfi1_init(struct hfi1_devdata * dd,int reinit)842 int hfi1_init(struct hfi1_devdata *dd, int reinit)
843 {
844 int ret = 0, pidx, lastfail = 0;
845 unsigned long len;
846 u16 i;
847 struct hfi1_ctxtdata *rcd;
848 struct hfi1_pportdata *ppd;
849
850 /* Set up send low level handlers */
851 dd->process_pio_send = hfi1_verbs_send_pio;
852 dd->process_dma_send = hfi1_verbs_send_dma;
853 dd->pio_inline_send = pio_copy;
854 dd->process_vnic_dma_send = hfi1_vnic_send_dma;
855
856 if (is_ax(dd)) {
857 atomic_set(&dd->drop_packet, DROP_PACKET_ON);
858 dd->do_drop = true;
859 } else {
860 atomic_set(&dd->drop_packet, DROP_PACKET_OFF);
861 dd->do_drop = false;
862 }
863
864 /* make sure the link is not "up" */
865 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
866 ppd = dd->pport + pidx;
867 ppd->linkup = 0;
868 }
869
870 if (reinit)
871 ret = init_after_reset(dd);
872 else
873 ret = loadtime_init(dd);
874 if (ret)
875 goto done;
876
877 /* dd->rcd can be NULL if early initialization failed */
878 for (i = 0; dd->rcd && i < dd->first_dyn_alloc_ctxt; ++i) {
879 /*
880 * Set up the (kernel) rcvhdr queue and egr TIDs. If doing
881 * re-init, the simplest way to handle this is to free
882 * existing, and re-allocate.
883 * Need to re-create rest of ctxt 0 ctxtdata as well.
884 */
885 rcd = hfi1_rcd_get_by_index(dd, i);
886 if (!rcd)
887 continue;
888
889 lastfail = hfi1_create_rcvhdrq(dd, rcd);
890 if (!lastfail)
891 lastfail = hfi1_setup_eagerbufs(rcd);
892 if (!lastfail)
893 lastfail = hfi1_kern_exp_rcv_init(rcd, reinit);
894 if (lastfail) {
895 dd_dev_err(dd,
896 "failed to allocate kernel ctxt's rcvhdrq and/or egr bufs\n");
897 ret = lastfail;
898 }
899 /* enable IRQ */
900 hfi1_rcd_put(rcd);
901 }
902
903 /* Allocate enough memory for user event notification. */
904 len = PAGE_ALIGN(chip_rcv_contexts(dd) * HFI1_MAX_SHARED_CTXTS *
905 sizeof(*dd->events));
906 dd->events = vmalloc_user(len);
907 if (!dd->events)
908 dd_dev_err(dd, "Failed to allocate user events page\n");
909 /*
910 * Allocate a page for device and port status.
911 * Page will be shared amongst all user processes.
912 */
913 dd->status = vmalloc_user(PAGE_SIZE);
914 if (!dd->status)
915 dd_dev_err(dd, "Failed to allocate dev status page\n");
916 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
917 ppd = dd->pport + pidx;
918 if (dd->status)
919 /* Currently, we only have one port */
920 ppd->statusp = &dd->status->port;
921
922 set_mtu(ppd);
923 }
924
925 /* enable chip even if we have an error, so we can debug cause */
926 enable_chip(dd);
927
928 done:
929 /*
930 * Set status even if port serdes is not initialized
931 * so that diags will work.
932 */
933 if (dd->status)
934 dd->status->dev |= HFI1_STATUS_CHIP_PRESENT |
935 HFI1_STATUS_INITTED;
936 if (!ret) {
937 /* enable all interrupts from the chip */
938 enable_general_intr(dd);
939 init_qsfp_int(dd);
940
941 /* chip is OK for user apps; mark it as initialized */
942 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
943 ppd = dd->pport + pidx;
944
945 /*
946 * start the serdes - must be after interrupts are
947 * enabled so we are notified when the link goes up
948 */
949 lastfail = bringup_serdes(ppd);
950 if (lastfail)
951 dd_dev_info(dd,
952 "Failed to bring up port %u\n",
953 ppd->port);
954
955 /*
956 * Set status even if port serdes is not initialized
957 * so that diags will work.
958 */
959 if (ppd->statusp)
960 *ppd->statusp |= HFI1_STATUS_CHIP_PRESENT |
961 HFI1_STATUS_INITTED;
962 if (!ppd->link_speed_enabled)
963 continue;
964 }
965 }
966
967 /* if ret is non-zero, we probably should do some cleanup here... */
968 return ret;
969 }
970
hfi1_lookup(int unit)971 struct hfi1_devdata *hfi1_lookup(int unit)
972 {
973 return xa_load(&hfi1_dev_table, unit);
974 }
975
976 /*
977 * Stop the timers during unit shutdown, or after an error late
978 * in initialization.
979 */
stop_timers(struct hfi1_devdata * dd)980 static void stop_timers(struct hfi1_devdata *dd)
981 {
982 struct hfi1_pportdata *ppd;
983 int pidx;
984
985 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
986 ppd = dd->pport + pidx;
987 if (ppd->led_override_timer.function) {
988 del_timer_sync(&ppd->led_override_timer);
989 atomic_set(&ppd->led_override_timer_active, 0);
990 }
991 }
992 }
993
994 /**
995 * shutdown_device - shut down a device
996 * @dd: the hfi1_ib device
997 *
998 * This is called to make the device quiet when we are about to
999 * unload the driver, and also when the device is administratively
1000 * disabled. It does not free any data structures.
1001 * Everything it does has to be setup again by hfi1_init(dd, 1)
1002 */
shutdown_device(struct hfi1_devdata * dd)1003 static void shutdown_device(struct hfi1_devdata *dd)
1004 {
1005 struct hfi1_pportdata *ppd;
1006 struct hfi1_ctxtdata *rcd;
1007 unsigned pidx;
1008 int i;
1009
1010 if (dd->flags & HFI1_SHUTDOWN)
1011 return;
1012 dd->flags |= HFI1_SHUTDOWN;
1013
1014 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1015 ppd = dd->pport + pidx;
1016
1017 ppd->linkup = 0;
1018 if (ppd->statusp)
1019 *ppd->statusp &= ~(HFI1_STATUS_IB_CONF |
1020 HFI1_STATUS_IB_READY);
1021 }
1022 dd->flags &= ~HFI1_INITTED;
1023
1024 /* mask and clean up interrupts */
1025 set_intr_bits(dd, IS_FIRST_SOURCE, IS_LAST_SOURCE, false);
1026 msix_clean_up_interrupts(dd);
1027
1028 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1029 ppd = dd->pport + pidx;
1030 for (i = 0; i < dd->num_rcv_contexts; i++) {
1031 rcd = hfi1_rcd_get_by_index(dd, i);
1032 hfi1_rcvctrl(dd, HFI1_RCVCTRL_TAILUPD_DIS |
1033 HFI1_RCVCTRL_CTXT_DIS |
1034 HFI1_RCVCTRL_INTRAVAIL_DIS |
1035 HFI1_RCVCTRL_PKEY_DIS |
1036 HFI1_RCVCTRL_ONE_PKT_EGR_DIS, rcd);
1037 hfi1_rcd_put(rcd);
1038 }
1039 /*
1040 * Gracefully stop all sends allowing any in progress to
1041 * trickle out first.
1042 */
1043 for (i = 0; i < dd->num_send_contexts; i++)
1044 sc_flush(dd->send_contexts[i].sc);
1045 }
1046
1047 /*
1048 * Enough for anything that's going to trickle out to have actually
1049 * done so.
1050 */
1051 udelay(20);
1052
1053 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1054 ppd = dd->pport + pidx;
1055
1056 /* disable all contexts */
1057 for (i = 0; i < dd->num_send_contexts; i++)
1058 sc_disable(dd->send_contexts[i].sc);
1059 /* disable the send device */
1060 pio_send_control(dd, PSC_GLOBAL_DISABLE);
1061
1062 shutdown_led_override(ppd);
1063
1064 /*
1065 * Clear SerdesEnable.
1066 * We can't count on interrupts since we are stopping.
1067 */
1068 hfi1_quiet_serdes(ppd);
1069 if (ppd->hfi1_wq)
1070 flush_workqueue(ppd->hfi1_wq);
1071 if (ppd->link_wq)
1072 flush_workqueue(ppd->link_wq);
1073 }
1074 sdma_exit(dd);
1075 }
1076
1077 /**
1078 * hfi1_free_ctxtdata - free a context's allocated data
1079 * @dd: the hfi1_ib device
1080 * @rcd: the ctxtdata structure
1081 *
1082 * free up any allocated data for a context
1083 * It should never change any chip state, or global driver state.
1084 */
hfi1_free_ctxtdata(struct hfi1_devdata * dd,struct hfi1_ctxtdata * rcd)1085 void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
1086 {
1087 u32 e;
1088
1089 if (!rcd)
1090 return;
1091
1092 if (rcd->rcvhdrq) {
1093 dma_free_coherent(&dd->pcidev->dev, rcvhdrq_size(rcd),
1094 rcd->rcvhdrq, rcd->rcvhdrq_dma);
1095 rcd->rcvhdrq = NULL;
1096 if (hfi1_rcvhdrtail_kvaddr(rcd)) {
1097 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
1098 (void *)hfi1_rcvhdrtail_kvaddr(rcd),
1099 rcd->rcvhdrqtailaddr_dma);
1100 rcd->rcvhdrtail_kvaddr = NULL;
1101 }
1102 }
1103
1104 /* all the RcvArray entries should have been cleared by now */
1105 kfree(rcd->egrbufs.rcvtids);
1106 rcd->egrbufs.rcvtids = NULL;
1107
1108 for (e = 0; e < rcd->egrbufs.alloced; e++) {
1109 if (rcd->egrbufs.buffers[e].addr)
1110 dma_free_coherent(&dd->pcidev->dev,
1111 rcd->egrbufs.buffers[e].len,
1112 rcd->egrbufs.buffers[e].addr,
1113 rcd->egrbufs.buffers[e].dma);
1114 }
1115 kfree(rcd->egrbufs.buffers);
1116 rcd->egrbufs.alloced = 0;
1117 rcd->egrbufs.buffers = NULL;
1118
1119 sc_free(rcd->sc);
1120 rcd->sc = NULL;
1121
1122 vfree(rcd->subctxt_uregbase);
1123 vfree(rcd->subctxt_rcvegrbuf);
1124 vfree(rcd->subctxt_rcvhdr_base);
1125 kfree(rcd->opstats);
1126
1127 rcd->subctxt_uregbase = NULL;
1128 rcd->subctxt_rcvegrbuf = NULL;
1129 rcd->subctxt_rcvhdr_base = NULL;
1130 rcd->opstats = NULL;
1131 }
1132
1133 /*
1134 * Release our hold on the shared asic data. If we are the last one,
1135 * return the structure to be finalized outside the lock. Must be
1136 * holding hfi1_dev_table lock.
1137 */
release_asic_data(struct hfi1_devdata * dd)1138 static struct hfi1_asic_data *release_asic_data(struct hfi1_devdata *dd)
1139 {
1140 struct hfi1_asic_data *ad;
1141 int other;
1142
1143 if (!dd->asic_data)
1144 return NULL;
1145 dd->asic_data->dds[dd->hfi1_id] = NULL;
1146 other = dd->hfi1_id ? 0 : 1;
1147 ad = dd->asic_data;
1148 dd->asic_data = NULL;
1149 /* return NULL if the other dd still has a link */
1150 return ad->dds[other] ? NULL : ad;
1151 }
1152
finalize_asic_data(struct hfi1_devdata * dd,struct hfi1_asic_data * ad)1153 static void finalize_asic_data(struct hfi1_devdata *dd,
1154 struct hfi1_asic_data *ad)
1155 {
1156 clean_up_i2c(dd, ad);
1157 kfree(ad);
1158 }
1159
1160 /**
1161 * hfi1_free_devdata - cleans up and frees per-unit data structure
1162 * @dd: pointer to a valid devdata structure
1163 *
1164 * It cleans up and frees all data structures set up by
1165 * by hfi1_alloc_devdata().
1166 */
hfi1_free_devdata(struct hfi1_devdata * dd)1167 void hfi1_free_devdata(struct hfi1_devdata *dd)
1168 {
1169 struct hfi1_asic_data *ad;
1170 unsigned long flags;
1171
1172 xa_lock_irqsave(&hfi1_dev_table, flags);
1173 __xa_erase(&hfi1_dev_table, dd->unit);
1174 ad = release_asic_data(dd);
1175 xa_unlock_irqrestore(&hfi1_dev_table, flags);
1176
1177 finalize_asic_data(dd, ad);
1178 free_platform_config(dd);
1179 rcu_barrier(); /* wait for rcu callbacks to complete */
1180 free_percpu(dd->int_counter);
1181 free_percpu(dd->rcv_limit);
1182 free_percpu(dd->send_schedule);
1183 free_percpu(dd->tx_opstats);
1184 dd->int_counter = NULL;
1185 dd->rcv_limit = NULL;
1186 dd->send_schedule = NULL;
1187 dd->tx_opstats = NULL;
1188 kfree(dd->comp_vect);
1189 dd->comp_vect = NULL;
1190 if (dd->rcvhdrtail_dummy_kvaddr)
1191 dma_free_coherent(&dd->pcidev->dev, sizeof(u64),
1192 (void *)dd->rcvhdrtail_dummy_kvaddr,
1193 dd->rcvhdrtail_dummy_dma);
1194 dd->rcvhdrtail_dummy_kvaddr = NULL;
1195 sdma_clean(dd, dd->num_sdma);
1196 rvt_dealloc_device(&dd->verbs_dev.rdi);
1197 }
1198
1199 /**
1200 * hfi1_alloc_devdata - Allocate our primary per-unit data structure.
1201 * @pdev: Valid PCI device
1202 * @extra: How many bytes to alloc past the default
1203 *
1204 * Must be done via verbs allocator, because the verbs cleanup process
1205 * both does cleanup and free of the data structure.
1206 * "extra" is for chip-specific data.
1207 */
hfi1_alloc_devdata(struct pci_dev * pdev,size_t extra)1208 static struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev,
1209 size_t extra)
1210 {
1211 struct hfi1_devdata *dd;
1212 int ret, nports;
1213
1214 /* extra is * number of ports */
1215 nports = extra / sizeof(struct hfi1_pportdata);
1216
1217 dd = (struct hfi1_devdata *)rvt_alloc_device(sizeof(*dd) + extra,
1218 nports);
1219 if (!dd)
1220 return ERR_PTR(-ENOMEM);
1221 dd->num_pports = nports;
1222 dd->pport = (struct hfi1_pportdata *)(dd + 1);
1223 dd->pcidev = pdev;
1224 pci_set_drvdata(pdev, dd);
1225
1226 ret = xa_alloc_irq(&hfi1_dev_table, &dd->unit, dd, xa_limit_32b,
1227 GFP_KERNEL);
1228 if (ret < 0) {
1229 dev_err(&pdev->dev,
1230 "Could not allocate unit ID: error %d\n", -ret);
1231 goto bail;
1232 }
1233 rvt_set_ibdev_name(&dd->verbs_dev.rdi, "%s_%d", class_name(), dd->unit);
1234 /*
1235 * If the BIOS does not have the NUMA node information set, select
1236 * NUMA 0 so we get consistent performance.
1237 */
1238 dd->node = pcibus_to_node(pdev->bus);
1239 if (dd->node == NUMA_NO_NODE) {
1240 dd_dev_err(dd, "Invalid PCI NUMA node. Performance may be affected\n");
1241 dd->node = 0;
1242 }
1243
1244 /*
1245 * Initialize all locks for the device. This needs to be as early as
1246 * possible so locks are usable.
1247 */
1248 spin_lock_init(&dd->sc_lock);
1249 spin_lock_init(&dd->sendctrl_lock);
1250 spin_lock_init(&dd->rcvctrl_lock);
1251 spin_lock_init(&dd->uctxt_lock);
1252 spin_lock_init(&dd->hfi1_diag_trans_lock);
1253 spin_lock_init(&dd->sc_init_lock);
1254 spin_lock_init(&dd->dc8051_memlock);
1255 seqlock_init(&dd->sc2vl_lock);
1256 spin_lock_init(&dd->sde_map_lock);
1257 spin_lock_init(&dd->pio_map_lock);
1258 mutex_init(&dd->dc8051_lock);
1259 init_waitqueue_head(&dd->event_queue);
1260 spin_lock_init(&dd->irq_src_lock);
1261
1262 dd->int_counter = alloc_percpu(u64);
1263 if (!dd->int_counter) {
1264 ret = -ENOMEM;
1265 goto bail;
1266 }
1267
1268 dd->rcv_limit = alloc_percpu(u64);
1269 if (!dd->rcv_limit) {
1270 ret = -ENOMEM;
1271 goto bail;
1272 }
1273
1274 dd->send_schedule = alloc_percpu(u64);
1275 if (!dd->send_schedule) {
1276 ret = -ENOMEM;
1277 goto bail;
1278 }
1279
1280 dd->tx_opstats = alloc_percpu(struct hfi1_opcode_stats_perctx);
1281 if (!dd->tx_opstats) {
1282 ret = -ENOMEM;
1283 goto bail;
1284 }
1285
1286 dd->comp_vect = kzalloc(sizeof(*dd->comp_vect), GFP_KERNEL);
1287 if (!dd->comp_vect) {
1288 ret = -ENOMEM;
1289 goto bail;
1290 }
1291
1292 /* allocate dummy tail memory for all receive contexts */
1293 dd->rcvhdrtail_dummy_kvaddr =
1294 dma_alloc_coherent(&dd->pcidev->dev, sizeof(u64),
1295 &dd->rcvhdrtail_dummy_dma, GFP_KERNEL);
1296 if (!dd->rcvhdrtail_dummy_kvaddr) {
1297 ret = -ENOMEM;
1298 goto bail;
1299 }
1300
1301 atomic_set(&dd->ipoib_rsm_usr_num, 0);
1302 return dd;
1303
1304 bail:
1305 hfi1_free_devdata(dd);
1306 return ERR_PTR(ret);
1307 }
1308
1309 /*
1310 * Called from freeze mode handlers, and from PCI error
1311 * reporting code. Should be paranoid about state of
1312 * system and data structures.
1313 */
hfi1_disable_after_error(struct hfi1_devdata * dd)1314 void hfi1_disable_after_error(struct hfi1_devdata *dd)
1315 {
1316 if (dd->flags & HFI1_INITTED) {
1317 u32 pidx;
1318
1319 dd->flags &= ~HFI1_INITTED;
1320 if (dd->pport)
1321 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1322 struct hfi1_pportdata *ppd;
1323
1324 ppd = dd->pport + pidx;
1325 if (dd->flags & HFI1_PRESENT)
1326 set_link_state(ppd, HLS_DN_DISABLE);
1327
1328 if (ppd->statusp)
1329 *ppd->statusp &= ~HFI1_STATUS_IB_READY;
1330 }
1331 }
1332
1333 /*
1334 * Mark as having had an error for driver, and also
1335 * for /sys and status word mapped to user programs.
1336 * This marks unit as not usable, until reset.
1337 */
1338 if (dd->status)
1339 dd->status->dev |= HFI1_STATUS_HWERROR;
1340 }
1341
1342 static void remove_one(struct pci_dev *);
1343 static int init_one(struct pci_dev *, const struct pci_device_id *);
1344 static void shutdown_one(struct pci_dev *);
1345
1346 #define DRIVER_LOAD_MSG "Intel " DRIVER_NAME " loaded: "
1347 #define PFX DRIVER_NAME ": "
1348
1349 const struct pci_device_id hfi1_pci_tbl[] = {
1350 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL0) },
1351 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL1) },
1352 { 0, }
1353 };
1354
1355 MODULE_DEVICE_TABLE(pci, hfi1_pci_tbl);
1356
1357 static struct pci_driver hfi1_pci_driver = {
1358 .name = DRIVER_NAME,
1359 .probe = init_one,
1360 .remove = remove_one,
1361 .shutdown = shutdown_one,
1362 .id_table = hfi1_pci_tbl,
1363 .err_handler = &hfi1_pci_err_handler,
1364 };
1365
compute_krcvqs(void)1366 static void __init compute_krcvqs(void)
1367 {
1368 int i;
1369
1370 for (i = 0; i < krcvqsset; i++)
1371 n_krcvqs += krcvqs[i];
1372 }
1373
1374 /*
1375 * Do all the generic driver unit- and chip-independent memory
1376 * allocation and initialization.
1377 */
hfi1_mod_init(void)1378 static int __init hfi1_mod_init(void)
1379 {
1380 int ret;
1381
1382 ret = dev_init();
1383 if (ret)
1384 goto bail;
1385
1386 ret = node_affinity_init();
1387 if (ret)
1388 goto bail;
1389
1390 /* validate max MTU before any devices start */
1391 if (!valid_opa_max_mtu(hfi1_max_mtu)) {
1392 pr_err("Invalid max_mtu 0x%x, using 0x%x instead\n",
1393 hfi1_max_mtu, HFI1_DEFAULT_MAX_MTU);
1394 hfi1_max_mtu = HFI1_DEFAULT_MAX_MTU;
1395 }
1396 /* valid CUs run from 1-128 in powers of 2 */
1397 if (hfi1_cu > 128 || !is_power_of_2(hfi1_cu))
1398 hfi1_cu = 1;
1399 /* valid credit return threshold is 0-100, variable is unsigned */
1400 if (user_credit_return_threshold > 100)
1401 user_credit_return_threshold = 100;
1402
1403 compute_krcvqs();
1404 /*
1405 * sanitize receive interrupt count, time must wait until after
1406 * the hardware type is known
1407 */
1408 if (rcv_intr_count > RCV_HDR_HEAD_COUNTER_MASK)
1409 rcv_intr_count = RCV_HDR_HEAD_COUNTER_MASK;
1410 /* reject invalid combinations */
1411 if (rcv_intr_count == 0 && rcv_intr_timeout == 0) {
1412 pr_err("Invalid mode: both receive interrupt count and available timeout are zero - setting interrupt count to 1\n");
1413 rcv_intr_count = 1;
1414 }
1415 if (rcv_intr_count > 1 && rcv_intr_timeout == 0) {
1416 /*
1417 * Avoid indefinite packet delivery by requiring a timeout
1418 * if count is > 1.
1419 */
1420 pr_err("Invalid mode: receive interrupt count greater than 1 and available timeout is zero - setting available timeout to 1\n");
1421 rcv_intr_timeout = 1;
1422 }
1423 if (rcv_intr_dynamic && !(rcv_intr_count > 1 && rcv_intr_timeout > 0)) {
1424 /*
1425 * The dynamic algorithm expects a non-zero timeout
1426 * and a count > 1.
1427 */
1428 pr_err("Invalid mode: dynamic receive interrupt mitigation with invalid count and timeout - turning dynamic off\n");
1429 rcv_intr_dynamic = 0;
1430 }
1431
1432 /* sanitize link CRC options */
1433 link_crc_mask &= SUPPORTED_CRCS;
1434
1435 ret = opfn_init();
1436 if (ret < 0) {
1437 pr_err("Failed to allocate opfn_wq");
1438 goto bail_dev;
1439 }
1440
1441 /*
1442 * These must be called before the driver is registered with
1443 * the PCI subsystem.
1444 */
1445 hfi1_dbg_init();
1446 ret = pci_register_driver(&hfi1_pci_driver);
1447 if (ret < 0) {
1448 pr_err("Unable to register driver: error %d\n", -ret);
1449 goto bail_dev;
1450 }
1451 goto bail; /* all OK */
1452
1453 bail_dev:
1454 hfi1_dbg_exit();
1455 dev_cleanup();
1456 bail:
1457 return ret;
1458 }
1459
1460 module_init(hfi1_mod_init);
1461
1462 /*
1463 * Do the non-unit driver cleanup, memory free, etc. at unload.
1464 */
hfi1_mod_cleanup(void)1465 static void __exit hfi1_mod_cleanup(void)
1466 {
1467 pci_unregister_driver(&hfi1_pci_driver);
1468 opfn_exit();
1469 node_affinity_destroy_all();
1470 hfi1_dbg_exit();
1471
1472 WARN_ON(!xa_empty(&hfi1_dev_table));
1473 dispose_firmware(); /* asymmetric with obtain_firmware() */
1474 dev_cleanup();
1475 }
1476
1477 module_exit(hfi1_mod_cleanup);
1478
1479 /* this can only be called after a successful initialization */
cleanup_device_data(struct hfi1_devdata * dd)1480 static void cleanup_device_data(struct hfi1_devdata *dd)
1481 {
1482 int ctxt;
1483 int pidx;
1484
1485 /* users can't do anything more with chip */
1486 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1487 struct hfi1_pportdata *ppd = &dd->pport[pidx];
1488 struct cc_state *cc_state;
1489 int i;
1490
1491 if (ppd->statusp)
1492 *ppd->statusp &= ~HFI1_STATUS_CHIP_PRESENT;
1493
1494 for (i = 0; i < OPA_MAX_SLS; i++)
1495 hrtimer_cancel(&ppd->cca_timer[i].hrtimer);
1496
1497 spin_lock(&ppd->cc_state_lock);
1498 cc_state = get_cc_state_protected(ppd);
1499 RCU_INIT_POINTER(ppd->cc_state, NULL);
1500 spin_unlock(&ppd->cc_state_lock);
1501
1502 if (cc_state)
1503 kfree_rcu(cc_state, rcu);
1504 }
1505
1506 free_credit_return(dd);
1507
1508 /*
1509 * Free any resources still in use (usually just kernel contexts)
1510 * at unload; we do for ctxtcnt, because that's what we allocate.
1511 */
1512 for (ctxt = 0; dd->rcd && ctxt < dd->num_rcv_contexts; ctxt++) {
1513 struct hfi1_ctxtdata *rcd = dd->rcd[ctxt];
1514
1515 if (rcd) {
1516 hfi1_free_ctxt_rcv_groups(rcd);
1517 hfi1_free_ctxt(rcd);
1518 }
1519 }
1520
1521 kfree(dd->rcd);
1522 dd->rcd = NULL;
1523
1524 free_pio_map(dd);
1525 /* must follow rcv context free - need to remove rcv's hooks */
1526 for (ctxt = 0; ctxt < dd->num_send_contexts; ctxt++)
1527 sc_free(dd->send_contexts[ctxt].sc);
1528 dd->num_send_contexts = 0;
1529 kfree(dd->send_contexts);
1530 dd->send_contexts = NULL;
1531 kfree(dd->hw_to_sw);
1532 dd->hw_to_sw = NULL;
1533 kfree(dd->boardname);
1534 vfree(dd->events);
1535 vfree(dd->status);
1536 }
1537
1538 /*
1539 * Clean up on unit shutdown, or error during unit load after
1540 * successful initialization.
1541 */
postinit_cleanup(struct hfi1_devdata * dd)1542 static void postinit_cleanup(struct hfi1_devdata *dd)
1543 {
1544 hfi1_start_cleanup(dd);
1545 hfi1_comp_vectors_clean_up(dd);
1546 hfi1_dev_affinity_clean_up(dd);
1547
1548 hfi1_pcie_ddcleanup(dd);
1549 hfi1_pcie_cleanup(dd->pcidev);
1550
1551 cleanup_device_data(dd);
1552
1553 hfi1_free_devdata(dd);
1554 }
1555
init_one(struct pci_dev * pdev,const struct pci_device_id * ent)1556 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1557 {
1558 int ret = 0, j, pidx, initfail;
1559 struct hfi1_devdata *dd;
1560 struct hfi1_pportdata *ppd;
1561
1562 /* First, lock the non-writable module parameters */
1563 HFI1_CAP_LOCK();
1564
1565 /* Validate dev ids */
1566 if (!(ent->device == PCI_DEVICE_ID_INTEL0 ||
1567 ent->device == PCI_DEVICE_ID_INTEL1)) {
1568 dev_err(&pdev->dev, "Failing on unknown Intel deviceid 0x%x\n",
1569 ent->device);
1570 ret = -ENODEV;
1571 goto bail;
1572 }
1573
1574 /* Allocate the dd so we can get to work */
1575 dd = hfi1_alloc_devdata(pdev, NUM_IB_PORTS *
1576 sizeof(struct hfi1_pportdata));
1577 if (IS_ERR(dd)) {
1578 ret = PTR_ERR(dd);
1579 goto bail;
1580 }
1581
1582 /* Validate some global module parameters */
1583 ret = hfi1_validate_rcvhdrcnt(dd, rcvhdrcnt);
1584 if (ret)
1585 goto bail;
1586
1587 /* use the encoding function as a sanitization check */
1588 if (!encode_rcv_header_entry_size(hfi1_hdrq_entsize)) {
1589 dd_dev_err(dd, "Invalid HdrQ Entry size %u\n",
1590 hfi1_hdrq_entsize);
1591 ret = -EINVAL;
1592 goto bail;
1593 }
1594
1595 /* The receive eager buffer size must be set before the receive
1596 * contexts are created.
1597 *
1598 * Set the eager buffer size. Validate that it falls in a range
1599 * allowed by the hardware - all powers of 2 between the min and
1600 * max. The maximum valid MTU is within the eager buffer range
1601 * so we do not need to cap the max_mtu by an eager buffer size
1602 * setting.
1603 */
1604 if (eager_buffer_size) {
1605 if (!is_power_of_2(eager_buffer_size))
1606 eager_buffer_size =
1607 roundup_pow_of_two(eager_buffer_size);
1608 eager_buffer_size =
1609 clamp_val(eager_buffer_size,
1610 MIN_EAGER_BUFFER * 8,
1611 MAX_EAGER_BUFFER_TOTAL);
1612 dd_dev_info(dd, "Eager buffer size %u\n",
1613 eager_buffer_size);
1614 } else {
1615 dd_dev_err(dd, "Invalid Eager buffer size of 0\n");
1616 ret = -EINVAL;
1617 goto bail;
1618 }
1619
1620 /* restrict value of hfi1_rcvarr_split */
1621 hfi1_rcvarr_split = clamp_val(hfi1_rcvarr_split, 0, 100);
1622
1623 ret = hfi1_pcie_init(dd);
1624 if (ret)
1625 goto bail;
1626
1627 /*
1628 * Do device-specific initialization, function table setup, dd
1629 * allocation, etc.
1630 */
1631 ret = hfi1_init_dd(dd);
1632 if (ret)
1633 goto clean_bail; /* error already printed */
1634
1635 ret = create_workqueues(dd);
1636 if (ret)
1637 goto clean_bail;
1638
1639 /* do the generic initialization */
1640 initfail = hfi1_init(dd, 0);
1641
1642 ret = hfi1_register_ib_device(dd);
1643
1644 /*
1645 * Now ready for use. this should be cleared whenever we
1646 * detect a reset, or initiate one. If earlier failure,
1647 * we still create devices, so diags, etc. can be used
1648 * to determine cause of problem.
1649 */
1650 if (!initfail && !ret) {
1651 dd->flags |= HFI1_INITTED;
1652 /* create debufs files after init and ib register */
1653 hfi1_dbg_ibdev_init(&dd->verbs_dev);
1654 }
1655
1656 j = hfi1_device_create(dd);
1657 if (j)
1658 dd_dev_err(dd, "Failed to create /dev devices: %d\n", -j);
1659
1660 if (initfail || ret) {
1661 msix_clean_up_interrupts(dd);
1662 stop_timers(dd);
1663 flush_workqueue(ib_wq);
1664 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1665 hfi1_quiet_serdes(dd->pport + pidx);
1666 ppd = dd->pport + pidx;
1667 if (ppd->hfi1_wq) {
1668 destroy_workqueue(ppd->hfi1_wq);
1669 ppd->hfi1_wq = NULL;
1670 }
1671 if (ppd->link_wq) {
1672 destroy_workqueue(ppd->link_wq);
1673 ppd->link_wq = NULL;
1674 }
1675 }
1676 if (!j)
1677 hfi1_device_remove(dd);
1678 if (!ret)
1679 hfi1_unregister_ib_device(dd);
1680 postinit_cleanup(dd);
1681 if (initfail)
1682 ret = initfail;
1683 goto bail; /* everything already cleaned */
1684 }
1685
1686 sdma_start(dd);
1687
1688 return 0;
1689
1690 clean_bail:
1691 hfi1_pcie_cleanup(pdev);
1692 bail:
1693 return ret;
1694 }
1695
wait_for_clients(struct hfi1_devdata * dd)1696 static void wait_for_clients(struct hfi1_devdata *dd)
1697 {
1698 /*
1699 * Remove the device init value and complete the device if there is
1700 * no clients or wait for active clients to finish.
1701 */
1702 if (refcount_dec_and_test(&dd->user_refcount))
1703 complete(&dd->user_comp);
1704
1705 wait_for_completion(&dd->user_comp);
1706 }
1707
remove_one(struct pci_dev * pdev)1708 static void remove_one(struct pci_dev *pdev)
1709 {
1710 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
1711
1712 /* close debugfs files before ib unregister */
1713 hfi1_dbg_ibdev_exit(&dd->verbs_dev);
1714
1715 /* remove the /dev hfi1 interface */
1716 hfi1_device_remove(dd);
1717
1718 /* wait for existing user space clients to finish */
1719 wait_for_clients(dd);
1720
1721 /* unregister from IB core */
1722 hfi1_unregister_ib_device(dd);
1723
1724 /* free netdev data */
1725 hfi1_free_rx(dd);
1726
1727 /*
1728 * Disable the IB link, disable interrupts on the device,
1729 * clear dma engines, etc.
1730 */
1731 shutdown_device(dd);
1732 destroy_workqueues(dd);
1733
1734 stop_timers(dd);
1735
1736 /* wait until all of our (qsfp) queue_work() calls complete */
1737 flush_workqueue(ib_wq);
1738
1739 postinit_cleanup(dd);
1740 }
1741
shutdown_one(struct pci_dev * pdev)1742 static void shutdown_one(struct pci_dev *pdev)
1743 {
1744 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
1745
1746 shutdown_device(dd);
1747 }
1748
1749 /**
1750 * hfi1_create_rcvhdrq - create a receive header queue
1751 * @dd: the hfi1_ib device
1752 * @rcd: the context data
1753 *
1754 * This must be contiguous memory (from an i/o perspective), and must be
1755 * DMA'able (which means for some systems, it will go through an IOMMU,
1756 * or be forced into a low address range).
1757 */
hfi1_create_rcvhdrq(struct hfi1_devdata * dd,struct hfi1_ctxtdata * rcd)1758 int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)
1759 {
1760 unsigned amt;
1761
1762 if (!rcd->rcvhdrq) {
1763 gfp_t gfp_flags;
1764
1765 amt = rcvhdrq_size(rcd);
1766
1767 if (rcd->ctxt < dd->first_dyn_alloc_ctxt || rcd->is_vnic)
1768 gfp_flags = GFP_KERNEL;
1769 else
1770 gfp_flags = GFP_USER;
1771 rcd->rcvhdrq = dma_alloc_coherent(&dd->pcidev->dev, amt,
1772 &rcd->rcvhdrq_dma,
1773 gfp_flags | __GFP_COMP);
1774
1775 if (!rcd->rcvhdrq) {
1776 dd_dev_err(dd,
1777 "attempt to allocate %d bytes for ctxt %u rcvhdrq failed\n",
1778 amt, rcd->ctxt);
1779 goto bail;
1780 }
1781
1782 if (HFI1_CAP_KGET_MASK(rcd->flags, DMA_RTAIL) ||
1783 HFI1_CAP_UGET_MASK(rcd->flags, DMA_RTAIL)) {
1784 rcd->rcvhdrtail_kvaddr = dma_alloc_coherent(&dd->pcidev->dev,
1785 PAGE_SIZE,
1786 &rcd->rcvhdrqtailaddr_dma,
1787 gfp_flags);
1788 if (!rcd->rcvhdrtail_kvaddr)
1789 goto bail_free;
1790 }
1791 }
1792
1793 set_hdrq_regs(rcd->dd, rcd->ctxt, rcd->rcvhdrqentsize,
1794 rcd->rcvhdrq_cnt);
1795
1796 return 0;
1797
1798 bail_free:
1799 dd_dev_err(dd,
1800 "attempt to allocate 1 page for ctxt %u rcvhdrqtailaddr failed\n",
1801 rcd->ctxt);
1802 dma_free_coherent(&dd->pcidev->dev, amt, rcd->rcvhdrq,
1803 rcd->rcvhdrq_dma);
1804 rcd->rcvhdrq = NULL;
1805 bail:
1806 return -ENOMEM;
1807 }
1808
1809 /**
1810 * hfi1_setup_eagerbufs - llocate eager buffers, both kernel and user
1811 * contexts.
1812 * @rcd: the context we are setting up.
1813 *
1814 * Allocate the eager TID buffers and program them into hip.
1815 * They are no longer completely contiguous, we do multiple allocation
1816 * calls. Otherwise we get the OOM code involved, by asking for too
1817 * much per call, with disastrous results on some kernels.
1818 */
hfi1_setup_eagerbufs(struct hfi1_ctxtdata * rcd)1819 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd)
1820 {
1821 struct hfi1_devdata *dd = rcd->dd;
1822 u32 max_entries, egrtop, alloced_bytes = 0;
1823 gfp_t gfp_flags;
1824 u16 order, idx = 0;
1825 int ret = 0;
1826 u16 round_mtu = roundup_pow_of_two(hfi1_max_mtu);
1827
1828 /*
1829 * GFP_USER, but without GFP_FS, so buffer cache can be
1830 * coalesced (we hope); otherwise, even at order 4,
1831 * heavy filesystem activity makes these fail, and we can
1832 * use compound pages.
1833 */
1834 gfp_flags = __GFP_RECLAIM | __GFP_IO | __GFP_COMP;
1835
1836 /*
1837 * The minimum size of the eager buffers is a groups of MTU-sized
1838 * buffers.
1839 * The global eager_buffer_size parameter is checked against the
1840 * theoretical lower limit of the value. Here, we check against the
1841 * MTU.
1842 */
1843 if (rcd->egrbufs.size < (round_mtu * dd->rcv_entries.group_size))
1844 rcd->egrbufs.size = round_mtu * dd->rcv_entries.group_size;
1845 /*
1846 * If using one-pkt-per-egr-buffer, lower the eager buffer
1847 * size to the max MTU (page-aligned).
1848 */
1849 if (!HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR))
1850 rcd->egrbufs.rcvtid_size = round_mtu;
1851
1852 /*
1853 * Eager buffers sizes of 1MB or less require smaller TID sizes
1854 * to satisfy the "multiple of 8 RcvArray entries" requirement.
1855 */
1856 if (rcd->egrbufs.size <= (1 << 20))
1857 rcd->egrbufs.rcvtid_size = max((unsigned long)round_mtu,
1858 rounddown_pow_of_two(rcd->egrbufs.size / 8));
1859
1860 while (alloced_bytes < rcd->egrbufs.size &&
1861 rcd->egrbufs.alloced < rcd->egrbufs.count) {
1862 rcd->egrbufs.buffers[idx].addr =
1863 dma_alloc_coherent(&dd->pcidev->dev,
1864 rcd->egrbufs.rcvtid_size,
1865 &rcd->egrbufs.buffers[idx].dma,
1866 gfp_flags);
1867 if (rcd->egrbufs.buffers[idx].addr) {
1868 rcd->egrbufs.buffers[idx].len =
1869 rcd->egrbufs.rcvtid_size;
1870 rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].addr =
1871 rcd->egrbufs.buffers[idx].addr;
1872 rcd->egrbufs.rcvtids[rcd->egrbufs.alloced].dma =
1873 rcd->egrbufs.buffers[idx].dma;
1874 rcd->egrbufs.alloced++;
1875 alloced_bytes += rcd->egrbufs.rcvtid_size;
1876 idx++;
1877 } else {
1878 u32 new_size, i, j;
1879 u64 offset = 0;
1880
1881 /*
1882 * Fail the eager buffer allocation if:
1883 * - we are already using the lowest acceptable size
1884 * - we are using one-pkt-per-egr-buffer (this implies
1885 * that we are accepting only one size)
1886 */
1887 if (rcd->egrbufs.rcvtid_size == round_mtu ||
1888 !HFI1_CAP_KGET_MASK(rcd->flags, MULTI_PKT_EGR)) {
1889 dd_dev_err(dd, "ctxt%u: Failed to allocate eager buffers\n",
1890 rcd->ctxt);
1891 ret = -ENOMEM;
1892 goto bail_rcvegrbuf_phys;
1893 }
1894
1895 new_size = rcd->egrbufs.rcvtid_size / 2;
1896
1897 /*
1898 * If the first attempt to allocate memory failed, don't
1899 * fail everything but continue with the next lower
1900 * size.
1901 */
1902 if (idx == 0) {
1903 rcd->egrbufs.rcvtid_size = new_size;
1904 continue;
1905 }
1906
1907 /*
1908 * Re-partition already allocated buffers to a smaller
1909 * size.
1910 */
1911 rcd->egrbufs.alloced = 0;
1912 for (i = 0, j = 0, offset = 0; j < idx; i++) {
1913 if (i >= rcd->egrbufs.count)
1914 break;
1915 rcd->egrbufs.rcvtids[i].dma =
1916 rcd->egrbufs.buffers[j].dma + offset;
1917 rcd->egrbufs.rcvtids[i].addr =
1918 rcd->egrbufs.buffers[j].addr + offset;
1919 rcd->egrbufs.alloced++;
1920 if ((rcd->egrbufs.buffers[j].dma + offset +
1921 new_size) ==
1922 (rcd->egrbufs.buffers[j].dma +
1923 rcd->egrbufs.buffers[j].len)) {
1924 j++;
1925 offset = 0;
1926 } else {
1927 offset += new_size;
1928 }
1929 }
1930 rcd->egrbufs.rcvtid_size = new_size;
1931 }
1932 }
1933 rcd->egrbufs.numbufs = idx;
1934 rcd->egrbufs.size = alloced_bytes;
1935
1936 hfi1_cdbg(PROC,
1937 "ctxt%u: Alloced %u rcv tid entries @ %uKB, total %uKB\n",
1938 rcd->ctxt, rcd->egrbufs.alloced,
1939 rcd->egrbufs.rcvtid_size / 1024, rcd->egrbufs.size / 1024);
1940
1941 /*
1942 * Set the contexts rcv array head update threshold to the closest
1943 * power of 2 (so we can use a mask instead of modulo) below half
1944 * the allocated entries.
1945 */
1946 rcd->egrbufs.threshold =
1947 rounddown_pow_of_two(rcd->egrbufs.alloced / 2);
1948 /*
1949 * Compute the expected RcvArray entry base. This is done after
1950 * allocating the eager buffers in order to maximize the
1951 * expected RcvArray entries for the context.
1952 */
1953 max_entries = rcd->rcv_array_groups * dd->rcv_entries.group_size;
1954 egrtop = roundup(rcd->egrbufs.alloced, dd->rcv_entries.group_size);
1955 rcd->expected_count = max_entries - egrtop;
1956 if (rcd->expected_count > MAX_TID_PAIR_ENTRIES * 2)
1957 rcd->expected_count = MAX_TID_PAIR_ENTRIES * 2;
1958
1959 rcd->expected_base = rcd->eager_base + egrtop;
1960 hfi1_cdbg(PROC, "ctxt%u: eager:%u, exp:%u, egrbase:%u, expbase:%u\n",
1961 rcd->ctxt, rcd->egrbufs.alloced, rcd->expected_count,
1962 rcd->eager_base, rcd->expected_base);
1963
1964 if (!hfi1_rcvbuf_validate(rcd->egrbufs.rcvtid_size, PT_EAGER, &order)) {
1965 hfi1_cdbg(PROC,
1966 "ctxt%u: current Eager buffer size is invalid %u\n",
1967 rcd->ctxt, rcd->egrbufs.rcvtid_size);
1968 ret = -EINVAL;
1969 goto bail_rcvegrbuf_phys;
1970 }
1971
1972 for (idx = 0; idx < rcd->egrbufs.alloced; idx++) {
1973 hfi1_put_tid(dd, rcd->eager_base + idx, PT_EAGER,
1974 rcd->egrbufs.rcvtids[idx].dma, order);
1975 cond_resched();
1976 }
1977
1978 return 0;
1979
1980 bail_rcvegrbuf_phys:
1981 for (idx = 0; idx < rcd->egrbufs.alloced &&
1982 rcd->egrbufs.buffers[idx].addr;
1983 idx++) {
1984 dma_free_coherent(&dd->pcidev->dev,
1985 rcd->egrbufs.buffers[idx].len,
1986 rcd->egrbufs.buffers[idx].addr,
1987 rcd->egrbufs.buffers[idx].dma);
1988 rcd->egrbufs.buffers[idx].addr = NULL;
1989 rcd->egrbufs.buffers[idx].dma = 0;
1990 rcd->egrbufs.buffers[idx].len = 0;
1991 }
1992
1993 return ret;
1994 }
1995