1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Contains CPU feature definitions
4 *
5 * Copyright (C) 2015 ARM Ltd.
6 *
7 * A note for the weary kernel hacker: the code here is confusing and hard to
8 * follow! That's partly because it's solving a nasty problem, but also because
9 * there's a little bit of over-abstraction that tends to obscure what's going
10 * on behind a maze of helper functions and macros.
11 *
12 * The basic problem is that hardware folks have started gluing together CPUs
13 * with distinct architectural features; in some cases even creating SoCs where
14 * user-visible instructions are available only on a subset of the available
15 * cores. We try to address this by snapshotting the feature registers of the
16 * boot CPU and comparing these with the feature registers of each secondary
17 * CPU when bringing them up. If there is a mismatch, then we update the
18 * snapshot state to indicate the lowest-common denominator of the feature,
19 * known as the "safe" value. This snapshot state can be queried to view the
20 * "sanitised" value of a feature register.
21 *
22 * The sanitised register values are used to decide which capabilities we
23 * have in the system. These may be in the form of traditional "hwcaps"
24 * advertised to userspace or internal "cpucaps" which are used to configure
25 * things like alternative patching and static keys. While a feature mismatch
26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch
27 * may prevent a CPU from being onlined at all.
28 *
29 * Some implementation details worth remembering:
30 *
31 * - Mismatched features are *always* sanitised to a "safe" value, which
32 * usually indicates that the feature is not supported.
33 *
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
35 * warning when onlining an offending CPU and the kernel will be tainted
36 * with TAINT_CPU_OUT_OF_SPEC.
37 *
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
39 * userspace. FTR_VISIBLE features in registers that are only visible
40 * to EL0 by trapping *must* have a corresponding HWCAP so that late
41 * onlining of CPUs cannot lead to features disappearing at runtime.
42 *
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
45 *
46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
47 * scheme for fields in ID registers") to understand when feature fields
48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly).
49 *
50 * - KVM exposes its own view of the feature registers to guest operating
51 * systems regardless of FTR_VISIBLE. This is typically driven from the
52 * sanitised register values to allow virtual CPUs to be migrated between
53 * arbitrary physical CPUs, but some features not present on the host are
54 * also advertised and emulated. Look at sys_reg_descs[] for the gory
55 * details.
56 *
57 * - If the arm64_ftr_bits[] for a register has a missing field, then this
58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg().
59 * This is stronger than FTR_HIDDEN and can be used to hide features from
60 * KVM guests.
61 */
62
63 #define pr_fmt(fmt) "CPU features: " fmt
64
65 #include <linux/bsearch.h>
66 #include <linux/cpumask.h>
67 #include <linux/crash_dump.h>
68 #include <linux/sort.h>
69 #include <linux/stop_machine.h>
70 #include <linux/sysfs.h>
71 #include <linux/types.h>
72 #include <linux/minmax.h>
73 #include <linux/mm.h>
74 #include <linux/cpu.h>
75 #include <linux/kasan.h>
76 #include <linux/percpu.h>
77
78 #include <asm/cpu.h>
79 #include <asm/cpufeature.h>
80 #include <asm/cpu_ops.h>
81 #include <asm/fpsimd.h>
82 #include <asm/insn.h>
83 #include <asm/kvm_host.h>
84 #include <asm/mmu_context.h>
85 #include <asm/mte.h>
86 #include <asm/processor.h>
87 #include <asm/smp.h>
88 #include <asm/sysreg.h>
89 #include <asm/traps.h>
90 #include <asm/vectors.h>
91 #include <asm/virt.h>
92
93 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
94 static unsigned long elf_hwcap __read_mostly;
95
96 #ifdef CONFIG_COMPAT
97 #define COMPAT_ELF_HWCAP_DEFAULT \
98 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
99 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
100 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
101 COMPAT_HWCAP_LPAE)
102 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
103 unsigned int compat_elf_hwcap2 __read_mostly;
104 #endif
105
106 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
107 EXPORT_SYMBOL(cpu_hwcaps);
108 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
109
110 /* Need also bit for ARM64_CB_PATCH */
111 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
112
113 bool arm64_use_ng_mappings = false;
114 EXPORT_SYMBOL(arm64_use_ng_mappings);
115
116 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors;
117
118 /*
119 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs
120 * support it?
121 */
122 static bool __read_mostly allow_mismatched_32bit_el0;
123
124 /*
125 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have
126 * seen at least one CPU capable of 32-bit EL0.
127 */
128 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
129
130 /*
131 * Mask of CPUs supporting 32-bit EL0.
132 * Only valid if arm64_mismatched_32bit_el0 is enabled.
133 */
134 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly;
135
136 /*
137 * Flag to indicate if we have computed the system wide
138 * capabilities based on the boot time active CPUs. This
139 * will be used to determine if a new booting CPU should
140 * go through the verification process to make sure that it
141 * supports the system capabilities, without using a hotplug
142 * notifier. This is also used to decide if we could use
143 * the fast path for checking constant CPU caps.
144 */
145 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
146 EXPORT_SYMBOL(arm64_const_caps_ready);
finalize_system_capabilities(void)147 static inline void finalize_system_capabilities(void)
148 {
149 static_branch_enable(&arm64_const_caps_ready);
150 }
151
dump_cpu_features(void)152 void dump_cpu_features(void)
153 {
154 /* file-wide pr_fmt adds "CPU features: " prefix */
155 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
156 }
157
158 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
159 EXPORT_SYMBOL(cpu_hwcap_keys);
160
161 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
162 { \
163 .sign = SIGNED, \
164 .visible = VISIBLE, \
165 .strict = STRICT, \
166 .type = TYPE, \
167 .shift = SHIFT, \
168 .width = WIDTH, \
169 .safe_val = SAFE_VAL, \
170 }
171
172 /* Define a feature with unsigned values */
173 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
174 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
175
176 /* Define a feature with a signed value */
177 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
178 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
179
180 #define ARM64_FTR_END \
181 { \
182 .width = 0, \
183 }
184
185 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
186
187 static bool __system_matches_cap(unsigned int n);
188
189 /*
190 * NOTE: Any changes to the visibility of features should be kept in
191 * sync with the documentation of the CPU feature register ABI.
192 */
193 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
195 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0),
196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
199 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
202 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
203 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
204 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
205 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
206 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
207 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
208 ARM64_FTR_END,
209 };
210
211 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
212 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0),
213 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0),
214 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0),
215 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0),
216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
218 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
219 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
220 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
221 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
222 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
224 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
225 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
226 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0),
227 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
228 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0),
229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
230 ARM64_FTR_END,
231 };
232
233 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0),
235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0),
236 ARM64_FTR_END,
237 };
238
239 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
240 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
242 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
243 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
244 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0),
245 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0),
246 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
247 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
248 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
250 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
251 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
252 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
253 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
254 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
255 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_ELx_64BIT_ONLY),
256 ARM64_FTR_END,
257 };
258
259 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
260 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0),
261 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0),
262 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),
263 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI),
264 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
265 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI),
266 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0),
267 ARM64_FTR_END,
268 };
269
270 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
271 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
272 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0),
273 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
274 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0),
275 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
276 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0),
277 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
278 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
279 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
280 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
281 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
282 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0),
283 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
284 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
285 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
286 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
287 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
288 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
289 ARM64_FTR_END,
290 };
291
292 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
293 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0),
295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),
296 /*
297 * Page size not being supported at Stage-2 is not fatal. You
298 * just give up KVM if PAGE_SIZE isn't supported there. Go fix
299 * your favourite nesting hypervisor.
300 *
301 * There is a small corner case where the hypervisor explicitly
302 * advertises a given granule size at Stage-2 (value 2) on some
303 * vCPUs, and uses the fallback to Stage-1 (value 0) for other
304 * vCPUs. Although this is not forbidden by the architecture, it
305 * indicates that the hypervisor is being silly (or buggy).
306 *
307 * We make no effort to cope with this and pretend that if these
308 * fields are inconsistent across vCPUs, then it isn't worth
309 * trying to bring KVM up.
310 */
311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1),
312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1),
313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1),
314 /*
315 * We already refuse to boot CPUs that don't support our configured
316 * page size, so we can only detect mismatches for a page size other
317 * than the one we're currently using. Unfortunately, SoCs like this
318 * exist in the wild so, even though we don't like it, we'll have to go
319 * along with it and treat them as non-strict.
320 */
321 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
322 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
323 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
324
325 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
326 /* Linux shouldn't care about secure memory */
327 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
330 /*
331 * Differing PARange is fine as long as all peripherals and memory are mapped
332 * within the minimum PARange of all CPUs
333 */
334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
335 ARM64_FTR_END,
336 };
337
338 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
339 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_AFP_SHIFT, 4, 0),
340 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
341 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
342 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
343 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0),
344 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
345 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
346 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
347 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
348 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
350 ARM64_FTR_END,
351 };
352
353 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
354 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0),
356 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0),
357 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0),
358 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
359 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0),
360 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
361 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0),
362 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0),
363 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0),
364 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
365 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
366 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
367 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
368 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
369 ARM64_FTR_END,
370 };
371
372 static const struct arm64_ftr_bits ftr_ctr[] = {
373 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
374 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
375 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
376 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
377 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
378 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
379 /*
380 * Linux can handle differing I-cache policies. Userspace JITs will
381 * make use of *minLine.
382 * If we have differing I-cache policies, report it as the weakest - VIPT.
383 */
384 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT), /* L1Ip */
385 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
386 ARM64_FTR_END,
387 };
388
389 static struct arm64_ftr_override __ro_after_init no_override = { };
390
391 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
392 .name = "SYS_CTR_EL0",
393 .ftr_bits = ftr_ctr,
394 .override = &no_override,
395 };
396
397 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
398 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf),
399 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0),
400 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0),
401 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0),
402 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0),
403 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf),
404 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0),
405 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0),
406 ARM64_FTR_END,
407 };
408
409 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
410 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0),
411 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
412 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
413 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
414 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
415 /*
416 * We can instantiate multiple PMU instances with different levels
417 * of support.
418 */
419 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
420 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
421 ARM64_FTR_END,
422 };
423
424 static const struct arm64_ftr_bits ftr_mvfr2[] = {
425 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0),
426 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0),
427 ARM64_FTR_END,
428 };
429
430 static const struct arm64_ftr_bits ftr_dczid[] = {
431 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1),
432 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0),
433 ARM64_FTR_END,
434 };
435
436 static const struct arm64_ftr_bits ftr_gmid[] = {
437 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0),
438 ARM64_FTR_END,
439 };
440
441 static const struct arm64_ftr_bits ftr_id_isar0[] = {
442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0),
445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0),
446 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0),
447 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0),
448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0),
449 ARM64_FTR_END,
450 };
451
452 static const struct arm64_ftr_bits ftr_id_isar5[] = {
453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
458 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
459 ARM64_FTR_END,
460 };
461
462 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0),
464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0),
465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0),
466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0),
467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0),
468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0),
469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0),
470
471 /*
472 * SpecSEI = 1 indicates that the PE might generate an SError on an
473 * external abort on speculative read. It is safe to assume that an
474 * SError might be generated than it will not be. Hence it has been
475 * classified as FTR_HIGHER_SAFE.
476 */
477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0),
478 ARM64_FTR_END,
479 };
480
481 static const struct arm64_ftr_bits ftr_id_isar4[] = {
482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),
483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),
484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),
485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),
486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),
487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),
488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),
489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),
490 ARM64_FTR_END,
491 };
492
493 static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0),
495 ARM64_FTR_END,
496 };
497
498 static const struct arm64_ftr_bits ftr_id_isar6[] = {
499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
506 ARM64_FTR_END,
507 };
508
509 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0),
513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0),
514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0),
515 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0),
516 ARM64_FTR_END,
517 };
518
519 static const struct arm64_ftr_bits ftr_id_pfr1[] = {
520 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),
521 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),
522 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),
523 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),
524 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),
525 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),
526 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),
527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),
528 ARM64_FTR_END,
529 };
530
531 static const struct arm64_ftr_bits ftr_id_pfr2[] = {
532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
533 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),
534 ARM64_FTR_END,
535 };
536
537 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
538 /* [31:28] TraceFilt */
539 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_PERFMON_SHIFT, 4, 0),
540 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0),
541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0),
542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0),
543 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0),
544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0),
545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0),
546 ARM64_FTR_END,
547 };
548
549 static const struct arm64_ftr_bits ftr_id_dfr1[] = {
550 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0),
551 ARM64_FTR_END,
552 };
553
554 static const struct arm64_ftr_bits ftr_zcr[] = {
555 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
556 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
557 ARM64_FTR_END,
558 };
559
560 /*
561 * Common ftr bits for a 32bit register with all hidden, strict
562 * attributes, with 4bit feature fields and a default safe value of
563 * 0. Covers the following 32bit registers:
564 * id_isar[1-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
565 */
566 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
567 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
569 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
570 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
571 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
572 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
573 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
574 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
575 ARM64_FTR_END,
576 };
577
578 /* Table for a single 32bit feature value */
579 static const struct arm64_ftr_bits ftr_single32[] = {
580 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
581 ARM64_FTR_END,
582 };
583
584 static const struct arm64_ftr_bits ftr_raz[] = {
585 ARM64_FTR_END,
586 };
587
588 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \
589 .sys_id = id, \
590 .reg = &(struct arm64_ftr_reg){ \
591 .name = id_str, \
592 .override = (ovr), \
593 .ftr_bits = &((table)[0]), \
594 }}
595
596 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \
597 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr)
598
599 #define ARM64_FTR_REG(id, table) \
600 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override)
601
602 struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override;
603 struct arm64_ftr_override __ro_after_init id_aa64pfr1_override;
604 struct arm64_ftr_override __ro_after_init id_aa64isar1_override;
605
606 static const struct __ftr_reg_entry {
607 u32 sys_id;
608 struct arm64_ftr_reg *reg;
609 } arm64_ftr_regs[] = {
610
611 /* Op1 = 0, CRn = 0, CRm = 1 */
612 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
613 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
614 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
615 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
616 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
617 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
618 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
619
620 /* Op1 = 0, CRn = 0, CRm = 2 */
621 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
622 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
623 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
624 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
625 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
626 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
627 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
628 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
629
630 /* Op1 = 0, CRn = 0, CRm = 3 */
631 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
632 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
633 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
634 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
635 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
636 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
637
638 /* Op1 = 0, CRn = 0, CRm = 4 */
639 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
640 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1,
641 &id_aa64pfr1_override),
642 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
643
644 /* Op1 = 0, CRn = 0, CRm = 5 */
645 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
646 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
647
648 /* Op1 = 0, CRn = 0, CRm = 6 */
649 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
650 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1,
651 &id_aa64isar1_override),
652 ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2),
653
654 /* Op1 = 0, CRn = 0, CRm = 7 */
655 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
656 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1,
657 &id_aa64mmfr1_override),
658 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
659
660 /* Op1 = 0, CRn = 1, CRm = 2 */
661 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
662
663 /* Op1 = 1, CRn = 0, CRm = 0 */
664 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
665
666 /* Op1 = 3, CRn = 0, CRm = 0 */
667 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
668 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
669
670 /* Op1 = 3, CRn = 14, CRm = 0 */
671 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
672 };
673
search_cmp_ftr_reg(const void * id,const void * regp)674 static int search_cmp_ftr_reg(const void *id, const void *regp)
675 {
676 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
677 }
678
679 /*
680 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using
681 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the
682 * ascending order of sys_id, we use binary search to find a matching
683 * entry.
684 *
685 * returns - Upon success, matching ftr_reg entry for id.
686 * - NULL on failure. It is upto the caller to decide
687 * the impact of a failure.
688 */
get_arm64_ftr_reg_nowarn(u32 sys_id)689 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
690 {
691 const struct __ftr_reg_entry *ret;
692
693 ret = bsearch((const void *)(unsigned long)sys_id,
694 arm64_ftr_regs,
695 ARRAY_SIZE(arm64_ftr_regs),
696 sizeof(arm64_ftr_regs[0]),
697 search_cmp_ftr_reg);
698 if (ret)
699 return ret->reg;
700 return NULL;
701 }
702
703 /*
704 * get_arm64_ftr_reg - Looks up a feature register entry using
705 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn().
706 *
707 * returns - Upon success, matching ftr_reg entry for id.
708 * - NULL on failure but with an WARN_ON().
709 */
get_arm64_ftr_reg(u32 sys_id)710 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
711 {
712 struct arm64_ftr_reg *reg;
713
714 reg = get_arm64_ftr_reg_nowarn(sys_id);
715
716 /*
717 * Requesting a non-existent register search is an error. Warn
718 * and let the caller handle it.
719 */
720 WARN_ON(!reg);
721 return reg;
722 }
723
arm64_ftr_set_value(const struct arm64_ftr_bits * ftrp,s64 reg,s64 ftr_val)724 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
725 s64 ftr_val)
726 {
727 u64 mask = arm64_ftr_mask(ftrp);
728
729 reg &= ~mask;
730 reg |= (ftr_val << ftrp->shift) & mask;
731 return reg;
732 }
733
arm64_ftr_safe_value(const struct arm64_ftr_bits * ftrp,s64 new,s64 cur)734 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
735 s64 cur)
736 {
737 s64 ret = 0;
738
739 switch (ftrp->type) {
740 case FTR_EXACT:
741 ret = ftrp->safe_val;
742 break;
743 case FTR_LOWER_SAFE:
744 ret = min(new, cur);
745 break;
746 case FTR_HIGHER_OR_ZERO_SAFE:
747 if (!cur || !new)
748 break;
749 fallthrough;
750 case FTR_HIGHER_SAFE:
751 ret = max(new, cur);
752 break;
753 default:
754 BUG();
755 }
756
757 return ret;
758 }
759
sort_ftr_regs(void)760 static void __init sort_ftr_regs(void)
761 {
762 unsigned int i;
763
764 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) {
765 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg;
766 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits;
767 unsigned int j = 0;
768
769 /*
770 * Features here must be sorted in descending order with respect
771 * to their shift values and should not overlap with each other.
772 */
773 for (; ftr_bits->width != 0; ftr_bits++, j++) {
774 unsigned int width = ftr_reg->ftr_bits[j].width;
775 unsigned int shift = ftr_reg->ftr_bits[j].shift;
776 unsigned int prev_shift;
777
778 WARN((shift + width) > 64,
779 "%s has invalid feature at shift %d\n",
780 ftr_reg->name, shift);
781
782 /*
783 * Skip the first feature. There is nothing to
784 * compare against for now.
785 */
786 if (j == 0)
787 continue;
788
789 prev_shift = ftr_reg->ftr_bits[j - 1].shift;
790 WARN((shift + width) > prev_shift,
791 "%s has feature overlap at shift %d\n",
792 ftr_reg->name, shift);
793 }
794
795 /*
796 * Skip the first register. There is nothing to
797 * compare against for now.
798 */
799 if (i == 0)
800 continue;
801 /*
802 * Registers here must be sorted in ascending order with respect
803 * to sys_id for subsequent binary search in get_arm64_ftr_reg()
804 * to work correctly.
805 */
806 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
807 }
808 }
809
810 /*
811 * Initialise the CPU feature register from Boot CPU values.
812 * Also initiliases the strict_mask for the register.
813 * Any bits that are not covered by an arm64_ftr_bits entry are considered
814 * RES0 for the system-wide value, and must strictly match.
815 */
init_cpu_ftr_reg(u32 sys_reg,u64 new)816 static void init_cpu_ftr_reg(u32 sys_reg, u64 new)
817 {
818 u64 val = 0;
819 u64 strict_mask = ~0x0ULL;
820 u64 user_mask = 0;
821 u64 valid_mask = 0;
822
823 const struct arm64_ftr_bits *ftrp;
824 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
825
826 if (!reg)
827 return;
828
829 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
830 u64 ftr_mask = arm64_ftr_mask(ftrp);
831 s64 ftr_new = arm64_ftr_value(ftrp, new);
832 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val);
833
834 if ((ftr_mask & reg->override->mask) == ftr_mask) {
835 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new);
836 char *str = NULL;
837
838 if (ftr_ovr != tmp) {
839 /* Unsafe, remove the override */
840 reg->override->mask &= ~ftr_mask;
841 reg->override->val &= ~ftr_mask;
842 tmp = ftr_ovr;
843 str = "ignoring override";
844 } else if (ftr_new != tmp) {
845 /* Override was valid */
846 ftr_new = tmp;
847 str = "forced";
848 } else if (ftr_ovr == tmp) {
849 /* Override was the safe value */
850 str = "already set";
851 }
852
853 if (str)
854 pr_warn("%s[%d:%d]: %s to %llx\n",
855 reg->name,
856 ftrp->shift + ftrp->width - 1,
857 ftrp->shift, str, tmp);
858 } else if ((ftr_mask & reg->override->val) == ftr_mask) {
859 reg->override->val &= ~ftr_mask;
860 pr_warn("%s[%d:%d]: impossible override, ignored\n",
861 reg->name,
862 ftrp->shift + ftrp->width - 1,
863 ftrp->shift);
864 }
865
866 val = arm64_ftr_set_value(ftrp, val, ftr_new);
867
868 valid_mask |= ftr_mask;
869 if (!ftrp->strict)
870 strict_mask &= ~ftr_mask;
871 if (ftrp->visible)
872 user_mask |= ftr_mask;
873 else
874 reg->user_val = arm64_ftr_set_value(ftrp,
875 reg->user_val,
876 ftrp->safe_val);
877 }
878
879 val &= valid_mask;
880
881 reg->sys_val = val;
882 reg->strict_mask = strict_mask;
883 reg->user_mask = user_mask;
884 }
885
886 extern const struct arm64_cpu_capabilities arm64_errata[];
887 static const struct arm64_cpu_capabilities arm64_features[];
888
889 static void __init
init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities * caps)890 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
891 {
892 for (; caps->matches; caps++) {
893 if (WARN(caps->capability >= ARM64_NCAPS,
894 "Invalid capability %d\n", caps->capability))
895 continue;
896 if (WARN(cpu_hwcaps_ptrs[caps->capability],
897 "Duplicate entry for capability %d\n",
898 caps->capability))
899 continue;
900 cpu_hwcaps_ptrs[caps->capability] = caps;
901 }
902 }
903
init_cpu_hwcaps_indirect_list(void)904 static void __init init_cpu_hwcaps_indirect_list(void)
905 {
906 init_cpu_hwcaps_indirect_list_from_array(arm64_features);
907 init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
908 }
909
910 static void __init setup_boot_cpu_capabilities(void);
911
init_32bit_cpu_features(struct cpuinfo_32bit * info)912 static void init_32bit_cpu_features(struct cpuinfo_32bit *info)
913 {
914 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
915 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);
916 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
917 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
918 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
919 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
920 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
921 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
922 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
923 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
924 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
925 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
926 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
927 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4);
928 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
929 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
930 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
931 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
932 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
933 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
934 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
935 }
936
init_cpu_features(struct cpuinfo_arm64 * info)937 void __init init_cpu_features(struct cpuinfo_arm64 *info)
938 {
939 /* Before we start using the tables, make sure it is sorted */
940 sort_ftr_regs();
941
942 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
943 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
944 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
945 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
946 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
947 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
948 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
949 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
950 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
951 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
952 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
953 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
954 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
955 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
956
957 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
958 init_32bit_cpu_features(&info->aarch32);
959
960 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
961 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
962 sve_init_vq_map();
963 }
964
965 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
966 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);
967
968 /*
969 * Initialize the indirect array of CPU hwcaps capabilities pointers
970 * before we handle the boot CPU below.
971 */
972 init_cpu_hwcaps_indirect_list();
973
974 /*
975 * Detect and enable early CPU capabilities based on the boot CPU,
976 * after we have initialised the CPU feature infrastructure.
977 */
978 setup_boot_cpu_capabilities();
979 }
980
update_cpu_ftr_reg(struct arm64_ftr_reg * reg,u64 new)981 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
982 {
983 const struct arm64_ftr_bits *ftrp;
984
985 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
986 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
987 s64 ftr_new = arm64_ftr_value(ftrp, new);
988
989 if (ftr_cur == ftr_new)
990 continue;
991 /* Find a safe value */
992 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
993 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
994 }
995
996 }
997
check_update_ftr_reg(u32 sys_id,int cpu,u64 val,u64 boot)998 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
999 {
1000 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1001
1002 if (!regp)
1003 return 0;
1004
1005 update_cpu_ftr_reg(regp, val);
1006 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
1007 return 0;
1008 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
1009 regp->name, boot, cpu, val);
1010 return 1;
1011 }
1012
relax_cpu_ftr_reg(u32 sys_id,int field)1013 static void relax_cpu_ftr_reg(u32 sys_id, int field)
1014 {
1015 const struct arm64_ftr_bits *ftrp;
1016 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
1017
1018 if (!regp)
1019 return;
1020
1021 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
1022 if (ftrp->shift == field) {
1023 regp->strict_mask &= ~arm64_ftr_mask(ftrp);
1024 break;
1025 }
1026 }
1027
1028 /* Bogus field? */
1029 WARN_ON(!ftrp->width);
1030 }
1031
lazy_init_32bit_cpu_features(struct cpuinfo_arm64 * info,struct cpuinfo_arm64 * boot)1032 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info,
1033 struct cpuinfo_arm64 *boot)
1034 {
1035 static bool boot_cpu_32bit_regs_overridden = false;
1036
1037 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden)
1038 return;
1039
1040 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0))
1041 return;
1042
1043 boot->aarch32 = info->aarch32;
1044 init_32bit_cpu_features(&boot->aarch32);
1045 boot_cpu_32bit_regs_overridden = true;
1046 }
1047
update_32bit_cpu_features(int cpu,struct cpuinfo_32bit * info,struct cpuinfo_32bit * boot)1048 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info,
1049 struct cpuinfo_32bit *boot)
1050 {
1051 int taint = 0;
1052 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1053
1054 /*
1055 * If we don't have AArch32 at EL1, then relax the strictness of
1056 * EL1-dependent register fields to avoid spurious sanity check fails.
1057 */
1058 if (!id_aa64pfr0_32bit_el1(pfr0)) {
1059 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT);
1060 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
1061 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
1062 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
1063 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT);
1064 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT);
1065 }
1066
1067 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
1068 info->reg_id_dfr0, boot->reg_id_dfr0);
1069 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu,
1070 info->reg_id_dfr1, boot->reg_id_dfr1);
1071 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
1072 info->reg_id_isar0, boot->reg_id_isar0);
1073 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
1074 info->reg_id_isar1, boot->reg_id_isar1);
1075 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
1076 info->reg_id_isar2, boot->reg_id_isar2);
1077 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
1078 info->reg_id_isar3, boot->reg_id_isar3);
1079 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
1080 info->reg_id_isar4, boot->reg_id_isar4);
1081 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
1082 info->reg_id_isar5, boot->reg_id_isar5);
1083 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
1084 info->reg_id_isar6, boot->reg_id_isar6);
1085
1086 /*
1087 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
1088 * ACTLR formats could differ across CPUs and therefore would have to
1089 * be trapped for virtualization anyway.
1090 */
1091 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
1092 info->reg_id_mmfr0, boot->reg_id_mmfr0);
1093 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
1094 info->reg_id_mmfr1, boot->reg_id_mmfr1);
1095 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
1096 info->reg_id_mmfr2, boot->reg_id_mmfr2);
1097 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
1098 info->reg_id_mmfr3, boot->reg_id_mmfr3);
1099 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
1100 info->reg_id_mmfr4, boot->reg_id_mmfr4);
1101 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
1102 info->reg_id_mmfr5, boot->reg_id_mmfr5);
1103 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
1104 info->reg_id_pfr0, boot->reg_id_pfr0);
1105 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
1106 info->reg_id_pfr1, boot->reg_id_pfr1);
1107 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
1108 info->reg_id_pfr2, boot->reg_id_pfr2);
1109 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
1110 info->reg_mvfr0, boot->reg_mvfr0);
1111 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
1112 info->reg_mvfr1, boot->reg_mvfr1);
1113 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
1114 info->reg_mvfr2, boot->reg_mvfr2);
1115
1116 return taint;
1117 }
1118
1119 /*
1120 * Update system wide CPU feature registers with the values from a
1121 * non-boot CPU. Also performs SANITY checks to make sure that there
1122 * aren't any insane variations from that of the boot CPU.
1123 */
update_cpu_features(int cpu,struct cpuinfo_arm64 * info,struct cpuinfo_arm64 * boot)1124 void update_cpu_features(int cpu,
1125 struct cpuinfo_arm64 *info,
1126 struct cpuinfo_arm64 *boot)
1127 {
1128 int taint = 0;
1129
1130 /*
1131 * The kernel can handle differing I-cache policies, but otherwise
1132 * caches should look identical. Userspace JITs will make use of
1133 * *minLine.
1134 */
1135 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
1136 info->reg_ctr, boot->reg_ctr);
1137
1138 /*
1139 * Userspace may perform DC ZVA instructions. Mismatched block sizes
1140 * could result in too much or too little memory being zeroed if a
1141 * process is preempted and migrated between CPUs.
1142 */
1143 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
1144 info->reg_dczid, boot->reg_dczid);
1145
1146 /* If different, timekeeping will be broken (especially with KVM) */
1147 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
1148 info->reg_cntfrq, boot->reg_cntfrq);
1149
1150 /*
1151 * The kernel uses self-hosted debug features and expects CPUs to
1152 * support identical debug features. We presently need CTX_CMPs, WRPs,
1153 * and BRPs to be identical.
1154 * ID_AA64DFR1 is currently RES0.
1155 */
1156 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
1157 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
1158 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
1159 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
1160 /*
1161 * Even in big.LITTLE, processors should be identical instruction-set
1162 * wise.
1163 */
1164 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
1165 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
1166 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
1167 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
1168 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
1169 info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
1170
1171 /*
1172 * Differing PARange support is fine as long as all peripherals and
1173 * memory are mapped within the minimum PARange of all CPUs.
1174 * Linux should not care about secure memory.
1175 */
1176 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
1177 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
1178 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
1179 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
1180 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
1181 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
1182
1183 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
1184 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
1185 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
1186 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
1187
1188 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
1189 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
1190
1191 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
1192 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
1193 info->reg_zcr, boot->reg_zcr);
1194
1195 /* Probe vector lengths, unless we already gave up on SVE */
1196 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
1197 !system_capabilities_finalized())
1198 sve_update_vq_map();
1199 }
1200
1201 /*
1202 * The kernel uses the LDGM/STGM instructions and the number of tags
1203 * they read/write depends on the GMID_EL1.BS field. Check that the
1204 * value is the same on all CPUs.
1205 */
1206 if (IS_ENABLED(CONFIG_ARM64_MTE) &&
1207 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) {
1208 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,
1209 info->reg_gmid, boot->reg_gmid);
1210 }
1211
1212 /*
1213 * If we don't have AArch32 at all then skip the checks entirely
1214 * as the register values may be UNKNOWN and we're not going to be
1215 * using them for anything.
1216 *
1217 * This relies on a sanitised view of the AArch64 ID registers
1218 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last.
1219 */
1220 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
1221 lazy_init_32bit_cpu_features(info, boot);
1222 taint |= update_32bit_cpu_features(cpu, &info->aarch32,
1223 &boot->aarch32);
1224 }
1225
1226 /*
1227 * Mismatched CPU features are a recipe for disaster. Don't even
1228 * pretend to support them.
1229 */
1230 if (taint) {
1231 pr_warn_once("Unsupported CPU feature variation detected.\n");
1232 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1233 }
1234 }
1235
read_sanitised_ftr_reg(u32 id)1236 u64 read_sanitised_ftr_reg(u32 id)
1237 {
1238 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
1239
1240 if (!regp)
1241 return 0;
1242 return regp->sys_val;
1243 }
1244 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
1245
1246 #define read_sysreg_case(r) \
1247 case r: val = read_sysreg_s(r); break;
1248
1249 /*
1250 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
1251 * Read the system register on the current CPU
1252 */
__read_sysreg_by_encoding(u32 sys_id)1253 u64 __read_sysreg_by_encoding(u32 sys_id)
1254 {
1255 struct arm64_ftr_reg *regp;
1256 u64 val;
1257
1258 switch (sys_id) {
1259 read_sysreg_case(SYS_ID_PFR0_EL1);
1260 read_sysreg_case(SYS_ID_PFR1_EL1);
1261 read_sysreg_case(SYS_ID_PFR2_EL1);
1262 read_sysreg_case(SYS_ID_DFR0_EL1);
1263 read_sysreg_case(SYS_ID_DFR1_EL1);
1264 read_sysreg_case(SYS_ID_MMFR0_EL1);
1265 read_sysreg_case(SYS_ID_MMFR1_EL1);
1266 read_sysreg_case(SYS_ID_MMFR2_EL1);
1267 read_sysreg_case(SYS_ID_MMFR3_EL1);
1268 read_sysreg_case(SYS_ID_MMFR4_EL1);
1269 read_sysreg_case(SYS_ID_MMFR5_EL1);
1270 read_sysreg_case(SYS_ID_ISAR0_EL1);
1271 read_sysreg_case(SYS_ID_ISAR1_EL1);
1272 read_sysreg_case(SYS_ID_ISAR2_EL1);
1273 read_sysreg_case(SYS_ID_ISAR3_EL1);
1274 read_sysreg_case(SYS_ID_ISAR4_EL1);
1275 read_sysreg_case(SYS_ID_ISAR5_EL1);
1276 read_sysreg_case(SYS_ID_ISAR6_EL1);
1277 read_sysreg_case(SYS_MVFR0_EL1);
1278 read_sysreg_case(SYS_MVFR1_EL1);
1279 read_sysreg_case(SYS_MVFR2_EL1);
1280
1281 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1282 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
1283 read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
1284 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1285 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1286 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1287 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1288 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1289 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1290 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1291 read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
1292
1293 read_sysreg_case(SYS_CNTFRQ_EL0);
1294 read_sysreg_case(SYS_CTR_EL0);
1295 read_sysreg_case(SYS_DCZID_EL0);
1296
1297 default:
1298 BUG();
1299 return 0;
1300 }
1301
1302 regp = get_arm64_ftr_reg(sys_id);
1303 if (regp) {
1304 val &= ~regp->override->mask;
1305 val |= (regp->override->val & regp->override->mask);
1306 }
1307
1308 return val;
1309 }
1310
1311 #include <linux/irqchip/arm-gic-v3.h>
1312
1313 static bool
feature_matches(u64 reg,const struct arm64_cpu_capabilities * entry)1314 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1315 {
1316 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
1317
1318 return val >= entry->min_field_value;
1319 }
1320
1321 static bool
has_cpuid_feature(const struct arm64_cpu_capabilities * entry,int scope)1322 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1323 {
1324 u64 val;
1325
1326 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1327 if (scope == SCOPE_SYSTEM)
1328 val = read_sanitised_ftr_reg(entry->sys_reg);
1329 else
1330 val = __read_sysreg_by_encoding(entry->sys_reg);
1331
1332 return feature_matches(val, entry);
1333 }
1334
system_32bit_el0_cpumask(void)1335 const struct cpumask *system_32bit_el0_cpumask(void)
1336 {
1337 if (!system_supports_32bit_el0())
1338 return cpu_none_mask;
1339
1340 if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
1341 return cpu_32bit_el0_mask;
1342
1343 return cpu_possible_mask;
1344 }
1345 EXPORT_SYMBOL_GPL(system_32bit_el0_cpumask);
1346
parse_32bit_el0_param(char * str)1347 static int __init parse_32bit_el0_param(char *str)
1348 {
1349 allow_mismatched_32bit_el0 = true;
1350 return 0;
1351 }
1352 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param);
1353
aarch32_el0_show(struct device * dev,struct device_attribute * attr,char * buf)1354 static ssize_t aarch32_el0_show(struct device *dev,
1355 struct device_attribute *attr, char *buf)
1356 {
1357 const struct cpumask *mask = system_32bit_el0_cpumask();
1358
1359 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask));
1360 }
1361 static const DEVICE_ATTR_RO(aarch32_el0);
1362
aarch32_el0_sysfs_init(void)1363 static int __init aarch32_el0_sysfs_init(void)
1364 {
1365 if (!allow_mismatched_32bit_el0)
1366 return 0;
1367
1368 return device_create_file(cpu_subsys.dev_root, &dev_attr_aarch32_el0);
1369 }
1370 device_initcall(aarch32_el0_sysfs_init);
1371
has_32bit_el0(const struct arm64_cpu_capabilities * entry,int scope)1372 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope)
1373 {
1374 if (!has_cpuid_feature(entry, scope))
1375 return allow_mismatched_32bit_el0;
1376
1377 if (scope == SCOPE_SYSTEM)
1378 pr_info("detected: 32-bit EL0 Support\n");
1379
1380 return true;
1381 }
1382
has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities * entry,int scope)1383 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
1384 {
1385 bool has_sre;
1386
1387 if (!has_cpuid_feature(entry, scope))
1388 return false;
1389
1390 has_sre = gic_enable_sre();
1391 if (!has_sre)
1392 pr_warn_once("%s present but disabled by higher exception level\n",
1393 entry->desc);
1394
1395 return has_sre;
1396 }
1397
has_no_fpsimd(const struct arm64_cpu_capabilities * entry,int __unused)1398 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
1399 {
1400 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1401
1402 return cpuid_feature_extract_signed_field(pfr0,
1403 ID_AA64PFR0_FP_SHIFT) < 0;
1404 }
1405
has_cache_idc(const struct arm64_cpu_capabilities * entry,int scope)1406 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
1407 int scope)
1408 {
1409 u64 ctr;
1410
1411 if (scope == SCOPE_SYSTEM)
1412 ctr = arm64_ftr_reg_ctrel0.sys_val;
1413 else
1414 ctr = read_cpuid_effective_cachetype();
1415
1416 return ctr & BIT(CTR_IDC_SHIFT);
1417 }
1418
cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities * __unused)1419 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1420 {
1421 /*
1422 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
1423 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
1424 * to the CTR_EL0 on this CPU and emulate it with the real/safe
1425 * value.
1426 */
1427 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
1428 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1429 }
1430
has_cache_dic(const struct arm64_cpu_capabilities * entry,int scope)1431 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
1432 int scope)
1433 {
1434 u64 ctr;
1435
1436 if (scope == SCOPE_SYSTEM)
1437 ctr = arm64_ftr_reg_ctrel0.sys_val;
1438 else
1439 ctr = read_cpuid_cachetype();
1440
1441 return ctr & BIT(CTR_DIC_SHIFT);
1442 }
1443
1444 static bool __maybe_unused
has_useable_cnp(const struct arm64_cpu_capabilities * entry,int scope)1445 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1446 {
1447 /*
1448 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
1449 * may share TLB entries with a CPU stuck in the crashed
1450 * kernel.
1451 */
1452 if (is_kdump_kernel())
1453 return false;
1454
1455 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP))
1456 return false;
1457
1458 return has_cpuid_feature(entry, scope);
1459 }
1460
1461 /*
1462 * This check is triggered during the early boot before the cpufeature
1463 * is initialised. Checking the status on the local CPU allows the boot
1464 * CPU to detect the need for non-global mappings and thus avoiding a
1465 * pagetable re-write after all the CPUs are booted. This check will be
1466 * anyway run on individual CPUs, allowing us to get the consistent
1467 * state once the SMP CPUs are up and thus make the switch to non-global
1468 * mappings if required.
1469 */
kaslr_requires_kpti(void)1470 bool kaslr_requires_kpti(void)
1471 {
1472 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1473 return false;
1474
1475 /*
1476 * E0PD does a similar job to KPTI so can be used instead
1477 * where available.
1478 */
1479 if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
1480 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1481 if (cpuid_feature_extract_unsigned_field(mmfr2,
1482 ID_AA64MMFR2_E0PD_SHIFT))
1483 return false;
1484 }
1485
1486 return kaslr_offset() > 0;
1487 }
1488
1489 static bool __meltdown_safe = true;
1490 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
1491
unmap_kernel_at_el0(const struct arm64_cpu_capabilities * entry,int scope)1492 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1493 int scope)
1494 {
1495 /* List of CPUs that are not vulnerable and don't need KPTI */
1496 static const struct midr_range kpti_safe_list[] = {
1497 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1498 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1499 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1500 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1501 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1502 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1503 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1504 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1505 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1506 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1507 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1508 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD),
1509 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
1510 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
1511 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
1512 { /* sentinel */ }
1513 };
1514 char const *str = "kpti command line option";
1515 bool meltdown_safe;
1516
1517 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1518
1519 /* Defer to CPU feature registers */
1520 if (has_cpuid_feature(entry, scope))
1521 meltdown_safe = true;
1522
1523 if (!meltdown_safe)
1524 __meltdown_safe = false;
1525
1526 /* Useful for KASLR robustness */
1527 if (kaslr_requires_kpti()) {
1528 if (!__kpti_forced) {
1529 str = "KASLR";
1530 __kpti_forced = 1;
1531 }
1532 }
1533
1534 if (cpu_mitigations_off() && !__kpti_forced) {
1535 str = "mitigations=off";
1536 __kpti_forced = -1;
1537 }
1538
1539 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1540 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1541 return false;
1542 }
1543
1544 /* Forced? */
1545 if (__kpti_forced) {
1546 pr_info_once("kernel page table isolation forced %s by %s\n",
1547 __kpti_forced > 0 ? "ON" : "OFF", str);
1548 return __kpti_forced > 0;
1549 }
1550
1551 return !meltdown_safe;
1552 }
1553
1554 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1555 static void __nocfi
kpti_install_ng_mappings(const struct arm64_cpu_capabilities * __unused)1556 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1557 {
1558 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1559 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1560 kpti_remap_fn *remap_fn;
1561
1562 int cpu = smp_processor_id();
1563
1564 if (__this_cpu_read(this_cpu_vector) == vectors) {
1565 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);
1566
1567 __this_cpu_write(this_cpu_vector, v);
1568 }
1569
1570 /*
1571 * We don't need to rewrite the page-tables if either we've done
1572 * it already or we have KASLR enabled and therefore have not
1573 * created any global mappings at all.
1574 */
1575 if (arm64_use_ng_mappings)
1576 return;
1577
1578 remap_fn = (void *)__pa_symbol(function_nocfi(idmap_kpti_install_ng_mappings));
1579
1580 cpu_install_idmap();
1581 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1582 cpu_uninstall_idmap();
1583
1584 if (!cpu)
1585 arm64_use_ng_mappings = true;
1586 }
1587 #else
1588 static void
kpti_install_ng_mappings(const struct arm64_cpu_capabilities * __unused)1589 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1590 {
1591 }
1592 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1593
parse_kpti(char * str)1594 static int __init parse_kpti(char *str)
1595 {
1596 bool enabled;
1597 int ret = strtobool(str, &enabled);
1598
1599 if (ret)
1600 return ret;
1601
1602 __kpti_forced = enabled ? 1 : -1;
1603 return 0;
1604 }
1605 early_param("kpti", parse_kpti);
1606
1607 #ifdef CONFIG_ARM64_HW_AFDBM
__cpu_enable_hw_dbm(void)1608 static inline void __cpu_enable_hw_dbm(void)
1609 {
1610 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1611
1612 write_sysreg(tcr, tcr_el1);
1613 isb();
1614 local_flush_tlb_all();
1615 }
1616
cpu_has_broken_dbm(void)1617 static bool cpu_has_broken_dbm(void)
1618 {
1619 /* List of CPUs which have broken DBM support. */
1620 static const struct midr_range cpus[] = {
1621 #ifdef CONFIG_ARM64_ERRATUM_1024718
1622 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1623 /* Kryo4xx Silver (rdpe => r1p0) */
1624 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
1625 #endif
1626 {},
1627 };
1628
1629 return is_midr_in_range_list(read_cpuid_id(), cpus);
1630 }
1631
cpu_can_use_dbm(const struct arm64_cpu_capabilities * cap)1632 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1633 {
1634 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1635 !cpu_has_broken_dbm();
1636 }
1637
cpu_enable_hw_dbm(struct arm64_cpu_capabilities const * cap)1638 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1639 {
1640 if (cpu_can_use_dbm(cap))
1641 __cpu_enable_hw_dbm();
1642 }
1643
has_hw_dbm(const struct arm64_cpu_capabilities * cap,int __unused)1644 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1645 int __unused)
1646 {
1647 static bool detected = false;
1648 /*
1649 * DBM is a non-conflicting feature. i.e, the kernel can safely
1650 * run a mix of CPUs with and without the feature. So, we
1651 * unconditionally enable the capability to allow any late CPU
1652 * to use the feature. We only enable the control bits on the
1653 * CPU, if it actually supports.
1654 *
1655 * We have to make sure we print the "feature" detection only
1656 * when at least one CPU actually uses it. So check if this CPU
1657 * can actually use it and print the message exactly once.
1658 *
1659 * This is safe as all CPUs (including secondary CPUs - due to the
1660 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1661 * goes through the "matches" check exactly once. Also if a CPU
1662 * matches the criteria, it is guaranteed that the CPU will turn
1663 * the DBM on, as the capability is unconditionally enabled.
1664 */
1665 if (!detected && cpu_can_use_dbm(cap)) {
1666 detected = true;
1667 pr_info("detected: Hardware dirty bit management\n");
1668 }
1669
1670 return true;
1671 }
1672
1673 #endif
1674
1675 #ifdef CONFIG_ARM64_AMU_EXTN
1676
1677 /*
1678 * The "amu_cpus" cpumask only signals that the CPU implementation for the
1679 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1680 * information regarding all the events that it supports. When a CPU bit is
1681 * set in the cpumask, the user of this feature can only rely on the presence
1682 * of the 4 fixed counters for that CPU. But this does not guarantee that the
1683 * counters are enabled or access to these counters is enabled by code
1684 * executed at higher exception levels (firmware).
1685 */
1686 static struct cpumask amu_cpus __read_mostly;
1687
cpu_has_amu_feat(int cpu)1688 bool cpu_has_amu_feat(int cpu)
1689 {
1690 return cpumask_test_cpu(cpu, &amu_cpus);
1691 }
1692
get_cpu_with_amu_feat(void)1693 int get_cpu_with_amu_feat(void)
1694 {
1695 return cpumask_any(&amu_cpus);
1696 }
1697
cpu_amu_enable(struct arm64_cpu_capabilities const * cap)1698 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1699 {
1700 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1701 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1702 smp_processor_id());
1703 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
1704
1705 /* 0 reference values signal broken/disabled counters */
1706 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168))
1707 update_freq_counters_refs();
1708 }
1709 }
1710
has_amu(const struct arm64_cpu_capabilities * cap,int __unused)1711 static bool has_amu(const struct arm64_cpu_capabilities *cap,
1712 int __unused)
1713 {
1714 /*
1715 * The AMU extension is a non-conflicting feature: the kernel can
1716 * safely run a mix of CPUs with and without support for the
1717 * activity monitors extension. Therefore, unconditionally enable
1718 * the capability to allow any late CPU to use the feature.
1719 *
1720 * With this feature unconditionally enabled, the cpu_enable
1721 * function will be called for all CPUs that match the criteria,
1722 * including secondary and hotplugged, marking this feature as
1723 * present on that respective CPU. The enable function will also
1724 * print a detection message.
1725 */
1726
1727 return true;
1728 }
1729 #else
get_cpu_with_amu_feat(void)1730 int get_cpu_with_amu_feat(void)
1731 {
1732 return nr_cpu_ids;
1733 }
1734 #endif
1735
runs_at_el2(const struct arm64_cpu_capabilities * entry,int __unused)1736 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1737 {
1738 return is_kernel_in_hyp_mode();
1739 }
1740
cpu_copy_el2regs(const struct arm64_cpu_capabilities * __unused)1741 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1742 {
1743 /*
1744 * Copy register values that aren't redirected by hardware.
1745 *
1746 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1747 * this value to tpidr_el2 before we patch the code. Once we've done
1748 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1749 * do anything here.
1750 */
1751 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1752 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1753 }
1754
cpu_has_fwb(const struct arm64_cpu_capabilities * __unused)1755 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1756 {
1757 u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1758
1759 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1760 WARN_ON(CLIDR_LOUU(val) || CLIDR_LOUIS(val));
1761 }
1762
1763 #ifdef CONFIG_ARM64_PAN
cpu_enable_pan(const struct arm64_cpu_capabilities * __unused)1764 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1765 {
1766 /*
1767 * We modify PSTATE. This won't work from irq context as the PSTATE
1768 * is discarded once we return from the exception.
1769 */
1770 WARN_ON_ONCE(in_interrupt());
1771
1772 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1773 set_pstate_pan(1);
1774 }
1775 #endif /* CONFIG_ARM64_PAN */
1776
1777 #ifdef CONFIG_ARM64_RAS_EXTN
cpu_clear_disr(const struct arm64_cpu_capabilities * __unused)1778 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1779 {
1780 /* Firmware may have left a deferred SError in this register. */
1781 write_sysreg_s(0, SYS_DISR_EL1);
1782 }
1783 #endif /* CONFIG_ARM64_RAS_EXTN */
1784
1785 #ifdef CONFIG_ARM64_PTR_AUTH
has_address_auth_cpucap(const struct arm64_cpu_capabilities * entry,int scope)1786 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope)
1787 {
1788 int boot_val, sec_val;
1789
1790 /* We don't expect to be called with SCOPE_SYSTEM */
1791 WARN_ON(scope == SCOPE_SYSTEM);
1792 /*
1793 * The ptr-auth feature levels are not intercompatible with lower
1794 * levels. Hence we must match ptr-auth feature level of the secondary
1795 * CPUs with that of the boot CPU. The level of boot cpu is fetched
1796 * from the sanitised register whereas direct register read is done for
1797 * the secondary CPUs.
1798 * The sanitised feature state is guaranteed to match that of the
1799 * boot CPU as a mismatched secondary CPU is parked before it gets
1800 * a chance to update the state, with the capability.
1801 */
1802 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg),
1803 entry->field_pos, entry->sign);
1804 if (scope & SCOPE_BOOT_CPU)
1805 return boot_val >= entry->min_field_value;
1806 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */
1807 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg),
1808 entry->field_pos, entry->sign);
1809 return sec_val == boot_val;
1810 }
1811
has_address_auth_metacap(const struct arm64_cpu_capabilities * entry,int scope)1812 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry,
1813 int scope)
1814 {
1815 return has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH], scope) ||
1816 has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope);
1817 }
1818
has_generic_auth(const struct arm64_cpu_capabilities * entry,int __unused)1819 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
1820 int __unused)
1821 {
1822 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) ||
1823 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
1824 }
1825 #endif /* CONFIG_ARM64_PTR_AUTH */
1826
1827 #ifdef CONFIG_ARM64_E0PD
cpu_enable_e0pd(struct arm64_cpu_capabilities const * cap)1828 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
1829 {
1830 if (this_cpu_has_cap(ARM64_HAS_E0PD))
1831 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
1832 }
1833 #endif /* CONFIG_ARM64_E0PD */
1834
1835 #ifdef CONFIG_ARM64_PSEUDO_NMI
1836 static bool enable_pseudo_nmi;
1837
early_enable_pseudo_nmi(char * p)1838 static int __init early_enable_pseudo_nmi(char *p)
1839 {
1840 return strtobool(p, &enable_pseudo_nmi);
1841 }
1842 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1843
can_use_gic_priorities(const struct arm64_cpu_capabilities * entry,int scope)1844 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1845 int scope)
1846 {
1847 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1848 }
1849 #endif
1850
1851 #ifdef CONFIG_ARM64_BTI
bti_enable(const struct arm64_cpu_capabilities * __unused)1852 static void bti_enable(const struct arm64_cpu_capabilities *__unused)
1853 {
1854 /*
1855 * Use of X16/X17 for tail-calls and trampolines that jump to
1856 * function entry points using BR is a requirement for
1857 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI.
1858 * So, be strict and forbid other BRs using other registers to
1859 * jump onto a PACIxSP instruction:
1860 */
1861 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1);
1862 isb();
1863 }
1864 #endif /* CONFIG_ARM64_BTI */
1865
1866 #ifdef CONFIG_ARM64_MTE
cpu_enable_mte(struct arm64_cpu_capabilities const * cap)1867 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
1868 {
1869 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0);
1870
1871 mte_cpu_setup();
1872
1873 /*
1874 * Clear the tags in the zero page. This needs to be done via the
1875 * linear map which has the Tagged attribute.
1876 */
1877 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags))
1878 mte_clear_page_tags(lm_alias(empty_zero_page));
1879
1880 kasan_init_hw_tags_cpu();
1881 }
1882 #endif /* CONFIG_ARM64_MTE */
1883
1884 #ifdef CONFIG_KVM
is_kvm_protected_mode(const struct arm64_cpu_capabilities * entry,int __unused)1885 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused)
1886 {
1887 return kvm_get_mode() == KVM_MODE_PROTECTED;
1888 }
1889 #endif /* CONFIG_KVM */
1890
1891 /* Internal helper functions to match cpu capability type */
1892 static bool
cpucap_late_cpu_optional(const struct arm64_cpu_capabilities * cap)1893 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
1894 {
1895 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
1896 }
1897
1898 static bool
cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities * cap)1899 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
1900 {
1901 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
1902 }
1903
1904 static bool
cpucap_panic_on_conflict(const struct arm64_cpu_capabilities * cap)1905 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
1906 {
1907 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
1908 }
1909
1910 static const struct arm64_cpu_capabilities arm64_features[] = {
1911 {
1912 .desc = "GIC system register CPU interface",
1913 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1914 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1915 .matches = has_useable_gicv3_cpuif,
1916 .sys_reg = SYS_ID_AA64PFR0_EL1,
1917 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1918 .sign = FTR_UNSIGNED,
1919 .min_field_value = 1,
1920 },
1921 #ifdef CONFIG_ARM64_PAN
1922 {
1923 .desc = "Privileged Access Never",
1924 .capability = ARM64_HAS_PAN,
1925 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1926 .matches = has_cpuid_feature,
1927 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1928 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1929 .sign = FTR_UNSIGNED,
1930 .min_field_value = 1,
1931 .cpu_enable = cpu_enable_pan,
1932 },
1933 #endif /* CONFIG_ARM64_PAN */
1934 #ifdef CONFIG_ARM64_EPAN
1935 {
1936 .desc = "Enhanced Privileged Access Never",
1937 .capability = ARM64_HAS_EPAN,
1938 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1939 .matches = has_cpuid_feature,
1940 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1941 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1942 .sign = FTR_UNSIGNED,
1943 .min_field_value = 3,
1944 },
1945 #endif /* CONFIG_ARM64_EPAN */
1946 #ifdef CONFIG_ARM64_LSE_ATOMICS
1947 {
1948 .desc = "LSE atomic instructions",
1949 .capability = ARM64_HAS_LSE_ATOMICS,
1950 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1951 .matches = has_cpuid_feature,
1952 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1953 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1954 .sign = FTR_UNSIGNED,
1955 .min_field_value = 2,
1956 },
1957 #endif /* CONFIG_ARM64_LSE_ATOMICS */
1958 {
1959 .desc = "Virtualization Host Extensions",
1960 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1961 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1962 .matches = runs_at_el2,
1963 .cpu_enable = cpu_copy_el2regs,
1964 },
1965 {
1966 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE,
1967 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1968 .matches = has_32bit_el0,
1969 .sys_reg = SYS_ID_AA64PFR0_EL1,
1970 .sign = FTR_UNSIGNED,
1971 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1972 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT,
1973 },
1974 #ifdef CONFIG_KVM
1975 {
1976 .desc = "32-bit EL1 Support",
1977 .capability = ARM64_HAS_32BIT_EL1,
1978 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1979 .matches = has_cpuid_feature,
1980 .sys_reg = SYS_ID_AA64PFR0_EL1,
1981 .sign = FTR_UNSIGNED,
1982 .field_pos = ID_AA64PFR0_EL1_SHIFT,
1983 .min_field_value = ID_AA64PFR0_ELx_32BIT_64BIT,
1984 },
1985 {
1986 .desc = "Protected KVM",
1987 .capability = ARM64_KVM_PROTECTED_MODE,
1988 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1989 .matches = is_kvm_protected_mode,
1990 },
1991 #endif
1992 {
1993 .desc = "Kernel page table isolation (KPTI)",
1994 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1995 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1996 /*
1997 * The ID feature fields below are used to indicate that
1998 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1999 * more details.
2000 */
2001 .sys_reg = SYS_ID_AA64PFR0_EL1,
2002 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
2003 .min_field_value = 1,
2004 .matches = unmap_kernel_at_el0,
2005 .cpu_enable = kpti_install_ng_mappings,
2006 },
2007 {
2008 /* FP/SIMD is not implemented */
2009 .capability = ARM64_HAS_NO_FPSIMD,
2010 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
2011 .min_field_value = 0,
2012 .matches = has_no_fpsimd,
2013 },
2014 #ifdef CONFIG_ARM64_PMEM
2015 {
2016 .desc = "Data cache clean to Point of Persistence",
2017 .capability = ARM64_HAS_DCPOP,
2018 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2019 .matches = has_cpuid_feature,
2020 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2021 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
2022 .min_field_value = 1,
2023 },
2024 {
2025 .desc = "Data cache clean to Point of Deep Persistence",
2026 .capability = ARM64_HAS_DCPODP,
2027 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2028 .matches = has_cpuid_feature,
2029 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2030 .sign = FTR_UNSIGNED,
2031 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
2032 .min_field_value = 2,
2033 },
2034 #endif
2035 #ifdef CONFIG_ARM64_SVE
2036 {
2037 .desc = "Scalable Vector Extension",
2038 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2039 .capability = ARM64_SVE,
2040 .sys_reg = SYS_ID_AA64PFR0_EL1,
2041 .sign = FTR_UNSIGNED,
2042 .field_pos = ID_AA64PFR0_SVE_SHIFT,
2043 .min_field_value = ID_AA64PFR0_SVE,
2044 .matches = has_cpuid_feature,
2045 .cpu_enable = sve_kernel_enable,
2046 },
2047 #endif /* CONFIG_ARM64_SVE */
2048 #ifdef CONFIG_ARM64_RAS_EXTN
2049 {
2050 .desc = "RAS Extension Support",
2051 .capability = ARM64_HAS_RAS_EXTN,
2052 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2053 .matches = has_cpuid_feature,
2054 .sys_reg = SYS_ID_AA64PFR0_EL1,
2055 .sign = FTR_UNSIGNED,
2056 .field_pos = ID_AA64PFR0_RAS_SHIFT,
2057 .min_field_value = ID_AA64PFR0_RAS_V1,
2058 .cpu_enable = cpu_clear_disr,
2059 },
2060 #endif /* CONFIG_ARM64_RAS_EXTN */
2061 #ifdef CONFIG_ARM64_AMU_EXTN
2062 {
2063 /*
2064 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
2065 * Therefore, don't provide .desc as we don't want the detection
2066 * message to be shown until at least one CPU is detected to
2067 * support the feature.
2068 */
2069 .capability = ARM64_HAS_AMU_EXTN,
2070 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2071 .matches = has_amu,
2072 .sys_reg = SYS_ID_AA64PFR0_EL1,
2073 .sign = FTR_UNSIGNED,
2074 .field_pos = ID_AA64PFR0_AMU_SHIFT,
2075 .min_field_value = ID_AA64PFR0_AMU,
2076 .cpu_enable = cpu_amu_enable,
2077 },
2078 #endif /* CONFIG_ARM64_AMU_EXTN */
2079 {
2080 .desc = "Data cache clean to the PoU not required for I/D coherence",
2081 .capability = ARM64_HAS_CACHE_IDC,
2082 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2083 .matches = has_cache_idc,
2084 .cpu_enable = cpu_emulate_effective_ctr,
2085 },
2086 {
2087 .desc = "Instruction cache invalidation not required for I/D coherence",
2088 .capability = ARM64_HAS_CACHE_DIC,
2089 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2090 .matches = has_cache_dic,
2091 },
2092 {
2093 .desc = "Stage-2 Force Write-Back",
2094 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2095 .capability = ARM64_HAS_STAGE2_FWB,
2096 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2097 .sign = FTR_UNSIGNED,
2098 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
2099 .min_field_value = 1,
2100 .matches = has_cpuid_feature,
2101 .cpu_enable = cpu_has_fwb,
2102 },
2103 {
2104 .desc = "ARMv8.4 Translation Table Level",
2105 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2106 .capability = ARM64_HAS_ARMv8_4_TTL,
2107 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2108 .sign = FTR_UNSIGNED,
2109 .field_pos = ID_AA64MMFR2_TTL_SHIFT,
2110 .min_field_value = 1,
2111 .matches = has_cpuid_feature,
2112 },
2113 {
2114 .desc = "TLB range maintenance instructions",
2115 .capability = ARM64_HAS_TLB_RANGE,
2116 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2117 .matches = has_cpuid_feature,
2118 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2119 .field_pos = ID_AA64ISAR0_TLB_SHIFT,
2120 .sign = FTR_UNSIGNED,
2121 .min_field_value = ID_AA64ISAR0_TLB_RANGE,
2122 },
2123 #ifdef CONFIG_ARM64_HW_AFDBM
2124 {
2125 /*
2126 * Since we turn this on always, we don't want the user to
2127 * think that the feature is available when it may not be.
2128 * So hide the description.
2129 *
2130 * .desc = "Hardware pagetable Dirty Bit Management",
2131 *
2132 */
2133 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2134 .capability = ARM64_HW_DBM,
2135 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2136 .sign = FTR_UNSIGNED,
2137 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
2138 .min_field_value = 2,
2139 .matches = has_hw_dbm,
2140 .cpu_enable = cpu_enable_hw_dbm,
2141 },
2142 #endif
2143 {
2144 .desc = "CRC32 instructions",
2145 .capability = ARM64_HAS_CRC32,
2146 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2147 .matches = has_cpuid_feature,
2148 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2149 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
2150 .min_field_value = 1,
2151 },
2152 {
2153 .desc = "Speculative Store Bypassing Safe (SSBS)",
2154 .capability = ARM64_SSBS,
2155 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2156 .matches = has_cpuid_feature,
2157 .sys_reg = SYS_ID_AA64PFR1_EL1,
2158 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
2159 .sign = FTR_UNSIGNED,
2160 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
2161 },
2162 #ifdef CONFIG_ARM64_CNP
2163 {
2164 .desc = "Common not Private translations",
2165 .capability = ARM64_HAS_CNP,
2166 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2167 .matches = has_useable_cnp,
2168 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2169 .sign = FTR_UNSIGNED,
2170 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
2171 .min_field_value = 1,
2172 .cpu_enable = cpu_enable_cnp,
2173 },
2174 #endif
2175 {
2176 .desc = "Speculation barrier (SB)",
2177 .capability = ARM64_HAS_SB,
2178 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2179 .matches = has_cpuid_feature,
2180 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2181 .field_pos = ID_AA64ISAR1_SB_SHIFT,
2182 .sign = FTR_UNSIGNED,
2183 .min_field_value = 1,
2184 },
2185 #ifdef CONFIG_ARM64_PTR_AUTH
2186 {
2187 .desc = "Address authentication (architected algorithm)",
2188 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
2189 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2190 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2191 .sign = FTR_UNSIGNED,
2192 .field_pos = ID_AA64ISAR1_APA_SHIFT,
2193 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
2194 .matches = has_address_auth_cpucap,
2195 },
2196 {
2197 .desc = "Address authentication (IMP DEF algorithm)",
2198 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
2199 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2200 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2201 .sign = FTR_UNSIGNED,
2202 .field_pos = ID_AA64ISAR1_API_SHIFT,
2203 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
2204 .matches = has_address_auth_cpucap,
2205 },
2206 {
2207 .capability = ARM64_HAS_ADDRESS_AUTH,
2208 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2209 .matches = has_address_auth_metacap,
2210 },
2211 {
2212 .desc = "Generic authentication (architected algorithm)",
2213 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
2214 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2215 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2216 .sign = FTR_UNSIGNED,
2217 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
2218 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
2219 .matches = has_cpuid_feature,
2220 },
2221 {
2222 .desc = "Generic authentication (IMP DEF algorithm)",
2223 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
2224 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2225 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2226 .sign = FTR_UNSIGNED,
2227 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
2228 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
2229 .matches = has_cpuid_feature,
2230 },
2231 {
2232 .capability = ARM64_HAS_GENERIC_AUTH,
2233 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2234 .matches = has_generic_auth,
2235 },
2236 #endif /* CONFIG_ARM64_PTR_AUTH */
2237 #ifdef CONFIG_ARM64_PSEUDO_NMI
2238 {
2239 /*
2240 * Depends on having GICv3
2241 */
2242 .desc = "IRQ priority masking",
2243 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
2244 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2245 .matches = can_use_gic_priorities,
2246 .sys_reg = SYS_ID_AA64PFR0_EL1,
2247 .field_pos = ID_AA64PFR0_GIC_SHIFT,
2248 .sign = FTR_UNSIGNED,
2249 .min_field_value = 1,
2250 },
2251 #endif
2252 #ifdef CONFIG_ARM64_E0PD
2253 {
2254 .desc = "E0PD",
2255 .capability = ARM64_HAS_E0PD,
2256 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2257 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2258 .sign = FTR_UNSIGNED,
2259 .field_pos = ID_AA64MMFR2_E0PD_SHIFT,
2260 .matches = has_cpuid_feature,
2261 .min_field_value = 1,
2262 .cpu_enable = cpu_enable_e0pd,
2263 },
2264 #endif
2265 #ifdef CONFIG_ARCH_RANDOM
2266 {
2267 .desc = "Random Number Generator",
2268 .capability = ARM64_HAS_RNG,
2269 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2270 .matches = has_cpuid_feature,
2271 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2272 .field_pos = ID_AA64ISAR0_RNDR_SHIFT,
2273 .sign = FTR_UNSIGNED,
2274 .min_field_value = 1,
2275 },
2276 #endif
2277 #ifdef CONFIG_ARM64_BTI
2278 {
2279 .desc = "Branch Target Identification",
2280 .capability = ARM64_BTI,
2281 #ifdef CONFIG_ARM64_BTI_KERNEL
2282 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2283 #else
2284 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2285 #endif
2286 .matches = has_cpuid_feature,
2287 .cpu_enable = bti_enable,
2288 .sys_reg = SYS_ID_AA64PFR1_EL1,
2289 .field_pos = ID_AA64PFR1_BT_SHIFT,
2290 .min_field_value = ID_AA64PFR1_BT_BTI,
2291 .sign = FTR_UNSIGNED,
2292 },
2293 #endif
2294 #ifdef CONFIG_ARM64_MTE
2295 {
2296 .desc = "Memory Tagging Extension",
2297 .capability = ARM64_MTE,
2298 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2299 .matches = has_cpuid_feature,
2300 .sys_reg = SYS_ID_AA64PFR1_EL1,
2301 .field_pos = ID_AA64PFR1_MTE_SHIFT,
2302 .min_field_value = ID_AA64PFR1_MTE,
2303 .sign = FTR_UNSIGNED,
2304 .cpu_enable = cpu_enable_mte,
2305 },
2306 {
2307 .desc = "Asymmetric MTE Tag Check Fault",
2308 .capability = ARM64_MTE_ASYMM,
2309 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2310 .matches = has_cpuid_feature,
2311 .sys_reg = SYS_ID_AA64PFR1_EL1,
2312 .field_pos = ID_AA64PFR1_MTE_SHIFT,
2313 .min_field_value = ID_AA64PFR1_MTE_ASYMM,
2314 .sign = FTR_UNSIGNED,
2315 },
2316 #endif /* CONFIG_ARM64_MTE */
2317 {
2318 .desc = "RCpc load-acquire (LDAPR)",
2319 .capability = ARM64_HAS_LDAPR,
2320 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2321 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2322 .sign = FTR_UNSIGNED,
2323 .field_pos = ID_AA64ISAR1_LRCPC_SHIFT,
2324 .matches = has_cpuid_feature,
2325 .min_field_value = 1,
2326 },
2327 {},
2328 };
2329
2330 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \
2331 .matches = has_cpuid_feature, \
2332 .sys_reg = reg, \
2333 .field_pos = field, \
2334 .sign = s, \
2335 .min_field_value = min_value,
2336
2337 #define __HWCAP_CAP(name, cap_type, cap) \
2338 .desc = name, \
2339 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
2340 .hwcap_type = cap_type, \
2341 .hwcap = cap, \
2342
2343 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
2344 { \
2345 __HWCAP_CAP(#cap, cap_type, cap) \
2346 HWCAP_CPUID_MATCH(reg, field, s, min_value) \
2347 }
2348
2349 #define HWCAP_MULTI_CAP(list, cap_type, cap) \
2350 { \
2351 __HWCAP_CAP(#cap, cap_type, cap) \
2352 .matches = cpucap_multi_entry_cap_matches, \
2353 .match_list = list, \
2354 }
2355
2356 #define HWCAP_CAP_MATCH(match, cap_type, cap) \
2357 { \
2358 __HWCAP_CAP(#cap, cap_type, cap) \
2359 .matches = match, \
2360 }
2361
2362 #ifdef CONFIG_ARM64_PTR_AUTH
2363 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
2364 {
2365 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
2366 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
2367 },
2368 {
2369 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
2370 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
2371 },
2372 {},
2373 };
2374
2375 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
2376 {
2377 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
2378 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
2379 },
2380 {
2381 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
2382 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
2383 },
2384 {},
2385 };
2386 #endif
2387
2388 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
2389 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
2390 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
2391 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
2392 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
2393 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
2394 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
2395 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
2396 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
2397 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
2398 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
2399 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
2400 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
2401 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
2402 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
2403 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
2404 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
2405 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
2406 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
2407 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2408 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2409 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
2410 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
2411 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
2412 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2413 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2414 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2415 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
2416 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
2417 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
2418 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
2419 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
2420 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2421 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
2422 #ifdef CONFIG_ARM64_SVE
2423 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
2424 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2425 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2426 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2427 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
2428 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
2429 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2430 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
2431 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2432 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2433 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
2434 #endif
2435 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
2436 #ifdef CONFIG_ARM64_BTI
2437 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI),
2438 #endif
2439 #ifdef CONFIG_ARM64_PTR_AUTH
2440 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2441 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
2442 #endif
2443 #ifdef CONFIG_ARM64_MTE
2444 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),
2445 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE_ASYMM, CAP_HWCAP, KERNEL_HWCAP_MTE3),
2446 #endif /* CONFIG_ARM64_MTE */
2447 HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
2448 HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
2449 HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
2450 {},
2451 };
2452
2453 #ifdef CONFIG_COMPAT
compat_has_neon(const struct arm64_cpu_capabilities * cap,int scope)2454 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
2455 {
2456 /*
2457 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
2458 * in line with that of arm32 as in vfp_init(). We make sure that the
2459 * check is future proof, by making sure value is non-zero.
2460 */
2461 u32 mvfr1;
2462
2463 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
2464 if (scope == SCOPE_SYSTEM)
2465 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
2466 else
2467 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
2468
2469 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
2470 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
2471 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
2472 }
2473 #endif
2474
2475 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
2476 #ifdef CONFIG_COMPAT
2477 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2478 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2479 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
2480 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2481 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
2482 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2483 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2484 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2485 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2486 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
2487 #endif
2488 {},
2489 };
2490
cap_set_elf_hwcap(const struct arm64_cpu_capabilities * cap)2491 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2492 {
2493 switch (cap->hwcap_type) {
2494 case CAP_HWCAP:
2495 cpu_set_feature(cap->hwcap);
2496 break;
2497 #ifdef CONFIG_COMPAT
2498 case CAP_COMPAT_HWCAP:
2499 compat_elf_hwcap |= (u32)cap->hwcap;
2500 break;
2501 case CAP_COMPAT_HWCAP2:
2502 compat_elf_hwcap2 |= (u32)cap->hwcap;
2503 break;
2504 #endif
2505 default:
2506 WARN_ON(1);
2507 break;
2508 }
2509 }
2510
2511 /* Check if we have a particular HWCAP enabled */
cpus_have_elf_hwcap(const struct arm64_cpu_capabilities * cap)2512 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2513 {
2514 bool rc;
2515
2516 switch (cap->hwcap_type) {
2517 case CAP_HWCAP:
2518 rc = cpu_have_feature(cap->hwcap);
2519 break;
2520 #ifdef CONFIG_COMPAT
2521 case CAP_COMPAT_HWCAP:
2522 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
2523 break;
2524 case CAP_COMPAT_HWCAP2:
2525 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
2526 break;
2527 #endif
2528 default:
2529 WARN_ON(1);
2530 rc = false;
2531 }
2532
2533 return rc;
2534 }
2535
setup_elf_hwcaps(const struct arm64_cpu_capabilities * hwcaps)2536 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
2537 {
2538 /* We support emulation of accesses to CPU ID feature registers */
2539 cpu_set_named_feature(CPUID);
2540 for (; hwcaps->matches; hwcaps++)
2541 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
2542 cap_set_elf_hwcap(hwcaps);
2543 }
2544
update_cpu_capabilities(u16 scope_mask)2545 static void update_cpu_capabilities(u16 scope_mask)
2546 {
2547 int i;
2548 const struct arm64_cpu_capabilities *caps;
2549
2550 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2551 for (i = 0; i < ARM64_NCAPS; i++) {
2552 caps = cpu_hwcaps_ptrs[i];
2553 if (!caps || !(caps->type & scope_mask) ||
2554 cpus_have_cap(caps->capability) ||
2555 !caps->matches(caps, cpucap_default_scope(caps)))
2556 continue;
2557
2558 if (caps->desc)
2559 pr_info("detected: %s\n", caps->desc);
2560 cpus_set_cap(caps->capability);
2561
2562 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
2563 set_bit(caps->capability, boot_capabilities);
2564 }
2565 }
2566
2567 /*
2568 * Enable all the available capabilities on this CPU. The capabilities
2569 * with BOOT_CPU scope are handled separately and hence skipped here.
2570 */
cpu_enable_non_boot_scope_capabilities(void * __unused)2571 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
2572 {
2573 int i;
2574 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
2575
2576 for_each_available_cap(i) {
2577 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
2578
2579 if (WARN_ON(!cap))
2580 continue;
2581
2582 if (!(cap->type & non_boot_scope))
2583 continue;
2584
2585 if (cap->cpu_enable)
2586 cap->cpu_enable(cap);
2587 }
2588 return 0;
2589 }
2590
2591 /*
2592 * Run through the enabled capabilities and enable() it on all active
2593 * CPUs
2594 */
enable_cpu_capabilities(u16 scope_mask)2595 static void __init enable_cpu_capabilities(u16 scope_mask)
2596 {
2597 int i;
2598 const struct arm64_cpu_capabilities *caps;
2599 bool boot_scope;
2600
2601 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2602 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
2603
2604 for (i = 0; i < ARM64_NCAPS; i++) {
2605 unsigned int num;
2606
2607 caps = cpu_hwcaps_ptrs[i];
2608 if (!caps || !(caps->type & scope_mask))
2609 continue;
2610 num = caps->capability;
2611 if (!cpus_have_cap(num))
2612 continue;
2613
2614 /* Ensure cpus_have_const_cap(num) works */
2615 static_branch_enable(&cpu_hwcap_keys[num]);
2616
2617 if (boot_scope && caps->cpu_enable)
2618 /*
2619 * Capabilities with SCOPE_BOOT_CPU scope are finalised
2620 * before any secondary CPU boots. Thus, each secondary
2621 * will enable the capability as appropriate via
2622 * check_local_cpu_capabilities(). The only exception is
2623 * the boot CPU, for which the capability must be
2624 * enabled here. This approach avoids costly
2625 * stop_machine() calls for this case.
2626 */
2627 caps->cpu_enable(caps);
2628 }
2629
2630 /*
2631 * For all non-boot scope capabilities, use stop_machine()
2632 * as it schedules the work allowing us to modify PSTATE,
2633 * instead of on_each_cpu() which uses an IPI, giving us a
2634 * PSTATE that disappears when we return.
2635 */
2636 if (!boot_scope)
2637 stop_machine(cpu_enable_non_boot_scope_capabilities,
2638 NULL, cpu_online_mask);
2639 }
2640
2641 /*
2642 * Run through the list of capabilities to check for conflicts.
2643 * If the system has already detected a capability, take necessary
2644 * action on this CPU.
2645 */
verify_local_cpu_caps(u16 scope_mask)2646 static void verify_local_cpu_caps(u16 scope_mask)
2647 {
2648 int i;
2649 bool cpu_has_cap, system_has_cap;
2650 const struct arm64_cpu_capabilities *caps;
2651
2652 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2653
2654 for (i = 0; i < ARM64_NCAPS; i++) {
2655 caps = cpu_hwcaps_ptrs[i];
2656 if (!caps || !(caps->type & scope_mask))
2657 continue;
2658
2659 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
2660 system_has_cap = cpus_have_cap(caps->capability);
2661
2662 if (system_has_cap) {
2663 /*
2664 * Check if the new CPU misses an advertised feature,
2665 * which is not safe to miss.
2666 */
2667 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
2668 break;
2669 /*
2670 * We have to issue cpu_enable() irrespective of
2671 * whether the CPU has it or not, as it is enabeld
2672 * system wide. It is upto the call back to take
2673 * appropriate action on this CPU.
2674 */
2675 if (caps->cpu_enable)
2676 caps->cpu_enable(caps);
2677 } else {
2678 /*
2679 * Check if the CPU has this capability if it isn't
2680 * safe to have when the system doesn't.
2681 */
2682 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
2683 break;
2684 }
2685 }
2686
2687 if (i < ARM64_NCAPS) {
2688 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
2689 smp_processor_id(), caps->capability,
2690 caps->desc, system_has_cap, cpu_has_cap);
2691
2692 if (cpucap_panic_on_conflict(caps))
2693 cpu_panic_kernel();
2694 else
2695 cpu_die_early();
2696 }
2697 }
2698
2699 /*
2700 * Check for CPU features that are used in early boot
2701 * based on the Boot CPU value.
2702 */
check_early_cpu_features(void)2703 static void check_early_cpu_features(void)
2704 {
2705 verify_cpu_asid_bits();
2706
2707 verify_local_cpu_caps(SCOPE_BOOT_CPU);
2708 }
2709
2710 static void
__verify_local_elf_hwcaps(const struct arm64_cpu_capabilities * caps)2711 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
2712 {
2713
2714 for (; caps->matches; caps++)
2715 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
2716 pr_crit("CPU%d: missing HWCAP: %s\n",
2717 smp_processor_id(), caps->desc);
2718 cpu_die_early();
2719 }
2720 }
2721
verify_local_elf_hwcaps(void)2722 static void verify_local_elf_hwcaps(void)
2723 {
2724 __verify_local_elf_hwcaps(arm64_elf_hwcaps);
2725
2726 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1)))
2727 __verify_local_elf_hwcaps(compat_elf_hwcaps);
2728 }
2729
verify_sve_features(void)2730 static void verify_sve_features(void)
2731 {
2732 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
2733 u64 zcr = read_zcr_features();
2734
2735 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
2736 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
2737
2738 if (len < safe_len || sve_verify_vq_map()) {
2739 pr_crit("CPU%d: SVE: vector length support mismatch\n",
2740 smp_processor_id());
2741 cpu_die_early();
2742 }
2743
2744 /* Add checks on other ZCR bits here if necessary */
2745 }
2746
verify_hyp_capabilities(void)2747 static void verify_hyp_capabilities(void)
2748 {
2749 u64 safe_mmfr1, mmfr0, mmfr1;
2750 int parange, ipa_max;
2751 unsigned int safe_vmid_bits, vmid_bits;
2752
2753 if (!IS_ENABLED(CONFIG_KVM))
2754 return;
2755
2756 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
2757 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
2758 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
2759
2760 /* Verify VMID bits */
2761 safe_vmid_bits = get_vmid_bits(safe_mmfr1);
2762 vmid_bits = get_vmid_bits(mmfr1);
2763 if (vmid_bits < safe_vmid_bits) {
2764 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
2765 cpu_die_early();
2766 }
2767
2768 /* Verify IPA range */
2769 parange = cpuid_feature_extract_unsigned_field(mmfr0,
2770 ID_AA64MMFR0_PARANGE_SHIFT);
2771 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
2772 if (ipa_max < get_kvm_ipa_limit()) {
2773 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
2774 cpu_die_early();
2775 }
2776 }
2777
2778 /*
2779 * Run through the enabled system capabilities and enable() it on this CPU.
2780 * The capabilities were decided based on the available CPUs at the boot time.
2781 * Any new CPU should match the system wide status of the capability. If the
2782 * new CPU doesn't have a capability which the system now has enabled, we
2783 * cannot do anything to fix it up and could cause unexpected failures. So
2784 * we park the CPU.
2785 */
verify_local_cpu_capabilities(void)2786 static void verify_local_cpu_capabilities(void)
2787 {
2788 /*
2789 * The capabilities with SCOPE_BOOT_CPU are checked from
2790 * check_early_cpu_features(), as they need to be verified
2791 * on all secondary CPUs.
2792 */
2793 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2794 verify_local_elf_hwcaps();
2795
2796 if (system_supports_sve())
2797 verify_sve_features();
2798
2799 if (is_hyp_mode_available())
2800 verify_hyp_capabilities();
2801 }
2802
check_local_cpu_capabilities(void)2803 void check_local_cpu_capabilities(void)
2804 {
2805 /*
2806 * All secondary CPUs should conform to the early CPU features
2807 * in use by the kernel based on boot CPU.
2808 */
2809 check_early_cpu_features();
2810
2811 /*
2812 * If we haven't finalised the system capabilities, this CPU gets
2813 * a chance to update the errata work arounds and local features.
2814 * Otherwise, this CPU should verify that it has all the system
2815 * advertised capabilities.
2816 */
2817 if (!system_capabilities_finalized())
2818 update_cpu_capabilities(SCOPE_LOCAL_CPU);
2819 else
2820 verify_local_cpu_capabilities();
2821 }
2822
setup_boot_cpu_capabilities(void)2823 static void __init setup_boot_cpu_capabilities(void)
2824 {
2825 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
2826 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2827 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
2828 enable_cpu_capabilities(SCOPE_BOOT_CPU);
2829 }
2830
this_cpu_has_cap(unsigned int n)2831 bool this_cpu_has_cap(unsigned int n)
2832 {
2833 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2834 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2835
2836 if (cap)
2837 return cap->matches(cap, SCOPE_LOCAL_CPU);
2838 }
2839
2840 return false;
2841 }
2842 EXPORT_SYMBOL_GPL(this_cpu_has_cap);
2843
2844 /*
2845 * This helper function is used in a narrow window when,
2846 * - The system wide safe registers are set with all the SMP CPUs and,
2847 * - The SYSTEM_FEATURE cpu_hwcaps may not have been set.
2848 * In all other cases cpus_have_{const_}cap() should be used.
2849 */
__system_matches_cap(unsigned int n)2850 static bool __maybe_unused __system_matches_cap(unsigned int n)
2851 {
2852 if (n < ARM64_NCAPS) {
2853 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2854
2855 if (cap)
2856 return cap->matches(cap, SCOPE_SYSTEM);
2857 }
2858 return false;
2859 }
2860
cpu_set_feature(unsigned int num)2861 void cpu_set_feature(unsigned int num)
2862 {
2863 WARN_ON(num >= MAX_CPU_FEATURES);
2864 elf_hwcap |= BIT(num);
2865 }
2866 EXPORT_SYMBOL_GPL(cpu_set_feature);
2867
cpu_have_feature(unsigned int num)2868 bool cpu_have_feature(unsigned int num)
2869 {
2870 WARN_ON(num >= MAX_CPU_FEATURES);
2871 return elf_hwcap & BIT(num);
2872 }
2873 EXPORT_SYMBOL_GPL(cpu_have_feature);
2874
cpu_get_elf_hwcap(void)2875 unsigned long cpu_get_elf_hwcap(void)
2876 {
2877 /*
2878 * We currently only populate the first 32 bits of AT_HWCAP. Please
2879 * note that for userspace compatibility we guarantee that bits 62
2880 * and 63 will always be returned as 0.
2881 */
2882 return lower_32_bits(elf_hwcap);
2883 }
2884
cpu_get_elf_hwcap2(void)2885 unsigned long cpu_get_elf_hwcap2(void)
2886 {
2887 return upper_32_bits(elf_hwcap);
2888 }
2889
setup_system_capabilities(void)2890 static void __init setup_system_capabilities(void)
2891 {
2892 /*
2893 * We have finalised the system-wide safe feature
2894 * registers, finalise the capabilities that depend
2895 * on it. Also enable all the available capabilities,
2896 * that are not enabled already.
2897 */
2898 update_cpu_capabilities(SCOPE_SYSTEM);
2899 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2900 }
2901
setup_cpu_features(void)2902 void __init setup_cpu_features(void)
2903 {
2904 u32 cwg;
2905
2906 setup_system_capabilities();
2907 setup_elf_hwcaps(arm64_elf_hwcaps);
2908
2909 if (system_supports_32bit_el0())
2910 setup_elf_hwcaps(compat_elf_hwcaps);
2911
2912 if (system_uses_ttbr0_pan())
2913 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2914
2915 sve_setup();
2916 minsigstksz_setup();
2917
2918 /* Advertise that we have computed the system capabilities */
2919 finalize_system_capabilities();
2920
2921 /*
2922 * Check for sane CTR_EL0.CWG value.
2923 */
2924 cwg = cache_type_cwg();
2925 if (!cwg)
2926 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2927 ARCH_DMA_MINALIGN);
2928 }
2929
enable_mismatched_32bit_el0(unsigned int cpu)2930 static int enable_mismatched_32bit_el0(unsigned int cpu)
2931 {
2932 /*
2933 * The first 32-bit-capable CPU we detected and so can no longer
2934 * be offlined by userspace. -1 indicates we haven't yet onlined
2935 * a 32-bit-capable CPU.
2936 */
2937 static int lucky_winner = -1;
2938
2939 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
2940 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0);
2941
2942 if (cpu_32bit) {
2943 cpumask_set_cpu(cpu, cpu_32bit_el0_mask);
2944 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0);
2945 }
2946
2947 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit)
2948 return 0;
2949
2950 if (lucky_winner >= 0)
2951 return 0;
2952
2953 /*
2954 * We've detected a mismatch. We need to keep one of our CPUs with
2955 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting
2956 * every CPU in the system for a 32-bit task.
2957 */
2958 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask,
2959 cpu_active_mask);
2960 get_cpu_device(lucky_winner)->offline_disabled = true;
2961 setup_elf_hwcaps(compat_elf_hwcaps);
2962 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n",
2963 cpu, lucky_winner);
2964 return 0;
2965 }
2966
init_32bit_el0_mask(void)2967 static int __init init_32bit_el0_mask(void)
2968 {
2969 if (!allow_mismatched_32bit_el0)
2970 return 0;
2971
2972 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL))
2973 return -ENOMEM;
2974
2975 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
2976 "arm64/mismatched_32bit_el0:online",
2977 enable_mismatched_32bit_el0, NULL);
2978 }
2979 subsys_initcall_sync(init_32bit_el0_mask);
2980
cpu_enable_cnp(struct arm64_cpu_capabilities const * cap)2981 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2982 {
2983 cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2984 }
2985
2986 /*
2987 * We emulate only the following system register space.
2988 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2989 * See Table C5-6 System instruction encodings for System register accesses,
2990 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2991 */
is_emulated(u32 id)2992 static inline bool __attribute_const__ is_emulated(u32 id)
2993 {
2994 return (sys_reg_Op0(id) == 0x3 &&
2995 sys_reg_CRn(id) == 0x0 &&
2996 sys_reg_Op1(id) == 0x0 &&
2997 (sys_reg_CRm(id) == 0 ||
2998 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2999 }
3000
3001 /*
3002 * With CRm == 0, reg should be one of :
3003 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
3004 */
emulate_id_reg(u32 id,u64 * valp)3005 static inline int emulate_id_reg(u32 id, u64 *valp)
3006 {
3007 switch (id) {
3008 case SYS_MIDR_EL1:
3009 *valp = read_cpuid_id();
3010 break;
3011 case SYS_MPIDR_EL1:
3012 *valp = SYS_MPIDR_SAFE_VAL;
3013 break;
3014 case SYS_REVIDR_EL1:
3015 /* IMPLEMENTATION DEFINED values are emulated with 0 */
3016 *valp = 0;
3017 break;
3018 default:
3019 return -EINVAL;
3020 }
3021
3022 return 0;
3023 }
3024
emulate_sys_reg(u32 id,u64 * valp)3025 static int emulate_sys_reg(u32 id, u64 *valp)
3026 {
3027 struct arm64_ftr_reg *regp;
3028
3029 if (!is_emulated(id))
3030 return -EINVAL;
3031
3032 if (sys_reg_CRm(id) == 0)
3033 return emulate_id_reg(id, valp);
3034
3035 regp = get_arm64_ftr_reg_nowarn(id);
3036 if (regp)
3037 *valp = arm64_ftr_reg_user_value(regp);
3038 else
3039 /*
3040 * The untracked registers are either IMPLEMENTATION DEFINED
3041 * (e.g, ID_AFR0_EL1) or reserved RAZ.
3042 */
3043 *valp = 0;
3044 return 0;
3045 }
3046
do_emulate_mrs(struct pt_regs * regs,u32 sys_reg,u32 rt)3047 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
3048 {
3049 int rc;
3050 u64 val;
3051
3052 rc = emulate_sys_reg(sys_reg, &val);
3053 if (!rc) {
3054 pt_regs_write_reg(regs, rt, val);
3055 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
3056 }
3057 return rc;
3058 }
3059
try_emulate_mrs(struct pt_regs * regs,u32 insn)3060 bool try_emulate_mrs(struct pt_regs *regs, u32 insn)
3061 {
3062 u32 sys_reg, rt;
3063
3064 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn))
3065 return false;
3066
3067 /*
3068 * sys_reg values are defined as used in mrs/msr instruction.
3069 * shift the imm value to get the encoding.
3070 */
3071 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
3072 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
3073 return do_emulate_mrs(regs, sys_reg, rt) == 0;
3074 }
3075
arm64_get_meltdown_state(void)3076 enum mitigation_state arm64_get_meltdown_state(void)
3077 {
3078 if (__meltdown_safe)
3079 return SPECTRE_UNAFFECTED;
3080
3081 if (arm64_kernel_unmapped_at_el0())
3082 return SPECTRE_MITIGATED;
3083
3084 return SPECTRE_VULNERABLE;
3085 }
3086
cpu_show_meltdown(struct device * dev,struct device_attribute * attr,char * buf)3087 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
3088 char *buf)
3089 {
3090 switch (arm64_get_meltdown_state()) {
3091 case SPECTRE_UNAFFECTED:
3092 return sprintf(buf, "Not affected\n");
3093
3094 case SPECTRE_MITIGATED:
3095 return sprintf(buf, "Mitigation: PTI\n");
3096
3097 default:
3098 return sprintf(buf, "Vulnerable\n");
3099 }
3100 }
3101