1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Hantro VPU codec driver
4 *
5 * Copyright (C) 2019 Pengutronix, Philipp Zabel <kernel@pengutronix.de>
6 */
7
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10
11 #include "hantro.h"
12 #include "hantro_jpeg.h"
13 #include "hantro_g1_regs.h"
14 #include "hantro_g2_regs.h"
15
16 #define CTRL_SOFT_RESET 0x00
17 #define RESET_G1 BIT(1)
18 #define RESET_G2 BIT(0)
19
20 #define CTRL_CLOCK_ENABLE 0x04
21 #define CLOCK_G1 BIT(1)
22 #define CLOCK_G2 BIT(0)
23
24 #define CTRL_G1_DEC_FUSE 0x08
25 #define CTRL_G1_PP_FUSE 0x0c
26 #define CTRL_G2_DEC_FUSE 0x10
27
imx8m_soft_reset(struct hantro_dev * vpu,u32 reset_bits)28 static void imx8m_soft_reset(struct hantro_dev *vpu, u32 reset_bits)
29 {
30 u32 val;
31
32 /* Assert */
33 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET);
34 val &= ~reset_bits;
35 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET);
36
37 udelay(2);
38
39 /* Release */
40 val = readl(vpu->ctrl_base + CTRL_SOFT_RESET);
41 val |= reset_bits;
42 writel(val, vpu->ctrl_base + CTRL_SOFT_RESET);
43 }
44
imx8m_clk_enable(struct hantro_dev * vpu,u32 clock_bits)45 static void imx8m_clk_enable(struct hantro_dev *vpu, u32 clock_bits)
46 {
47 u32 val;
48
49 val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE);
50 val |= clock_bits;
51 writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE);
52 }
53
imx8mq_runtime_resume(struct hantro_dev * vpu)54 static int imx8mq_runtime_resume(struct hantro_dev *vpu)
55 {
56 int ret;
57
58 ret = clk_bulk_prepare_enable(vpu->variant->num_clocks, vpu->clocks);
59 if (ret) {
60 dev_err(vpu->dev, "Failed to enable clocks\n");
61 return ret;
62 }
63
64 imx8m_soft_reset(vpu, RESET_G1 | RESET_G2);
65 imx8m_clk_enable(vpu, CLOCK_G1 | CLOCK_G2);
66
67 /* Set values of the fuse registers */
68 writel(0xffffffff, vpu->ctrl_base + CTRL_G1_DEC_FUSE);
69 writel(0xffffffff, vpu->ctrl_base + CTRL_G1_PP_FUSE);
70 writel(0xffffffff, vpu->ctrl_base + CTRL_G2_DEC_FUSE);
71
72 clk_bulk_disable_unprepare(vpu->variant->num_clocks, vpu->clocks);
73
74 return 0;
75 }
76
77 /*
78 * Supported formats.
79 */
80
81 static const struct hantro_fmt imx8m_vpu_postproc_fmts[] = {
82 {
83 .fourcc = V4L2_PIX_FMT_YUYV,
84 .codec_mode = HANTRO_MODE_NONE,
85 .postprocessed = true,
86 },
87 };
88
89 static const struct hantro_fmt imx8m_vpu_dec_fmts[] = {
90 {
91 .fourcc = V4L2_PIX_FMT_NV12,
92 .codec_mode = HANTRO_MODE_NONE,
93 },
94 {
95 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
96 .codec_mode = HANTRO_MODE_MPEG2_DEC,
97 .max_depth = 2,
98 .frmsize = {
99 .min_width = 48,
100 .max_width = 1920,
101 .step_width = MB_DIM,
102 .min_height = 48,
103 .max_height = 1088,
104 .step_height = MB_DIM,
105 },
106 },
107 {
108 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
109 .codec_mode = HANTRO_MODE_VP8_DEC,
110 .max_depth = 2,
111 .frmsize = {
112 .min_width = 48,
113 .max_width = 3840,
114 .step_width = MB_DIM,
115 .min_height = 48,
116 .max_height = 2160,
117 .step_height = MB_DIM,
118 },
119 },
120 {
121 .fourcc = V4L2_PIX_FMT_H264_SLICE,
122 .codec_mode = HANTRO_MODE_H264_DEC,
123 .max_depth = 2,
124 .frmsize = {
125 .min_width = 48,
126 .max_width = 3840,
127 .step_width = MB_DIM,
128 .min_height = 48,
129 .max_height = 2160,
130 .step_height = MB_DIM,
131 },
132 },
133 };
134
135 static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = {
136 {
137 .fourcc = V4L2_PIX_FMT_NV12,
138 .codec_mode = HANTRO_MODE_NONE,
139 },
140 {
141 .fourcc = V4L2_PIX_FMT_HEVC_SLICE,
142 .codec_mode = HANTRO_MODE_HEVC_DEC,
143 .max_depth = 2,
144 .frmsize = {
145 .min_width = 48,
146 .max_width = 3840,
147 .step_width = MB_DIM,
148 .min_height = 48,
149 .max_height = 2160,
150 .step_height = MB_DIM,
151 },
152 },
153 };
154
imx8m_vpu_g1_irq(int irq,void * dev_id)155 static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id)
156 {
157 struct hantro_dev *vpu = dev_id;
158 enum vb2_buffer_state state;
159 u32 status;
160
161 status = vdpu_read(vpu, G1_REG_INTERRUPT);
162 state = (status & G1_REG_INTERRUPT_DEC_RDY_INT) ?
163 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
164
165 vdpu_write(vpu, 0, G1_REG_INTERRUPT);
166 vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);
167
168 hantro_irq_done(vpu, state);
169
170 return IRQ_HANDLED;
171 }
172
imx8m_vpu_g2_irq(int irq,void * dev_id)173 static irqreturn_t imx8m_vpu_g2_irq(int irq, void *dev_id)
174 {
175 struct hantro_dev *vpu = dev_id;
176 enum vb2_buffer_state state;
177 u32 status;
178
179 status = vdpu_read(vpu, G2_REG_INTERRUPT);
180 state = (status & G2_REG_INTERRUPT_DEC_RDY_INT) ?
181 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
182
183 vdpu_write(vpu, 0, G2_REG_INTERRUPT);
184 vdpu_write(vpu, G2_REG_CONFIG_DEC_CLK_GATE_E, G2_REG_CONFIG);
185
186 hantro_irq_done(vpu, state);
187
188 return IRQ_HANDLED;
189 }
190
imx8mq_vpu_hw_init(struct hantro_dev * vpu)191 static int imx8mq_vpu_hw_init(struct hantro_dev *vpu)
192 {
193 vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1];
194
195 return 0;
196 }
197
imx8m_vpu_g1_reset(struct hantro_ctx * ctx)198 static void imx8m_vpu_g1_reset(struct hantro_ctx *ctx)
199 {
200 struct hantro_dev *vpu = ctx->dev;
201
202 imx8m_soft_reset(vpu, RESET_G1);
203 }
204
imx8m_vpu_g2_reset(struct hantro_ctx * ctx)205 static void imx8m_vpu_g2_reset(struct hantro_ctx *ctx)
206 {
207 struct hantro_dev *vpu = ctx->dev;
208
209 imx8m_soft_reset(vpu, RESET_G2);
210 }
211
212 /*
213 * Supported codec ops.
214 */
215
216 static const struct hantro_codec_ops imx8mq_vpu_codec_ops[] = {
217 [HANTRO_MODE_MPEG2_DEC] = {
218 .run = hantro_g1_mpeg2_dec_run,
219 .reset = imx8m_vpu_g1_reset,
220 .init = hantro_mpeg2_dec_init,
221 .exit = hantro_mpeg2_dec_exit,
222 },
223 [HANTRO_MODE_VP8_DEC] = {
224 .run = hantro_g1_vp8_dec_run,
225 .reset = imx8m_vpu_g1_reset,
226 .init = hantro_vp8_dec_init,
227 .exit = hantro_vp8_dec_exit,
228 },
229 [HANTRO_MODE_H264_DEC] = {
230 .run = hantro_g1_h264_dec_run,
231 .reset = imx8m_vpu_g1_reset,
232 .init = hantro_h264_dec_init,
233 .exit = hantro_h264_dec_exit,
234 },
235 };
236
237 static const struct hantro_codec_ops imx8mq_vpu_g2_codec_ops[] = {
238 [HANTRO_MODE_HEVC_DEC] = {
239 .run = hantro_g2_hevc_dec_run,
240 .reset = imx8m_vpu_g2_reset,
241 .init = hantro_hevc_dec_init,
242 .exit = hantro_hevc_dec_exit,
243 },
244 };
245
246 /*
247 * VPU variants.
248 */
249
250 static const struct hantro_irq imx8mq_irqs[] = {
251 { "g1", imx8m_vpu_g1_irq },
252 };
253
254 static const struct hantro_irq imx8mq_g2_irqs[] = {
255 { "g2", imx8m_vpu_g2_irq },
256 };
257
258 static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus" };
259 static const char * const imx8mq_reg_names[] = { "g1", "g2", "ctrl" };
260
261 const struct hantro_variant imx8mq_vpu_variant = {
262 .dec_fmts = imx8m_vpu_dec_fmts,
263 .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts),
264 .postproc_fmts = imx8m_vpu_postproc_fmts,
265 .num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_postproc_fmts),
266 .postproc_regs = &hantro_g1_postproc_regs,
267 .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
268 HANTRO_H264_DECODER,
269 .codec_ops = imx8mq_vpu_codec_ops,
270 .init = imx8mq_vpu_hw_init,
271 .runtime_resume = imx8mq_runtime_resume,
272 .irqs = imx8mq_irqs,
273 .num_irqs = ARRAY_SIZE(imx8mq_irqs),
274 .clk_names = imx8mq_clk_names,
275 .num_clocks = ARRAY_SIZE(imx8mq_clk_names),
276 .reg_names = imx8mq_reg_names,
277 .num_regs = ARRAY_SIZE(imx8mq_reg_names)
278 };
279
280 const struct hantro_variant imx8mq_vpu_g2_variant = {
281 .dec_offset = 0x0,
282 .dec_fmts = imx8m_vpu_g2_dec_fmts,
283 .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_g2_dec_fmts),
284 .codec = HANTRO_HEVC_DECODER,
285 .codec_ops = imx8mq_vpu_g2_codec_ops,
286 .init = imx8mq_vpu_hw_init,
287 .runtime_resume = imx8mq_runtime_resume,
288 .irqs = imx8mq_g2_irqs,
289 .num_irqs = ARRAY_SIZE(imx8mq_g2_irqs),
290 .clk_names = imx8mq_clk_names,
291 .num_clocks = ARRAY_SIZE(imx8mq_clk_names),
292 };
293