1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright 2018-2021 NXP
4 * Dong Aisheng <aisheng.dong@nxp.com>
5 */
6
7 #ifndef __IMX_CLK_SCU_H
8 #define __IMX_CLK_SCU_H
9
10 #include <linux/firmware/imx/sci.h>
11 #include <linux/of.h>
12
13 #define IMX_SCU_GPR_CLK_GATE BIT(0)
14 #define IMX_SCU_GPR_CLK_DIV BIT(1)
15 #define IMX_SCU_GPR_CLK_MUX BIT(2)
16
17 struct imx_clk_scu_rsrc_table {
18 const u32 *rsrc;
19 u8 num;
20 };
21
22 extern struct list_head imx_scu_clks[];
23 extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops;
24 extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp;
25 extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm;
26
27 int imx_clk_scu_init(struct device_node *np,
28 const struct imx_clk_scu_rsrc_table *data);
29 struct clk_hw *imx_scu_of_clk_src_get(struct of_phandle_args *clkspec,
30 void *data);
31 struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
32 const char * const *parents,
33 int num_parents, u32 rsrc_id, u8 clk_type);
34
35 struct clk_hw *__imx_clk_scu(struct device *dev, const char *name,
36 const char * const *parents, int num_parents,
37 u32 rsrc_id, u8 clk_type);
38
39 void imx_clk_scu_unregister(void);
40
41 struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name,
42 const char *parent_name, unsigned long flags,
43 void __iomem *reg, u8 bit_idx, bool hw_gate);
44 void imx_clk_lpcg_scu_unregister(struct clk_hw *hw);
45
46 struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
47 int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
48 bool invert);
49
imx_clk_scu(const char * name,u32 rsrc_id,u8 clk_type)50 static inline struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id,
51 u8 clk_type)
52 {
53 return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type);
54 }
55
imx_clk_scu2(const char * name,const char * const * parents,int num_parents,u32 rsrc_id,u8 clk_type)56 static inline struct clk_hw *imx_clk_scu2(const char *name, const char * const *parents,
57 int num_parents, u32 rsrc_id, u8 clk_type)
58 {
59 return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type);
60 }
61
imx_clk_lpcg_scu_dev(struct device * dev,const char * name,const char * parent_name,unsigned long flags,void __iomem * reg,u8 bit_idx,bool hw_gate)62 static inline struct clk_hw *imx_clk_lpcg_scu_dev(struct device *dev, const char *name,
63 const char *parent_name, unsigned long flags,
64 void __iomem *reg, u8 bit_idx, bool hw_gate)
65 {
66 return __imx_clk_lpcg_scu(dev, name, parent_name, flags, reg,
67 bit_idx, hw_gate);
68 }
69
imx_clk_lpcg_scu(const char * name,const char * parent_name,unsigned long flags,void __iomem * reg,u8 bit_idx,bool hw_gate)70 static inline struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *parent_name,
71 unsigned long flags, void __iomem *reg,
72 u8 bit_idx, bool hw_gate)
73 {
74 return __imx_clk_lpcg_scu(NULL, name, parent_name, flags, reg,
75 bit_idx, hw_gate);
76 }
77
imx_clk_gate_gpr_scu(const char * name,const char * parent_name,u32 rsrc_id,u8 gpr_id,bool invert)78 static inline struct clk_hw *imx_clk_gate_gpr_scu(const char *name, const char *parent_name,
79 u32 rsrc_id, u8 gpr_id, bool invert)
80 {
81 return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
82 IMX_SCU_GPR_CLK_GATE, invert);
83 }
84
imx_clk_divider_gpr_scu(const char * name,const char * parent_name,u32 rsrc_id,u8 gpr_id)85 static inline struct clk_hw *imx_clk_divider_gpr_scu(const char *name, const char *parent_name,
86 u32 rsrc_id, u8 gpr_id)
87 {
88 return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
89 IMX_SCU_GPR_CLK_DIV, 0);
90 }
91
imx_clk_mux_gpr_scu(const char * name,const char * const * parent_names,int num_parents,u32 rsrc_id,u8 gpr_id)92 static inline struct clk_hw *imx_clk_mux_gpr_scu(const char *name, const char * const *parent_names,
93 int num_parents, u32 rsrc_id, u8 gpr_id)
94 {
95 return __imx_clk_gpr_scu(name, parent_names, num_parents, rsrc_id,
96 gpr_id, IMX_SCU_GPR_CLK_MUX, 0);
97 }
98 #endif
99