1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25
26 #ifndef __INTEL_DISPLAY_TYPES_H__
27 #define __INTEL_DISPLAY_TYPES_H__
28
29 #include <linux/async.h>
30 #include <linux/i2c.h>
31 #include <linux/pwm.h>
32 #include <linux/sched/clock.h>
33
34 #include <drm/drm_atomic.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_dp_dual_mode_helper.h>
37 #include <drm/drm_dp_mst_helper.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_fb_helper.h>
40 #include <drm/drm_fourcc.h>
41 #include <drm/drm_probe_helper.h>
42 #include <drm/drm_rect.h>
43 #include <drm/drm_vblank.h>
44 #include <drm/i915_mei_hdcp_interface.h>
45 #include <media/cec-notifier.h>
46
47 #include "i915_drv.h"
48
49 struct drm_printer;
50 struct __intel_global_objs_state;
51 struct intel_ddi_buf_trans;
52
53 /*
54 * Display related stuff
55 */
56
57 /* these are outputs from the chip - integrated only
58 external chips are via DVO or SDVO output */
59 enum intel_output_type {
60 INTEL_OUTPUT_UNUSED = 0,
61 INTEL_OUTPUT_ANALOG = 1,
62 INTEL_OUTPUT_DVO = 2,
63 INTEL_OUTPUT_SDVO = 3,
64 INTEL_OUTPUT_LVDS = 4,
65 INTEL_OUTPUT_TVOUT = 5,
66 INTEL_OUTPUT_HDMI = 6,
67 INTEL_OUTPUT_DP = 7,
68 INTEL_OUTPUT_EDP = 8,
69 INTEL_OUTPUT_DSI = 9,
70 INTEL_OUTPUT_DDI = 10,
71 INTEL_OUTPUT_DP_MST = 11,
72 };
73
74 enum hdmi_force_audio {
75 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
76 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
77 HDMI_AUDIO_AUTO, /* trust EDID */
78 HDMI_AUDIO_ON, /* force turn on HDMI audio */
79 };
80
81 /* "Broadcast RGB" property */
82 enum intel_broadcast_rgb {
83 INTEL_BROADCAST_RGB_AUTO,
84 INTEL_BROADCAST_RGB_FULL,
85 INTEL_BROADCAST_RGB_LIMITED,
86 };
87
88 struct intel_fb_view {
89 /*
90 * The remap information used in the remapped and rotated views to
91 * create the DMA scatter-gather list for each FB color plane. This sg
92 * list is created along with the view type (gtt.type) specific
93 * i915_vma object and contains the list of FB object pages (reordered
94 * in the rotated view) that are visible in the view.
95 * In the normal view the FB object's backing store sg list is used
96 * directly and hence the remap information here is not used.
97 */
98 struct i915_ggtt_view gtt;
99
100 /*
101 * The GTT view (gtt.type) specific information for each FB color
102 * plane. In the normal GTT view all formats (up to 4 color planes),
103 * in the rotated and remapped GTT view all no-CCS formats (up to 2
104 * color planes) are supported.
105 *
106 * TODO: add support for CCS formats in the remapped GTT view.
107 *
108 * The view information shared by all FB color planes in the FB,
109 * like dst x/y and src/dst width, is stored separately in
110 * intel_plane_state.
111 */
112 struct i915_color_plane_view {
113 u32 offset;
114 unsigned int x, y;
115 /*
116 * Plane stride in:
117 * bytes for 0/180 degree rotation
118 * pixels for 90/270 degree rotation
119 */
120 unsigned int stride;
121 } color_plane[4];
122 };
123
124 struct intel_framebuffer {
125 struct drm_framebuffer base;
126 struct intel_frontbuffer *frontbuffer;
127
128 /* Params to remap the FB pages and program the plane registers in each view. */
129 struct intel_fb_view normal_view;
130 union {
131 struct intel_fb_view rotated_view;
132 struct intel_fb_view remapped_view;
133 };
134
135 struct i915_address_space *dpt_vm;
136 };
137
138 struct intel_fbdev {
139 struct drm_fb_helper helper;
140 struct intel_framebuffer *fb;
141 struct i915_vma *vma;
142 unsigned long vma_flags;
143 async_cookie_t cookie;
144 int preferred_bpp;
145
146 /* Whether or not fbdev hpd processing is temporarily suspended */
147 bool hpd_suspended : 1;
148 /* Set when a hotplug was received while HPD processing was
149 * suspended
150 */
151 bool hpd_waiting : 1;
152
153 /* Protects hpd_suspended */
154 struct mutex hpd_lock;
155 };
156
157 enum intel_hotplug_state {
158 INTEL_HOTPLUG_UNCHANGED,
159 INTEL_HOTPLUG_CHANGED,
160 INTEL_HOTPLUG_RETRY,
161 };
162
163 struct intel_encoder {
164 struct drm_encoder base;
165
166 enum intel_output_type type;
167 enum port port;
168 u16 cloneable;
169 u8 pipe_mask;
170 enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder,
171 struct intel_connector *connector);
172 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
173 struct intel_crtc_state *,
174 struct drm_connector_state *);
175 int (*compute_config)(struct intel_encoder *,
176 struct intel_crtc_state *,
177 struct drm_connector_state *);
178 int (*compute_config_late)(struct intel_encoder *,
179 struct intel_crtc_state *,
180 struct drm_connector_state *);
181 void (*update_prepare)(struct intel_atomic_state *,
182 struct intel_encoder *,
183 struct intel_crtc *);
184 void (*pre_pll_enable)(struct intel_atomic_state *,
185 struct intel_encoder *,
186 const struct intel_crtc_state *,
187 const struct drm_connector_state *);
188 void (*pre_enable)(struct intel_atomic_state *,
189 struct intel_encoder *,
190 const struct intel_crtc_state *,
191 const struct drm_connector_state *);
192 void (*enable)(struct intel_atomic_state *,
193 struct intel_encoder *,
194 const struct intel_crtc_state *,
195 const struct drm_connector_state *);
196 void (*update_complete)(struct intel_atomic_state *,
197 struct intel_encoder *,
198 struct intel_crtc *);
199 void (*pre_disable)(struct intel_atomic_state *,
200 struct intel_encoder *,
201 const struct intel_crtc_state *,
202 const struct drm_connector_state *);
203 void (*disable)(struct intel_atomic_state *,
204 struct intel_encoder *,
205 const struct intel_crtc_state *,
206 const struct drm_connector_state *);
207 void (*post_disable)(struct intel_atomic_state *,
208 struct intel_encoder *,
209 const struct intel_crtc_state *,
210 const struct drm_connector_state *);
211 void (*post_pll_disable)(struct intel_atomic_state *,
212 struct intel_encoder *,
213 const struct intel_crtc_state *,
214 const struct drm_connector_state *);
215 void (*update_pipe)(struct intel_atomic_state *,
216 struct intel_encoder *,
217 const struct intel_crtc_state *,
218 const struct drm_connector_state *);
219 /* Read out the current hw state of this connector, returning true if
220 * the encoder is active. If the encoder is enabled it also set the pipe
221 * it is connected to in the pipe parameter. */
222 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
223 /* Reconstructs the equivalent mode flags for the current hardware
224 * state. This must be called _after_ display->get_pipe_config has
225 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
226 * be set correctly before calling this function. */
227 void (*get_config)(struct intel_encoder *,
228 struct intel_crtc_state *pipe_config);
229
230 /*
231 * Optional hook called during init/resume to sync any state
232 * stored in the encoder (eg. DP link parameters) wrt. the HW state.
233 */
234 void (*sync_state)(struct intel_encoder *encoder,
235 const struct intel_crtc_state *crtc_state);
236
237 /*
238 * Optional hook, returning true if this encoder allows a fastset
239 * during the initial commit, false otherwise.
240 */
241 bool (*initial_fastset_check)(struct intel_encoder *encoder,
242 struct intel_crtc_state *crtc_state);
243
244 /*
245 * Acquires the power domains needed for an active encoder during
246 * hardware state readout.
247 */
248 void (*get_power_domains)(struct intel_encoder *encoder,
249 struct intel_crtc_state *crtc_state);
250 /*
251 * Called during system suspend after all pending requests for the
252 * encoder are flushed (for example for DP AUX transactions) and
253 * device interrupts are disabled.
254 */
255 void (*suspend)(struct intel_encoder *);
256 /*
257 * Called during system reboot/shutdown after all the
258 * encoders have been disabled and suspended.
259 */
260 void (*shutdown)(struct intel_encoder *encoder);
261 /*
262 * Enable/disable the clock to the port.
263 */
264 void (*enable_clock)(struct intel_encoder *encoder,
265 const struct intel_crtc_state *crtc_state);
266 void (*disable_clock)(struct intel_encoder *encoder);
267 /*
268 * Returns whether the port clock is enabled or not.
269 */
270 bool (*is_clock_enabled)(struct intel_encoder *encoder);
271 const struct intel_ddi_buf_trans *(*get_buf_trans)(struct intel_encoder *encoder,
272 const struct intel_crtc_state *crtc_state,
273 int *n_entries);
274 enum hpd_pin hpd_pin;
275 enum intel_display_power_domain power_domain;
276 /* for communication with audio component; protected by av_mutex */
277 const struct drm_connector *audio_connector;
278
279 /* VBT information for this encoder (may be NULL for older platforms) */
280 const struct intel_bios_encoder_data *devdata;
281 };
282
283 struct intel_panel_bl_funcs {
284 /* Connector and platform specific backlight functions */
285 int (*setup)(struct intel_connector *connector, enum pipe pipe);
286 u32 (*get)(struct intel_connector *connector, enum pipe pipe);
287 void (*set)(const struct drm_connector_state *conn_state, u32 level);
288 void (*disable)(const struct drm_connector_state *conn_state, u32 level);
289 void (*enable)(const struct intel_crtc_state *crtc_state,
290 const struct drm_connector_state *conn_state, u32 level);
291 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz);
292 };
293
294 struct intel_panel {
295 struct drm_display_mode *fixed_mode;
296 struct drm_display_mode *downclock_mode;
297
298 /* backlight */
299 struct {
300 bool present;
301 u32 level;
302 u32 min;
303 u32 max;
304 bool enabled;
305 bool combination_mode; /* gen 2/4 only */
306 bool active_low_pwm;
307 bool alternate_pwm_increment; /* lpt+ */
308
309 /* PWM chip */
310 u32 pwm_level_min;
311 u32 pwm_level_max;
312 bool pwm_enabled;
313 bool util_pin_active_low; /* bxt+ */
314 u8 controller; /* bxt+ only */
315 struct pwm_device *pwm;
316 struct pwm_state pwm_state;
317
318 /* DPCD backlight */
319 union {
320 struct {
321 struct drm_edp_backlight_info info;
322 } vesa;
323 struct {
324 bool sdr_uses_aux;
325 } intel;
326 } edp;
327
328 struct backlight_device *device;
329
330 const struct intel_panel_bl_funcs *funcs;
331 const struct intel_panel_bl_funcs *pwm_funcs;
332 void (*power)(struct intel_connector *, bool enable);
333 } backlight;
334 };
335
336 struct intel_digital_port;
337
338 enum check_link_response {
339 HDCP_LINK_PROTECTED = 0,
340 HDCP_TOPOLOGY_CHANGE,
341 HDCP_LINK_INTEGRITY_FAILURE,
342 HDCP_REAUTH_REQUEST
343 };
344
345 /*
346 * This structure serves as a translation layer between the generic HDCP code
347 * and the bus-specific code. What that means is that HDCP over HDMI differs
348 * from HDCP over DP, so to account for these differences, we need to
349 * communicate with the receiver through this shim.
350 *
351 * For completeness, the 2 buses differ in the following ways:
352 * - DP AUX vs. DDC
353 * HDCP registers on the receiver are set via DP AUX for DP, and
354 * they are set via DDC for HDMI.
355 * - Receiver register offsets
356 * The offsets of the registers are different for DP vs. HDMI
357 * - Receiver register masks/offsets
358 * For instance, the ready bit for the KSV fifo is in a different
359 * place on DP vs HDMI
360 * - Receiver register names
361 * Seriously. In the DP spec, the 16-bit register containing
362 * downstream information is called BINFO, on HDMI it's called
363 * BSTATUS. To confuse matters further, DP has a BSTATUS register
364 * with a completely different definition.
365 * - KSV FIFO
366 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
367 * be read 3 keys at a time
368 * - Aksv output
369 * Since Aksv is hidden in hardware, there's different procedures
370 * to send it over DP AUX vs DDC
371 */
372 struct intel_hdcp_shim {
373 /* Outputs the transmitter's An and Aksv values to the receiver. */
374 int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an);
375
376 /* Reads the receiver's key selection vector */
377 int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv);
378
379 /*
380 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
381 * definitions are the same in the respective specs, but the names are
382 * different. Call it BSTATUS since that's the name the HDMI spec
383 * uses and it was there first.
384 */
385 int (*read_bstatus)(struct intel_digital_port *dig_port,
386 u8 *bstatus);
387
388 /* Determines whether a repeater is present downstream */
389 int (*repeater_present)(struct intel_digital_port *dig_port,
390 bool *repeater_present);
391
392 /* Reads the receiver's Ri' value */
393 int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri);
394
395 /* Determines if the receiver's KSV FIFO is ready for consumption */
396 int (*read_ksv_ready)(struct intel_digital_port *dig_port,
397 bool *ksv_ready);
398
399 /* Reads the ksv fifo for num_downstream devices */
400 int (*read_ksv_fifo)(struct intel_digital_port *dig_port,
401 int num_downstream, u8 *ksv_fifo);
402
403 /* Reads a 32-bit part of V' from the receiver */
404 int (*read_v_prime_part)(struct intel_digital_port *dig_port,
405 int i, u32 *part);
406
407 /* Enables HDCP signalling on the port */
408 int (*toggle_signalling)(struct intel_digital_port *dig_port,
409 enum transcoder cpu_transcoder,
410 bool enable);
411
412 /* Enable/Disable stream encryption on DP MST Transport Link */
413 int (*stream_encryption)(struct intel_connector *connector,
414 bool enable);
415
416 /* Ensures the link is still protected */
417 bool (*check_link)(struct intel_digital_port *dig_port,
418 struct intel_connector *connector);
419
420 /* Detects panel's hdcp capability. This is optional for HDMI. */
421 int (*hdcp_capable)(struct intel_digital_port *dig_port,
422 bool *hdcp_capable);
423
424 /* HDCP adaptation(DP/HDMI) required on the port */
425 enum hdcp_wired_protocol protocol;
426
427 /* Detects whether sink is HDCP2.2 capable */
428 int (*hdcp_2_2_capable)(struct intel_digital_port *dig_port,
429 bool *capable);
430
431 /* Detects whether a HDCP 1.4 sink connected in MST topology */
432 int (*streams_type1_capable)(struct intel_connector *connector,
433 bool *capable);
434
435 /* Write HDCP2.2 messages */
436 int (*write_2_2_msg)(struct intel_digital_port *dig_port,
437 void *buf, size_t size);
438
439 /* Read HDCP2.2 messages */
440 int (*read_2_2_msg)(struct intel_digital_port *dig_port,
441 u8 msg_id, void *buf, size_t size);
442
443 /*
444 * Implementation of DP HDCP2.2 Errata for the communication of stream
445 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
446 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
447 */
448 int (*config_stream_type)(struct intel_digital_port *dig_port,
449 bool is_repeater, u8 type);
450
451 /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
452 int (*stream_2_2_encryption)(struct intel_connector *connector,
453 bool enable);
454
455 /* HDCP2.2 Link Integrity Check */
456 int (*check_2_2_link)(struct intel_digital_port *dig_port,
457 struct intel_connector *connector);
458 };
459
460 struct intel_hdcp {
461 const struct intel_hdcp_shim *shim;
462 /* Mutex for hdcp state of the connector */
463 struct mutex mutex;
464 u64 value;
465 struct delayed_work check_work;
466 struct work_struct prop_work;
467
468 /* HDCP1.4 Encryption status */
469 bool hdcp_encrypted;
470
471 /* HDCP2.2 related definitions */
472 /* Flag indicates whether this connector supports HDCP2.2 or not. */
473 bool hdcp2_supported;
474
475 /* HDCP2.2 Encryption status */
476 bool hdcp2_encrypted;
477
478 /*
479 * Content Stream Type defined by content owner. TYPE0(0x0) content can
480 * flow in the link protected by HDCP2.2 or HDCP1.4, where as TYPE1(0x1)
481 * content can flow only through a link protected by HDCP2.2.
482 */
483 u8 content_type;
484
485 bool is_paired;
486 bool is_repeater;
487
488 /*
489 * Count of ReceiverID_List received. Initialized to 0 at AKE_INIT.
490 * Incremented after processing the RepeaterAuth_Send_ReceiverID_List.
491 * When it rolls over re-auth has to be triggered.
492 */
493 u32 seq_num_v;
494
495 /*
496 * Count of RepeaterAuth_Stream_Manage msg propagated.
497 * Initialized to 0 on AKE_INIT. Incremented after every successful
498 * transmission of RepeaterAuth_Stream_Manage message. When it rolls
499 * over re-Auth has to be triggered.
500 */
501 u32 seq_num_m;
502
503 /*
504 * Work queue to signal the CP_IRQ. Used for the waiters to read the
505 * available information from HDCP DP sink.
506 */
507 wait_queue_head_t cp_irq_queue;
508 atomic_t cp_irq_count;
509 int cp_irq_count_cached;
510
511 /*
512 * HDCP register access for gen12+ need the transcoder associated.
513 * Transcoder attached to the connector could be changed at modeset.
514 * Hence caching the transcoder here.
515 */
516 enum transcoder cpu_transcoder;
517 /* Only used for DP MST stream encryption */
518 enum transcoder stream_transcoder;
519 };
520
521 struct intel_connector {
522 struct drm_connector base;
523 /*
524 * The fixed encoder this connector is connected to.
525 */
526 struct intel_encoder *encoder;
527
528 /* ACPI device id for ACPI and driver cooperation */
529 u32 acpi_device_id;
530
531 /* Reads out the current hw, returning true if the connector is enabled
532 * and active (i.e. dpms ON state). */
533 bool (*get_hw_state)(struct intel_connector *);
534
535 /* Panel info for eDP and LVDS */
536 struct intel_panel panel;
537
538 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
539 struct edid *edid;
540 struct edid *detect_edid;
541
542 /* Number of times hotplug detection was tried after an HPD interrupt */
543 int hotplug_retries;
544
545 /* since POLL and HPD connectors may use the same HPD line keep the native
546 state of connector->polled in case hotplug storm detection changes it */
547 u8 polled;
548
549 struct drm_dp_mst_port *port;
550
551 struct intel_dp *mst_port;
552
553 /* Work struct to schedule a uevent on link train failure */
554 struct work_struct modeset_retry_work;
555
556 struct intel_hdcp hdcp;
557 };
558
559 struct intel_digital_connector_state {
560 struct drm_connector_state base;
561
562 enum hdmi_force_audio force_audio;
563 int broadcast_rgb;
564 };
565
566 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
567
568 struct dpll {
569 /* given values */
570 int n;
571 int m1, m2;
572 int p1, p2;
573 /* derived values */
574 int dot;
575 int vco;
576 int m;
577 int p;
578 };
579
580 struct intel_atomic_state {
581 struct drm_atomic_state base;
582
583 intel_wakeref_t wakeref;
584
585 struct __intel_global_objs_state *global_objs;
586 int num_global_objs;
587
588 bool dpll_set, modeset;
589
590 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
591
592 /*
593 * Current watermarks can't be trusted during hardware readout, so
594 * don't bother calculating intermediate watermarks.
595 */
596 bool skip_intermediate_wm;
597
598 bool rps_interactive;
599
600 struct i915_sw_fence commit_ready;
601
602 struct llist_node freed;
603 };
604
605 struct intel_plane_state {
606 struct drm_plane_state uapi;
607
608 /*
609 * actual hardware state, the state we program to the hardware.
610 * The following members are used to verify the hardware state:
611 * During initial hw readout, they need to be copied from uapi.
612 */
613 struct {
614 struct drm_crtc *crtc;
615 struct drm_framebuffer *fb;
616
617 u16 alpha;
618 u16 pixel_blend_mode;
619 unsigned int rotation;
620 enum drm_color_encoding color_encoding;
621 enum drm_color_range color_range;
622 enum drm_scaling_filter scaling_filter;
623 } hw;
624
625 struct i915_vma *ggtt_vma;
626 struct i915_vma *dpt_vma;
627 unsigned long flags;
628 #define PLANE_HAS_FENCE BIT(0)
629
630 struct intel_fb_view view;
631
632 /* plane control register */
633 u32 ctl;
634
635 /* plane color control register */
636 u32 color_ctl;
637
638 /* chroma upsampler control register */
639 u32 cus_ctl;
640
641 /*
642 * scaler_id
643 * = -1 : not using a scaler
644 * >= 0 : using a scalers
645 *
646 * plane requiring a scaler:
647 * - During check_plane, its bit is set in
648 * crtc_state->scaler_state.scaler_users by calling helper function
649 * update_scaler_plane.
650 * - scaler_id indicates the scaler it got assigned.
651 *
652 * plane doesn't require a scaler:
653 * - this can happen when scaling is no more required or plane simply
654 * got disabled.
655 * - During check_plane, corresponding bit is reset in
656 * crtc_state->scaler_state.scaler_users by calling helper function
657 * update_scaler_plane.
658 */
659 int scaler_id;
660
661 /*
662 * planar_linked_plane:
663 *
664 * ICL planar formats require 2 planes that are updated as pairs.
665 * This member is used to make sure the other plane is also updated
666 * when required, and for update_slave() to find the correct
667 * plane_state to pass as argument.
668 */
669 struct intel_plane *planar_linked_plane;
670
671 /*
672 * planar_slave:
673 * If set don't update use the linked plane's state for updating
674 * this plane during atomic commit with the update_slave() callback.
675 *
676 * It's also used by the watermark code to ignore wm calculations on
677 * this plane. They're calculated by the linked plane's wm code.
678 */
679 u32 planar_slave;
680
681 struct drm_intel_sprite_colorkey ckey;
682
683 struct drm_rect psr2_sel_fetch_area;
684
685 /* Clear Color Value */
686 u64 ccval;
687 };
688
689 struct intel_initial_plane_config {
690 struct intel_framebuffer *fb;
691 struct i915_vma *vma;
692 unsigned int tiling;
693 int size;
694 u32 base;
695 u8 rotation;
696 };
697
698 struct intel_scaler {
699 int in_use;
700 u32 mode;
701 };
702
703 struct intel_crtc_scaler_state {
704 #define SKL_NUM_SCALERS 2
705 struct intel_scaler scalers[SKL_NUM_SCALERS];
706
707 /*
708 * scaler_users: keeps track of users requesting scalers on this crtc.
709 *
710 * If a bit is set, a user is using a scaler.
711 * Here user can be a plane or crtc as defined below:
712 * bits 0-30 - plane (bit position is index from drm_plane_index)
713 * bit 31 - crtc
714 *
715 * Instead of creating a new index to cover planes and crtc, using
716 * existing drm_plane_index for planes which is well less than 31
717 * planes and bit 31 for crtc. This should be fine to cover all
718 * our platforms.
719 *
720 * intel_atomic_setup_scalers will setup available scalers to users
721 * requesting scalers. It will gracefully fail if request exceeds
722 * avilability.
723 */
724 #define SKL_CRTC_INDEX 31
725 unsigned scaler_users;
726
727 /* scaler used by crtc for panel fitting purpose */
728 int scaler_id;
729 };
730
731 /* {crtc,crtc_state}->mode_flags */
732 /* Flag to get scanline using frame time stamps */
733 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
734 /* Flag to use the scanline counter instead of the pixel counter */
735 #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2)
736 /*
737 * TE0 or TE1 flag is set if the crtc has a DSI encoder which
738 * is operating in command mode.
739 * Flag to use TE from DSI0 instead of VBI in command mode
740 */
741 #define I915_MODE_FLAG_DSI_USE_TE0 (1<<3)
742 /* Flag to use TE from DSI1 instead of VBI in command mode */
743 #define I915_MODE_FLAG_DSI_USE_TE1 (1<<4)
744 /* Flag to indicate mipi dsi periodic command mode where we do not get TE */
745 #define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
746 /* Do tricks to make vblank timestamps sane with VRR? */
747 #define I915_MODE_FLAG_VRR (1<<6)
748
749 struct intel_wm_level {
750 bool enable;
751 u32 pri_val;
752 u32 spr_val;
753 u32 cur_val;
754 u32 fbc_val;
755 };
756
757 struct intel_pipe_wm {
758 struct intel_wm_level wm[5];
759 bool fbc_wm_enabled;
760 bool pipe_enabled;
761 bool sprites_enabled;
762 bool sprites_scaled;
763 };
764
765 struct skl_wm_level {
766 u16 min_ddb_alloc;
767 u16 blocks;
768 u8 lines;
769 bool enable;
770 bool ignore_lines;
771 bool can_sagv;
772 };
773
774 struct skl_plane_wm {
775 struct skl_wm_level wm[8];
776 struct skl_wm_level uv_wm[8];
777 struct skl_wm_level trans_wm;
778 struct {
779 struct skl_wm_level wm0;
780 struct skl_wm_level trans_wm;
781 } sagv;
782 bool is_planar;
783 };
784
785 struct skl_pipe_wm {
786 struct skl_plane_wm planes[I915_MAX_PLANES];
787 bool use_sagv_wm;
788 };
789
790 enum vlv_wm_level {
791 VLV_WM_LEVEL_PM2,
792 VLV_WM_LEVEL_PM5,
793 VLV_WM_LEVEL_DDR_DVFS,
794 NUM_VLV_WM_LEVELS,
795 };
796
797 struct vlv_wm_state {
798 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
799 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
800 u8 num_levels;
801 bool cxsr;
802 };
803
804 struct vlv_fifo_state {
805 u16 plane[I915_MAX_PLANES];
806 };
807
808 enum g4x_wm_level {
809 G4X_WM_LEVEL_NORMAL,
810 G4X_WM_LEVEL_SR,
811 G4X_WM_LEVEL_HPLL,
812 NUM_G4X_WM_LEVELS,
813 };
814
815 struct g4x_wm_state {
816 struct g4x_pipe_wm wm;
817 struct g4x_sr_wm sr;
818 struct g4x_sr_wm hpll;
819 bool cxsr;
820 bool hpll_en;
821 bool fbc_en;
822 };
823
824 struct intel_crtc_wm_state {
825 union {
826 /*
827 * raw:
828 * The "raw" watermark values produced by the formula
829 * given the plane's current state. They do not consider
830 * how much FIFO is actually allocated for each plane.
831 *
832 * optimal:
833 * The "optimal" watermark values given the current
834 * state of the planes and the amount of FIFO
835 * allocated to each, ignoring any previous state
836 * of the planes.
837 *
838 * intermediate:
839 * The "intermediate" watermark values when transitioning
840 * between the old and new "optimal" values. Used when
841 * the watermark registers are single buffered and hence
842 * their state changes asynchronously with regards to the
843 * actual plane registers. These are essentially the
844 * worst case combination of the old and new "optimal"
845 * watermarks, which are therefore safe to use when the
846 * plane is in either its old or new state.
847 */
848 struct {
849 struct intel_pipe_wm intermediate;
850 struct intel_pipe_wm optimal;
851 } ilk;
852
853 struct {
854 struct skl_pipe_wm raw;
855 /* gen9+ only needs 1-step wm programming */
856 struct skl_pipe_wm optimal;
857 struct skl_ddb_entry ddb;
858 struct skl_ddb_entry plane_ddb_y[I915_MAX_PLANES];
859 struct skl_ddb_entry plane_ddb_uv[I915_MAX_PLANES];
860 } skl;
861
862 struct {
863 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS]; /* not inverted */
864 struct vlv_wm_state intermediate; /* inverted */
865 struct vlv_wm_state optimal; /* inverted */
866 struct vlv_fifo_state fifo_state;
867 } vlv;
868
869 struct {
870 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
871 struct g4x_wm_state intermediate;
872 struct g4x_wm_state optimal;
873 } g4x;
874 };
875
876 /*
877 * Platforms with two-step watermark programming will need to
878 * update watermark programming post-vblank to switch from the
879 * safe intermediate watermarks to the optimal final
880 * watermarks.
881 */
882 bool need_postvbl_update;
883 };
884
885 enum intel_output_format {
886 INTEL_OUTPUT_FORMAT_RGB,
887 INTEL_OUTPUT_FORMAT_YCBCR420,
888 INTEL_OUTPUT_FORMAT_YCBCR444,
889 };
890
891 struct intel_mpllb_state {
892 u32 clock; /* in KHz */
893 u32 ref_control;
894 u32 mpllb_cp;
895 u32 mpllb_div;
896 u32 mpllb_div2;
897 u32 mpllb_fracn1;
898 u32 mpllb_fracn2;
899 u32 mpllb_sscen;
900 u32 mpllb_sscstep;
901 };
902
903 struct intel_crtc_state {
904 /*
905 * uapi (drm) state. This is the software state shown to userspace.
906 * In particular, the following members are used for bookkeeping:
907 * - crtc
908 * - state
909 * - *_changed
910 * - event
911 * - commit
912 * - mode_blob
913 */
914 struct drm_crtc_state uapi;
915
916 /*
917 * actual hardware state, the state we program to the hardware.
918 * The following members are used to verify the hardware state:
919 * - enable
920 * - active
921 * - mode / pipe_mode / adjusted_mode
922 * - color property blobs.
923 *
924 * During initial hw readout, they need to be copied to uapi.
925 *
926 * Bigjoiner will allow a transcoder mode that spans 2 pipes;
927 * Use the pipe_mode for calculations like watermarks, pipe
928 * scaler, and bandwidth.
929 *
930 * Use adjusted_mode for things that need to know the full
931 * mode on the transcoder, which spans all pipes.
932 */
933 struct {
934 bool active, enable;
935 struct drm_property_blob *degamma_lut, *gamma_lut, *ctm;
936 struct drm_display_mode mode, pipe_mode, adjusted_mode;
937 enum drm_scaling_filter scaling_filter;
938 } hw;
939
940 /**
941 * quirks - bitfield with hw state readout quirks
942 *
943 * For various reasons the hw state readout code might not be able to
944 * completely faithfully read out the current state. These cases are
945 * tracked with quirk flags so that fastboot and state checker can act
946 * accordingly.
947 */
948 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
949 #define PIPE_CONFIG_QUIRK_BIGJOINER_SLAVE (1<<1) /* bigjoiner slave, partial readout */
950 unsigned long quirks;
951
952 unsigned fb_bits; /* framebuffers to flip */
953 bool update_pipe; /* can a fast modeset be performed? */
954 bool disable_cxsr;
955 bool update_wm_pre, update_wm_post; /* watermarks are updated */
956 bool fifo_changed; /* FIFO split is changed */
957 bool preload_luts;
958 bool inherited; /* state inherited from BIOS? */
959
960 /* Pipe source size (ie. panel fitter input size)
961 * All planes will be positioned inside this space,
962 * and get clipped at the edges. */
963 int pipe_src_w, pipe_src_h;
964
965 /*
966 * Pipe pixel rate, adjusted for
967 * panel fitter/pipe scaler downscaling.
968 */
969 unsigned int pixel_rate;
970
971 /* Whether to set up the PCH/FDI. Note that we never allow sharing
972 * between pch encoders and cpu encoders. */
973 bool has_pch_encoder;
974
975 /* Are we sending infoframes on the attached port */
976 bool has_infoframe;
977
978 /* CPU Transcoder for the pipe. Currently this can only differ from the
979 * pipe on Haswell and later (where we have a special eDP transcoder)
980 * and Broxton (where we have special DSI transcoders). */
981 enum transcoder cpu_transcoder;
982
983 /*
984 * Use reduced/limited/broadcast rbg range, compressing from the full
985 * range fed into the crtcs.
986 */
987 bool limited_color_range;
988
989 /* Bitmask of encoder types (enum intel_output_type)
990 * driven by the pipe.
991 */
992 unsigned int output_types;
993
994 /* Whether we should send NULL infoframes. Required for audio. */
995 bool has_hdmi_sink;
996
997 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
998 * has_dp_encoder is set. */
999 bool has_audio;
1000
1001 /*
1002 * Enable dithering, used when the selected pipe bpp doesn't match the
1003 * plane bpp.
1004 */
1005 bool dither;
1006
1007 /*
1008 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
1009 * compliance video pattern tests.
1010 * Disable dither only if it is a compliance test request for
1011 * 18bpp.
1012 */
1013 bool dither_force_disable;
1014
1015 /* Controls for the clock computation, to override various stages. */
1016 bool clock_set;
1017
1018 /* SDVO TV has a bunch of special case. To make multifunction encoders
1019 * work correctly, we need to track this at runtime.*/
1020 bool sdvo_tv_clock;
1021
1022 /*
1023 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
1024 * required. This is set in the 2nd loop of calling encoder's
1025 * ->compute_config if the first pick doesn't work out.
1026 */
1027 bool bw_constrained;
1028
1029 /* Settings for the intel dpll used on pretty much everything but
1030 * haswell. */
1031 struct dpll dpll;
1032
1033 /* Selected dpll when shared or NULL. */
1034 struct intel_shared_dpll *shared_dpll;
1035
1036 /* Actual register state of the dpll, for shared dpll cross-checking. */
1037 union {
1038 struct intel_dpll_hw_state dpll_hw_state;
1039 struct intel_mpllb_state mpllb_state;
1040 };
1041
1042 /*
1043 * ICL reserved DPLLs for the CRTC/port. The active PLL is selected by
1044 * setting shared_dpll and dpll_hw_state to one of these reserved ones.
1045 */
1046 struct icl_port_dpll {
1047 struct intel_shared_dpll *pll;
1048 struct intel_dpll_hw_state hw_state;
1049 } icl_port_dplls[ICL_PORT_DPLL_COUNT];
1050
1051 /* DSI PLL registers */
1052 struct {
1053 u32 ctrl, div;
1054 } dsi_pll;
1055
1056 int pipe_bpp;
1057 struct intel_link_m_n dp_m_n;
1058
1059 /* m2_n2 for eDP downclock */
1060 struct intel_link_m_n dp_m2_n2;
1061 bool has_drrs;
1062
1063 bool has_psr;
1064 bool has_psr2;
1065 bool enable_psr2_sel_fetch;
1066 bool req_psr2_sdp_prior_scanline;
1067 u32 dc3co_exitline;
1068 u16 su_y_granularity;
1069
1070 /*
1071 * Frequence the dpll for the port should run at. Differs from the
1072 * adjusted dotclock e.g. for DP or 10/12bpc hdmi mode. This is also
1073 * already multiplied by pixel_multiplier.
1074 */
1075 int port_clock;
1076
1077 /* Used by SDVO (and if we ever fix it, HDMI). */
1078 unsigned pixel_multiplier;
1079
1080 /* I915_MODE_FLAG_* */
1081 u8 mode_flags;
1082
1083 u8 lane_count;
1084
1085 /*
1086 * Used by platforms having DP/HDMI PHY with programmable lane
1087 * latency optimization.
1088 */
1089 u8 lane_lat_optim_mask;
1090
1091 /* minimum acceptable voltage level */
1092 u8 min_voltage_level;
1093
1094 /* Panel fitter controls for gen2-gen4 + VLV */
1095 struct {
1096 u32 control;
1097 u32 pgm_ratios;
1098 u32 lvds_border_bits;
1099 } gmch_pfit;
1100
1101 /* Panel fitter placement and size for Ironlake+ */
1102 struct {
1103 struct drm_rect dst;
1104 bool enabled;
1105 bool force_thru;
1106 } pch_pfit;
1107
1108 /* FDI configuration, only valid if has_pch_encoder is set. */
1109 int fdi_lanes;
1110 struct intel_link_m_n fdi_m_n;
1111
1112 bool ips_enabled;
1113
1114 bool crc_enabled;
1115
1116 bool enable_fbc;
1117
1118 bool double_wide;
1119
1120 int pbn;
1121
1122 struct intel_crtc_scaler_state scaler_state;
1123
1124 /* w/a for waiting 2 vblanks during crtc enable */
1125 enum pipe hsw_workaround_pipe;
1126
1127 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
1128 bool disable_lp_wm;
1129
1130 struct intel_crtc_wm_state wm;
1131
1132 int min_cdclk[I915_MAX_PLANES];
1133
1134 u32 data_rate[I915_MAX_PLANES];
1135
1136 /* FIXME unify with data_rate[] */
1137 u64 plane_data_rate[I915_MAX_PLANES];
1138 u64 uv_plane_data_rate[I915_MAX_PLANES];
1139
1140 /* Gamma mode programmed on the pipe */
1141 u32 gamma_mode;
1142
1143 union {
1144 /* CSC mode programmed on the pipe */
1145 u32 csc_mode;
1146
1147 /* CHV CGM mode */
1148 u32 cgm_mode;
1149 };
1150
1151 /* bitmask of logically enabled planes (enum plane_id) */
1152 u8 enabled_planes;
1153
1154 /* bitmask of actually visible planes (enum plane_id) */
1155 u8 active_planes;
1156 u8 nv12_planes;
1157 u8 c8_planes;
1158
1159 /* bitmask of planes that will be updated during the commit */
1160 u8 update_planes;
1161
1162 struct {
1163 u32 enable;
1164 u32 gcp;
1165 union hdmi_infoframe avi;
1166 union hdmi_infoframe spd;
1167 union hdmi_infoframe hdmi;
1168 union hdmi_infoframe drm;
1169 struct drm_dp_vsc_sdp vsc;
1170 } infoframes;
1171
1172 /* HDMI scrambling status */
1173 bool hdmi_scrambling;
1174
1175 /* HDMI High TMDS char rate ratio */
1176 bool hdmi_high_tmds_clock_ratio;
1177
1178 /* Output format RGB/YCBCR etc */
1179 enum intel_output_format output_format;
1180
1181 /* enable pipe gamma? */
1182 bool gamma_enable;
1183
1184 /* enable pipe csc? */
1185 bool csc_enable;
1186
1187 /* enable pipe big joiner? */
1188 bool bigjoiner;
1189
1190 /* big joiner slave crtc? */
1191 bool bigjoiner_slave;
1192
1193 /* linked crtc for bigjoiner, either slave or master */
1194 struct intel_crtc *bigjoiner_linked_crtc;
1195
1196 /* Display Stream compression state */
1197 struct {
1198 bool compression_enable;
1199 bool dsc_split;
1200 u16 compressed_bpp;
1201 u8 slice_count;
1202 struct drm_dsc_config config;
1203 } dsc;
1204
1205 /* HSW+ linetime watermarks */
1206 u16 linetime;
1207 u16 ips_linetime;
1208
1209 /* Forward Error correction State */
1210 bool fec_enable;
1211
1212 /* Pointer to master transcoder in case of tiled displays */
1213 enum transcoder master_transcoder;
1214
1215 /* Bitmask to indicate slaves attached */
1216 u8 sync_mode_slaves_mask;
1217
1218 /* Only valid on TGL+ */
1219 enum transcoder mst_master_transcoder;
1220
1221 /* For DSB related info */
1222 struct intel_dsb *dsb;
1223
1224 u32 psr2_man_track_ctl;
1225
1226 /* Variable Refresh Rate state */
1227 struct {
1228 bool enable;
1229 u8 pipeline_full;
1230 u16 flipline, vmin, vmax, guardband;
1231 } vrr;
1232
1233 /* Stream Splitter for eDP MSO */
1234 struct {
1235 bool enable;
1236 u8 link_count;
1237 u8 pixel_overlap;
1238 } splitter;
1239 };
1240
1241 enum intel_pipe_crc_source {
1242 INTEL_PIPE_CRC_SOURCE_NONE,
1243 INTEL_PIPE_CRC_SOURCE_PLANE1,
1244 INTEL_PIPE_CRC_SOURCE_PLANE2,
1245 INTEL_PIPE_CRC_SOURCE_PLANE3,
1246 INTEL_PIPE_CRC_SOURCE_PLANE4,
1247 INTEL_PIPE_CRC_SOURCE_PLANE5,
1248 INTEL_PIPE_CRC_SOURCE_PLANE6,
1249 INTEL_PIPE_CRC_SOURCE_PLANE7,
1250 INTEL_PIPE_CRC_SOURCE_PIPE,
1251 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1252 INTEL_PIPE_CRC_SOURCE_TV,
1253 INTEL_PIPE_CRC_SOURCE_DP_B,
1254 INTEL_PIPE_CRC_SOURCE_DP_C,
1255 INTEL_PIPE_CRC_SOURCE_DP_D,
1256 INTEL_PIPE_CRC_SOURCE_AUTO,
1257 INTEL_PIPE_CRC_SOURCE_MAX,
1258 };
1259
1260 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1261 struct intel_pipe_crc {
1262 spinlock_t lock;
1263 int skipped;
1264 enum intel_pipe_crc_source source;
1265 };
1266
1267 struct intel_crtc {
1268 struct drm_crtc base;
1269 enum pipe pipe;
1270 /*
1271 * Whether the crtc and the connected output pipeline is active. Implies
1272 * that crtc->enabled is set, i.e. the current mode configuration has
1273 * some outputs connected to this crtc.
1274 */
1275 bool active;
1276 u8 plane_ids_mask;
1277
1278 /* I915_MODE_FLAG_* */
1279 u8 mode_flags;
1280
1281 u16 vmax_vblank_start;
1282
1283 struct intel_display_power_domain_set enabled_power_domains;
1284 struct intel_overlay *overlay;
1285
1286 struct intel_crtc_state *config;
1287
1288 /* Access to these should be protected by dev_priv->irq_lock. */
1289 bool cpu_fifo_underrun_disabled;
1290 bool pch_fifo_underrun_disabled;
1291
1292 /* per-pipe watermark state */
1293 struct {
1294 /* watermarks currently being used */
1295 union {
1296 struct intel_pipe_wm ilk;
1297 struct vlv_wm_state vlv;
1298 struct g4x_wm_state g4x;
1299 } active;
1300 } wm;
1301
1302 int scanline_offset;
1303
1304 struct {
1305 unsigned start_vbl_count;
1306 ktime_t start_vbl_time;
1307 int min_vbl, max_vbl;
1308 int scanline_start;
1309 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
1310 struct {
1311 u64 min;
1312 u64 max;
1313 u64 sum;
1314 unsigned int over;
1315 unsigned int times[17]; /* [1us, 16ms] */
1316 } vbl;
1317 #endif
1318 } debug;
1319
1320 /* scalers available on this crtc */
1321 int num_scalers;
1322
1323 #ifdef CONFIG_DEBUG_FS
1324 struct intel_pipe_crc pipe_crc;
1325 #endif
1326 };
1327
1328 struct intel_plane {
1329 struct drm_plane base;
1330 enum i9xx_plane_id i9xx_plane;
1331 enum plane_id id;
1332 enum pipe pipe;
1333 bool has_fbc;
1334 bool has_ccs;
1335 bool need_async_flip_disable_wa;
1336 u32 frontbuffer_bit;
1337
1338 struct {
1339 u32 base, cntl, size;
1340 } cursor;
1341
1342 /*
1343 * NOTE: Do not place new plane state fields here (e.g., when adding
1344 * new plane properties). New runtime state should now be placed in
1345 * the intel_plane_state structure and accessed via plane_state.
1346 */
1347
1348 int (*min_width)(const struct drm_framebuffer *fb,
1349 int color_plane,
1350 unsigned int rotation);
1351 int (*max_width)(const struct drm_framebuffer *fb,
1352 int color_plane,
1353 unsigned int rotation);
1354 int (*max_height)(const struct drm_framebuffer *fb,
1355 int color_plane,
1356 unsigned int rotation);
1357 unsigned int (*max_stride)(struct intel_plane *plane,
1358 u32 pixel_format, u64 modifier,
1359 unsigned int rotation);
1360 void (*update_plane)(struct intel_plane *plane,
1361 const struct intel_crtc_state *crtc_state,
1362 const struct intel_plane_state *plane_state);
1363 void (*disable_plane)(struct intel_plane *plane,
1364 const struct intel_crtc_state *crtc_state);
1365 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
1366 int (*check_plane)(struct intel_crtc_state *crtc_state,
1367 struct intel_plane_state *plane_state);
1368 int (*min_cdclk)(const struct intel_crtc_state *crtc_state,
1369 const struct intel_plane_state *plane_state);
1370 void (*async_flip)(struct intel_plane *plane,
1371 const struct intel_crtc_state *crtc_state,
1372 const struct intel_plane_state *plane_state,
1373 bool async_flip);
1374 void (*enable_flip_done)(struct intel_plane *plane);
1375 void (*disable_flip_done)(struct intel_plane *plane);
1376 };
1377
1378 struct intel_watermark_params {
1379 u16 fifo_size;
1380 u16 max_wm;
1381 u8 default_wm;
1382 u8 guard_size;
1383 u8 cacheline_size;
1384 };
1385
1386 struct cxsr_latency {
1387 bool is_desktop : 1;
1388 bool is_ddr3 : 1;
1389 u16 fsb_freq;
1390 u16 mem_freq;
1391 u16 display_sr;
1392 u16 display_hpll_disable;
1393 u16 cursor_sr;
1394 u16 cursor_hpll_disable;
1395 };
1396
1397 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1398 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1399 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, uapi)
1400 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1401 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1402 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1403 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1404 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, uapi)
1405 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1406
1407 struct intel_hdmi {
1408 i915_reg_t hdmi_reg;
1409 int ddc_bus;
1410 struct {
1411 enum drm_dp_dual_mode_type type;
1412 int max_tmds_clock;
1413 } dp_dual_mode;
1414 bool has_hdmi_sink;
1415 bool has_audio;
1416 struct intel_connector *attached_connector;
1417 struct cec_notifier *cec_notifier;
1418 };
1419
1420 struct intel_dp_mst_encoder;
1421 /*
1422 * enum link_m_n_set:
1423 * When platform provides two set of M_N registers for dp, we can
1424 * program them and switch between them incase of DRRS.
1425 * But When only one such register is provided, we have to program the
1426 * required divider value on that registers itself based on the DRRS state.
1427 *
1428 * M1_N1 : Program dp_m_n on M1_N1 registers
1429 * dp_m2_n2 on M2_N2 registers (If supported)
1430 *
1431 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1432 * M2_N2 registers are not supported
1433 */
1434
1435 enum link_m_n_set {
1436 /* Sets the m1_n1 and m2_n2 */
1437 M1_N1 = 0,
1438 M2_N2
1439 };
1440
1441 struct intel_dp_compliance_data {
1442 unsigned long edid;
1443 u8 video_pattern;
1444 u16 hdisplay, vdisplay;
1445 u8 bpc;
1446 struct drm_dp_phy_test_params phytest;
1447 };
1448
1449 struct intel_dp_compliance {
1450 unsigned long test_type;
1451 struct intel_dp_compliance_data test_data;
1452 bool test_active;
1453 int test_link_rate;
1454 u8 test_lane_count;
1455 };
1456
1457 struct intel_dp_pcon_frl {
1458 bool is_trained;
1459 int trained_rate_gbps;
1460 };
1461
1462 struct intel_pps {
1463 int panel_power_up_delay;
1464 int panel_power_down_delay;
1465 int panel_power_cycle_delay;
1466 int backlight_on_delay;
1467 int backlight_off_delay;
1468 struct delayed_work panel_vdd_work;
1469 bool want_panel_vdd;
1470 unsigned long last_power_on;
1471 unsigned long last_backlight_off;
1472 ktime_t panel_power_off_time;
1473 intel_wakeref_t vdd_wakeref;
1474
1475 /*
1476 * Pipe whose power sequencer is currently locked into
1477 * this port. Only relevant on VLV/CHV.
1478 */
1479 enum pipe pps_pipe;
1480 /*
1481 * Pipe currently driving the port. Used for preventing
1482 * the use of the PPS for any pipe currentrly driving
1483 * external DP as that will mess things up on VLV.
1484 */
1485 enum pipe active_pipe;
1486 /*
1487 * Set if the sequencer may be reset due to a power transition,
1488 * requiring a reinitialization. Only relevant on BXT.
1489 */
1490 bool pps_reset;
1491 struct edp_power_seq pps_delays;
1492 };
1493
1494 struct intel_psr {
1495 /* Mutex for PSR state of the transcoder */
1496 struct mutex lock;
1497
1498 #define I915_PSR_DEBUG_MODE_MASK 0x0f
1499 #define I915_PSR_DEBUG_DEFAULT 0x00
1500 #define I915_PSR_DEBUG_DISABLE 0x01
1501 #define I915_PSR_DEBUG_ENABLE 0x02
1502 #define I915_PSR_DEBUG_FORCE_PSR1 0x03
1503 #define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4
1504 #define I915_PSR_DEBUG_IRQ 0x10
1505
1506 u32 debug;
1507 bool sink_support;
1508 bool source_support;
1509 bool enabled;
1510 bool paused;
1511 enum pipe pipe;
1512 enum transcoder transcoder;
1513 bool active;
1514 struct work_struct work;
1515 unsigned int busy_frontbuffer_bits;
1516 bool sink_psr2_support;
1517 bool link_standby;
1518 bool colorimetry_support;
1519 bool psr2_enabled;
1520 bool psr2_sel_fetch_enabled;
1521 bool req_psr2_sdp_prior_scanline;
1522 u8 sink_sync_latency;
1523 u8 io_wake_lines;
1524 u8 fast_wake_lines;
1525 ktime_t last_entry_attempt;
1526 ktime_t last_exit;
1527 bool sink_not_reliable;
1528 bool irq_aux_error;
1529 u16 su_w_granularity;
1530 u16 su_y_granularity;
1531 u32 dc3co_exitline;
1532 u32 dc3co_exit_delay;
1533 struct delayed_work dc3co_work;
1534 struct drm_dp_vsc_sdp vsc;
1535 };
1536
1537 struct intel_dp {
1538 i915_reg_t output_reg;
1539 u32 DP;
1540 int link_rate;
1541 u8 lane_count;
1542 u8 sink_count;
1543 bool link_trained;
1544 bool has_hdmi_sink;
1545 bool has_audio;
1546 bool reset_link_params;
1547 bool use_max_params;
1548 u8 dpcd[DP_RECEIVER_CAP_SIZE];
1549 u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1550 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1551 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1552 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
1553 u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE];
1554 u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE];
1555 u8 fec_capable;
1556 u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE];
1557 /* source rates */
1558 int num_source_rates;
1559 const int *source_rates;
1560 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1561 int num_sink_rates;
1562 int sink_rates[DP_MAX_SUPPORTED_RATES];
1563 bool use_rate_select;
1564 /* intersection of source and sink rates */
1565 int num_common_rates;
1566 int common_rates[DP_MAX_SUPPORTED_RATES];
1567 /* Max lane count for the current link */
1568 int max_link_lane_count;
1569 /* Max rate for the current link */
1570 int max_link_rate;
1571 int mso_link_count;
1572 int mso_pixel_overlap;
1573 /* sink or branch descriptor */
1574 struct drm_dp_desc desc;
1575 struct drm_dp_aux aux;
1576 u32 aux_busy_last_status;
1577 u8 train_set[4];
1578
1579 struct intel_pps pps;
1580
1581 bool can_mst; /* this port supports mst */
1582 bool is_mst;
1583 int active_mst_links;
1584
1585 /* connector directly attached - won't be use for modeset in mst world */
1586 struct intel_connector *attached_connector;
1587
1588 /* mst connector list */
1589 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1590 struct drm_dp_mst_topology_mgr mst_mgr;
1591
1592 u32 (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1593 /*
1594 * This function returns the value we have to program the AUX_CTL
1595 * register with to kick off an AUX transaction.
1596 */
1597 u32 (*get_aux_send_ctl)(struct intel_dp *dp, int send_bytes,
1598 u32 aux_clock_divider);
1599
1600 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1601 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1602
1603 /* This is called before a link training is starterd */
1604 void (*prepare_link_retrain)(struct intel_dp *intel_dp,
1605 const struct intel_crtc_state *crtc_state);
1606 void (*set_link_train)(struct intel_dp *intel_dp,
1607 const struct intel_crtc_state *crtc_state,
1608 u8 dp_train_pat);
1609 void (*set_idle_link_train)(struct intel_dp *intel_dp,
1610 const struct intel_crtc_state *crtc_state);
1611 void (*set_signal_levels)(struct intel_dp *intel_dp,
1612 const struct intel_crtc_state *crtc_state);
1613
1614 u8 (*preemph_max)(struct intel_dp *intel_dp);
1615 u8 (*voltage_max)(struct intel_dp *intel_dp,
1616 const struct intel_crtc_state *crtc_state);
1617
1618 /* Displayport compliance testing */
1619 struct intel_dp_compliance compliance;
1620
1621 /* Downstream facing port caps */
1622 struct {
1623 int min_tmds_clock, max_tmds_clock;
1624 int max_dotclock;
1625 int pcon_max_frl_bw;
1626 u8 max_bpc;
1627 bool ycbcr_444_to_420;
1628 bool rgb_to_ycbcr;
1629 } dfp;
1630
1631 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1632 struct pm_qos_request pm_qos;
1633
1634 /* Display stream compression testing */
1635 bool force_dsc_en;
1636 int force_dsc_bpp;
1637
1638 bool hobl_failed;
1639 bool hobl_active;
1640
1641 struct intel_dp_pcon_frl frl;
1642
1643 struct intel_psr psr;
1644
1645 /* When we last wrote the OUI for eDP */
1646 unsigned long last_oui_write;
1647 };
1648
1649 enum lspcon_vendor {
1650 LSPCON_VENDOR_MCA,
1651 LSPCON_VENDOR_PARADE
1652 };
1653
1654 struct intel_lspcon {
1655 bool active;
1656 bool hdr_supported;
1657 enum drm_lspcon_mode mode;
1658 enum lspcon_vendor vendor;
1659 };
1660
1661 struct intel_digital_port {
1662 struct intel_encoder base;
1663 u32 saved_port_bits;
1664 struct intel_dp dp;
1665 struct intel_hdmi hdmi;
1666 struct intel_lspcon lspcon;
1667 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1668 bool release_cl2_override;
1669 u8 max_lanes;
1670 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
1671 enum aux_ch aux_ch;
1672 enum intel_display_power_domain ddi_io_power_domain;
1673 intel_wakeref_t ddi_io_wakeref;
1674 intel_wakeref_t aux_wakeref;
1675 struct mutex tc_lock; /* protects the TypeC port mode */
1676 intel_wakeref_t tc_lock_wakeref;
1677 int tc_link_refcount;
1678 bool tc_legacy_port:1;
1679 char tc_port_name[8];
1680 enum tc_port_mode tc_mode;
1681 enum phy_fia tc_phy_fia;
1682 u8 tc_phy_fia_idx;
1683
1684 /* protects num_hdcp_streams reference count, hdcp_port_data and hdcp_auth_status */
1685 struct mutex hdcp_mutex;
1686 /* the number of pipes using HDCP signalling out of this port */
1687 unsigned int num_hdcp_streams;
1688 /* port HDCP auth status */
1689 bool hdcp_auth_status;
1690 /* HDCP port data need to pass to security f/w */
1691 struct hdcp_port_data hdcp_port_data;
1692
1693 void (*write_infoframe)(struct intel_encoder *encoder,
1694 const struct intel_crtc_state *crtc_state,
1695 unsigned int type,
1696 const void *frame, ssize_t len);
1697 void (*read_infoframe)(struct intel_encoder *encoder,
1698 const struct intel_crtc_state *crtc_state,
1699 unsigned int type,
1700 void *frame, ssize_t len);
1701 void (*set_infoframes)(struct intel_encoder *encoder,
1702 bool enable,
1703 const struct intel_crtc_state *crtc_state,
1704 const struct drm_connector_state *conn_state);
1705 u32 (*infoframes_enabled)(struct intel_encoder *encoder,
1706 const struct intel_crtc_state *pipe_config);
1707 bool (*connected)(struct intel_encoder *encoder);
1708 };
1709
1710 struct intel_dp_mst_encoder {
1711 struct intel_encoder base;
1712 enum pipe pipe;
1713 struct intel_digital_port *primary;
1714 struct intel_connector *connector;
1715 };
1716
1717 static inline enum dpio_channel
vlv_dig_port_to_channel(struct intel_digital_port * dig_port)1718 vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
1719 {
1720 switch (dig_port->base.port) {
1721 case PORT_B:
1722 case PORT_D:
1723 return DPIO_CH0;
1724 case PORT_C:
1725 return DPIO_CH1;
1726 default:
1727 BUG();
1728 }
1729 }
1730
1731 static inline enum dpio_phy
vlv_dig_port_to_phy(struct intel_digital_port * dig_port)1732 vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
1733 {
1734 switch (dig_port->base.port) {
1735 case PORT_B:
1736 case PORT_C:
1737 return DPIO_PHY0;
1738 case PORT_D:
1739 return DPIO_PHY1;
1740 default:
1741 BUG();
1742 }
1743 }
1744
1745 static inline enum dpio_channel
vlv_pipe_to_channel(enum pipe pipe)1746 vlv_pipe_to_channel(enum pipe pipe)
1747 {
1748 switch (pipe) {
1749 case PIPE_A:
1750 case PIPE_C:
1751 return DPIO_CH0;
1752 case PIPE_B:
1753 return DPIO_CH1;
1754 default:
1755 BUG();
1756 }
1757 }
1758
intel_pipe_valid(struct drm_i915_private * i915,enum pipe pipe)1759 static inline bool intel_pipe_valid(struct drm_i915_private *i915, enum pipe pipe)
1760 {
1761 return (pipe >= 0 &&
1762 pipe < ARRAY_SIZE(i915->pipe_to_crtc_mapping) &&
1763 INTEL_INFO(i915)->pipe_mask & BIT(pipe) &&
1764 i915->pipe_to_crtc_mapping[pipe]);
1765 }
1766
1767 static inline struct intel_crtc *
intel_get_first_crtc(struct drm_i915_private * dev_priv)1768 intel_get_first_crtc(struct drm_i915_private *dev_priv)
1769 {
1770 return to_intel_crtc(drm_crtc_from_index(&dev_priv->drm, 0));
1771 }
1772
1773 static inline struct intel_crtc *
intel_get_crtc_for_pipe(struct drm_i915_private * dev_priv,enum pipe pipe)1774 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1775 {
1776 /* pipe_to_crtc_mapping may have hole on any of 3 display pipe system */
1777 drm_WARN_ON(&dev_priv->drm,
1778 !(INTEL_INFO(dev_priv)->pipe_mask & BIT(pipe)));
1779 return dev_priv->pipe_to_crtc_mapping[pipe];
1780 }
1781
1782 static inline struct intel_crtc *
intel_get_crtc_for_plane(struct drm_i915_private * dev_priv,enum i9xx_plane_id plane)1783 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1784 {
1785 return dev_priv->plane_to_crtc_mapping[plane];
1786 }
1787
1788 struct intel_load_detect_pipe {
1789 struct drm_atomic_state *restore_state;
1790 };
1791
1792 static inline struct intel_encoder *
intel_attached_encoder(struct intel_connector * connector)1793 intel_attached_encoder(struct intel_connector *connector)
1794 {
1795 return connector->encoder;
1796 }
1797
intel_encoder_is_dig_port(struct intel_encoder * encoder)1798 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1799 {
1800 switch (encoder->type) {
1801 case INTEL_OUTPUT_DDI:
1802 case INTEL_OUTPUT_DP:
1803 case INTEL_OUTPUT_EDP:
1804 case INTEL_OUTPUT_HDMI:
1805 return true;
1806 default:
1807 return false;
1808 }
1809 }
1810
intel_encoder_is_mst(struct intel_encoder * encoder)1811 static inline bool intel_encoder_is_mst(struct intel_encoder *encoder)
1812 {
1813 return encoder->type == INTEL_OUTPUT_DP_MST;
1814 }
1815
1816 static inline struct intel_dp_mst_encoder *
enc_to_mst(struct intel_encoder * encoder)1817 enc_to_mst(struct intel_encoder *encoder)
1818 {
1819 return container_of(&encoder->base, struct intel_dp_mst_encoder,
1820 base.base);
1821 }
1822
1823 static inline struct intel_digital_port *
enc_to_dig_port(struct intel_encoder * encoder)1824 enc_to_dig_port(struct intel_encoder *encoder)
1825 {
1826 struct intel_encoder *intel_encoder = encoder;
1827
1828 if (intel_encoder_is_dig_port(intel_encoder))
1829 return container_of(&encoder->base, struct intel_digital_port,
1830 base.base);
1831 else if (intel_encoder_is_mst(intel_encoder))
1832 return enc_to_mst(encoder)->primary;
1833 else
1834 return NULL;
1835 }
1836
1837 static inline struct intel_digital_port *
intel_attached_dig_port(struct intel_connector * connector)1838 intel_attached_dig_port(struct intel_connector *connector)
1839 {
1840 return enc_to_dig_port(intel_attached_encoder(connector));
1841 }
1842
1843 static inline struct intel_hdmi *
enc_to_intel_hdmi(struct intel_encoder * encoder)1844 enc_to_intel_hdmi(struct intel_encoder *encoder)
1845 {
1846 return &enc_to_dig_port(encoder)->hdmi;
1847 }
1848
1849 static inline struct intel_hdmi *
intel_attached_hdmi(struct intel_connector * connector)1850 intel_attached_hdmi(struct intel_connector *connector)
1851 {
1852 return enc_to_intel_hdmi(intel_attached_encoder(connector));
1853 }
1854
enc_to_intel_dp(struct intel_encoder * encoder)1855 static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder)
1856 {
1857 return &enc_to_dig_port(encoder)->dp;
1858 }
1859
intel_attached_dp(struct intel_connector * connector)1860 static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector)
1861 {
1862 return enc_to_intel_dp(intel_attached_encoder(connector));
1863 }
1864
intel_encoder_is_dp(struct intel_encoder * encoder)1865 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1866 {
1867 switch (encoder->type) {
1868 case INTEL_OUTPUT_DP:
1869 case INTEL_OUTPUT_EDP:
1870 return true;
1871 case INTEL_OUTPUT_DDI:
1872 /* Skip pure HDMI/DVI DDI encoders */
1873 return i915_mmio_reg_valid(enc_to_intel_dp(encoder)->output_reg);
1874 default:
1875 return false;
1876 }
1877 }
1878
1879 static inline struct intel_lspcon *
enc_to_intel_lspcon(struct intel_encoder * encoder)1880 enc_to_intel_lspcon(struct intel_encoder *encoder)
1881 {
1882 return &enc_to_dig_port(encoder)->lspcon;
1883 }
1884
1885 static inline struct intel_digital_port *
dp_to_dig_port(struct intel_dp * intel_dp)1886 dp_to_dig_port(struct intel_dp *intel_dp)
1887 {
1888 return container_of(intel_dp, struct intel_digital_port, dp);
1889 }
1890
1891 static inline struct intel_lspcon *
dp_to_lspcon(struct intel_dp * intel_dp)1892 dp_to_lspcon(struct intel_dp *intel_dp)
1893 {
1894 return &dp_to_dig_port(intel_dp)->lspcon;
1895 }
1896
1897 static inline struct drm_i915_private *
dp_to_i915(struct intel_dp * intel_dp)1898 dp_to_i915(struct intel_dp *intel_dp)
1899 {
1900 return to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
1901 }
1902
1903 #define CAN_PSR(intel_dp) ((intel_dp)->psr.sink_support && \
1904 (intel_dp)->psr.source_support)
1905
intel_encoder_can_psr(struct intel_encoder * encoder)1906 static inline bool intel_encoder_can_psr(struct intel_encoder *encoder)
1907 {
1908 if (!intel_encoder_is_dp(encoder))
1909 return false;
1910
1911 return CAN_PSR(enc_to_intel_dp(encoder));
1912 }
1913
1914 static inline struct intel_digital_port *
hdmi_to_dig_port(struct intel_hdmi * intel_hdmi)1915 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1916 {
1917 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1918 }
1919
1920 static inline struct intel_plane_state *
intel_atomic_get_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)1921 intel_atomic_get_plane_state(struct intel_atomic_state *state,
1922 struct intel_plane *plane)
1923 {
1924 struct drm_plane_state *ret =
1925 drm_atomic_get_plane_state(&state->base, &plane->base);
1926
1927 if (IS_ERR(ret))
1928 return ERR_CAST(ret);
1929
1930 return to_intel_plane_state(ret);
1931 }
1932
1933 static inline struct intel_plane_state *
intel_atomic_get_old_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)1934 intel_atomic_get_old_plane_state(struct intel_atomic_state *state,
1935 struct intel_plane *plane)
1936 {
1937 return to_intel_plane_state(drm_atomic_get_old_plane_state(&state->base,
1938 &plane->base));
1939 }
1940
1941 static inline struct intel_plane_state *
intel_atomic_get_new_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)1942 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1943 struct intel_plane *plane)
1944 {
1945 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1946 &plane->base));
1947 }
1948
1949 static inline struct intel_crtc_state *
intel_atomic_get_old_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)1950 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1951 struct intel_crtc *crtc)
1952 {
1953 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1954 &crtc->base));
1955 }
1956
1957 static inline struct intel_crtc_state *
intel_atomic_get_new_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)1958 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1959 struct intel_crtc *crtc)
1960 {
1961 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1962 &crtc->base));
1963 }
1964
1965 static inline struct intel_digital_connector_state *
intel_atomic_get_new_connector_state(struct intel_atomic_state * state,struct intel_connector * connector)1966 intel_atomic_get_new_connector_state(struct intel_atomic_state *state,
1967 struct intel_connector *connector)
1968 {
1969 return to_intel_digital_connector_state(
1970 drm_atomic_get_new_connector_state(&state->base,
1971 &connector->base));
1972 }
1973
1974 static inline struct intel_digital_connector_state *
intel_atomic_get_old_connector_state(struct intel_atomic_state * state,struct intel_connector * connector)1975 intel_atomic_get_old_connector_state(struct intel_atomic_state *state,
1976 struct intel_connector *connector)
1977 {
1978 return to_intel_digital_connector_state(
1979 drm_atomic_get_old_connector_state(&state->base,
1980 &connector->base));
1981 }
1982
1983 /* intel_display.c */
1984 static inline bool
intel_crtc_has_type(const struct intel_crtc_state * crtc_state,enum intel_output_type type)1985 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1986 enum intel_output_type type)
1987 {
1988 return crtc_state->output_types & (1 << type);
1989 }
1990 static inline bool
intel_crtc_has_dp_encoder(const struct intel_crtc_state * crtc_state)1991 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1992 {
1993 return crtc_state->output_types &
1994 ((1 << INTEL_OUTPUT_DP) |
1995 (1 << INTEL_OUTPUT_DP_MST) |
1996 (1 << INTEL_OUTPUT_EDP));
1997 }
1998
1999 static inline bool
intel_crtc_needs_modeset(const struct intel_crtc_state * crtc_state)2000 intel_crtc_needs_modeset(const struct intel_crtc_state *crtc_state)
2001 {
2002 return drm_atomic_crtc_needs_modeset(&crtc_state->uapi);
2003 }
2004
2005 static inline void
intel_wait_for_vblank(struct drm_i915_private * dev_priv,enum pipe pipe)2006 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
2007 {
2008 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
2009
2010 drm_crtc_wait_one_vblank(&crtc->base);
2011 }
2012
2013 static inline void
intel_wait_for_vblank_if_active(struct drm_i915_private * dev_priv,enum pipe pipe)2014 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pipe)
2015 {
2016 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
2017
2018 if (crtc->active)
2019 intel_wait_for_vblank(dev_priv, pipe);
2020 }
2021
intel_modifier_uses_dpt(struct drm_i915_private * i915,u64 modifier)2022 static inline bool intel_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier)
2023 {
2024 return DISPLAY_VER(i915) >= 13 && modifier != DRM_FORMAT_MOD_LINEAR;
2025 }
2026
intel_fb_uses_dpt(const struct drm_framebuffer * fb)2027 static inline bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
2028 {
2029 return fb && intel_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
2030 }
2031
intel_plane_ggtt_offset(const struct intel_plane_state * plane_state)2032 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state)
2033 {
2034 return i915_ggtt_offset(plane_state->ggtt_vma);
2035 }
2036
2037 static inline struct intel_frontbuffer *
to_intel_frontbuffer(struct drm_framebuffer * fb)2038 to_intel_frontbuffer(struct drm_framebuffer *fb)
2039 {
2040 return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
2041 }
2042
intel_panel_use_ssc(struct drm_i915_private * dev_priv)2043 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
2044 {
2045 if (dev_priv->params.panel_use_ssc >= 0)
2046 return dev_priv->params.panel_use_ssc != 0;
2047 return dev_priv->vbt.lvds_use_ssc
2048 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
2049 }
2050
i9xx_dpll_compute_fp(struct dpll * dpll)2051 static inline u32 i9xx_dpll_compute_fp(struct dpll *dpll)
2052 {
2053 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
2054 }
2055
intel_fdi_link_freq(struct drm_i915_private * dev_priv,const struct intel_crtc_state * pipe_config)2056 static inline u32 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
2057 const struct intel_crtc_state *pipe_config)
2058 {
2059 if (HAS_DDI(dev_priv))
2060 return pipe_config->port_clock; /* SPLL */
2061 else
2062 return dev_priv->fdi_pll_freq;
2063 }
2064
is_ccs_modifier(u64 modifier)2065 static inline bool is_ccs_modifier(u64 modifier)
2066 {
2067 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
2068 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
2069 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
2070 modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
2071 modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
2072 }
2073
is_gen12_ccs_modifier(u64 modifier)2074 static inline bool is_gen12_ccs_modifier(u64 modifier)
2075 {
2076 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
2077 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
2078 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
2079 }
2080
2081 #endif /* __INTEL_DISPLAY_TYPES_H__ */
2082