1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/bitops.h>
3 #include <linux/types.h>
4 #include <linux/slab.h>
5
6 #include <asm/cpu_entry_area.h>
7 #include <asm/perf_event.h>
8 #include <asm/tlbflush.h>
9 #include <asm/insn.h>
10 #include <asm/io.h>
11
12 #include "../perf_event.h"
13
14 /* Waste a full page so it can be mapped into the cpu_entry_area */
15 DEFINE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store);
16
17 /* The size of a BTS record in bytes: */
18 #define BTS_RECORD_SIZE 24
19
20 #define PEBS_FIXUP_SIZE PAGE_SIZE
21
22 /*
23 * pebs_record_32 for p4 and core not supported
24
25 struct pebs_record_32 {
26 u32 flags, ip;
27 u32 ax, bc, cx, dx;
28 u32 si, di, bp, sp;
29 };
30
31 */
32
33 union intel_x86_pebs_dse {
34 u64 val;
35 struct {
36 unsigned int ld_dse:4;
37 unsigned int ld_stlb_miss:1;
38 unsigned int ld_locked:1;
39 unsigned int ld_data_blk:1;
40 unsigned int ld_addr_blk:1;
41 unsigned int ld_reserved:24;
42 };
43 struct {
44 unsigned int st_l1d_hit:1;
45 unsigned int st_reserved1:3;
46 unsigned int st_stlb_miss:1;
47 unsigned int st_locked:1;
48 unsigned int st_reserved2:26;
49 };
50 struct {
51 unsigned int st_lat_dse:4;
52 unsigned int st_lat_stlb_miss:1;
53 unsigned int st_lat_locked:1;
54 unsigned int ld_reserved3:26;
55 };
56 };
57
58
59 /*
60 * Map PEBS Load Latency Data Source encodings to generic
61 * memory data source information
62 */
63 #define P(a, b) PERF_MEM_S(a, b)
64 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
65 #define LEVEL(x) P(LVLNUM, x)
66 #define REM P(REMOTE, REMOTE)
67 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
68
69 /* Version for Sandy Bridge and later */
70 static u64 pebs_data_source[] = {
71 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
72 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 local */
73 OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
74 OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
75 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
76 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
77 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
78 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
79 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
80 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
81 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
82 OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
83 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | SNOOP_NONE_MISS, /* 0x0c: L3 miss, excl */
84 OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */
85 OP_LH | P(LVL, IO) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0e: I/O */
86 OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0f: uncached */
87 };
88
89 /* Patch up minor differences in the bits */
intel_pmu_pebs_data_source_nhm(void)90 void __init intel_pmu_pebs_data_source_nhm(void)
91 {
92 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
93 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
94 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
95 }
96
intel_pmu_pebs_data_source_skl(bool pmem)97 void __init intel_pmu_pebs_data_source_skl(bool pmem)
98 {
99 u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4);
100
101 pebs_data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT);
102 pebs_data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT);
103 pebs_data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE);
104 pebs_data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD);
105 pebs_data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM);
106 }
107
precise_store_data(u64 status)108 static u64 precise_store_data(u64 status)
109 {
110 union intel_x86_pebs_dse dse;
111 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
112
113 dse.val = status;
114
115 /*
116 * bit 4: TLB access
117 * 1 = stored missed 2nd level TLB
118 *
119 * so it either hit the walker or the OS
120 * otherwise hit 2nd level TLB
121 */
122 if (dse.st_stlb_miss)
123 val |= P(TLB, MISS);
124 else
125 val |= P(TLB, HIT);
126
127 /*
128 * bit 0: hit L1 data cache
129 * if not set, then all we know is that
130 * it missed L1D
131 */
132 if (dse.st_l1d_hit)
133 val |= P(LVL, HIT);
134 else
135 val |= P(LVL, MISS);
136
137 /*
138 * bit 5: Locked prefix
139 */
140 if (dse.st_locked)
141 val |= P(LOCK, LOCKED);
142
143 return val;
144 }
145
precise_datala_hsw(struct perf_event * event,u64 status)146 static u64 precise_datala_hsw(struct perf_event *event, u64 status)
147 {
148 union perf_mem_data_src dse;
149
150 dse.val = PERF_MEM_NA;
151
152 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
153 dse.mem_op = PERF_MEM_OP_STORE;
154 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
155 dse.mem_op = PERF_MEM_OP_LOAD;
156
157 /*
158 * L1 info only valid for following events:
159 *
160 * MEM_UOPS_RETIRED.STLB_MISS_STORES
161 * MEM_UOPS_RETIRED.LOCK_STORES
162 * MEM_UOPS_RETIRED.SPLIT_STORES
163 * MEM_UOPS_RETIRED.ALL_STORES
164 */
165 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
166 if (status & 1)
167 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
168 else
169 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
170 }
171 return dse.val;
172 }
173
load_latency_data(u64 status)174 static u64 load_latency_data(u64 status)
175 {
176 union intel_x86_pebs_dse dse;
177 u64 val;
178
179 dse.val = status;
180
181 /*
182 * use the mapping table for bit 0-3
183 */
184 val = pebs_data_source[dse.ld_dse];
185
186 /*
187 * Nehalem models do not support TLB, Lock infos
188 */
189 if (x86_pmu.pebs_no_tlb) {
190 val |= P(TLB, NA) | P(LOCK, NA);
191 return val;
192 }
193 /*
194 * bit 4: TLB access
195 * 0 = did not miss 2nd level TLB
196 * 1 = missed 2nd level TLB
197 */
198 if (dse.ld_stlb_miss)
199 val |= P(TLB, MISS) | P(TLB, L2);
200 else
201 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
202
203 /*
204 * bit 5: locked prefix
205 */
206 if (dse.ld_locked)
207 val |= P(LOCK, LOCKED);
208
209 /*
210 * Ice Lake and earlier models do not support block infos.
211 */
212 if (!x86_pmu.pebs_block) {
213 val |= P(BLK, NA);
214 return val;
215 }
216 /*
217 * bit 6: load was blocked since its data could not be forwarded
218 * from a preceding store
219 */
220 if (dse.ld_data_blk)
221 val |= P(BLK, DATA);
222
223 /*
224 * bit 7: load was blocked due to potential address conflict with
225 * a preceding store
226 */
227 if (dse.ld_addr_blk)
228 val |= P(BLK, ADDR);
229
230 if (!dse.ld_data_blk && !dse.ld_addr_blk)
231 val |= P(BLK, NA);
232
233 return val;
234 }
235
store_latency_data(u64 status)236 static u64 store_latency_data(u64 status)
237 {
238 union intel_x86_pebs_dse dse;
239 union perf_mem_data_src src;
240 u64 val;
241
242 dse.val = status;
243
244 /*
245 * use the mapping table for bit 0-3
246 */
247 val = pebs_data_source[dse.st_lat_dse];
248
249 /*
250 * bit 4: TLB access
251 * 0 = did not miss 2nd level TLB
252 * 1 = missed 2nd level TLB
253 */
254 if (dse.st_lat_stlb_miss)
255 val |= P(TLB, MISS) | P(TLB, L2);
256 else
257 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
258
259 /*
260 * bit 5: locked prefix
261 */
262 if (dse.st_lat_locked)
263 val |= P(LOCK, LOCKED);
264
265 val |= P(BLK, NA);
266
267 /*
268 * the pebs_data_source table is only for loads
269 * so override the mem_op to say STORE instead
270 */
271 src.val = val;
272 src.mem_op = P(OP,STORE);
273
274 return src.val;
275 }
276
277 struct pebs_record_core {
278 u64 flags, ip;
279 u64 ax, bx, cx, dx;
280 u64 si, di, bp, sp;
281 u64 r8, r9, r10, r11;
282 u64 r12, r13, r14, r15;
283 };
284
285 struct pebs_record_nhm {
286 u64 flags, ip;
287 u64 ax, bx, cx, dx;
288 u64 si, di, bp, sp;
289 u64 r8, r9, r10, r11;
290 u64 r12, r13, r14, r15;
291 u64 status, dla, dse, lat;
292 };
293
294 /*
295 * Same as pebs_record_nhm, with two additional fields.
296 */
297 struct pebs_record_hsw {
298 u64 flags, ip;
299 u64 ax, bx, cx, dx;
300 u64 si, di, bp, sp;
301 u64 r8, r9, r10, r11;
302 u64 r12, r13, r14, r15;
303 u64 status, dla, dse, lat;
304 u64 real_ip, tsx_tuning;
305 };
306
307 union hsw_tsx_tuning {
308 struct {
309 u32 cycles_last_block : 32,
310 hle_abort : 1,
311 rtm_abort : 1,
312 instruction_abort : 1,
313 non_instruction_abort : 1,
314 retry : 1,
315 data_conflict : 1,
316 capacity_writes : 1,
317 capacity_reads : 1;
318 };
319 u64 value;
320 };
321
322 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
323
324 /* Same as HSW, plus TSC */
325
326 struct pebs_record_skl {
327 u64 flags, ip;
328 u64 ax, bx, cx, dx;
329 u64 si, di, bp, sp;
330 u64 r8, r9, r10, r11;
331 u64 r12, r13, r14, r15;
332 u64 status, dla, dse, lat;
333 u64 real_ip, tsx_tuning;
334 u64 tsc;
335 };
336
init_debug_store_on_cpu(int cpu)337 void init_debug_store_on_cpu(int cpu)
338 {
339 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
340
341 if (!ds)
342 return;
343
344 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
345 (u32)((u64)(unsigned long)ds),
346 (u32)((u64)(unsigned long)ds >> 32));
347 }
348
fini_debug_store_on_cpu(int cpu)349 void fini_debug_store_on_cpu(int cpu)
350 {
351 if (!per_cpu(cpu_hw_events, cpu).ds)
352 return;
353
354 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
355 }
356
357 static DEFINE_PER_CPU(void *, insn_buffer);
358
ds_update_cea(void * cea,void * addr,size_t size,pgprot_t prot)359 static void ds_update_cea(void *cea, void *addr, size_t size, pgprot_t prot)
360 {
361 unsigned long start = (unsigned long)cea;
362 phys_addr_t pa;
363 size_t msz = 0;
364
365 pa = virt_to_phys(addr);
366
367 preempt_disable();
368 for (; msz < size; msz += PAGE_SIZE, pa += PAGE_SIZE, cea += PAGE_SIZE)
369 cea_set_pte(cea, pa, prot);
370
371 /*
372 * This is a cross-CPU update of the cpu_entry_area, we must shoot down
373 * all TLB entries for it.
374 */
375 flush_tlb_kernel_range(start, start + size);
376 preempt_enable();
377 }
378
ds_clear_cea(void * cea,size_t size)379 static void ds_clear_cea(void *cea, size_t size)
380 {
381 unsigned long start = (unsigned long)cea;
382 size_t msz = 0;
383
384 preempt_disable();
385 for (; msz < size; msz += PAGE_SIZE, cea += PAGE_SIZE)
386 cea_set_pte(cea, 0, PAGE_NONE);
387
388 flush_tlb_kernel_range(start, start + size);
389 preempt_enable();
390 }
391
dsalloc_pages(size_t size,gfp_t flags,int cpu)392 static void *dsalloc_pages(size_t size, gfp_t flags, int cpu)
393 {
394 unsigned int order = get_order(size);
395 int node = cpu_to_node(cpu);
396 struct page *page;
397
398 page = __alloc_pages_node(node, flags | __GFP_ZERO, order);
399 return page ? page_address(page) : NULL;
400 }
401
dsfree_pages(const void * buffer,size_t size)402 static void dsfree_pages(const void *buffer, size_t size)
403 {
404 if (buffer)
405 free_pages((unsigned long)buffer, get_order(size));
406 }
407
alloc_pebs_buffer(int cpu)408 static int alloc_pebs_buffer(int cpu)
409 {
410 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
411 struct debug_store *ds = hwev->ds;
412 size_t bsiz = x86_pmu.pebs_buffer_size;
413 int max, node = cpu_to_node(cpu);
414 void *buffer, *insn_buff, *cea;
415
416 if (!x86_pmu.pebs)
417 return 0;
418
419 buffer = dsalloc_pages(bsiz, GFP_KERNEL, cpu);
420 if (unlikely(!buffer))
421 return -ENOMEM;
422
423 /*
424 * HSW+ already provides us the eventing ip; no need to allocate this
425 * buffer then.
426 */
427 if (x86_pmu.intel_cap.pebs_format < 2) {
428 insn_buff = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
429 if (!insn_buff) {
430 dsfree_pages(buffer, bsiz);
431 return -ENOMEM;
432 }
433 per_cpu(insn_buffer, cpu) = insn_buff;
434 }
435 hwev->ds_pebs_vaddr = buffer;
436 /* Update the cpu entry area mapping */
437 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
438 ds->pebs_buffer_base = (unsigned long) cea;
439 ds_update_cea(cea, buffer, bsiz, PAGE_KERNEL);
440 ds->pebs_index = ds->pebs_buffer_base;
441 max = x86_pmu.pebs_record_size * (bsiz / x86_pmu.pebs_record_size);
442 ds->pebs_absolute_maximum = ds->pebs_buffer_base + max;
443 return 0;
444 }
445
release_pebs_buffer(int cpu)446 static void release_pebs_buffer(int cpu)
447 {
448 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
449 void *cea;
450
451 if (!x86_pmu.pebs)
452 return;
453
454 kfree(per_cpu(insn_buffer, cpu));
455 per_cpu(insn_buffer, cpu) = NULL;
456
457 /* Clear the fixmap */
458 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
459 ds_clear_cea(cea, x86_pmu.pebs_buffer_size);
460 dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size);
461 hwev->ds_pebs_vaddr = NULL;
462 }
463
alloc_bts_buffer(int cpu)464 static int alloc_bts_buffer(int cpu)
465 {
466 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
467 struct debug_store *ds = hwev->ds;
468 void *buffer, *cea;
469 int max;
470
471 if (!x86_pmu.bts)
472 return 0;
473
474 buffer = dsalloc_pages(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, cpu);
475 if (unlikely(!buffer)) {
476 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
477 return -ENOMEM;
478 }
479 hwev->ds_bts_vaddr = buffer;
480 /* Update the fixmap */
481 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer;
482 ds->bts_buffer_base = (unsigned long) cea;
483 ds_update_cea(cea, buffer, BTS_BUFFER_SIZE, PAGE_KERNEL);
484 ds->bts_index = ds->bts_buffer_base;
485 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
486 ds->bts_absolute_maximum = ds->bts_buffer_base +
487 max * BTS_RECORD_SIZE;
488 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
489 (max / 16) * BTS_RECORD_SIZE;
490 return 0;
491 }
492
release_bts_buffer(int cpu)493 static void release_bts_buffer(int cpu)
494 {
495 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
496 void *cea;
497
498 if (!x86_pmu.bts)
499 return;
500
501 /* Clear the fixmap */
502 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer;
503 ds_clear_cea(cea, BTS_BUFFER_SIZE);
504 dsfree_pages(hwev->ds_bts_vaddr, BTS_BUFFER_SIZE);
505 hwev->ds_bts_vaddr = NULL;
506 }
507
alloc_ds_buffer(int cpu)508 static int alloc_ds_buffer(int cpu)
509 {
510 struct debug_store *ds = &get_cpu_entry_area(cpu)->cpu_debug_store;
511
512 memset(ds, 0, sizeof(*ds));
513 per_cpu(cpu_hw_events, cpu).ds = ds;
514 return 0;
515 }
516
release_ds_buffer(int cpu)517 static void release_ds_buffer(int cpu)
518 {
519 per_cpu(cpu_hw_events, cpu).ds = NULL;
520 }
521
release_ds_buffers(void)522 void release_ds_buffers(void)
523 {
524 int cpu;
525
526 if (!x86_pmu.bts && !x86_pmu.pebs)
527 return;
528
529 for_each_possible_cpu(cpu)
530 release_ds_buffer(cpu);
531
532 for_each_possible_cpu(cpu) {
533 /*
534 * Again, ignore errors from offline CPUs, they will no longer
535 * observe cpu_hw_events.ds and not program the DS_AREA when
536 * they come up.
537 */
538 fini_debug_store_on_cpu(cpu);
539 }
540
541 for_each_possible_cpu(cpu) {
542 release_pebs_buffer(cpu);
543 release_bts_buffer(cpu);
544 }
545 }
546
reserve_ds_buffers(void)547 void reserve_ds_buffers(void)
548 {
549 int bts_err = 0, pebs_err = 0;
550 int cpu;
551
552 x86_pmu.bts_active = 0;
553 x86_pmu.pebs_active = 0;
554
555 if (!x86_pmu.bts && !x86_pmu.pebs)
556 return;
557
558 if (!x86_pmu.bts)
559 bts_err = 1;
560
561 if (!x86_pmu.pebs)
562 pebs_err = 1;
563
564 for_each_possible_cpu(cpu) {
565 if (alloc_ds_buffer(cpu)) {
566 bts_err = 1;
567 pebs_err = 1;
568 }
569
570 if (!bts_err && alloc_bts_buffer(cpu))
571 bts_err = 1;
572
573 if (!pebs_err && alloc_pebs_buffer(cpu))
574 pebs_err = 1;
575
576 if (bts_err && pebs_err)
577 break;
578 }
579
580 if (bts_err) {
581 for_each_possible_cpu(cpu)
582 release_bts_buffer(cpu);
583 }
584
585 if (pebs_err) {
586 for_each_possible_cpu(cpu)
587 release_pebs_buffer(cpu);
588 }
589
590 if (bts_err && pebs_err) {
591 for_each_possible_cpu(cpu)
592 release_ds_buffer(cpu);
593 } else {
594 if (x86_pmu.bts && !bts_err)
595 x86_pmu.bts_active = 1;
596
597 if (x86_pmu.pebs && !pebs_err)
598 x86_pmu.pebs_active = 1;
599
600 for_each_possible_cpu(cpu) {
601 /*
602 * Ignores wrmsr_on_cpu() errors for offline CPUs they
603 * will get this call through intel_pmu_cpu_starting().
604 */
605 init_debug_store_on_cpu(cpu);
606 }
607 }
608 }
609
610 /*
611 * BTS
612 */
613
614 struct event_constraint bts_constraint =
615 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
616
intel_pmu_enable_bts(u64 config)617 void intel_pmu_enable_bts(u64 config)
618 {
619 unsigned long debugctlmsr;
620
621 debugctlmsr = get_debugctlmsr();
622
623 debugctlmsr |= DEBUGCTLMSR_TR;
624 debugctlmsr |= DEBUGCTLMSR_BTS;
625 if (config & ARCH_PERFMON_EVENTSEL_INT)
626 debugctlmsr |= DEBUGCTLMSR_BTINT;
627
628 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
629 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
630
631 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
632 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
633
634 update_debugctlmsr(debugctlmsr);
635 }
636
intel_pmu_disable_bts(void)637 void intel_pmu_disable_bts(void)
638 {
639 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
640 unsigned long debugctlmsr;
641
642 if (!cpuc->ds)
643 return;
644
645 debugctlmsr = get_debugctlmsr();
646
647 debugctlmsr &=
648 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
649 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
650
651 update_debugctlmsr(debugctlmsr);
652 }
653
intel_pmu_drain_bts_buffer(void)654 int intel_pmu_drain_bts_buffer(void)
655 {
656 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
657 struct debug_store *ds = cpuc->ds;
658 struct bts_record {
659 u64 from;
660 u64 to;
661 u64 flags;
662 };
663 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
664 struct bts_record *at, *base, *top;
665 struct perf_output_handle handle;
666 struct perf_event_header header;
667 struct perf_sample_data data;
668 unsigned long skip = 0;
669 struct pt_regs regs;
670
671 if (!event)
672 return 0;
673
674 if (!x86_pmu.bts_active)
675 return 0;
676
677 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
678 top = (struct bts_record *)(unsigned long)ds->bts_index;
679
680 if (top <= base)
681 return 0;
682
683 memset(®s, 0, sizeof(regs));
684
685 ds->bts_index = ds->bts_buffer_base;
686
687 perf_sample_data_init(&data, 0, event->hw.last_period);
688
689 /*
690 * BTS leaks kernel addresses in branches across the cpl boundary,
691 * such as traps or system calls, so unless the user is asking for
692 * kernel tracing (and right now it's not possible), we'd need to
693 * filter them out. But first we need to count how many of those we
694 * have in the current batch. This is an extra O(n) pass, however,
695 * it's much faster than the other one especially considering that
696 * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the
697 * alloc_bts_buffer()).
698 */
699 for (at = base; at < top; at++) {
700 /*
701 * Note that right now *this* BTS code only works if
702 * attr::exclude_kernel is set, but let's keep this extra
703 * check here in case that changes.
704 */
705 if (event->attr.exclude_kernel &&
706 (kernel_ip(at->from) || kernel_ip(at->to)))
707 skip++;
708 }
709
710 /*
711 * Prepare a generic sample, i.e. fill in the invariant fields.
712 * We will overwrite the from and to address before we output
713 * the sample.
714 */
715 rcu_read_lock();
716 perf_prepare_sample(&header, &data, event, ®s);
717
718 if (perf_output_begin(&handle, &data, event,
719 header.size * (top - base - skip)))
720 goto unlock;
721
722 for (at = base; at < top; at++) {
723 /* Filter out any records that contain kernel addresses. */
724 if (event->attr.exclude_kernel &&
725 (kernel_ip(at->from) || kernel_ip(at->to)))
726 continue;
727
728 data.ip = at->from;
729 data.addr = at->to;
730
731 perf_output_sample(&handle, &header, &data, event);
732 }
733
734 perf_output_end(&handle);
735
736 /* There's new data available. */
737 event->hw.interrupts++;
738 event->pending_kill = POLL_IN;
739 unlock:
740 rcu_read_unlock();
741 return 1;
742 }
743
intel_pmu_drain_pebs_buffer(void)744 static inline void intel_pmu_drain_pebs_buffer(void)
745 {
746 struct perf_sample_data data;
747
748 x86_pmu.drain_pebs(NULL, &data);
749 }
750
751 /*
752 * PEBS
753 */
754 struct event_constraint intel_core2_pebs_event_constraints[] = {
755 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
756 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
757 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
758 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
759 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
760 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
761 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
762 EVENT_CONSTRAINT_END
763 };
764
765 struct event_constraint intel_atom_pebs_event_constraints[] = {
766 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
767 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
768 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
769 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
770 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
771 /* Allow all events as PEBS with no flags */
772 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
773 EVENT_CONSTRAINT_END
774 };
775
776 struct event_constraint intel_slm_pebs_event_constraints[] = {
777 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
778 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x1),
779 /* Allow all events as PEBS with no flags */
780 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
781 EVENT_CONSTRAINT_END
782 };
783
784 struct event_constraint intel_glm_pebs_event_constraints[] = {
785 /* Allow all events as PEBS with no flags */
786 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
787 EVENT_CONSTRAINT_END
788 };
789
790 struct event_constraint intel_grt_pebs_event_constraints[] = {
791 /* Allow all events as PEBS with no flags */
792 INTEL_PLD_CONSTRAINT(0x5d0, 0xf),
793 INTEL_PSD_CONSTRAINT(0x6d0, 0xf),
794 EVENT_CONSTRAINT_END
795 };
796
797 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
798 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
799 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
800 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
801 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
802 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
803 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
804 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
805 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
806 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
807 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
808 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
809 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
810 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
811 EVENT_CONSTRAINT_END
812 };
813
814 struct event_constraint intel_westmere_pebs_event_constraints[] = {
815 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
816 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
817 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
818 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
819 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
820 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
821 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
822 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
823 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
824 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
825 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
826 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
827 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
828 EVENT_CONSTRAINT_END
829 };
830
831 struct event_constraint intel_snb_pebs_event_constraints[] = {
832 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
833 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
834 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
835 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
836 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
837 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
838 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
839 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
840 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
841 /* Allow all events as PEBS with no flags */
842 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
843 EVENT_CONSTRAINT_END
844 };
845
846 struct event_constraint intel_ivb_pebs_event_constraints[] = {
847 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
848 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
849 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
850 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
851 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
852 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
853 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
854 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
855 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
856 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
857 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
858 /* Allow all events as PEBS with no flags */
859 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
860 EVENT_CONSTRAINT_END
861 };
862
863 struct event_constraint intel_hsw_pebs_event_constraints[] = {
864 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
865 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
866 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
867 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
868 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
869 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
870 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
871 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
872 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
873 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
874 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
875 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
876 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
877 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
878 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
879 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
880 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
881 /* Allow all events as PEBS with no flags */
882 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
883 EVENT_CONSTRAINT_END
884 };
885
886 struct event_constraint intel_bdw_pebs_event_constraints[] = {
887 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
888 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
889 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
890 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
891 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
892 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
893 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
894 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
895 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
896 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
897 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
898 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
899 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
900 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
901 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
902 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
903 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
904 /* Allow all events as PEBS with no flags */
905 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
906 EVENT_CONSTRAINT_END
907 };
908
909
910 struct event_constraint intel_skl_pebs_event_constraints[] = {
911 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
912 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
913 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
914 /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */
915 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
916 INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */
917 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
918 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
919 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
920 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
921 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
922 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
923 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
924 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
925 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
926 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
927 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */
928 /* Allow all events as PEBS with no flags */
929 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
930 EVENT_CONSTRAINT_END
931 };
932
933 struct event_constraint intel_icl_pebs_event_constraints[] = {
934 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x100000000ULL), /* old INST_RETIRED.PREC_DIST */
935 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
936 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), /* SLOTS */
937
938 INTEL_PLD_CONSTRAINT(0x1cd, 0xff), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
939 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
940 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
941 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
942 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
943 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
944 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
945 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
946
947 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf), /* MEM_LOAD_*_RETIRED.* */
948
949 INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
950
951 /*
952 * Everything else is handled by PMU_FL_PEBS_ALL, because we
953 * need the full constraints from the main table.
954 */
955
956 EVENT_CONSTRAINT_END
957 };
958
959 struct event_constraint intel_spr_pebs_event_constraints[] = {
960 INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
961 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
962
963 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xfe),
964 INTEL_PLD_CONSTRAINT(0x1cd, 0xfe),
965 INTEL_PSD_CONSTRAINT(0x2cd, 0x1),
966 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
967 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
968 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
969 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
970 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
971 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
972 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
973
974 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),
975
976 INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf),
977
978 /*
979 * Everything else is handled by PMU_FL_PEBS_ALL, because we
980 * need the full constraints from the main table.
981 */
982
983 EVENT_CONSTRAINT_END
984 };
985
intel_pebs_constraints(struct perf_event * event)986 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
987 {
988 struct event_constraint *pebs_constraints = hybrid(event->pmu, pebs_constraints);
989 struct event_constraint *c;
990
991 if (!event->attr.precise_ip)
992 return NULL;
993
994 if (pebs_constraints) {
995 for_each_event_constraint(c, pebs_constraints) {
996 if (constraint_match(c, event->hw.config)) {
997 event->hw.flags |= c->flags;
998 return c;
999 }
1000 }
1001 }
1002
1003 /*
1004 * Extended PEBS support
1005 * Makes the PEBS code search the normal constraints.
1006 */
1007 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
1008 return NULL;
1009
1010 return &emptyconstraint;
1011 }
1012
1013 /*
1014 * We need the sched_task callback even for per-cpu events when we use
1015 * the large interrupt threshold, such that we can provide PID and TID
1016 * to PEBS samples.
1017 */
pebs_needs_sched_cb(struct cpu_hw_events * cpuc)1018 static inline bool pebs_needs_sched_cb(struct cpu_hw_events *cpuc)
1019 {
1020 if (cpuc->n_pebs == cpuc->n_pebs_via_pt)
1021 return false;
1022
1023 return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs);
1024 }
1025
intel_pmu_pebs_sched_task(struct perf_event_context * ctx,bool sched_in)1026 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
1027 {
1028 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1029
1030 if (!sched_in && pebs_needs_sched_cb(cpuc))
1031 intel_pmu_drain_pebs_buffer();
1032 }
1033
pebs_update_threshold(struct cpu_hw_events * cpuc)1034 static inline void pebs_update_threshold(struct cpu_hw_events *cpuc)
1035 {
1036 struct debug_store *ds = cpuc->ds;
1037 int max_pebs_events = hybrid(cpuc->pmu, max_pebs_events);
1038 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
1039 u64 threshold;
1040 int reserved;
1041
1042 if (cpuc->n_pebs_via_pt)
1043 return;
1044
1045 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
1046 reserved = max_pebs_events + num_counters_fixed;
1047 else
1048 reserved = max_pebs_events;
1049
1050 if (cpuc->n_pebs == cpuc->n_large_pebs) {
1051 threshold = ds->pebs_absolute_maximum -
1052 reserved * cpuc->pebs_record_size;
1053 } else {
1054 threshold = ds->pebs_buffer_base + cpuc->pebs_record_size;
1055 }
1056
1057 ds->pebs_interrupt_threshold = threshold;
1058 }
1059
adaptive_pebs_record_size_update(void)1060 static void adaptive_pebs_record_size_update(void)
1061 {
1062 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1063 u64 pebs_data_cfg = cpuc->pebs_data_cfg;
1064 int sz = sizeof(struct pebs_basic);
1065
1066 if (pebs_data_cfg & PEBS_DATACFG_MEMINFO)
1067 sz += sizeof(struct pebs_meminfo);
1068 if (pebs_data_cfg & PEBS_DATACFG_GP)
1069 sz += sizeof(struct pebs_gprs);
1070 if (pebs_data_cfg & PEBS_DATACFG_XMMS)
1071 sz += sizeof(struct pebs_xmm);
1072 if (pebs_data_cfg & PEBS_DATACFG_LBRS)
1073 sz += x86_pmu.lbr_nr * sizeof(struct lbr_entry);
1074
1075 cpuc->pebs_record_size = sz;
1076 }
1077
1078 #define PERF_PEBS_MEMINFO_TYPE (PERF_SAMPLE_ADDR | PERF_SAMPLE_DATA_SRC | \
1079 PERF_SAMPLE_PHYS_ADDR | \
1080 PERF_SAMPLE_WEIGHT_TYPE | \
1081 PERF_SAMPLE_TRANSACTION | \
1082 PERF_SAMPLE_DATA_PAGE_SIZE)
1083
pebs_update_adaptive_cfg(struct perf_event * event)1084 static u64 pebs_update_adaptive_cfg(struct perf_event *event)
1085 {
1086 struct perf_event_attr *attr = &event->attr;
1087 u64 sample_type = attr->sample_type;
1088 u64 pebs_data_cfg = 0;
1089 bool gprs, tsx_weight;
1090
1091 if (!(sample_type & ~(PERF_SAMPLE_IP|PERF_SAMPLE_TIME)) &&
1092 attr->precise_ip > 1)
1093 return pebs_data_cfg;
1094
1095 if (sample_type & PERF_PEBS_MEMINFO_TYPE)
1096 pebs_data_cfg |= PEBS_DATACFG_MEMINFO;
1097
1098 /*
1099 * We need GPRs when:
1100 * + user requested them
1101 * + precise_ip < 2 for the non event IP
1102 * + For RTM TSX weight we need GPRs for the abort code.
1103 */
1104 gprs = (sample_type & PERF_SAMPLE_REGS_INTR) &&
1105 (attr->sample_regs_intr & PEBS_GP_REGS);
1106
1107 tsx_weight = (sample_type & PERF_SAMPLE_WEIGHT_TYPE) &&
1108 ((attr->config & INTEL_ARCH_EVENT_MASK) ==
1109 x86_pmu.rtm_abort_event);
1110
1111 if (gprs || (attr->precise_ip < 2) || tsx_weight)
1112 pebs_data_cfg |= PEBS_DATACFG_GP;
1113
1114 if ((sample_type & PERF_SAMPLE_REGS_INTR) &&
1115 (attr->sample_regs_intr & PERF_REG_EXTENDED_MASK))
1116 pebs_data_cfg |= PEBS_DATACFG_XMMS;
1117
1118 if (sample_type & PERF_SAMPLE_BRANCH_STACK) {
1119 /*
1120 * For now always log all LBRs. Could configure this
1121 * later.
1122 */
1123 pebs_data_cfg |= PEBS_DATACFG_LBRS |
1124 ((x86_pmu.lbr_nr-1) << PEBS_DATACFG_LBR_SHIFT);
1125 }
1126
1127 return pebs_data_cfg;
1128 }
1129
1130 static void
pebs_update_state(bool needed_cb,struct cpu_hw_events * cpuc,struct perf_event * event,bool add)1131 pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc,
1132 struct perf_event *event, bool add)
1133 {
1134 struct pmu *pmu = event->ctx->pmu;
1135 /*
1136 * Make sure we get updated with the first PEBS
1137 * event. It will trigger also during removal, but
1138 * that does not hurt:
1139 */
1140 bool update = cpuc->n_pebs == 1;
1141
1142 if (needed_cb != pebs_needs_sched_cb(cpuc)) {
1143 if (!needed_cb)
1144 perf_sched_cb_inc(pmu);
1145 else
1146 perf_sched_cb_dec(pmu);
1147
1148 update = true;
1149 }
1150
1151 /*
1152 * The PEBS record doesn't shrink on pmu::del(). Doing so would require
1153 * iterating all remaining PEBS events to reconstruct the config.
1154 */
1155 if (x86_pmu.intel_cap.pebs_baseline && add) {
1156 u64 pebs_data_cfg;
1157
1158 /* Clear pebs_data_cfg and pebs_record_size for first PEBS. */
1159 if (cpuc->n_pebs == 1) {
1160 cpuc->pebs_data_cfg = 0;
1161 cpuc->pebs_record_size = sizeof(struct pebs_basic);
1162 }
1163
1164 pebs_data_cfg = pebs_update_adaptive_cfg(event);
1165
1166 /* Update pebs_record_size if new event requires more data. */
1167 if (pebs_data_cfg & ~cpuc->pebs_data_cfg) {
1168 cpuc->pebs_data_cfg |= pebs_data_cfg;
1169 adaptive_pebs_record_size_update();
1170 update = true;
1171 }
1172 }
1173
1174 if (update)
1175 pebs_update_threshold(cpuc);
1176 }
1177
intel_pmu_pebs_add(struct perf_event * event)1178 void intel_pmu_pebs_add(struct perf_event *event)
1179 {
1180 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1181 struct hw_perf_event *hwc = &event->hw;
1182 bool needed_cb = pebs_needs_sched_cb(cpuc);
1183
1184 cpuc->n_pebs++;
1185 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
1186 cpuc->n_large_pebs++;
1187 if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT)
1188 cpuc->n_pebs_via_pt++;
1189
1190 pebs_update_state(needed_cb, cpuc, event, true);
1191 }
1192
intel_pmu_pebs_via_pt_disable(struct perf_event * event)1193 static void intel_pmu_pebs_via_pt_disable(struct perf_event *event)
1194 {
1195 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1196
1197 if (!is_pebs_pt(event))
1198 return;
1199
1200 if (!(cpuc->pebs_enabled & ~PEBS_VIA_PT_MASK))
1201 cpuc->pebs_enabled &= ~PEBS_VIA_PT_MASK;
1202 }
1203
intel_pmu_pebs_via_pt_enable(struct perf_event * event)1204 static void intel_pmu_pebs_via_pt_enable(struct perf_event *event)
1205 {
1206 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1207 struct hw_perf_event *hwc = &event->hw;
1208 struct debug_store *ds = cpuc->ds;
1209 u64 value = ds->pebs_event_reset[hwc->idx];
1210 u32 base = MSR_RELOAD_PMC0;
1211 unsigned int idx = hwc->idx;
1212
1213 if (!is_pebs_pt(event))
1214 return;
1215
1216 if (!(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
1217 cpuc->pebs_enabled |= PEBS_PMI_AFTER_EACH_RECORD;
1218
1219 cpuc->pebs_enabled |= PEBS_OUTPUT_PT;
1220
1221 if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
1222 base = MSR_RELOAD_FIXED_CTR0;
1223 idx = hwc->idx - INTEL_PMC_IDX_FIXED;
1224 value = ds->pebs_event_reset[MAX_PEBS_EVENTS + idx];
1225 }
1226 wrmsrl(base + idx, value);
1227 }
1228
intel_pmu_pebs_enable(struct perf_event * event)1229 void intel_pmu_pebs_enable(struct perf_event *event)
1230 {
1231 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1232 struct hw_perf_event *hwc = &event->hw;
1233 struct debug_store *ds = cpuc->ds;
1234 unsigned int idx = hwc->idx;
1235
1236 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
1237
1238 cpuc->pebs_enabled |= 1ULL << hwc->idx;
1239
1240 if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && (x86_pmu.version < 5))
1241 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
1242 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
1243 cpuc->pebs_enabled |= 1ULL << 63;
1244
1245 if (x86_pmu.intel_cap.pebs_baseline) {
1246 hwc->config |= ICL_EVENTSEL_ADAPTIVE;
1247 if (cpuc->pebs_data_cfg != cpuc->active_pebs_data_cfg) {
1248 wrmsrl(MSR_PEBS_DATA_CFG, cpuc->pebs_data_cfg);
1249 cpuc->active_pebs_data_cfg = cpuc->pebs_data_cfg;
1250 }
1251 }
1252
1253 if (idx >= INTEL_PMC_IDX_FIXED)
1254 idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED);
1255
1256 /*
1257 * Use auto-reload if possible to save a MSR write in the PMI.
1258 * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD.
1259 */
1260 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
1261 ds->pebs_event_reset[idx] =
1262 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
1263 } else {
1264 ds->pebs_event_reset[idx] = 0;
1265 }
1266
1267 intel_pmu_pebs_via_pt_enable(event);
1268 }
1269
intel_pmu_pebs_del(struct perf_event * event)1270 void intel_pmu_pebs_del(struct perf_event *event)
1271 {
1272 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1273 struct hw_perf_event *hwc = &event->hw;
1274 bool needed_cb = pebs_needs_sched_cb(cpuc);
1275
1276 cpuc->n_pebs--;
1277 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
1278 cpuc->n_large_pebs--;
1279 if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT)
1280 cpuc->n_pebs_via_pt--;
1281
1282 pebs_update_state(needed_cb, cpuc, event, false);
1283 }
1284
intel_pmu_pebs_disable(struct perf_event * event)1285 void intel_pmu_pebs_disable(struct perf_event *event)
1286 {
1287 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1288 struct hw_perf_event *hwc = &event->hw;
1289
1290 if (cpuc->n_pebs == cpuc->n_large_pebs &&
1291 cpuc->n_pebs != cpuc->n_pebs_via_pt)
1292 intel_pmu_drain_pebs_buffer();
1293
1294 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
1295
1296 if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) &&
1297 (x86_pmu.version < 5))
1298 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
1299 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
1300 cpuc->pebs_enabled &= ~(1ULL << 63);
1301
1302 intel_pmu_pebs_via_pt_disable(event);
1303
1304 if (cpuc->enabled)
1305 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
1306
1307 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
1308 }
1309
intel_pmu_pebs_enable_all(void)1310 void intel_pmu_pebs_enable_all(void)
1311 {
1312 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1313
1314 if (cpuc->pebs_enabled)
1315 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
1316 }
1317
intel_pmu_pebs_disable_all(void)1318 void intel_pmu_pebs_disable_all(void)
1319 {
1320 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1321
1322 if (cpuc->pebs_enabled)
1323 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1324 }
1325
intel_pmu_pebs_fixup_ip(struct pt_regs * regs)1326 static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
1327 {
1328 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1329 unsigned long from = cpuc->lbr_entries[0].from;
1330 unsigned long old_to, to = cpuc->lbr_entries[0].to;
1331 unsigned long ip = regs->ip;
1332 int is_64bit = 0;
1333 void *kaddr;
1334 int size;
1335
1336 /*
1337 * We don't need to fixup if the PEBS assist is fault like
1338 */
1339 if (!x86_pmu.intel_cap.pebs_trap)
1340 return 1;
1341
1342 /*
1343 * No LBR entry, no basic block, no rewinding
1344 */
1345 if (!cpuc->lbr_stack.nr || !from || !to)
1346 return 0;
1347
1348 /*
1349 * Basic blocks should never cross user/kernel boundaries
1350 */
1351 if (kernel_ip(ip) != kernel_ip(to))
1352 return 0;
1353
1354 /*
1355 * unsigned math, either ip is before the start (impossible) or
1356 * the basic block is larger than 1 page (sanity)
1357 */
1358 if ((ip - to) > PEBS_FIXUP_SIZE)
1359 return 0;
1360
1361 /*
1362 * We sampled a branch insn, rewind using the LBR stack
1363 */
1364 if (ip == to) {
1365 set_linear_ip(regs, from);
1366 return 1;
1367 }
1368
1369 size = ip - to;
1370 if (!kernel_ip(ip)) {
1371 int bytes;
1372 u8 *buf = this_cpu_read(insn_buffer);
1373
1374 /* 'size' must fit our buffer, see above */
1375 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
1376 if (bytes != 0)
1377 return 0;
1378
1379 kaddr = buf;
1380 } else {
1381 kaddr = (void *)to;
1382 }
1383
1384 do {
1385 struct insn insn;
1386
1387 old_to = to;
1388
1389 #ifdef CONFIG_X86_64
1390 is_64bit = kernel_ip(to) || any_64bit_mode(regs);
1391 #endif
1392 insn_init(&insn, kaddr, size, is_64bit);
1393
1394 /*
1395 * Make sure there was not a problem decoding the instruction.
1396 * This is doubly important because we have an infinite loop if
1397 * insn.length=0.
1398 */
1399 if (insn_get_length(&insn))
1400 break;
1401
1402 to += insn.length;
1403 kaddr += insn.length;
1404 size -= insn.length;
1405 } while (to < ip);
1406
1407 if (to == ip) {
1408 set_linear_ip(regs, old_to);
1409 return 1;
1410 }
1411
1412 /*
1413 * Even though we decoded the basic block, the instruction stream
1414 * never matched the given IP, either the TO or the IP got corrupted.
1415 */
1416 return 0;
1417 }
1418
intel_get_tsx_weight(u64 tsx_tuning)1419 static inline u64 intel_get_tsx_weight(u64 tsx_tuning)
1420 {
1421 if (tsx_tuning) {
1422 union hsw_tsx_tuning tsx = { .value = tsx_tuning };
1423 return tsx.cycles_last_block;
1424 }
1425 return 0;
1426 }
1427
intel_get_tsx_transaction(u64 tsx_tuning,u64 ax)1428 static inline u64 intel_get_tsx_transaction(u64 tsx_tuning, u64 ax)
1429 {
1430 u64 txn = (tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
1431
1432 /* For RTM XABORTs also log the abort code from AX */
1433 if ((txn & PERF_TXN_TRANSACTION) && (ax & 1))
1434 txn |= ((ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
1435 return txn;
1436 }
1437
get_pebs_status(void * n)1438 static inline u64 get_pebs_status(void *n)
1439 {
1440 if (x86_pmu.intel_cap.pebs_format < 4)
1441 return ((struct pebs_record_nhm *)n)->status;
1442 return ((struct pebs_basic *)n)->applicable_counters;
1443 }
1444
1445 #define PERF_X86_EVENT_PEBS_HSW_PREC \
1446 (PERF_X86_EVENT_PEBS_ST_HSW | \
1447 PERF_X86_EVENT_PEBS_LD_HSW | \
1448 PERF_X86_EVENT_PEBS_NA_HSW)
1449
get_data_src(struct perf_event * event,u64 aux)1450 static u64 get_data_src(struct perf_event *event, u64 aux)
1451 {
1452 u64 val = PERF_MEM_NA;
1453 int fl = event->hw.flags;
1454 bool fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
1455
1456 if (fl & PERF_X86_EVENT_PEBS_LDLAT)
1457 val = load_latency_data(aux);
1458 else if (fl & PERF_X86_EVENT_PEBS_STLAT)
1459 val = store_latency_data(aux);
1460 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
1461 val = precise_datala_hsw(event, aux);
1462 else if (fst)
1463 val = precise_store_data(aux);
1464 return val;
1465 }
1466
1467 #define PERF_SAMPLE_ADDR_TYPE (PERF_SAMPLE_ADDR | \
1468 PERF_SAMPLE_PHYS_ADDR | \
1469 PERF_SAMPLE_DATA_PAGE_SIZE)
1470
setup_pebs_fixed_sample_data(struct perf_event * event,struct pt_regs * iregs,void * __pebs,struct perf_sample_data * data,struct pt_regs * regs)1471 static void setup_pebs_fixed_sample_data(struct perf_event *event,
1472 struct pt_regs *iregs, void *__pebs,
1473 struct perf_sample_data *data,
1474 struct pt_regs *regs)
1475 {
1476 /*
1477 * We cast to the biggest pebs_record but are careful not to
1478 * unconditionally access the 'extra' entries.
1479 */
1480 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1481 struct pebs_record_skl *pebs = __pebs;
1482 u64 sample_type;
1483 int fll;
1484
1485 if (pebs == NULL)
1486 return;
1487
1488 sample_type = event->attr.sample_type;
1489 fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
1490
1491 perf_sample_data_init(data, 0, event->hw.last_period);
1492
1493 data->period = event->hw.last_period;
1494
1495 /*
1496 * Use latency for weight (only avail with PEBS-LL)
1497 */
1498 if (fll && (sample_type & PERF_SAMPLE_WEIGHT_TYPE))
1499 data->weight.full = pebs->lat;
1500
1501 /*
1502 * data.data_src encodes the data source
1503 */
1504 if (sample_type & PERF_SAMPLE_DATA_SRC)
1505 data->data_src.val = get_data_src(event, pebs->dse);
1506
1507 /*
1508 * We must however always use iregs for the unwinder to stay sane; the
1509 * record BP,SP,IP can point into thin air when the record is from a
1510 * previous PMI context or an (I)RET happened between the record and
1511 * PMI.
1512 */
1513 if (sample_type & PERF_SAMPLE_CALLCHAIN)
1514 data->callchain = perf_callchain(event, iregs);
1515
1516 /*
1517 * We use the interrupt regs as a base because the PEBS record does not
1518 * contain a full regs set, specifically it seems to lack segment
1519 * descriptors, which get used by things like user_mode().
1520 *
1521 * In the simple case fix up only the IP for PERF_SAMPLE_IP.
1522 */
1523 *regs = *iregs;
1524
1525 /*
1526 * Initialize regs_>flags from PEBS,
1527 * Clear exact bit (which uses x86 EFLAGS Reserved bit 3),
1528 * i.e., do not rely on it being zero:
1529 */
1530 regs->flags = pebs->flags & ~PERF_EFLAGS_EXACT;
1531
1532 if (sample_type & PERF_SAMPLE_REGS_INTR) {
1533 regs->ax = pebs->ax;
1534 regs->bx = pebs->bx;
1535 regs->cx = pebs->cx;
1536 regs->dx = pebs->dx;
1537 regs->si = pebs->si;
1538 regs->di = pebs->di;
1539
1540 regs->bp = pebs->bp;
1541 regs->sp = pebs->sp;
1542
1543 #ifndef CONFIG_X86_32
1544 regs->r8 = pebs->r8;
1545 regs->r9 = pebs->r9;
1546 regs->r10 = pebs->r10;
1547 regs->r11 = pebs->r11;
1548 regs->r12 = pebs->r12;
1549 regs->r13 = pebs->r13;
1550 regs->r14 = pebs->r14;
1551 regs->r15 = pebs->r15;
1552 #endif
1553 }
1554
1555 if (event->attr.precise_ip > 1) {
1556 /*
1557 * Haswell and later processors have an 'eventing IP'
1558 * (real IP) which fixes the off-by-1 skid in hardware.
1559 * Use it when precise_ip >= 2 :
1560 */
1561 if (x86_pmu.intel_cap.pebs_format >= 2) {
1562 set_linear_ip(regs, pebs->real_ip);
1563 regs->flags |= PERF_EFLAGS_EXACT;
1564 } else {
1565 /* Otherwise, use PEBS off-by-1 IP: */
1566 set_linear_ip(regs, pebs->ip);
1567
1568 /*
1569 * With precise_ip >= 2, try to fix up the off-by-1 IP
1570 * using the LBR. If successful, the fixup function
1571 * corrects regs->ip and calls set_linear_ip() on regs:
1572 */
1573 if (intel_pmu_pebs_fixup_ip(regs))
1574 regs->flags |= PERF_EFLAGS_EXACT;
1575 }
1576 } else {
1577 /*
1578 * When precise_ip == 1, return the PEBS off-by-1 IP,
1579 * no fixup attempted:
1580 */
1581 set_linear_ip(regs, pebs->ip);
1582 }
1583
1584
1585 if ((sample_type & PERF_SAMPLE_ADDR_TYPE) &&
1586 x86_pmu.intel_cap.pebs_format >= 1)
1587 data->addr = pebs->dla;
1588
1589 if (x86_pmu.intel_cap.pebs_format >= 2) {
1590 /* Only set the TSX weight when no memory weight. */
1591 if ((sample_type & PERF_SAMPLE_WEIGHT_TYPE) && !fll)
1592 data->weight.full = intel_get_tsx_weight(pebs->tsx_tuning);
1593
1594 if (sample_type & PERF_SAMPLE_TRANSACTION)
1595 data->txn = intel_get_tsx_transaction(pebs->tsx_tuning,
1596 pebs->ax);
1597 }
1598
1599 /*
1600 * v3 supplies an accurate time stamp, so we use that
1601 * for the time stamp.
1602 *
1603 * We can only do this for the default trace clock.
1604 */
1605 if (x86_pmu.intel_cap.pebs_format >= 3 &&
1606 event->attr.use_clockid == 0)
1607 data->time = native_sched_clock_from_tsc(pebs->tsc);
1608
1609 if (has_branch_stack(event))
1610 data->br_stack = &cpuc->lbr_stack;
1611 }
1612
adaptive_pebs_save_regs(struct pt_regs * regs,struct pebs_gprs * gprs)1613 static void adaptive_pebs_save_regs(struct pt_regs *regs,
1614 struct pebs_gprs *gprs)
1615 {
1616 regs->ax = gprs->ax;
1617 regs->bx = gprs->bx;
1618 regs->cx = gprs->cx;
1619 regs->dx = gprs->dx;
1620 regs->si = gprs->si;
1621 regs->di = gprs->di;
1622 regs->bp = gprs->bp;
1623 regs->sp = gprs->sp;
1624 #ifndef CONFIG_X86_32
1625 regs->r8 = gprs->r8;
1626 regs->r9 = gprs->r9;
1627 regs->r10 = gprs->r10;
1628 regs->r11 = gprs->r11;
1629 regs->r12 = gprs->r12;
1630 regs->r13 = gprs->r13;
1631 regs->r14 = gprs->r14;
1632 regs->r15 = gprs->r15;
1633 #endif
1634 }
1635
1636 #define PEBS_LATENCY_MASK 0xffff
1637 #define PEBS_CACHE_LATENCY_OFFSET 32
1638
1639 /*
1640 * With adaptive PEBS the layout depends on what fields are configured.
1641 */
1642
setup_pebs_adaptive_sample_data(struct perf_event * event,struct pt_regs * iregs,void * __pebs,struct perf_sample_data * data,struct pt_regs * regs)1643 static void setup_pebs_adaptive_sample_data(struct perf_event *event,
1644 struct pt_regs *iregs, void *__pebs,
1645 struct perf_sample_data *data,
1646 struct pt_regs *regs)
1647 {
1648 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1649 struct pebs_basic *basic = __pebs;
1650 void *next_record = basic + 1;
1651 u64 sample_type;
1652 u64 format_size;
1653 struct pebs_meminfo *meminfo = NULL;
1654 struct pebs_gprs *gprs = NULL;
1655 struct x86_perf_regs *perf_regs;
1656
1657 if (basic == NULL)
1658 return;
1659
1660 perf_regs = container_of(regs, struct x86_perf_regs, regs);
1661 perf_regs->xmm_regs = NULL;
1662
1663 sample_type = event->attr.sample_type;
1664 format_size = basic->format_size;
1665 perf_sample_data_init(data, 0, event->hw.last_period);
1666 data->period = event->hw.last_period;
1667
1668 if (event->attr.use_clockid == 0)
1669 data->time = native_sched_clock_from_tsc(basic->tsc);
1670
1671 /*
1672 * We must however always use iregs for the unwinder to stay sane; the
1673 * record BP,SP,IP can point into thin air when the record is from a
1674 * previous PMI context or an (I)RET happened between the record and
1675 * PMI.
1676 */
1677 if (sample_type & PERF_SAMPLE_CALLCHAIN)
1678 data->callchain = perf_callchain(event, iregs);
1679
1680 *regs = *iregs;
1681 /* The ip in basic is EventingIP */
1682 set_linear_ip(regs, basic->ip);
1683 regs->flags = PERF_EFLAGS_EXACT;
1684
1685 /*
1686 * The record for MEMINFO is in front of GP
1687 * But PERF_SAMPLE_TRANSACTION needs gprs->ax.
1688 * Save the pointer here but process later.
1689 */
1690 if (format_size & PEBS_DATACFG_MEMINFO) {
1691 meminfo = next_record;
1692 next_record = meminfo + 1;
1693 }
1694
1695 if (format_size & PEBS_DATACFG_GP) {
1696 gprs = next_record;
1697 next_record = gprs + 1;
1698
1699 if (event->attr.precise_ip < 2) {
1700 set_linear_ip(regs, gprs->ip);
1701 regs->flags &= ~PERF_EFLAGS_EXACT;
1702 }
1703
1704 if (sample_type & PERF_SAMPLE_REGS_INTR)
1705 adaptive_pebs_save_regs(regs, gprs);
1706 }
1707
1708 if (format_size & PEBS_DATACFG_MEMINFO) {
1709 if (sample_type & PERF_SAMPLE_WEIGHT_TYPE) {
1710 u64 weight = meminfo->latency;
1711
1712 if (x86_pmu.flags & PMU_FL_INSTR_LATENCY) {
1713 data->weight.var2_w = weight & PEBS_LATENCY_MASK;
1714 weight >>= PEBS_CACHE_LATENCY_OFFSET;
1715 }
1716
1717 /*
1718 * Although meminfo::latency is defined as a u64,
1719 * only the lower 32 bits include the valid data
1720 * in practice on Ice Lake and earlier platforms.
1721 */
1722 if (sample_type & PERF_SAMPLE_WEIGHT) {
1723 data->weight.full = weight ?:
1724 intel_get_tsx_weight(meminfo->tsx_tuning);
1725 } else {
1726 data->weight.var1_dw = (u32)(weight & PEBS_LATENCY_MASK) ?:
1727 intel_get_tsx_weight(meminfo->tsx_tuning);
1728 }
1729 }
1730
1731 if (sample_type & PERF_SAMPLE_DATA_SRC)
1732 data->data_src.val = get_data_src(event, meminfo->aux);
1733
1734 if (sample_type & PERF_SAMPLE_ADDR_TYPE)
1735 data->addr = meminfo->address;
1736
1737 if (sample_type & PERF_SAMPLE_TRANSACTION)
1738 data->txn = intel_get_tsx_transaction(meminfo->tsx_tuning,
1739 gprs ? gprs->ax : 0);
1740 }
1741
1742 if (format_size & PEBS_DATACFG_XMMS) {
1743 struct pebs_xmm *xmm = next_record;
1744
1745 next_record = xmm + 1;
1746 perf_regs->xmm_regs = xmm->xmm;
1747 }
1748
1749 if (format_size & PEBS_DATACFG_LBRS) {
1750 struct lbr_entry *lbr = next_record;
1751 int num_lbr = ((format_size >> PEBS_DATACFG_LBR_SHIFT)
1752 & 0xff) + 1;
1753 next_record = next_record + num_lbr * sizeof(struct lbr_entry);
1754
1755 if (has_branch_stack(event)) {
1756 intel_pmu_store_pebs_lbrs(lbr);
1757 data->br_stack = &cpuc->lbr_stack;
1758 }
1759 }
1760
1761 WARN_ONCE(next_record != __pebs + (format_size >> 48),
1762 "PEBS record size %llu, expected %llu, config %llx\n",
1763 format_size >> 48,
1764 (u64)(next_record - __pebs),
1765 basic->format_size);
1766 }
1767
1768 static inline void *
get_next_pebs_record_by_bit(void * base,void * top,int bit)1769 get_next_pebs_record_by_bit(void *base, void *top, int bit)
1770 {
1771 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1772 void *at;
1773 u64 pebs_status;
1774
1775 /*
1776 * fmt0 does not have a status bitfield (does not use
1777 * perf_record_nhm format)
1778 */
1779 if (x86_pmu.intel_cap.pebs_format < 1)
1780 return base;
1781
1782 if (base == NULL)
1783 return NULL;
1784
1785 for (at = base; at < top; at += cpuc->pebs_record_size) {
1786 unsigned long status = get_pebs_status(at);
1787
1788 if (test_bit(bit, (unsigned long *)&status)) {
1789 /* PEBS v3 has accurate status bits */
1790 if (x86_pmu.intel_cap.pebs_format >= 3)
1791 return at;
1792
1793 if (status == (1 << bit))
1794 return at;
1795
1796 /* clear non-PEBS bit and re-check */
1797 pebs_status = status & cpuc->pebs_enabled;
1798 pebs_status &= PEBS_COUNTER_MASK;
1799 if (pebs_status == (1 << bit))
1800 return at;
1801 }
1802 }
1803 return NULL;
1804 }
1805
intel_pmu_auto_reload_read(struct perf_event * event)1806 void intel_pmu_auto_reload_read(struct perf_event *event)
1807 {
1808 WARN_ON(!(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD));
1809
1810 perf_pmu_disable(event->pmu);
1811 intel_pmu_drain_pebs_buffer();
1812 perf_pmu_enable(event->pmu);
1813 }
1814
1815 /*
1816 * Special variant of intel_pmu_save_and_restart() for auto-reload.
1817 */
1818 static int
intel_pmu_save_and_restart_reload(struct perf_event * event,int count)1819 intel_pmu_save_and_restart_reload(struct perf_event *event, int count)
1820 {
1821 struct hw_perf_event *hwc = &event->hw;
1822 int shift = 64 - x86_pmu.cntval_bits;
1823 u64 period = hwc->sample_period;
1824 u64 prev_raw_count, new_raw_count;
1825 s64 new, old;
1826
1827 WARN_ON(!period);
1828
1829 /*
1830 * drain_pebs() only happens when the PMU is disabled.
1831 */
1832 WARN_ON(this_cpu_read(cpu_hw_events.enabled));
1833
1834 prev_raw_count = local64_read(&hwc->prev_count);
1835 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
1836 local64_set(&hwc->prev_count, new_raw_count);
1837
1838 /*
1839 * Since the counter increments a negative counter value and
1840 * overflows on the sign switch, giving the interval:
1841 *
1842 * [-period, 0]
1843 *
1844 * the difference between two consecutive reads is:
1845 *
1846 * A) value2 - value1;
1847 * when no overflows have happened in between,
1848 *
1849 * B) (0 - value1) + (value2 - (-period));
1850 * when one overflow happened in between,
1851 *
1852 * C) (0 - value1) + (n - 1) * (period) + (value2 - (-period));
1853 * when @n overflows happened in between.
1854 *
1855 * Here A) is the obvious difference, B) is the extension to the
1856 * discrete interval, where the first term is to the top of the
1857 * interval and the second term is from the bottom of the next
1858 * interval and C) the extension to multiple intervals, where the
1859 * middle term is the whole intervals covered.
1860 *
1861 * An equivalent of C, by reduction, is:
1862 *
1863 * value2 - value1 + n * period
1864 */
1865 new = ((s64)(new_raw_count << shift) >> shift);
1866 old = ((s64)(prev_raw_count << shift) >> shift);
1867 local64_add(new - old + count * period, &event->count);
1868
1869 local64_set(&hwc->period_left, -new);
1870
1871 perf_event_update_userpage(event);
1872
1873 return 0;
1874 }
1875
1876 static __always_inline void
__intel_pmu_pebs_event(struct perf_event * event,struct pt_regs * iregs,struct perf_sample_data * data,void * base,void * top,int bit,int count,void (* setup_sample)(struct perf_event *,struct pt_regs *,void *,struct perf_sample_data *,struct pt_regs *))1877 __intel_pmu_pebs_event(struct perf_event *event,
1878 struct pt_regs *iregs,
1879 struct perf_sample_data *data,
1880 void *base, void *top,
1881 int bit, int count,
1882 void (*setup_sample)(struct perf_event *,
1883 struct pt_regs *,
1884 void *,
1885 struct perf_sample_data *,
1886 struct pt_regs *))
1887 {
1888 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1889 struct hw_perf_event *hwc = &event->hw;
1890 struct x86_perf_regs perf_regs;
1891 struct pt_regs *regs = &perf_regs.regs;
1892 void *at = get_next_pebs_record_by_bit(base, top, bit);
1893 static struct pt_regs dummy_iregs;
1894
1895 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
1896 /*
1897 * Now, auto-reload is only enabled in fixed period mode.
1898 * The reload value is always hwc->sample_period.
1899 * May need to change it, if auto-reload is enabled in
1900 * freq mode later.
1901 */
1902 intel_pmu_save_and_restart_reload(event, count);
1903 } else if (!intel_pmu_save_and_restart(event))
1904 return;
1905
1906 if (!iregs)
1907 iregs = &dummy_iregs;
1908
1909 while (count > 1) {
1910 setup_sample(event, iregs, at, data, regs);
1911 perf_event_output(event, data, regs);
1912 at += cpuc->pebs_record_size;
1913 at = get_next_pebs_record_by_bit(at, top, bit);
1914 count--;
1915 }
1916
1917 setup_sample(event, iregs, at, data, regs);
1918 if (iregs == &dummy_iregs) {
1919 /*
1920 * The PEBS records may be drained in the non-overflow context,
1921 * e.g., large PEBS + context switch. Perf should treat the
1922 * last record the same as other PEBS records, and doesn't
1923 * invoke the generic overflow handler.
1924 */
1925 perf_event_output(event, data, regs);
1926 } else {
1927 /*
1928 * All but the last records are processed.
1929 * The last one is left to be able to call the overflow handler.
1930 */
1931 if (perf_event_overflow(event, data, regs))
1932 x86_pmu_stop(event, 0);
1933 }
1934 }
1935
intel_pmu_drain_pebs_core(struct pt_regs * iregs,struct perf_sample_data * data)1936 static void intel_pmu_drain_pebs_core(struct pt_regs *iregs, struct perf_sample_data *data)
1937 {
1938 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1939 struct debug_store *ds = cpuc->ds;
1940 struct perf_event *event = cpuc->events[0]; /* PMC0 only */
1941 struct pebs_record_core *at, *top;
1942 int n;
1943
1944 if (!x86_pmu.pebs_active)
1945 return;
1946
1947 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
1948 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
1949
1950 /*
1951 * Whatever else happens, drain the thing
1952 */
1953 ds->pebs_index = ds->pebs_buffer_base;
1954
1955 if (!test_bit(0, cpuc->active_mask))
1956 return;
1957
1958 WARN_ON_ONCE(!event);
1959
1960 if (!event->attr.precise_ip)
1961 return;
1962
1963 n = top - at;
1964 if (n <= 0) {
1965 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
1966 intel_pmu_save_and_restart_reload(event, 0);
1967 return;
1968 }
1969
1970 __intel_pmu_pebs_event(event, iregs, data, at, top, 0, n,
1971 setup_pebs_fixed_sample_data);
1972 }
1973
intel_pmu_pebs_event_update_no_drain(struct cpu_hw_events * cpuc,int size)1974 static void intel_pmu_pebs_event_update_no_drain(struct cpu_hw_events *cpuc, int size)
1975 {
1976 struct perf_event *event;
1977 int bit;
1978
1979 /*
1980 * The drain_pebs() could be called twice in a short period
1981 * for auto-reload event in pmu::read(). There are no
1982 * overflows have happened in between.
1983 * It needs to call intel_pmu_save_and_restart_reload() to
1984 * update the event->count for this case.
1985 */
1986 for_each_set_bit(bit, (unsigned long *)&cpuc->pebs_enabled, size) {
1987 event = cpuc->events[bit];
1988 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
1989 intel_pmu_save_and_restart_reload(event, 0);
1990 }
1991 }
1992
intel_pmu_drain_pebs_nhm(struct pt_regs * iregs,struct perf_sample_data * data)1993 static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_data *data)
1994 {
1995 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1996 struct debug_store *ds = cpuc->ds;
1997 struct perf_event *event;
1998 void *base, *at, *top;
1999 short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
2000 short error[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
2001 int bit, i, size;
2002 u64 mask;
2003
2004 if (!x86_pmu.pebs_active)
2005 return;
2006
2007 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
2008 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
2009
2010 ds->pebs_index = ds->pebs_buffer_base;
2011
2012 mask = (1ULL << x86_pmu.max_pebs_events) - 1;
2013 size = x86_pmu.max_pebs_events;
2014 if (x86_pmu.flags & PMU_FL_PEBS_ALL) {
2015 mask |= ((1ULL << x86_pmu.num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED;
2016 size = INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed;
2017 }
2018
2019 if (unlikely(base >= top)) {
2020 intel_pmu_pebs_event_update_no_drain(cpuc, size);
2021 return;
2022 }
2023
2024 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
2025 struct pebs_record_nhm *p = at;
2026 u64 pebs_status;
2027
2028 pebs_status = p->status & cpuc->pebs_enabled;
2029 pebs_status &= mask;
2030
2031 /* PEBS v3 has more accurate status bits */
2032 if (x86_pmu.intel_cap.pebs_format >= 3) {
2033 for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
2034 counts[bit]++;
2035
2036 continue;
2037 }
2038
2039 /*
2040 * On some CPUs the PEBS status can be zero when PEBS is
2041 * racing with clearing of GLOBAL_STATUS.
2042 *
2043 * Normally we would drop that record, but in the
2044 * case when there is only a single active PEBS event
2045 * we can assume it's for that event.
2046 */
2047 if (!pebs_status && cpuc->pebs_enabled &&
2048 !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1)))
2049 pebs_status = p->status = cpuc->pebs_enabled;
2050
2051 bit = find_first_bit((unsigned long *)&pebs_status,
2052 x86_pmu.max_pebs_events);
2053 if (bit >= x86_pmu.max_pebs_events)
2054 continue;
2055
2056 /*
2057 * The PEBS hardware does not deal well with the situation
2058 * when events happen near to each other and multiple bits
2059 * are set. But it should happen rarely.
2060 *
2061 * If these events include one PEBS and multiple non-PEBS
2062 * events, it doesn't impact PEBS record. The record will
2063 * be handled normally. (slow path)
2064 *
2065 * If these events include two or more PEBS events, the
2066 * records for the events can be collapsed into a single
2067 * one, and it's not possible to reconstruct all events
2068 * that caused the PEBS record. It's called collision.
2069 * If collision happened, the record will be dropped.
2070 */
2071 if (pebs_status != (1ULL << bit)) {
2072 for_each_set_bit(i, (unsigned long *)&pebs_status, size)
2073 error[i]++;
2074 continue;
2075 }
2076
2077 counts[bit]++;
2078 }
2079
2080 for_each_set_bit(bit, (unsigned long *)&mask, size) {
2081 if ((counts[bit] == 0) && (error[bit] == 0))
2082 continue;
2083
2084 event = cpuc->events[bit];
2085 if (WARN_ON_ONCE(!event))
2086 continue;
2087
2088 if (WARN_ON_ONCE(!event->attr.precise_ip))
2089 continue;
2090
2091 /* log dropped samples number */
2092 if (error[bit]) {
2093 perf_log_lost_samples(event, error[bit]);
2094
2095 if (iregs && perf_event_account_interrupt(event))
2096 x86_pmu_stop(event, 0);
2097 }
2098
2099 if (counts[bit]) {
2100 __intel_pmu_pebs_event(event, iregs, data, base,
2101 top, bit, counts[bit],
2102 setup_pebs_fixed_sample_data);
2103 }
2104 }
2105 }
2106
intel_pmu_drain_pebs_icl(struct pt_regs * iregs,struct perf_sample_data * data)2107 static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_data *data)
2108 {
2109 short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
2110 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2111 int max_pebs_events = hybrid(cpuc->pmu, max_pebs_events);
2112 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
2113 struct debug_store *ds = cpuc->ds;
2114 struct perf_event *event;
2115 void *base, *at, *top;
2116 int bit, size;
2117 u64 mask;
2118
2119 if (!x86_pmu.pebs_active)
2120 return;
2121
2122 base = (struct pebs_basic *)(unsigned long)ds->pebs_buffer_base;
2123 top = (struct pebs_basic *)(unsigned long)ds->pebs_index;
2124
2125 ds->pebs_index = ds->pebs_buffer_base;
2126
2127 mask = ((1ULL << max_pebs_events) - 1) |
2128 (((1ULL << num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED);
2129 size = INTEL_PMC_IDX_FIXED + num_counters_fixed;
2130
2131 if (unlikely(base >= top)) {
2132 intel_pmu_pebs_event_update_no_drain(cpuc, size);
2133 return;
2134 }
2135
2136 for (at = base; at < top; at += cpuc->pebs_record_size) {
2137 u64 pebs_status;
2138
2139 pebs_status = get_pebs_status(at) & cpuc->pebs_enabled;
2140 pebs_status &= mask;
2141
2142 for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
2143 counts[bit]++;
2144 }
2145
2146 for_each_set_bit(bit, (unsigned long *)&mask, size) {
2147 if (counts[bit] == 0)
2148 continue;
2149
2150 event = cpuc->events[bit];
2151 if (WARN_ON_ONCE(!event))
2152 continue;
2153
2154 if (WARN_ON_ONCE(!event->attr.precise_ip))
2155 continue;
2156
2157 __intel_pmu_pebs_event(event, iregs, data, base,
2158 top, bit, counts[bit],
2159 setup_pebs_adaptive_sample_data);
2160 }
2161 }
2162
2163 /*
2164 * BTS, PEBS probe and setup
2165 */
2166
intel_ds_init(void)2167 void __init intel_ds_init(void)
2168 {
2169 /*
2170 * No support for 32bit formats
2171 */
2172 if (!boot_cpu_has(X86_FEATURE_DTES64))
2173 return;
2174
2175 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
2176 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
2177 x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
2178 if (x86_pmu.version <= 4)
2179 x86_pmu.pebs_no_isolation = 1;
2180
2181 if (x86_pmu.pebs) {
2182 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
2183 char *pebs_qual = "";
2184 int format = x86_pmu.intel_cap.pebs_format;
2185
2186 if (format < 4)
2187 x86_pmu.intel_cap.pebs_baseline = 0;
2188
2189 switch (format) {
2190 case 0:
2191 pr_cont("PEBS fmt0%c, ", pebs_type);
2192 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
2193 /*
2194 * Using >PAGE_SIZE buffers makes the WRMSR to
2195 * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
2196 * mysteriously hang on Core2.
2197 *
2198 * As a workaround, we don't do this.
2199 */
2200 x86_pmu.pebs_buffer_size = PAGE_SIZE;
2201 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
2202 break;
2203
2204 case 1:
2205 pr_cont("PEBS fmt1%c, ", pebs_type);
2206 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
2207 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
2208 break;
2209
2210 case 2:
2211 pr_cont("PEBS fmt2%c, ", pebs_type);
2212 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
2213 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
2214 break;
2215
2216 case 3:
2217 pr_cont("PEBS fmt3%c, ", pebs_type);
2218 x86_pmu.pebs_record_size =
2219 sizeof(struct pebs_record_skl);
2220 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
2221 x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
2222 break;
2223
2224 case 4:
2225 x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl;
2226 x86_pmu.pebs_record_size = sizeof(struct pebs_basic);
2227 if (x86_pmu.intel_cap.pebs_baseline) {
2228 x86_pmu.large_pebs_flags |=
2229 PERF_SAMPLE_BRANCH_STACK |
2230 PERF_SAMPLE_TIME;
2231 x86_pmu.flags |= PMU_FL_PEBS_ALL;
2232 pebs_qual = "-baseline";
2233 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
2234 } else {
2235 /* Only basic record supported */
2236 x86_pmu.large_pebs_flags &=
2237 ~(PERF_SAMPLE_ADDR |
2238 PERF_SAMPLE_TIME |
2239 PERF_SAMPLE_DATA_SRC |
2240 PERF_SAMPLE_TRANSACTION |
2241 PERF_SAMPLE_REGS_USER |
2242 PERF_SAMPLE_REGS_INTR);
2243 }
2244 pr_cont("PEBS fmt4%c%s, ", pebs_type, pebs_qual);
2245
2246 if (!is_hybrid() && x86_pmu.intel_cap.pebs_output_pt_available) {
2247 pr_cont("PEBS-via-PT, ");
2248 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_AUX_OUTPUT;
2249 }
2250
2251 break;
2252
2253 default:
2254 pr_cont("no PEBS fmt%d%c, ", format, pebs_type);
2255 x86_pmu.pebs = 0;
2256 }
2257 }
2258 }
2259
perf_restore_debug_store(void)2260 void perf_restore_debug_store(void)
2261 {
2262 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2263
2264 if (!x86_pmu.bts && !x86_pmu.pebs)
2265 return;
2266
2267 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
2268 }
2269