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1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3  * Copyright (C) 2007-2015, 2018-2020 Intel Corporation
4  * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5  * Copyright (C) 2016-2017 Intel Deutschland GmbH
6  */
7 #include <linux/pci.h>
8 #include <linux/interrupt.h>
9 #include <linux/debugfs.h>
10 #include <linux/sched.h>
11 #include <linux/bitops.h>
12 #include <linux/gfp.h>
13 #include <linux/vmalloc.h>
14 #include <linux/module.h>
15 #include <linux/wait.h>
16 #include <linux/seq_file.h>
17 
18 #include "iwl-drv.h"
19 #include "iwl-trans.h"
20 #include "iwl-csr.h"
21 #include "iwl-prph.h"
22 #include "iwl-scd.h"
23 #include "iwl-agn-hw.h"
24 #include "fw/error-dump.h"
25 #include "fw/dbg.h"
26 #include "fw/api/tx.h"
27 #include "internal.h"
28 #include "iwl-fh.h"
29 #include "iwl-context-info-gen3.h"
30 
31 /* extended range in FW SRAM */
32 #define IWL_FW_MEM_EXTENDED_START	0x40000
33 #define IWL_FW_MEM_EXTENDED_END		0x57FFF
34 
iwl_trans_pcie_dump_regs(struct iwl_trans * trans)35 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
36 {
37 #define PCI_DUMP_SIZE		352
38 #define PCI_MEM_DUMP_SIZE	64
39 #define PCI_PARENT_DUMP_SIZE	524
40 #define PREFIX_LEN		32
41 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
42 	struct pci_dev *pdev = trans_pcie->pci_dev;
43 	u32 i, pos, alloc_size, *ptr, *buf;
44 	char *prefix;
45 
46 	if (trans_pcie->pcie_dbg_dumped_once)
47 		return;
48 
49 	/* Should be a multiple of 4 */
50 	BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
51 	BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3);
52 	BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3);
53 
54 	/* Alloc a max size buffer */
55 	alloc_size = PCI_ERR_ROOT_ERR_SRC +  4 + PREFIX_LEN;
56 	alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN);
57 	alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN);
58 	alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN);
59 
60 	buf = kmalloc(alloc_size, GFP_ATOMIC);
61 	if (!buf)
62 		return;
63 	prefix = (char *)buf + alloc_size - PREFIX_LEN;
64 
65 	IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
66 
67 	/* Print wifi device registers */
68 	sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
69 	IWL_ERR(trans, "iwlwifi device config registers:\n");
70 	for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
71 		if (pci_read_config_dword(pdev, i, ptr))
72 			goto err_read;
73 	print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
74 
75 	IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
76 	for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++)
77 		*ptr = iwl_read32(trans, i);
78 	print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
79 
80 	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
81 	if (pos) {
82 		IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
83 		for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
84 			if (pci_read_config_dword(pdev, pos + i, ptr))
85 				goto err_read;
86 		print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
87 			       32, 4, buf, i, 0);
88 	}
89 
90 	/* Print parent device registers next */
91 	if (!pdev->bus->self)
92 		goto out;
93 
94 	pdev = pdev->bus->self;
95 	sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
96 
97 	IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
98 		pci_name(pdev));
99 	for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++)
100 		if (pci_read_config_dword(pdev, i, ptr))
101 			goto err_read;
102 	print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
103 
104 	/* Print root port AER registers */
105 	pos = 0;
106 	pdev = pcie_find_root_port(pdev);
107 	if (pdev)
108 		pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
109 	if (pos) {
110 		IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
111 			pci_name(pdev));
112 		sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
113 		for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
114 			if (pci_read_config_dword(pdev, pos + i, ptr))
115 				goto err_read;
116 		print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
117 			       4, buf, i, 0);
118 	}
119 	goto out;
120 
121 err_read:
122 	print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
123 	IWL_ERR(trans, "Read failed at 0x%X\n", i);
124 out:
125 	trans_pcie->pcie_dbg_dumped_once = 1;
126 	kfree(buf);
127 }
128 
iwl_trans_pcie_sw_reset(struct iwl_trans * trans)129 static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans)
130 {
131 	/* Reset entire device - do controller reset (results in SHRD_HW_RST) */
132 	iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
133 	usleep_range(5000, 6000);
134 }
135 
iwl_pcie_free_fw_monitor(struct iwl_trans * trans)136 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
137 {
138 	struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
139 
140 	if (!fw_mon->size)
141 		return;
142 
143 	dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block,
144 			  fw_mon->physical);
145 
146 	fw_mon->block = NULL;
147 	fw_mon->physical = 0;
148 	fw_mon->size = 0;
149 }
150 
iwl_pcie_alloc_fw_monitor_block(struct iwl_trans * trans,u8 max_power,u8 min_power)151 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
152 					    u8 max_power, u8 min_power)
153 {
154 	struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
155 	void *block = NULL;
156 	dma_addr_t physical = 0;
157 	u32 size = 0;
158 	u8 power;
159 
160 	if (fw_mon->size)
161 		return;
162 
163 	for (power = max_power; power >= min_power; power--) {
164 		size = BIT(power);
165 		block = dma_alloc_coherent(trans->dev, size, &physical,
166 					   GFP_KERNEL | __GFP_NOWARN);
167 		if (!block)
168 			continue;
169 
170 		IWL_INFO(trans,
171 			 "Allocated 0x%08x bytes for firmware monitor.\n",
172 			 size);
173 		break;
174 	}
175 
176 	if (WARN_ON_ONCE(!block))
177 		return;
178 
179 	if (power != max_power)
180 		IWL_ERR(trans,
181 			"Sorry - debug buffer is only %luK while you requested %luK\n",
182 			(unsigned long)BIT(power - 10),
183 			(unsigned long)BIT(max_power - 10));
184 
185 	fw_mon->block = block;
186 	fw_mon->physical = physical;
187 	fw_mon->size = size;
188 }
189 
iwl_pcie_alloc_fw_monitor(struct iwl_trans * trans,u8 max_power)190 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
191 {
192 	if (!max_power) {
193 		/* default max_power is maximum */
194 		max_power = 26;
195 	} else {
196 		max_power += 11;
197 	}
198 
199 	if (WARN(max_power > 26,
200 		 "External buffer size for monitor is too big %d, check the FW TLV\n",
201 		 max_power))
202 		return;
203 
204 	if (trans->dbg.fw_mon.size)
205 		return;
206 
207 	iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11);
208 }
209 
iwl_trans_pcie_read_shr(struct iwl_trans * trans,u32 reg)210 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
211 {
212 	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
213 		    ((reg & 0x0000ffff) | (2 << 28)));
214 	return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
215 }
216 
iwl_trans_pcie_write_shr(struct iwl_trans * trans,u32 reg,u32 val)217 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
218 {
219 	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
220 	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
221 		    ((reg & 0x0000ffff) | (3 << 28)));
222 }
223 
iwl_pcie_set_pwr(struct iwl_trans * trans,bool vaux)224 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
225 {
226 	if (trans->cfg->apmg_not_supported)
227 		return;
228 
229 	if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
230 		iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
231 				       APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
232 				       ~APMG_PS_CTRL_MSK_PWR_SRC);
233 	else
234 		iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
235 				       APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
236 				       ~APMG_PS_CTRL_MSK_PWR_SRC);
237 }
238 
239 /* PCI registers */
240 #define PCI_CFG_RETRY_TIMEOUT	0x041
241 
iwl_pcie_apm_config(struct iwl_trans * trans)242 void iwl_pcie_apm_config(struct iwl_trans *trans)
243 {
244 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
245 	u16 lctl;
246 	u16 cap;
247 
248 	/*
249 	 * L0S states have been found to be unstable with our devices
250 	 * and in newer hardware they are not officially supported at
251 	 * all, so we must always set the L0S_DISABLED bit.
252 	 */
253 	iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
254 
255 	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
256 	trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
257 
258 	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
259 	trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
260 	IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
261 			(lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
262 			trans->ltr_enabled ? "En" : "Dis");
263 }
264 
265 /*
266  * Start up NIC's basic functionality after it has been reset
267  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
268  * NOTE:  This does not load uCode nor start the embedded processor
269  */
iwl_pcie_apm_init(struct iwl_trans * trans)270 static int iwl_pcie_apm_init(struct iwl_trans *trans)
271 {
272 	int ret;
273 
274 	IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
275 
276 	/*
277 	 * Use "set_bit" below rather than "write", to preserve any hardware
278 	 * bits already set by default after reset.
279 	 */
280 
281 	/* Disable L0S exit timer (platform NMI Work/Around) */
282 	if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
283 		iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
284 			    CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
285 
286 	/*
287 	 * Disable L0s without affecting L1;
288 	 *  don't wait for ICH L0s (ICH bug W/A)
289 	 */
290 	iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
291 		    CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
292 
293 	/* Set FH wait threshold to maximum (HW error during stress W/A) */
294 	iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
295 
296 	/*
297 	 * Enable HAP INTA (interrupt from management bus) to
298 	 * wake device's PCI Express link L1a -> L0s
299 	 */
300 	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
301 		    CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
302 
303 	iwl_pcie_apm_config(trans);
304 
305 	/* Configure analog phase-lock-loop before activating to D0A */
306 	if (trans->trans_cfg->base_params->pll_cfg)
307 		iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
308 
309 	ret = iwl_finish_nic_init(trans, trans->trans_cfg);
310 	if (ret)
311 		return ret;
312 
313 	if (trans->cfg->host_interrupt_operation_mode) {
314 		/*
315 		 * This is a bit of an abuse - This is needed for 7260 / 3160
316 		 * only check host_interrupt_operation_mode even if this is
317 		 * not related to host_interrupt_operation_mode.
318 		 *
319 		 * Enable the oscillator to count wake up time for L1 exit. This
320 		 * consumes slightly more power (100uA) - but allows to be sure
321 		 * that we wake up from L1 on time.
322 		 *
323 		 * This looks weird: read twice the same register, discard the
324 		 * value, set a bit, and yet again, read that same register
325 		 * just to discard the value. But that's the way the hardware
326 		 * seems to like it.
327 		 */
328 		iwl_read_prph(trans, OSC_CLK);
329 		iwl_read_prph(trans, OSC_CLK);
330 		iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
331 		iwl_read_prph(trans, OSC_CLK);
332 		iwl_read_prph(trans, OSC_CLK);
333 	}
334 
335 	/*
336 	 * Enable DMA clock and wait for it to stabilize.
337 	 *
338 	 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
339 	 * bits do not disable clocks.  This preserves any hardware
340 	 * bits already set by default in "CLK_CTRL_REG" after reset.
341 	 */
342 	if (!trans->cfg->apmg_not_supported) {
343 		iwl_write_prph(trans, APMG_CLK_EN_REG,
344 			       APMG_CLK_VAL_DMA_CLK_RQT);
345 		udelay(20);
346 
347 		/* Disable L1-Active */
348 		iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
349 				  APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
350 
351 		/* Clear the interrupt in APMG if the NIC is in RFKILL */
352 		iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
353 			       APMG_RTC_INT_STT_RFKILL);
354 	}
355 
356 	set_bit(STATUS_DEVICE_ENABLED, &trans->status);
357 
358 	return 0;
359 }
360 
361 /*
362  * Enable LP XTAL to avoid HW bug where device may consume much power if
363  * FW is not loaded after device reset. LP XTAL is disabled by default
364  * after device HW reset. Do it only if XTAL is fed by internal source.
365  * Configure device's "persistence" mode to avoid resetting XTAL again when
366  * SHRD_HW_RST occurs in S3.
367  */
iwl_pcie_apm_lp_xtal_enable(struct iwl_trans * trans)368 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
369 {
370 	int ret;
371 	u32 apmg_gp1_reg;
372 	u32 apmg_xtal_cfg_reg;
373 	u32 dl_cfg_reg;
374 
375 	/* Force XTAL ON */
376 	__iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
377 				 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
378 
379 	iwl_trans_pcie_sw_reset(trans);
380 
381 	ret = iwl_finish_nic_init(trans, trans->trans_cfg);
382 	if (WARN_ON(ret)) {
383 		/* Release XTAL ON request */
384 		__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
385 					   CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
386 		return;
387 	}
388 
389 	/*
390 	 * Clear "disable persistence" to avoid LP XTAL resetting when
391 	 * SHRD_HW_RST is applied in S3.
392 	 */
393 	iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
394 				    APMG_PCIDEV_STT_VAL_PERSIST_DIS);
395 
396 	/*
397 	 * Force APMG XTAL to be active to prevent its disabling by HW
398 	 * caused by APMG idle state.
399 	 */
400 	apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
401 						    SHR_APMG_XTAL_CFG_REG);
402 	iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
403 				 apmg_xtal_cfg_reg |
404 				 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
405 
406 	iwl_trans_pcie_sw_reset(trans);
407 
408 	/* Enable LP XTAL by indirect access through CSR */
409 	apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
410 	iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
411 				 SHR_APMG_GP1_WF_XTAL_LP_EN |
412 				 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
413 
414 	/* Clear delay line clock power up */
415 	dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
416 	iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
417 				 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
418 
419 	/*
420 	 * Enable persistence mode to avoid LP XTAL resetting when
421 	 * SHRD_HW_RST is applied in S3.
422 	 */
423 	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
424 		    CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
425 
426 	/*
427 	 * Clear "initialization complete" bit to move adapter from
428 	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
429 	 */
430 	iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
431 
432 	/* Activates XTAL resources monitor */
433 	__iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
434 				 CSR_MONITOR_XTAL_RESOURCES);
435 
436 	/* Release XTAL ON request */
437 	__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
438 				   CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
439 	udelay(10);
440 
441 	/* Release APMG XTAL */
442 	iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
443 				 apmg_xtal_cfg_reg &
444 				 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
445 }
446 
iwl_pcie_apm_stop_master(struct iwl_trans * trans)447 void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
448 {
449 	int ret;
450 
451 	/* stop device's busmaster DMA activity */
452 
453 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
454 		iwl_set_bit(trans, CSR_GP_CNTRL,
455 			    CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ);
456 
457 		ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
458 				   CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
459 				   CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
460 				   100);
461 	} else {
462 		iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
463 
464 		ret = iwl_poll_bit(trans, CSR_RESET,
465 				   CSR_RESET_REG_FLAG_MASTER_DISABLED,
466 				   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
467 	}
468 
469 	if (ret < 0)
470 		IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
471 
472 	IWL_DEBUG_INFO(trans, "stop master\n");
473 }
474 
iwl_pcie_apm_stop(struct iwl_trans * trans,bool op_mode_leave)475 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
476 {
477 	IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
478 
479 	if (op_mode_leave) {
480 		if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
481 			iwl_pcie_apm_init(trans);
482 
483 		/* inform ME that we are leaving */
484 		if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000)
485 			iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
486 					  APMG_PCIDEV_STT_VAL_WAKE_ME);
487 		else if (trans->trans_cfg->device_family >=
488 			 IWL_DEVICE_FAMILY_8000) {
489 			iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
490 				    CSR_RESET_LINK_PWR_MGMT_DISABLED);
491 			iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
492 				    CSR_HW_IF_CONFIG_REG_PREPARE |
493 				    CSR_HW_IF_CONFIG_REG_ENABLE_PME);
494 			mdelay(1);
495 			iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
496 				      CSR_RESET_LINK_PWR_MGMT_DISABLED);
497 		}
498 		mdelay(5);
499 	}
500 
501 	clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
502 
503 	/* Stop device's DMA activity */
504 	iwl_pcie_apm_stop_master(trans);
505 
506 	if (trans->cfg->lp_xtal_workaround) {
507 		iwl_pcie_apm_lp_xtal_enable(trans);
508 		return;
509 	}
510 
511 	iwl_trans_pcie_sw_reset(trans);
512 
513 	/*
514 	 * Clear "initialization complete" bit to move adapter from
515 	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
516 	 */
517 	iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
518 }
519 
iwl_pcie_nic_init(struct iwl_trans * trans)520 static int iwl_pcie_nic_init(struct iwl_trans *trans)
521 {
522 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
523 	int ret;
524 
525 	/* nic_init */
526 	spin_lock_bh(&trans_pcie->irq_lock);
527 	ret = iwl_pcie_apm_init(trans);
528 	spin_unlock_bh(&trans_pcie->irq_lock);
529 
530 	if (ret)
531 		return ret;
532 
533 	iwl_pcie_set_pwr(trans, false);
534 
535 	iwl_op_mode_nic_config(trans->op_mode);
536 
537 	/* Allocate the RX queue, or reset if it is already allocated */
538 	ret = iwl_pcie_rx_init(trans);
539 	if (ret)
540 		return ret;
541 
542 	/* Allocate or reset and init all Tx and Command queues */
543 	if (iwl_pcie_tx_init(trans)) {
544 		iwl_pcie_rx_free(trans);
545 		return -ENOMEM;
546 	}
547 
548 	if (trans->trans_cfg->base_params->shadow_reg_enable) {
549 		/* enable shadow regs in HW */
550 		iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
551 		IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
552 	}
553 
554 	return 0;
555 }
556 
557 #define HW_READY_TIMEOUT (50)
558 
559 /* Note: returns poll_bit return value, which is >= 0 if success */
iwl_pcie_set_hw_ready(struct iwl_trans * trans)560 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
561 {
562 	int ret;
563 
564 	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
565 		    CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
566 
567 	/* See if we got it */
568 	ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
569 			   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
570 			   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
571 			   HW_READY_TIMEOUT);
572 
573 	if (ret >= 0)
574 		iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
575 
576 	IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
577 	return ret;
578 }
579 
580 /* Note: returns standard 0/-ERROR code */
iwl_pcie_prepare_card_hw(struct iwl_trans * trans)581 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
582 {
583 	int ret;
584 	int iter;
585 
586 	IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
587 
588 	ret = iwl_pcie_set_hw_ready(trans);
589 	/* If the card is ready, exit 0 */
590 	if (ret >= 0)
591 		return 0;
592 
593 	iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
594 		    CSR_RESET_LINK_PWR_MGMT_DISABLED);
595 	usleep_range(1000, 2000);
596 
597 	for (iter = 0; iter < 10; iter++) {
598 		int t = 0;
599 
600 		/* If HW is not ready, prepare the conditions to check again */
601 		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
602 			    CSR_HW_IF_CONFIG_REG_PREPARE);
603 
604 		do {
605 			ret = iwl_pcie_set_hw_ready(trans);
606 			if (ret >= 0)
607 				return 0;
608 
609 			usleep_range(200, 1000);
610 			t += 200;
611 		} while (t < 150000);
612 		msleep(25);
613 	}
614 
615 	IWL_ERR(trans, "Couldn't prepare the card\n");
616 
617 	return ret;
618 }
619 
620 /*
621  * ucode
622  */
iwl_pcie_load_firmware_chunk_fh(struct iwl_trans * trans,u32 dst_addr,dma_addr_t phy_addr,u32 byte_cnt)623 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
624 					    u32 dst_addr, dma_addr_t phy_addr,
625 					    u32 byte_cnt)
626 {
627 	iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
628 		    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
629 
630 	iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
631 		    dst_addr);
632 
633 	iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
634 		    phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
635 
636 	iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
637 		    (iwl_get_dma_hi_addr(phy_addr)
638 			<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
639 
640 	iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
641 		    BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
642 		    BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
643 		    FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
644 
645 	iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
646 		    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
647 		    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
648 		    FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
649 }
650 
iwl_pcie_load_firmware_chunk(struct iwl_trans * trans,u32 dst_addr,dma_addr_t phy_addr,u32 byte_cnt)651 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
652 					u32 dst_addr, dma_addr_t phy_addr,
653 					u32 byte_cnt)
654 {
655 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
656 	int ret;
657 
658 	trans_pcie->ucode_write_complete = false;
659 
660 	if (!iwl_trans_grab_nic_access(trans))
661 		return -EIO;
662 
663 	iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
664 					byte_cnt);
665 	iwl_trans_release_nic_access(trans);
666 
667 	ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
668 				 trans_pcie->ucode_write_complete, 5 * HZ);
669 	if (!ret) {
670 		IWL_ERR(trans, "Failed to load firmware chunk!\n");
671 		iwl_trans_pcie_dump_regs(trans);
672 		return -ETIMEDOUT;
673 	}
674 
675 	return 0;
676 }
677 
iwl_pcie_load_section(struct iwl_trans * trans,u8 section_num,const struct fw_desc * section)678 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
679 			    const struct fw_desc *section)
680 {
681 	u8 *v_addr;
682 	dma_addr_t p_addr;
683 	u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
684 	int ret = 0;
685 
686 	IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
687 		     section_num);
688 
689 	v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
690 				    GFP_KERNEL | __GFP_NOWARN);
691 	if (!v_addr) {
692 		IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
693 		chunk_sz = PAGE_SIZE;
694 		v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
695 					    &p_addr, GFP_KERNEL);
696 		if (!v_addr)
697 			return -ENOMEM;
698 	}
699 
700 	for (offset = 0; offset < section->len; offset += chunk_sz) {
701 		u32 copy_size, dst_addr;
702 		bool extended_addr = false;
703 
704 		copy_size = min_t(u32, chunk_sz, section->len - offset);
705 		dst_addr = section->offset + offset;
706 
707 		if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
708 		    dst_addr <= IWL_FW_MEM_EXTENDED_END)
709 			extended_addr = true;
710 
711 		if (extended_addr)
712 			iwl_set_bits_prph(trans, LMPM_CHICK,
713 					  LMPM_CHICK_EXTENDED_ADDR_SPACE);
714 
715 		memcpy(v_addr, (u8 *)section->data + offset, copy_size);
716 		ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
717 						   copy_size);
718 
719 		if (extended_addr)
720 			iwl_clear_bits_prph(trans, LMPM_CHICK,
721 					    LMPM_CHICK_EXTENDED_ADDR_SPACE);
722 
723 		if (ret) {
724 			IWL_ERR(trans,
725 				"Could not load the [%d] uCode section\n",
726 				section_num);
727 			break;
728 		}
729 	}
730 
731 	dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
732 	return ret;
733 }
734 
iwl_pcie_load_cpu_sections_8000(struct iwl_trans * trans,const struct fw_img * image,int cpu,int * first_ucode_section)735 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
736 					   const struct fw_img *image,
737 					   int cpu,
738 					   int *first_ucode_section)
739 {
740 	int shift_param;
741 	int i, ret = 0, sec_num = 0x1;
742 	u32 val, last_read_idx = 0;
743 
744 	if (cpu == 1) {
745 		shift_param = 0;
746 		*first_ucode_section = 0;
747 	} else {
748 		shift_param = 16;
749 		(*first_ucode_section)++;
750 	}
751 
752 	for (i = *first_ucode_section; i < image->num_sec; i++) {
753 		last_read_idx = i;
754 
755 		/*
756 		 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
757 		 * CPU1 to CPU2.
758 		 * PAGING_SEPARATOR_SECTION delimiter - separate between
759 		 * CPU2 non paged to CPU2 paging sec.
760 		 */
761 		if (!image->sec[i].data ||
762 		    image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
763 		    image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
764 			IWL_DEBUG_FW(trans,
765 				     "Break since Data not valid or Empty section, sec = %d\n",
766 				     i);
767 			break;
768 		}
769 
770 		ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
771 		if (ret)
772 			return ret;
773 
774 		/* Notify ucode of loaded section number and status */
775 		val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
776 		val = val | (sec_num << shift_param);
777 		iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
778 
779 		sec_num = (sec_num << 1) | 0x1;
780 	}
781 
782 	*first_ucode_section = last_read_idx;
783 
784 	iwl_enable_interrupts(trans);
785 
786 	if (trans->trans_cfg->use_tfh) {
787 		if (cpu == 1)
788 			iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
789 				       0xFFFF);
790 		else
791 			iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
792 				       0xFFFFFFFF);
793 	} else {
794 		if (cpu == 1)
795 			iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
796 					   0xFFFF);
797 		else
798 			iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
799 					   0xFFFFFFFF);
800 	}
801 
802 	return 0;
803 }
804 
iwl_pcie_load_cpu_sections(struct iwl_trans * trans,const struct fw_img * image,int cpu,int * first_ucode_section)805 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
806 				      const struct fw_img *image,
807 				      int cpu,
808 				      int *first_ucode_section)
809 {
810 	int i, ret = 0;
811 	u32 last_read_idx = 0;
812 
813 	if (cpu == 1)
814 		*first_ucode_section = 0;
815 	else
816 		(*first_ucode_section)++;
817 
818 	for (i = *first_ucode_section; i < image->num_sec; i++) {
819 		last_read_idx = i;
820 
821 		/*
822 		 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
823 		 * CPU1 to CPU2.
824 		 * PAGING_SEPARATOR_SECTION delimiter - separate between
825 		 * CPU2 non paged to CPU2 paging sec.
826 		 */
827 		if (!image->sec[i].data ||
828 		    image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
829 		    image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
830 			IWL_DEBUG_FW(trans,
831 				     "Break since Data not valid or Empty section, sec = %d\n",
832 				     i);
833 			break;
834 		}
835 
836 		ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
837 		if (ret)
838 			return ret;
839 	}
840 
841 	*first_ucode_section = last_read_idx;
842 
843 	return 0;
844 }
845 
iwl_pcie_apply_destination_ini(struct iwl_trans * trans)846 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)
847 {
848 	enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
849 	struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
850 		&trans->dbg.fw_mon_cfg[alloc_id];
851 	struct iwl_dram_data *frag;
852 
853 	if (!iwl_trans_dbg_ini_valid(trans))
854 		return;
855 
856 	if (le32_to_cpu(fw_mon_cfg->buf_location) ==
857 	    IWL_FW_INI_LOCATION_SRAM_PATH) {
858 		IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n");
859 		/* set sram monitor by enabling bit 7 */
860 		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
861 			    CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);
862 
863 		return;
864 	}
865 
866 	if (le32_to_cpu(fw_mon_cfg->buf_location) !=
867 	    IWL_FW_INI_LOCATION_DRAM_PATH ||
868 	    !trans->dbg.fw_mon_ini[alloc_id].num_frags)
869 		return;
870 
871 	frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0];
872 
873 	IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n",
874 		     alloc_id);
875 
876 	iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,
877 			    frag->physical >> MON_BUFF_SHIFT_VER2);
878 	iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,
879 			    (frag->physical + frag->size - 256) >>
880 			    MON_BUFF_SHIFT_VER2);
881 }
882 
iwl_pcie_apply_destination(struct iwl_trans * trans)883 void iwl_pcie_apply_destination(struct iwl_trans *trans)
884 {
885 	const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv;
886 	const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
887 	int i;
888 
889 	if (iwl_trans_dbg_ini_valid(trans)) {
890 		iwl_pcie_apply_destination_ini(trans);
891 		return;
892 	}
893 
894 	IWL_INFO(trans, "Applying debug destination %s\n",
895 		 get_fw_dbg_mode_string(dest->monitor_mode));
896 
897 	if (dest->monitor_mode == EXTERNAL_MODE)
898 		iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
899 	else
900 		IWL_WARN(trans, "PCI should have external buffer debug\n");
901 
902 	for (i = 0; i < trans->dbg.n_dest_reg; i++) {
903 		u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
904 		u32 val = le32_to_cpu(dest->reg_ops[i].val);
905 
906 		switch (dest->reg_ops[i].op) {
907 		case CSR_ASSIGN:
908 			iwl_write32(trans, addr, val);
909 			break;
910 		case CSR_SETBIT:
911 			iwl_set_bit(trans, addr, BIT(val));
912 			break;
913 		case CSR_CLEARBIT:
914 			iwl_clear_bit(trans, addr, BIT(val));
915 			break;
916 		case PRPH_ASSIGN:
917 			iwl_write_prph(trans, addr, val);
918 			break;
919 		case PRPH_SETBIT:
920 			iwl_set_bits_prph(trans, addr, BIT(val));
921 			break;
922 		case PRPH_CLEARBIT:
923 			iwl_clear_bits_prph(trans, addr, BIT(val));
924 			break;
925 		case PRPH_BLOCKBIT:
926 			if (iwl_read_prph(trans, addr) & BIT(val)) {
927 				IWL_ERR(trans,
928 					"BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
929 					val, addr);
930 				goto monitor;
931 			}
932 			break;
933 		default:
934 			IWL_ERR(trans, "FW debug - unknown OP %d\n",
935 				dest->reg_ops[i].op);
936 			break;
937 		}
938 	}
939 
940 monitor:
941 	if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) {
942 		iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
943 			       fw_mon->physical >> dest->base_shift);
944 		if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
945 			iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
946 				       (fw_mon->physical + fw_mon->size -
947 					256) >> dest->end_shift);
948 		else
949 			iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
950 				       (fw_mon->physical + fw_mon->size) >>
951 				       dest->end_shift);
952 	}
953 }
954 
iwl_pcie_load_given_ucode(struct iwl_trans * trans,const struct fw_img * image)955 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
956 				const struct fw_img *image)
957 {
958 	int ret = 0;
959 	int first_ucode_section;
960 
961 	IWL_DEBUG_FW(trans, "working with %s CPU\n",
962 		     image->is_dual_cpus ? "Dual" : "Single");
963 
964 	/* load to FW the binary non secured sections of CPU1 */
965 	ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
966 	if (ret)
967 		return ret;
968 
969 	if (image->is_dual_cpus) {
970 		/* set CPU2 header address */
971 		iwl_write_prph(trans,
972 			       LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
973 			       LMPM_SECURE_CPU2_HDR_MEM_SPACE);
974 
975 		/* load to FW the binary sections of CPU2 */
976 		ret = iwl_pcie_load_cpu_sections(trans, image, 2,
977 						 &first_ucode_section);
978 		if (ret)
979 			return ret;
980 	}
981 
982 	if (iwl_pcie_dbg_on(trans))
983 		iwl_pcie_apply_destination(trans);
984 
985 	iwl_enable_interrupts(trans);
986 
987 	/* release CPU reset */
988 	iwl_write32(trans, CSR_RESET, 0);
989 
990 	return 0;
991 }
992 
iwl_pcie_load_given_ucode_8000(struct iwl_trans * trans,const struct fw_img * image)993 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
994 					  const struct fw_img *image)
995 {
996 	int ret = 0;
997 	int first_ucode_section;
998 
999 	IWL_DEBUG_FW(trans, "working with %s CPU\n",
1000 		     image->is_dual_cpus ? "Dual" : "Single");
1001 
1002 	if (iwl_pcie_dbg_on(trans))
1003 		iwl_pcie_apply_destination(trans);
1004 
1005 	IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1006 			iwl_read_prph(trans, WFPM_GP2));
1007 
1008 	/*
1009 	 * Set default value. On resume reading the values that were
1010 	 * zeored can provide debug data on the resume flow.
1011 	 * This is for debugging only and has no functional impact.
1012 	 */
1013 	iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1014 
1015 	/* configure the ucode to be ready to get the secured image */
1016 	/* release CPU reset */
1017 	iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1018 
1019 	/* load to FW the binary Secured sections of CPU1 */
1020 	ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1021 					      &first_ucode_section);
1022 	if (ret)
1023 		return ret;
1024 
1025 	/* load to FW the binary sections of CPU2 */
1026 	return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1027 					       &first_ucode_section);
1028 }
1029 
iwl_pcie_check_hw_rf_kill(struct iwl_trans * trans)1030 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
1031 {
1032 	struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1033 	bool hw_rfkill = iwl_is_rfkill_set(trans);
1034 	bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1035 	bool report;
1036 
1037 	if (hw_rfkill) {
1038 		set_bit(STATUS_RFKILL_HW, &trans->status);
1039 		set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1040 	} else {
1041 		clear_bit(STATUS_RFKILL_HW, &trans->status);
1042 		if (trans_pcie->opmode_down)
1043 			clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1044 	}
1045 
1046 	report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1047 
1048 	if (prev != report)
1049 		iwl_trans_pcie_rf_kill(trans, report, false);
1050 
1051 	return hw_rfkill;
1052 }
1053 
1054 struct iwl_causes_list {
1055 	u32 cause_num;
1056 	u32 mask_reg;
1057 	u8 addr;
1058 };
1059 
1060 static struct iwl_causes_list causes_list[] = {
1061 	{MSIX_FH_INT_CAUSES_D2S_CH0_NUM,	CSR_MSIX_FH_INT_MASK_AD, 0},
1062 	{MSIX_FH_INT_CAUSES_D2S_CH1_NUM,	CSR_MSIX_FH_INT_MASK_AD, 0x1},
1063 	{MSIX_FH_INT_CAUSES_S2D,		CSR_MSIX_FH_INT_MASK_AD, 0x3},
1064 	{MSIX_FH_INT_CAUSES_FH_ERR,		CSR_MSIX_FH_INT_MASK_AD, 0x5},
1065 	{MSIX_HW_INT_CAUSES_REG_ALIVE,		CSR_MSIX_HW_INT_MASK_AD, 0x10},
1066 	{MSIX_HW_INT_CAUSES_REG_WAKEUP,		CSR_MSIX_HW_INT_MASK_AD, 0x11},
1067 	{MSIX_HW_INT_CAUSES_REG_RESET_DONE,	CSR_MSIX_HW_INT_MASK_AD, 0x12},
1068 	{MSIX_HW_INT_CAUSES_REG_CT_KILL,	CSR_MSIX_HW_INT_MASK_AD, 0x16},
1069 	{MSIX_HW_INT_CAUSES_REG_RF_KILL,	CSR_MSIX_HW_INT_MASK_AD, 0x17},
1070 	{MSIX_HW_INT_CAUSES_REG_PERIODIC,	CSR_MSIX_HW_INT_MASK_AD, 0x18},
1071 	{MSIX_HW_INT_CAUSES_REG_SW_ERR,		CSR_MSIX_HW_INT_MASK_AD, 0x29},
1072 	{MSIX_HW_INT_CAUSES_REG_SCD,		CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1073 	{MSIX_HW_INT_CAUSES_REG_FH_TX,		CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1074 	{MSIX_HW_INT_CAUSES_REG_HW_ERR,		CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1075 	{MSIX_HW_INT_CAUSES_REG_HAP,		CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1076 };
1077 
iwl_pcie_map_non_rx_causes(struct iwl_trans * trans)1078 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1079 {
1080 	struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1081 	int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1082 	int i, arr_size = ARRAY_SIZE(causes_list);
1083 	struct iwl_causes_list *causes = causes_list;
1084 
1085 	/*
1086 	 * Access all non RX causes and map them to the default irq.
1087 	 * In case we are missing at least one interrupt vector,
1088 	 * the first interrupt vector will serve non-RX and FBQ causes.
1089 	 */
1090 	for (i = 0; i < arr_size; i++) {
1091 		iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1092 		iwl_clear_bit(trans, causes[i].mask_reg,
1093 			      causes[i].cause_num);
1094 	}
1095 }
1096 
iwl_pcie_map_rx_causes(struct iwl_trans * trans)1097 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1098 {
1099 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1100 	u32 offset =
1101 		trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1102 	u32 val, idx;
1103 
1104 	/*
1105 	 * The first RX queue - fallback queue, which is designated for
1106 	 * management frame, command responses etc, is always mapped to the
1107 	 * first interrupt vector. The other RX queues are mapped to
1108 	 * the other (N - 2) interrupt vectors.
1109 	 */
1110 	val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1111 	for (idx = 1; idx < trans->num_rx_queues; idx++) {
1112 		iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1113 			   MSIX_FH_INT_CAUSES_Q(idx - offset));
1114 		val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1115 	}
1116 	iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1117 
1118 	val = MSIX_FH_INT_CAUSES_Q(0);
1119 	if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1120 		val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1121 	iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1122 
1123 	if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1124 		iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1125 }
1126 
iwl_pcie_conf_msix_hw(struct iwl_trans_pcie * trans_pcie)1127 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
1128 {
1129 	struct iwl_trans *trans = trans_pcie->trans;
1130 
1131 	if (!trans_pcie->msix_enabled) {
1132 		if (trans->trans_cfg->mq_rx_supported &&
1133 		    test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1134 			iwl_write_umac_prph(trans, UREG_CHICK,
1135 					    UREG_CHICK_MSI_ENABLE);
1136 		return;
1137 	}
1138 	/*
1139 	 * The IVAR table needs to be configured again after reset,
1140 	 * but if the device is disabled, we can't write to
1141 	 * prph.
1142 	 */
1143 	if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1144 		iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1145 
1146 	/*
1147 	 * Each cause from the causes list above and the RX causes is
1148 	 * represented as a byte in the IVAR table. The first nibble
1149 	 * represents the bound interrupt vector of the cause, the second
1150 	 * represents no auto clear for this cause. This will be set if its
1151 	 * interrupt vector is bound to serve other causes.
1152 	 */
1153 	iwl_pcie_map_rx_causes(trans);
1154 
1155 	iwl_pcie_map_non_rx_causes(trans);
1156 }
1157 
iwl_pcie_init_msix(struct iwl_trans_pcie * trans_pcie)1158 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1159 {
1160 	struct iwl_trans *trans = trans_pcie->trans;
1161 
1162 	iwl_pcie_conf_msix_hw(trans_pcie);
1163 
1164 	if (!trans_pcie->msix_enabled)
1165 		return;
1166 
1167 	trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1168 	trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1169 	trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1170 	trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1171 }
1172 
_iwl_trans_pcie_stop_device(struct iwl_trans * trans,bool from_irq)1173 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool from_irq)
1174 {
1175 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1176 
1177 	lockdep_assert_held(&trans_pcie->mutex);
1178 
1179 	if (trans_pcie->is_down)
1180 		return;
1181 
1182 	trans_pcie->is_down = true;
1183 
1184 	/* tell the device to stop sending interrupts */
1185 	iwl_disable_interrupts(trans);
1186 
1187 	/* device going down, Stop using ICT table */
1188 	iwl_pcie_disable_ict(trans);
1189 
1190 	/*
1191 	 * If a HW restart happens during firmware loading,
1192 	 * then the firmware loading might call this function
1193 	 * and later it might be called again due to the
1194 	 * restart. So don't process again if the device is
1195 	 * already dead.
1196 	 */
1197 	if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1198 		IWL_DEBUG_INFO(trans,
1199 			       "DEVICE_ENABLED bit was set and is now cleared\n");
1200 		if (!from_irq)
1201 			iwl_pcie_synchronize_irqs(trans);
1202 		iwl_pcie_rx_napi_sync(trans);
1203 		iwl_pcie_tx_stop(trans);
1204 		iwl_pcie_rx_stop(trans);
1205 
1206 		/* Power-down device's busmaster DMA clocks */
1207 		if (!trans->cfg->apmg_not_supported) {
1208 			iwl_write_prph(trans, APMG_CLK_DIS_REG,
1209 				       APMG_CLK_VAL_DMA_CLK_RQT);
1210 			udelay(5);
1211 		}
1212 	}
1213 
1214 	/* Make sure (redundant) we've released our request to stay awake */
1215 	iwl_clear_bit(trans, CSR_GP_CNTRL,
1216 		      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1217 
1218 	/* Stop the device, and put it in low power state */
1219 	iwl_pcie_apm_stop(trans, false);
1220 
1221 	iwl_trans_pcie_sw_reset(trans);
1222 
1223 	/*
1224 	 * Upon stop, the IVAR table gets erased, so msi-x won't
1225 	 * work. This causes a bug in RF-KILL flows, since the interrupt
1226 	 * that enables radio won't fire on the correct irq, and the
1227 	 * driver won't be able to handle the interrupt.
1228 	 * Configure the IVAR table again after reset.
1229 	 */
1230 	iwl_pcie_conf_msix_hw(trans_pcie);
1231 
1232 	/*
1233 	 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1234 	 * This is a bug in certain verions of the hardware.
1235 	 * Certain devices also keep sending HW RF kill interrupt all
1236 	 * the time, unless the interrupt is ACKed even if the interrupt
1237 	 * should be masked. Re-ACK all the interrupts here.
1238 	 */
1239 	iwl_disable_interrupts(trans);
1240 
1241 	/* clear all status bits */
1242 	clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1243 	clear_bit(STATUS_INT_ENABLED, &trans->status);
1244 	clear_bit(STATUS_TPOWER_PMI, &trans->status);
1245 
1246 	/*
1247 	 * Even if we stop the HW, we still want the RF kill
1248 	 * interrupt
1249 	 */
1250 	iwl_enable_rfkill_int(trans);
1251 
1252 	/* re-take ownership to prevent other users from stealing the device */
1253 	iwl_pcie_prepare_card_hw(trans);
1254 }
1255 
iwl_pcie_synchronize_irqs(struct iwl_trans * trans)1256 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1257 {
1258 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1259 
1260 	if (trans_pcie->msix_enabled) {
1261 		int i;
1262 
1263 		for (i = 0; i < trans_pcie->alloc_vecs; i++)
1264 			synchronize_irq(trans_pcie->msix_entries[i].vector);
1265 	} else {
1266 		synchronize_irq(trans_pcie->pci_dev->irq);
1267 	}
1268 }
1269 
iwl_trans_pcie_start_fw(struct iwl_trans * trans,const struct fw_img * fw,bool run_in_rfkill)1270 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1271 				   const struct fw_img *fw, bool run_in_rfkill)
1272 {
1273 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1274 	bool hw_rfkill;
1275 	int ret;
1276 
1277 	/* This may fail if AMT took ownership of the device */
1278 	if (iwl_pcie_prepare_card_hw(trans)) {
1279 		IWL_WARN(trans, "Exit HW not ready\n");
1280 		return -EIO;
1281 	}
1282 
1283 	iwl_enable_rfkill_int(trans);
1284 
1285 	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1286 
1287 	/*
1288 	 * We enabled the RF-Kill interrupt and the handler may very
1289 	 * well be running. Disable the interrupts to make sure no other
1290 	 * interrupt can be fired.
1291 	 */
1292 	iwl_disable_interrupts(trans);
1293 
1294 	/* Make sure it finished running */
1295 	iwl_pcie_synchronize_irqs(trans);
1296 
1297 	mutex_lock(&trans_pcie->mutex);
1298 
1299 	/* If platform's RF_KILL switch is NOT set to KILL */
1300 	hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1301 	if (hw_rfkill && !run_in_rfkill) {
1302 		ret = -ERFKILL;
1303 		goto out;
1304 	}
1305 
1306 	/* Someone called stop_device, don't try to start_fw */
1307 	if (trans_pcie->is_down) {
1308 		IWL_WARN(trans,
1309 			 "Can't start_fw since the HW hasn't been started\n");
1310 		ret = -EIO;
1311 		goto out;
1312 	}
1313 
1314 	/* make sure rfkill handshake bits are cleared */
1315 	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1316 	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1317 		    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1318 
1319 	/* clear (again), then enable host interrupts */
1320 	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1321 
1322 	ret = iwl_pcie_nic_init(trans);
1323 	if (ret) {
1324 		IWL_ERR(trans, "Unable to init nic\n");
1325 		goto out;
1326 	}
1327 
1328 	/*
1329 	 * Now, we load the firmware and don't want to be interrupted, even
1330 	 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1331 	 * FH_TX interrupt which is needed to load the firmware). If the
1332 	 * RF-Kill switch is toggled, we will find out after having loaded
1333 	 * the firmware and return the proper value to the caller.
1334 	 */
1335 	iwl_enable_fw_load_int(trans);
1336 
1337 	/* really make sure rfkill handshake bits are cleared */
1338 	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1339 	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1340 
1341 	/* Load the given image to the HW */
1342 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1343 		ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1344 	else
1345 		ret = iwl_pcie_load_given_ucode(trans, fw);
1346 
1347 	/* re-check RF-Kill state since we may have missed the interrupt */
1348 	hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1349 	if (hw_rfkill && !run_in_rfkill)
1350 		ret = -ERFKILL;
1351 
1352 out:
1353 	mutex_unlock(&trans_pcie->mutex);
1354 	return ret;
1355 }
1356 
iwl_trans_pcie_fw_alive(struct iwl_trans * trans,u32 scd_addr)1357 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1358 {
1359 	iwl_pcie_reset_ict(trans);
1360 	iwl_pcie_tx_start(trans, scd_addr);
1361 }
1362 
iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans * trans,bool was_in_rfkill)1363 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1364 				       bool was_in_rfkill)
1365 {
1366 	bool hw_rfkill;
1367 
1368 	/*
1369 	 * Check again since the RF kill state may have changed while
1370 	 * all the interrupts were disabled, in this case we couldn't
1371 	 * receive the RF kill interrupt and update the state in the
1372 	 * op_mode.
1373 	 * Don't call the op_mode if the rkfill state hasn't changed.
1374 	 * This allows the op_mode to call stop_device from the rfkill
1375 	 * notification without endless recursion. Under very rare
1376 	 * circumstances, we might have a small recursion if the rfkill
1377 	 * state changed exactly now while we were called from stop_device.
1378 	 * This is very unlikely but can happen and is supported.
1379 	 */
1380 	hw_rfkill = iwl_is_rfkill_set(trans);
1381 	if (hw_rfkill) {
1382 		set_bit(STATUS_RFKILL_HW, &trans->status);
1383 		set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1384 	} else {
1385 		clear_bit(STATUS_RFKILL_HW, &trans->status);
1386 		clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1387 	}
1388 	if (hw_rfkill != was_in_rfkill)
1389 		iwl_trans_pcie_rf_kill(trans, hw_rfkill, false);
1390 }
1391 
iwl_trans_pcie_stop_device(struct iwl_trans * trans)1392 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1393 {
1394 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1395 	bool was_in_rfkill;
1396 
1397 	iwl_op_mode_time_point(trans->op_mode,
1398 			       IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,
1399 			       NULL);
1400 
1401 	mutex_lock(&trans_pcie->mutex);
1402 	trans_pcie->opmode_down = true;
1403 	was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1404 	_iwl_trans_pcie_stop_device(trans, false);
1405 	iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
1406 	mutex_unlock(&trans_pcie->mutex);
1407 }
1408 
iwl_trans_pcie_rf_kill(struct iwl_trans * trans,bool state,bool from_irq)1409 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state, bool from_irq)
1410 {
1411 	struct iwl_trans_pcie __maybe_unused *trans_pcie =
1412 		IWL_TRANS_GET_PCIE_TRANS(trans);
1413 
1414 	lockdep_assert_held(&trans_pcie->mutex);
1415 
1416 	IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1417 		 state ? "disabled" : "enabled");
1418 	if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1419 		if (trans->trans_cfg->gen2)
1420 			_iwl_trans_pcie_gen2_stop_device(trans);
1421 		else
1422 			_iwl_trans_pcie_stop_device(trans, from_irq);
1423 	}
1424 }
1425 
iwl_pcie_d3_complete_suspend(struct iwl_trans * trans,bool test,bool reset)1426 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
1427 				  bool test, bool reset)
1428 {
1429 	iwl_disable_interrupts(trans);
1430 
1431 	/*
1432 	 * in testing mode, the host stays awake and the
1433 	 * hardware won't be reset (not even partially)
1434 	 */
1435 	if (test)
1436 		return;
1437 
1438 	iwl_pcie_disable_ict(trans);
1439 
1440 	iwl_pcie_synchronize_irqs(trans);
1441 
1442 	iwl_clear_bit(trans, CSR_GP_CNTRL,
1443 		      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1444 	iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1445 
1446 	if (reset) {
1447 		/*
1448 		 * reset TX queues -- some of their registers reset during S3
1449 		 * so if we don't reset everything here the D3 image would try
1450 		 * to execute some invalid memory upon resume
1451 		 */
1452 		iwl_trans_pcie_tx_reset(trans);
1453 	}
1454 
1455 	iwl_pcie_set_pwr(trans, true);
1456 }
1457 
iwl_trans_pcie_d3_suspend(struct iwl_trans * trans,bool test,bool reset)1458 static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1459 				     bool reset)
1460 {
1461 	int ret;
1462 	struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1463 
1464 	if (!reset)
1465 		/* Enable persistence mode to avoid reset */
1466 		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1467 			    CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1468 
1469 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1470 		iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1471 				    UREG_DOORBELL_TO_ISR6_SUSPEND);
1472 
1473 		ret = wait_event_timeout(trans_pcie->sx_waitq,
1474 					 trans_pcie->sx_complete, 2 * HZ);
1475 		/*
1476 		 * Invalidate it toward resume.
1477 		 */
1478 		trans_pcie->sx_complete = false;
1479 
1480 		if (!ret) {
1481 			IWL_ERR(trans, "Timeout entering D3\n");
1482 			return -ETIMEDOUT;
1483 		}
1484 	}
1485 	iwl_pcie_d3_complete_suspend(trans, test, reset);
1486 
1487 	return 0;
1488 }
1489 
iwl_trans_pcie_d3_resume(struct iwl_trans * trans,enum iwl_d3_status * status,bool test,bool reset)1490 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1491 				    enum iwl_d3_status *status,
1492 				    bool test,  bool reset)
1493 {
1494 	struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1495 	u32 val;
1496 	int ret;
1497 
1498 	if (test) {
1499 		iwl_enable_interrupts(trans);
1500 		*status = IWL_D3_STATUS_ALIVE;
1501 		goto out;
1502 	}
1503 
1504 	iwl_set_bit(trans, CSR_GP_CNTRL,
1505 		    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1506 
1507 	ret = iwl_finish_nic_init(trans, trans->trans_cfg);
1508 	if (ret)
1509 		return ret;
1510 
1511 	/*
1512 	 * Reconfigure IVAR table in case of MSIX or reset ict table in
1513 	 * MSI mode since HW reset erased it.
1514 	 * Also enables interrupts - none will happen as
1515 	 * the device doesn't know we're waking it up, only when
1516 	 * the opmode actually tells it after this call.
1517 	 */
1518 	iwl_pcie_conf_msix_hw(trans_pcie);
1519 	if (!trans_pcie->msix_enabled)
1520 		iwl_pcie_reset_ict(trans);
1521 	iwl_enable_interrupts(trans);
1522 
1523 	iwl_pcie_set_pwr(trans, false);
1524 
1525 	if (!reset) {
1526 		iwl_clear_bit(trans, CSR_GP_CNTRL,
1527 			      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1528 	} else {
1529 		iwl_trans_pcie_tx_reset(trans);
1530 
1531 		ret = iwl_pcie_rx_init(trans);
1532 		if (ret) {
1533 			IWL_ERR(trans,
1534 				"Failed to resume the device (RX reset)\n");
1535 			return ret;
1536 		}
1537 	}
1538 
1539 	IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1540 			iwl_read_umac_prph(trans, WFPM_GP2));
1541 
1542 	val = iwl_read32(trans, CSR_RESET);
1543 	if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1544 		*status = IWL_D3_STATUS_RESET;
1545 	else
1546 		*status = IWL_D3_STATUS_ALIVE;
1547 
1548 out:
1549 	if (*status == IWL_D3_STATUS_ALIVE &&
1550 	    trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1551 		trans_pcie->sx_complete = false;
1552 		iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1553 				    UREG_DOORBELL_TO_ISR6_RESUME);
1554 
1555 		ret = wait_event_timeout(trans_pcie->sx_waitq,
1556 					 trans_pcie->sx_complete, 2 * HZ);
1557 		/*
1558 		 * Invalidate it toward next suspend.
1559 		 */
1560 		trans_pcie->sx_complete = false;
1561 
1562 		if (!ret) {
1563 			IWL_ERR(trans, "Timeout exiting D3\n");
1564 			return -ETIMEDOUT;
1565 		}
1566 	}
1567 	return 0;
1568 }
1569 
1570 static void
iwl_pcie_set_interrupt_capa(struct pci_dev * pdev,struct iwl_trans * trans,const struct iwl_cfg_trans_params * cfg_trans)1571 iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1572 			    struct iwl_trans *trans,
1573 			    const struct iwl_cfg_trans_params *cfg_trans)
1574 {
1575 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1576 	int max_irqs, num_irqs, i, ret;
1577 	u16 pci_cmd;
1578 	u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES;
1579 
1580 	if (!cfg_trans->mq_rx_supported)
1581 		goto enable_msi;
1582 
1583 	if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000)
1584 		max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES;
1585 
1586 	max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues);
1587 	for (i = 0; i < max_irqs; i++)
1588 		trans_pcie->msix_entries[i].entry = i;
1589 
1590 	num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1591 					 MSIX_MIN_INTERRUPT_VECTORS,
1592 					 max_irqs);
1593 	if (num_irqs < 0) {
1594 		IWL_DEBUG_INFO(trans,
1595 			       "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1596 			       num_irqs);
1597 		goto enable_msi;
1598 	}
1599 	trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
1600 
1601 	IWL_DEBUG_INFO(trans,
1602 		       "MSI-X enabled. %d interrupt vectors were allocated\n",
1603 		       num_irqs);
1604 
1605 	/*
1606 	 * In case the OS provides fewer interrupts than requested, different
1607 	 * causes will share the same interrupt vector as follows:
1608 	 * One interrupt less: non rx causes shared with FBQ.
1609 	 * Two interrupts less: non rx causes shared with FBQ and RSS.
1610 	 * More than two interrupts: we will use fewer RSS queues.
1611 	 */
1612 	if (num_irqs <= max_irqs - 2) {
1613 		trans_pcie->trans->num_rx_queues = num_irqs + 1;
1614 		trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1615 			IWL_SHARED_IRQ_FIRST_RSS;
1616 	} else if (num_irqs == max_irqs - 1) {
1617 		trans_pcie->trans->num_rx_queues = num_irqs;
1618 		trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1619 	} else {
1620 		trans_pcie->trans->num_rx_queues = num_irqs - 1;
1621 	}
1622 
1623 	IWL_DEBUG_INFO(trans,
1624 		       "MSI-X enabled with rx queues %d, vec mask 0x%x\n",
1625 		       trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask);
1626 
1627 	WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
1628 
1629 	trans_pcie->alloc_vecs = num_irqs;
1630 	trans_pcie->msix_enabled = true;
1631 	return;
1632 
1633 enable_msi:
1634 	ret = pci_enable_msi(pdev);
1635 	if (ret) {
1636 		dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1637 		/* enable rfkill interrupt: hw bug w/a */
1638 		pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1639 		if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1640 			pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1641 			pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1642 		}
1643 	}
1644 }
1645 
iwl_pcie_irq_set_affinity(struct iwl_trans * trans)1646 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1647 {
1648 	int iter_rx_q, i, ret, cpu, offset;
1649 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1650 
1651 	i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1652 	iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1653 	offset = 1 + i;
1654 	for (; i < iter_rx_q ; i++) {
1655 		/*
1656 		 * Get the cpu prior to the place to search
1657 		 * (i.e. return will be > i - 1).
1658 		 */
1659 		cpu = cpumask_next(i - offset, cpu_online_mask);
1660 		cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1661 		ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1662 					    &trans_pcie->affinity_mask[i]);
1663 		if (ret)
1664 			IWL_ERR(trans_pcie->trans,
1665 				"Failed to set affinity mask for IRQ %d\n",
1666 				trans_pcie->msix_entries[i].vector);
1667 	}
1668 }
1669 
iwl_pcie_init_msix_handler(struct pci_dev * pdev,struct iwl_trans_pcie * trans_pcie)1670 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1671 				      struct iwl_trans_pcie *trans_pcie)
1672 {
1673 	int i;
1674 
1675 	for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1676 		int ret;
1677 		struct msix_entry *msix_entry;
1678 		const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1679 
1680 		if (!qname)
1681 			return -ENOMEM;
1682 
1683 		msix_entry = &trans_pcie->msix_entries[i];
1684 		ret = devm_request_threaded_irq(&pdev->dev,
1685 						msix_entry->vector,
1686 						iwl_pcie_msix_isr,
1687 						(i == trans_pcie->def_irq) ?
1688 						iwl_pcie_irq_msix_handler :
1689 						iwl_pcie_irq_rx_msix_handler,
1690 						IRQF_SHARED,
1691 						qname,
1692 						msix_entry);
1693 		if (ret) {
1694 			IWL_ERR(trans_pcie->trans,
1695 				"Error allocating IRQ %d\n", i);
1696 
1697 			return ret;
1698 		}
1699 	}
1700 	iwl_pcie_irq_set_affinity(trans_pcie->trans);
1701 
1702 	return 0;
1703 }
1704 
iwl_trans_pcie_clear_persistence_bit(struct iwl_trans * trans)1705 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)
1706 {
1707 	u32 hpm, wprot;
1708 
1709 	switch (trans->trans_cfg->device_family) {
1710 	case IWL_DEVICE_FAMILY_9000:
1711 		wprot = PREG_PRPH_WPROT_9000;
1712 		break;
1713 	case IWL_DEVICE_FAMILY_22000:
1714 		wprot = PREG_PRPH_WPROT_22000;
1715 		break;
1716 	default:
1717 		return 0;
1718 	}
1719 
1720 	hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
1721 	if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) {
1722 		u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
1723 
1724 		if (wprot_val & PREG_WFPM_ACCESS) {
1725 			IWL_ERR(trans,
1726 				"Error, can not clear persistence bit\n");
1727 			return -EPERM;
1728 		}
1729 		iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,
1730 					    hpm & ~PERSISTENCE_BIT);
1731 	}
1732 
1733 	return 0;
1734 }
1735 
iwl_pcie_gen2_force_power_gating(struct iwl_trans * trans)1736 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)
1737 {
1738 	int ret;
1739 
1740 	ret = iwl_finish_nic_init(trans, trans->trans_cfg);
1741 	if (ret < 0)
1742 		return ret;
1743 
1744 	iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1745 			  HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1746 	udelay(20);
1747 	iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1748 			  HPM_HIPM_GEN_CFG_CR_PG_EN |
1749 			  HPM_HIPM_GEN_CFG_CR_SLP_EN);
1750 	udelay(20);
1751 	iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,
1752 			    HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1753 
1754 	iwl_trans_pcie_sw_reset(trans);
1755 
1756 	return 0;
1757 }
1758 
_iwl_trans_pcie_start_hw(struct iwl_trans * trans)1759 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1760 {
1761 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1762 	int err;
1763 
1764 	lockdep_assert_held(&trans_pcie->mutex);
1765 
1766 	err = iwl_pcie_prepare_card_hw(trans);
1767 	if (err) {
1768 		IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1769 		return err;
1770 	}
1771 
1772 	err = iwl_trans_pcie_clear_persistence_bit(trans);
1773 	if (err)
1774 		return err;
1775 
1776 	iwl_trans_pcie_sw_reset(trans);
1777 
1778 	if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
1779 	    trans->trans_cfg->integrated) {
1780 		err = iwl_pcie_gen2_force_power_gating(trans);
1781 		if (err)
1782 			return err;
1783 	}
1784 
1785 	err = iwl_pcie_apm_init(trans);
1786 	if (err)
1787 		return err;
1788 
1789 	iwl_pcie_init_msix(trans_pcie);
1790 
1791 	/* From now on, the op_mode will be kept updated about RF kill state */
1792 	iwl_enable_rfkill_int(trans);
1793 
1794 	trans_pcie->opmode_down = false;
1795 
1796 	/* Set is_down to false here so that...*/
1797 	trans_pcie->is_down = false;
1798 
1799 	/* ...rfkill can call stop_device and set it false if needed */
1800 	iwl_pcie_check_hw_rf_kill(trans);
1801 
1802 	return 0;
1803 }
1804 
iwl_trans_pcie_start_hw(struct iwl_trans * trans)1805 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1806 {
1807 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1808 	int ret;
1809 
1810 	mutex_lock(&trans_pcie->mutex);
1811 	ret = _iwl_trans_pcie_start_hw(trans);
1812 	mutex_unlock(&trans_pcie->mutex);
1813 
1814 	return ret;
1815 }
1816 
iwl_trans_pcie_op_mode_leave(struct iwl_trans * trans)1817 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1818 {
1819 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1820 
1821 	mutex_lock(&trans_pcie->mutex);
1822 
1823 	/* disable interrupts - don't enable HW RF kill interrupt */
1824 	iwl_disable_interrupts(trans);
1825 
1826 	iwl_pcie_apm_stop(trans, true);
1827 
1828 	iwl_disable_interrupts(trans);
1829 
1830 	iwl_pcie_disable_ict(trans);
1831 
1832 	mutex_unlock(&trans_pcie->mutex);
1833 
1834 	iwl_pcie_synchronize_irqs(trans);
1835 }
1836 
iwl_trans_pcie_write8(struct iwl_trans * trans,u32 ofs,u8 val)1837 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1838 {
1839 	writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1840 }
1841 
iwl_trans_pcie_write32(struct iwl_trans * trans,u32 ofs,u32 val)1842 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1843 {
1844 	writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1845 }
1846 
iwl_trans_pcie_read32(struct iwl_trans * trans,u32 ofs)1847 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1848 {
1849 	return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1850 }
1851 
iwl_trans_pcie_prph_msk(struct iwl_trans * trans)1852 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
1853 {
1854 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1855 		return 0x00FFFFFF;
1856 	else
1857 		return 0x000FFFFF;
1858 }
1859 
iwl_trans_pcie_read_prph(struct iwl_trans * trans,u32 reg)1860 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1861 {
1862 	u32 mask = iwl_trans_pcie_prph_msk(trans);
1863 
1864 	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1865 			       ((reg & mask) | (3 << 24)));
1866 	return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1867 }
1868 
iwl_trans_pcie_write_prph(struct iwl_trans * trans,u32 addr,u32 val)1869 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1870 				      u32 val)
1871 {
1872 	u32 mask = iwl_trans_pcie_prph_msk(trans);
1873 
1874 	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1875 			       ((addr & mask) | (3 << 24)));
1876 	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1877 }
1878 
iwl_trans_pcie_configure(struct iwl_trans * trans,const struct iwl_trans_config * trans_cfg)1879 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1880 				     const struct iwl_trans_config *trans_cfg)
1881 {
1882 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1883 
1884 	/* free all first - we might be reconfigured for a different size */
1885 	iwl_pcie_free_rbs_pool(trans);
1886 
1887 	trans->txqs.cmd.q_id = trans_cfg->cmd_queue;
1888 	trans->txqs.cmd.fifo = trans_cfg->cmd_fifo;
1889 	trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1890 	trans->txqs.page_offs = trans_cfg->cb_data_offs;
1891 	trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1892 
1893 	if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1894 		trans_pcie->n_no_reclaim_cmds = 0;
1895 	else
1896 		trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1897 	if (trans_pcie->n_no_reclaim_cmds)
1898 		memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1899 		       trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1900 
1901 	trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1902 	trans_pcie->rx_page_order =
1903 		iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1904 	trans_pcie->rx_buf_bytes =
1905 		iwl_trans_get_rb_size(trans_pcie->rx_buf_size);
1906 	trans_pcie->supported_dma_mask = DMA_BIT_MASK(12);
1907 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1908 		trans_pcie->supported_dma_mask = DMA_BIT_MASK(11);
1909 
1910 	trans->txqs.bc_table_dword = trans_cfg->bc_table_dword;
1911 	trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1912 
1913 	trans->command_groups = trans_cfg->command_groups;
1914 	trans->command_groups_size = trans_cfg->command_groups_size;
1915 
1916 	/* Initialize NAPI here - it should be before registering to mac80211
1917 	 * in the opmode but after the HW struct is allocated.
1918 	 * As this function may be called again in some corner cases don't
1919 	 * do anything if NAPI was already initialized.
1920 	 */
1921 	if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1922 		init_dummy_netdev(&trans_pcie->napi_dev);
1923 
1924 	trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake;
1925 }
1926 
iwl_trans_pcie_free(struct iwl_trans * trans)1927 void iwl_trans_pcie_free(struct iwl_trans *trans)
1928 {
1929 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1930 	int i;
1931 
1932 	iwl_pcie_synchronize_irqs(trans);
1933 
1934 	if (trans->trans_cfg->gen2)
1935 		iwl_txq_gen2_tx_free(trans);
1936 	else
1937 		iwl_pcie_tx_free(trans);
1938 	iwl_pcie_rx_free(trans);
1939 
1940 	if (trans_pcie->rba.alloc_wq) {
1941 		destroy_workqueue(trans_pcie->rba.alloc_wq);
1942 		trans_pcie->rba.alloc_wq = NULL;
1943 	}
1944 
1945 	if (trans_pcie->msix_enabled) {
1946 		for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1947 			irq_set_affinity_hint(
1948 				trans_pcie->msix_entries[i].vector,
1949 				NULL);
1950 		}
1951 
1952 		trans_pcie->msix_enabled = false;
1953 	} else {
1954 		iwl_pcie_free_ict(trans);
1955 	}
1956 
1957 	iwl_pcie_free_fw_monitor(trans);
1958 
1959 	if (trans_pcie->pnvm_dram.size)
1960 		dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size,
1961 				  trans_pcie->pnvm_dram.block,
1962 				  trans_pcie->pnvm_dram.physical);
1963 
1964 	if (trans_pcie->reduce_power_dram.size)
1965 		dma_free_coherent(trans->dev,
1966 				  trans_pcie->reduce_power_dram.size,
1967 				  trans_pcie->reduce_power_dram.block,
1968 				  trans_pcie->reduce_power_dram.physical);
1969 
1970 	mutex_destroy(&trans_pcie->mutex);
1971 	iwl_trans_free(trans);
1972 }
1973 
iwl_trans_pcie_set_pmi(struct iwl_trans * trans,bool state)1974 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1975 {
1976 	if (state)
1977 		set_bit(STATUS_TPOWER_PMI, &trans->status);
1978 	else
1979 		clear_bit(STATUS_TPOWER_PMI, &trans->status);
1980 }
1981 
1982 struct iwl_trans_pcie_removal {
1983 	struct pci_dev *pdev;
1984 	struct work_struct work;
1985 };
1986 
iwl_trans_pcie_removal_wk(struct work_struct * wk)1987 static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
1988 {
1989 	struct iwl_trans_pcie_removal *removal =
1990 		container_of(wk, struct iwl_trans_pcie_removal, work);
1991 	struct pci_dev *pdev = removal->pdev;
1992 	static char *prop[] = {"EVENT=INACCESSIBLE", NULL};
1993 
1994 	dev_err(&pdev->dev, "Device gone - attempting removal\n");
1995 	kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
1996 	pci_lock_rescan_remove();
1997 	pci_dev_put(pdev);
1998 	pci_stop_and_remove_bus_device(pdev);
1999 	pci_unlock_rescan_remove();
2000 
2001 	kfree(removal);
2002 	module_put(THIS_MODULE);
2003 }
2004 
2005 /*
2006  * This version doesn't disable BHs but rather assumes they're
2007  * already disabled.
2008  */
__iwl_trans_pcie_grab_nic_access(struct iwl_trans * trans)2009 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans)
2010 {
2011 	int ret;
2012 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2013 	u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ;
2014 	u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
2015 		   CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP;
2016 	u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN;
2017 
2018 	spin_lock(&trans_pcie->reg_lock);
2019 
2020 	if (trans_pcie->cmd_hold_nic_awake)
2021 		goto out;
2022 
2023 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
2024 		write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ;
2025 		mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;
2026 		poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;
2027 	}
2028 
2029 	/* this bit wakes up the NIC */
2030 	__iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write);
2031 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
2032 		udelay(2);
2033 
2034 	/*
2035 	 * These bits say the device is running, and should keep running for
2036 	 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2037 	 * but they do not indicate that embedded SRAM is restored yet;
2038 	 * HW with volatile SRAM must save/restore contents to/from
2039 	 * host DRAM when sleeping/waking for power-saving.
2040 	 * Each direction takes approximately 1/4 millisecond; with this
2041 	 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2042 	 * series of register accesses are expected (e.g. reading Event Log),
2043 	 * to keep device from sleeping.
2044 	 *
2045 	 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2046 	 * SRAM is okay/restored.  We don't check that here because this call
2047 	 * is just for hardware register access; but GP1 MAC_SLEEP
2048 	 * check is a good idea before accessing the SRAM of HW with
2049 	 * volatile SRAM (e.g. reading Event Log).
2050 	 *
2051 	 * 5000 series and later (including 1000 series) have non-volatile SRAM,
2052 	 * and do not save/restore SRAM when power cycling.
2053 	 */
2054 	ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000);
2055 	if (unlikely(ret < 0)) {
2056 		u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
2057 
2058 		WARN_ONCE(1,
2059 			  "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
2060 			  cntrl);
2061 
2062 		iwl_trans_pcie_dump_regs(trans);
2063 
2064 		if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) {
2065 			struct iwl_trans_pcie_removal *removal;
2066 
2067 			if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2068 				goto err;
2069 
2070 			IWL_ERR(trans, "Device gone - scheduling removal!\n");
2071 
2072 			/*
2073 			 * get a module reference to avoid doing this
2074 			 * while unloading anyway and to avoid
2075 			 * scheduling a work with code that's being
2076 			 * removed.
2077 			 */
2078 			if (!try_module_get(THIS_MODULE)) {
2079 				IWL_ERR(trans,
2080 					"Module is being unloaded - abort\n");
2081 				goto err;
2082 			}
2083 
2084 			removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
2085 			if (!removal) {
2086 				module_put(THIS_MODULE);
2087 				goto err;
2088 			}
2089 			/*
2090 			 * we don't need to clear this flag, because
2091 			 * the trans will be freed and reallocated.
2092 			*/
2093 			set_bit(STATUS_TRANS_DEAD, &trans->status);
2094 
2095 			removal->pdev = to_pci_dev(trans->dev);
2096 			INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
2097 			pci_dev_get(removal->pdev);
2098 			schedule_work(&removal->work);
2099 		} else {
2100 			iwl_write32(trans, CSR_RESET,
2101 				    CSR_RESET_REG_FLAG_FORCE_NMI);
2102 		}
2103 
2104 err:
2105 		spin_unlock(&trans_pcie->reg_lock);
2106 		return false;
2107 	}
2108 
2109 out:
2110 	/*
2111 	 * Fool sparse by faking we release the lock - sparse will
2112 	 * track nic_access anyway.
2113 	 */
2114 	__release(&trans_pcie->reg_lock);
2115 	return true;
2116 }
2117 
iwl_trans_pcie_grab_nic_access(struct iwl_trans * trans)2118 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans)
2119 {
2120 	bool ret;
2121 
2122 	local_bh_disable();
2123 	ret = __iwl_trans_pcie_grab_nic_access(trans);
2124 	if (ret) {
2125 		/* keep BHs disabled until iwl_trans_pcie_release_nic_access */
2126 		return ret;
2127 	}
2128 	local_bh_enable();
2129 	return false;
2130 }
2131 
iwl_trans_pcie_release_nic_access(struct iwl_trans * trans)2132 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans)
2133 {
2134 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2135 
2136 	lockdep_assert_held(&trans_pcie->reg_lock);
2137 
2138 	/*
2139 	 * Fool sparse by faking we acquiring the lock - sparse will
2140 	 * track nic_access anyway.
2141 	 */
2142 	__acquire(&trans_pcie->reg_lock);
2143 
2144 	if (trans_pcie->cmd_hold_nic_awake)
2145 		goto out;
2146 
2147 	__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2148 				   CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2149 	/*
2150 	 * Above we read the CSR_GP_CNTRL register, which will flush
2151 	 * any previous writes, but we need the write that clears the
2152 	 * MAC_ACCESS_REQ bit to be performed before any other writes
2153 	 * scheduled on different CPUs (after we drop reg_lock).
2154 	 */
2155 out:
2156 	spin_unlock_bh(&trans_pcie->reg_lock);
2157 }
2158 
iwl_trans_pcie_read_mem(struct iwl_trans * trans,u32 addr,void * buf,int dwords)2159 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2160 				   void *buf, int dwords)
2161 {
2162 	int offs = 0;
2163 	u32 *vals = buf;
2164 
2165 	while (offs < dwords) {
2166 		/* limit the time we spin here under lock to 1/2s */
2167 		unsigned long end = jiffies + HZ / 2;
2168 		bool resched = false;
2169 
2170 		if (iwl_trans_grab_nic_access(trans)) {
2171 			iwl_write32(trans, HBUS_TARG_MEM_RADDR,
2172 				    addr + 4 * offs);
2173 
2174 			while (offs < dwords) {
2175 				vals[offs] = iwl_read32(trans,
2176 							HBUS_TARG_MEM_RDAT);
2177 				offs++;
2178 
2179 				if (time_after(jiffies, end)) {
2180 					resched = true;
2181 					break;
2182 				}
2183 			}
2184 			iwl_trans_release_nic_access(trans);
2185 
2186 			if (resched)
2187 				cond_resched();
2188 		} else {
2189 			return -EBUSY;
2190 		}
2191 	}
2192 
2193 	return 0;
2194 }
2195 
iwl_trans_pcie_write_mem(struct iwl_trans * trans,u32 addr,const void * buf,int dwords)2196 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
2197 				    const void *buf, int dwords)
2198 {
2199 	int offs, ret = 0;
2200 	const u32 *vals = buf;
2201 
2202 	if (iwl_trans_grab_nic_access(trans)) {
2203 		iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2204 		for (offs = 0; offs < dwords; offs++)
2205 			iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2206 				    vals ? vals[offs] : 0);
2207 		iwl_trans_release_nic_access(trans);
2208 	} else {
2209 		ret = -EBUSY;
2210 	}
2211 	return ret;
2212 }
2213 
iwl_trans_pcie_read_config32(struct iwl_trans * trans,u32 ofs,u32 * val)2214 static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs,
2215 					u32 *val)
2216 {
2217 	return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev,
2218 				     ofs, val);
2219 }
2220 
iwl_trans_pcie_block_txq_ptrs(struct iwl_trans * trans,bool block)2221 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2222 {
2223 	int i;
2224 
2225 	for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
2226 		struct iwl_txq *txq = trans->txqs.txq[i];
2227 
2228 		if (i == trans->txqs.cmd.q_id)
2229 			continue;
2230 
2231 		spin_lock_bh(&txq->lock);
2232 
2233 		if (!block && !(WARN_ON_ONCE(!txq->block))) {
2234 			txq->block--;
2235 			if (!txq->block) {
2236 				iwl_write32(trans, HBUS_TARG_WRPTR,
2237 					    txq->write_ptr | (i << 8));
2238 			}
2239 		} else if (block) {
2240 			txq->block++;
2241 		}
2242 
2243 		spin_unlock_bh(&txq->lock);
2244 	}
2245 }
2246 
2247 #define IWL_FLUSH_WAIT_MS	2000
2248 
iwl_trans_pcie_rxq_dma_data(struct iwl_trans * trans,int queue,struct iwl_trans_rxq_dma_data * data)2249 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2250 				       struct iwl_trans_rxq_dma_data *data)
2251 {
2252 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2253 
2254 	if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
2255 		return -EINVAL;
2256 
2257 	data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
2258 	data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
2259 	data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
2260 	data->fr_bd_wid = 0;
2261 
2262 	return 0;
2263 }
2264 
iwl_trans_pcie_wait_txq_empty(struct iwl_trans * trans,int txq_idx)2265 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
2266 {
2267 	struct iwl_txq *txq;
2268 	unsigned long now = jiffies;
2269 	bool overflow_tx;
2270 	u8 wr_ptr;
2271 
2272 	/* Make sure the NIC is still alive in the bus */
2273 	if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2274 		return -ENODEV;
2275 
2276 	if (!test_bit(txq_idx, trans->txqs.queue_used))
2277 		return -EINVAL;
2278 
2279 	IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2280 	txq = trans->txqs.txq[txq_idx];
2281 
2282 	spin_lock_bh(&txq->lock);
2283 	overflow_tx = txq->overflow_tx ||
2284 		      !skb_queue_empty(&txq->overflow_q);
2285 	spin_unlock_bh(&txq->lock);
2286 
2287 	wr_ptr = READ_ONCE(txq->write_ptr);
2288 
2289 	while ((txq->read_ptr != READ_ONCE(txq->write_ptr) ||
2290 		overflow_tx) &&
2291 	       !time_after(jiffies,
2292 			   now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2293 		u8 write_ptr = READ_ONCE(txq->write_ptr);
2294 
2295 		/*
2296 		 * If write pointer moved during the wait, warn only
2297 		 * if the TX came from op mode. In case TX came from
2298 		 * trans layer (overflow TX) don't warn.
2299 		 */
2300 		if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx,
2301 			      "WR pointer moved while flushing %d -> %d\n",
2302 			      wr_ptr, write_ptr))
2303 			return -ETIMEDOUT;
2304 		wr_ptr = write_ptr;
2305 
2306 		usleep_range(1000, 2000);
2307 
2308 		spin_lock_bh(&txq->lock);
2309 		overflow_tx = txq->overflow_tx ||
2310 			      !skb_queue_empty(&txq->overflow_q);
2311 		spin_unlock_bh(&txq->lock);
2312 	}
2313 
2314 	if (txq->read_ptr != txq->write_ptr) {
2315 		IWL_ERR(trans,
2316 			"fail to flush all tx fifo queues Q %d\n", txq_idx);
2317 		iwl_txq_log_scd_error(trans, txq);
2318 		return -ETIMEDOUT;
2319 	}
2320 
2321 	IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2322 
2323 	return 0;
2324 }
2325 
iwl_trans_pcie_wait_txqs_empty(struct iwl_trans * trans,u32 txq_bm)2326 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2327 {
2328 	int cnt;
2329 	int ret = 0;
2330 
2331 	/* waiting for all the tx frames complete might take a while */
2332 	for (cnt = 0;
2333 	     cnt < trans->trans_cfg->base_params->num_of_queues;
2334 	     cnt++) {
2335 
2336 		if (cnt == trans->txqs.cmd.q_id)
2337 			continue;
2338 		if (!test_bit(cnt, trans->txqs.queue_used))
2339 			continue;
2340 		if (!(BIT(cnt) & txq_bm))
2341 			continue;
2342 
2343 		ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2344 		if (ret)
2345 			break;
2346 	}
2347 
2348 	return ret;
2349 }
2350 
iwl_trans_pcie_set_bits_mask(struct iwl_trans * trans,u32 reg,u32 mask,u32 value)2351 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2352 					 u32 mask, u32 value)
2353 {
2354 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2355 
2356 	spin_lock_bh(&trans_pcie->reg_lock);
2357 	__iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2358 	spin_unlock_bh(&trans_pcie->reg_lock);
2359 }
2360 
get_csr_string(int cmd)2361 static const char *get_csr_string(int cmd)
2362 {
2363 #define IWL_CMD(x) case x: return #x
2364 	switch (cmd) {
2365 	IWL_CMD(CSR_HW_IF_CONFIG_REG);
2366 	IWL_CMD(CSR_INT_COALESCING);
2367 	IWL_CMD(CSR_INT);
2368 	IWL_CMD(CSR_INT_MASK);
2369 	IWL_CMD(CSR_FH_INT_STATUS);
2370 	IWL_CMD(CSR_GPIO_IN);
2371 	IWL_CMD(CSR_RESET);
2372 	IWL_CMD(CSR_GP_CNTRL);
2373 	IWL_CMD(CSR_HW_REV);
2374 	IWL_CMD(CSR_EEPROM_REG);
2375 	IWL_CMD(CSR_EEPROM_GP);
2376 	IWL_CMD(CSR_OTP_GP_REG);
2377 	IWL_CMD(CSR_GIO_REG);
2378 	IWL_CMD(CSR_GP_UCODE_REG);
2379 	IWL_CMD(CSR_GP_DRIVER_REG);
2380 	IWL_CMD(CSR_UCODE_DRV_GP1);
2381 	IWL_CMD(CSR_UCODE_DRV_GP2);
2382 	IWL_CMD(CSR_LED_REG);
2383 	IWL_CMD(CSR_DRAM_INT_TBL_REG);
2384 	IWL_CMD(CSR_GIO_CHICKEN_BITS);
2385 	IWL_CMD(CSR_ANA_PLL_CFG);
2386 	IWL_CMD(CSR_HW_REV_WA_REG);
2387 	IWL_CMD(CSR_MONITOR_STATUS_REG);
2388 	IWL_CMD(CSR_DBG_HPET_MEM_REG);
2389 	default:
2390 		return "UNKNOWN";
2391 	}
2392 #undef IWL_CMD
2393 }
2394 
iwl_pcie_dump_csr(struct iwl_trans * trans)2395 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2396 {
2397 	int i;
2398 	static const u32 csr_tbl[] = {
2399 		CSR_HW_IF_CONFIG_REG,
2400 		CSR_INT_COALESCING,
2401 		CSR_INT,
2402 		CSR_INT_MASK,
2403 		CSR_FH_INT_STATUS,
2404 		CSR_GPIO_IN,
2405 		CSR_RESET,
2406 		CSR_GP_CNTRL,
2407 		CSR_HW_REV,
2408 		CSR_EEPROM_REG,
2409 		CSR_EEPROM_GP,
2410 		CSR_OTP_GP_REG,
2411 		CSR_GIO_REG,
2412 		CSR_GP_UCODE_REG,
2413 		CSR_GP_DRIVER_REG,
2414 		CSR_UCODE_DRV_GP1,
2415 		CSR_UCODE_DRV_GP2,
2416 		CSR_LED_REG,
2417 		CSR_DRAM_INT_TBL_REG,
2418 		CSR_GIO_CHICKEN_BITS,
2419 		CSR_ANA_PLL_CFG,
2420 		CSR_MONITOR_STATUS_REG,
2421 		CSR_HW_REV_WA_REG,
2422 		CSR_DBG_HPET_MEM_REG
2423 	};
2424 	IWL_ERR(trans, "CSR values:\n");
2425 	IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2426 		"CSR_INT_PERIODIC_REG)\n");
2427 	for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2428 		IWL_ERR(trans, "  %25s: 0X%08x\n",
2429 			get_csr_string(csr_tbl[i]),
2430 			iwl_read32(trans, csr_tbl[i]));
2431 	}
2432 }
2433 
2434 #ifdef CONFIG_IWLWIFI_DEBUGFS
2435 /* create and remove of files */
2436 #define DEBUGFS_ADD_FILE(name, parent, mode) do {			\
2437 	debugfs_create_file(#name, mode, parent, trans,			\
2438 			    &iwl_dbgfs_##name##_ops);			\
2439 } while (0)
2440 
2441 /* file operation */
2442 #define DEBUGFS_READ_FILE_OPS(name)					\
2443 static const struct file_operations iwl_dbgfs_##name##_ops = {		\
2444 	.read = iwl_dbgfs_##name##_read,				\
2445 	.open = simple_open,						\
2446 	.llseek = generic_file_llseek,					\
2447 };
2448 
2449 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
2450 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2451 	.write = iwl_dbgfs_##name##_write,                              \
2452 	.open = simple_open,						\
2453 	.llseek = generic_file_llseek,					\
2454 };
2455 
2456 #define DEBUGFS_READ_WRITE_FILE_OPS(name)				\
2457 static const struct file_operations iwl_dbgfs_##name##_ops = {		\
2458 	.write = iwl_dbgfs_##name##_write,				\
2459 	.read = iwl_dbgfs_##name##_read,				\
2460 	.open = simple_open,						\
2461 	.llseek = generic_file_llseek,					\
2462 };
2463 
2464 struct iwl_dbgfs_tx_queue_priv {
2465 	struct iwl_trans *trans;
2466 };
2467 
2468 struct iwl_dbgfs_tx_queue_state {
2469 	loff_t pos;
2470 };
2471 
iwl_dbgfs_tx_queue_seq_start(struct seq_file * seq,loff_t * pos)2472 static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos)
2473 {
2474 	struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2475 	struct iwl_dbgfs_tx_queue_state *state;
2476 
2477 	if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2478 		return NULL;
2479 
2480 	state = kmalloc(sizeof(*state), GFP_KERNEL);
2481 	if (!state)
2482 		return NULL;
2483 	state->pos = *pos;
2484 	return state;
2485 }
2486 
iwl_dbgfs_tx_queue_seq_next(struct seq_file * seq,void * v,loff_t * pos)2487 static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq,
2488 					 void *v, loff_t *pos)
2489 {
2490 	struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2491 	struct iwl_dbgfs_tx_queue_state *state = v;
2492 
2493 	*pos = ++state->pos;
2494 
2495 	if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2496 		return NULL;
2497 
2498 	return state;
2499 }
2500 
iwl_dbgfs_tx_queue_seq_stop(struct seq_file * seq,void * v)2501 static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v)
2502 {
2503 	kfree(v);
2504 }
2505 
iwl_dbgfs_tx_queue_seq_show(struct seq_file * seq,void * v)2506 static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v)
2507 {
2508 	struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2509 	struct iwl_dbgfs_tx_queue_state *state = v;
2510 	struct iwl_trans *trans = priv->trans;
2511 	struct iwl_txq *txq = trans->txqs.txq[state->pos];
2512 
2513 	seq_printf(seq, "hwq %.3u: used=%d stopped=%d ",
2514 		   (unsigned int)state->pos,
2515 		   !!test_bit(state->pos, trans->txqs.queue_used),
2516 		   !!test_bit(state->pos, trans->txqs.queue_stopped));
2517 	if (txq)
2518 		seq_printf(seq,
2519 			   "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d",
2520 			   txq->read_ptr, txq->write_ptr,
2521 			   txq->need_update, txq->frozen,
2522 			   txq->n_window, txq->ampdu);
2523 	else
2524 		seq_puts(seq, "(unallocated)");
2525 
2526 	if (state->pos == trans->txqs.cmd.q_id)
2527 		seq_puts(seq, " (HCMD)");
2528 	seq_puts(seq, "\n");
2529 
2530 	return 0;
2531 }
2532 
2533 static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = {
2534 	.start = iwl_dbgfs_tx_queue_seq_start,
2535 	.next = iwl_dbgfs_tx_queue_seq_next,
2536 	.stop = iwl_dbgfs_tx_queue_seq_stop,
2537 	.show = iwl_dbgfs_tx_queue_seq_show,
2538 };
2539 
iwl_dbgfs_tx_queue_open(struct inode * inode,struct file * filp)2540 static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp)
2541 {
2542 	struct iwl_dbgfs_tx_queue_priv *priv;
2543 
2544 	priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops,
2545 				  sizeof(*priv));
2546 
2547 	if (!priv)
2548 		return -ENOMEM;
2549 
2550 	priv->trans = inode->i_private;
2551 	return 0;
2552 }
2553 
iwl_dbgfs_rx_queue_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)2554 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2555 				       char __user *user_buf,
2556 				       size_t count, loff_t *ppos)
2557 {
2558 	struct iwl_trans *trans = file->private_data;
2559 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2560 	char *buf;
2561 	int pos = 0, i, ret;
2562 	size_t bufsz;
2563 
2564 	bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2565 
2566 	if (!trans_pcie->rxq)
2567 		return -EAGAIN;
2568 
2569 	buf = kzalloc(bufsz, GFP_KERNEL);
2570 	if (!buf)
2571 		return -ENOMEM;
2572 
2573 	for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2574 		struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2575 
2576 		pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2577 				 i);
2578 		pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2579 				 rxq->read);
2580 		pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2581 				 rxq->write);
2582 		pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2583 				 rxq->write_actual);
2584 		pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2585 				 rxq->need_update);
2586 		pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2587 				 rxq->free_count);
2588 		if (rxq->rb_stts) {
2589 			u32 r =	__le16_to_cpu(iwl_get_closed_rb_stts(trans,
2590 								     rxq));
2591 			pos += scnprintf(buf + pos, bufsz - pos,
2592 					 "\tclosed_rb_num: %u\n",
2593 					 r & 0x0FFF);
2594 		} else {
2595 			pos += scnprintf(buf + pos, bufsz - pos,
2596 					 "\tclosed_rb_num: Not Allocated\n");
2597 		}
2598 	}
2599 	ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2600 	kfree(buf);
2601 
2602 	return ret;
2603 }
2604 
iwl_dbgfs_interrupt_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)2605 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2606 					char __user *user_buf,
2607 					size_t count, loff_t *ppos)
2608 {
2609 	struct iwl_trans *trans = file->private_data;
2610 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2611 	struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2612 
2613 	int pos = 0;
2614 	char *buf;
2615 	int bufsz = 24 * 64; /* 24 items * 64 char per item */
2616 	ssize_t ret;
2617 
2618 	buf = kzalloc(bufsz, GFP_KERNEL);
2619 	if (!buf)
2620 		return -ENOMEM;
2621 
2622 	pos += scnprintf(buf + pos, bufsz - pos,
2623 			"Interrupt Statistics Report:\n");
2624 
2625 	pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2626 		isr_stats->hw);
2627 	pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2628 		isr_stats->sw);
2629 	if (isr_stats->sw || isr_stats->hw) {
2630 		pos += scnprintf(buf + pos, bufsz - pos,
2631 			"\tLast Restarting Code:  0x%X\n",
2632 			isr_stats->err_code);
2633 	}
2634 #ifdef CONFIG_IWLWIFI_DEBUG
2635 	pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2636 		isr_stats->sch);
2637 	pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2638 		isr_stats->alive);
2639 #endif
2640 	pos += scnprintf(buf + pos, bufsz - pos,
2641 		"HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2642 
2643 	pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2644 		isr_stats->ctkill);
2645 
2646 	pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2647 		isr_stats->wakeup);
2648 
2649 	pos += scnprintf(buf + pos, bufsz - pos,
2650 		"Rx command responses:\t\t %u\n", isr_stats->rx);
2651 
2652 	pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2653 		isr_stats->tx);
2654 
2655 	pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2656 		isr_stats->unhandled);
2657 
2658 	ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2659 	kfree(buf);
2660 	return ret;
2661 }
2662 
iwl_dbgfs_interrupt_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)2663 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2664 					 const char __user *user_buf,
2665 					 size_t count, loff_t *ppos)
2666 {
2667 	struct iwl_trans *trans = file->private_data;
2668 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2669 	struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2670 	u32 reset_flag;
2671 	int ret;
2672 
2673 	ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2674 	if (ret)
2675 		return ret;
2676 	if (reset_flag == 0)
2677 		memset(isr_stats, 0, sizeof(*isr_stats));
2678 
2679 	return count;
2680 }
2681 
iwl_dbgfs_csr_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)2682 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2683 				   const char __user *user_buf,
2684 				   size_t count, loff_t *ppos)
2685 {
2686 	struct iwl_trans *trans = file->private_data;
2687 
2688 	iwl_pcie_dump_csr(trans);
2689 
2690 	return count;
2691 }
2692 
iwl_dbgfs_fh_reg_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)2693 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2694 				     char __user *user_buf,
2695 				     size_t count, loff_t *ppos)
2696 {
2697 	struct iwl_trans *trans = file->private_data;
2698 	char *buf = NULL;
2699 	ssize_t ret;
2700 
2701 	ret = iwl_dump_fh(trans, &buf);
2702 	if (ret < 0)
2703 		return ret;
2704 	if (!buf)
2705 		return -EINVAL;
2706 	ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2707 	kfree(buf);
2708 	return ret;
2709 }
2710 
iwl_dbgfs_rfkill_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)2711 static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2712 				     char __user *user_buf,
2713 				     size_t count, loff_t *ppos)
2714 {
2715 	struct iwl_trans *trans = file->private_data;
2716 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2717 	char buf[100];
2718 	int pos;
2719 
2720 	pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2721 			trans_pcie->debug_rfkill,
2722 			!(iwl_read32(trans, CSR_GP_CNTRL) &
2723 				CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2724 
2725 	return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2726 }
2727 
iwl_dbgfs_rfkill_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)2728 static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2729 				      const char __user *user_buf,
2730 				      size_t count, loff_t *ppos)
2731 {
2732 	struct iwl_trans *trans = file->private_data;
2733 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2734 	bool new_value;
2735 	int ret;
2736 
2737 	ret = kstrtobool_from_user(user_buf, count, &new_value);
2738 	if (ret)
2739 		return ret;
2740 	if (new_value == trans_pcie->debug_rfkill)
2741 		return count;
2742 	IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2743 		 trans_pcie->debug_rfkill, new_value);
2744 	trans_pcie->debug_rfkill = new_value;
2745 	iwl_pcie_handle_rfkill_irq(trans, false);
2746 
2747 	return count;
2748 }
2749 
iwl_dbgfs_monitor_data_open(struct inode * inode,struct file * file)2750 static int iwl_dbgfs_monitor_data_open(struct inode *inode,
2751 				       struct file *file)
2752 {
2753 	struct iwl_trans *trans = inode->i_private;
2754 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2755 
2756 	if (!trans->dbg.dest_tlv ||
2757 	    trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) {
2758 		IWL_ERR(trans, "Debug destination is not set to DRAM\n");
2759 		return -ENOENT;
2760 	}
2761 
2762 	if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED)
2763 		return -EBUSY;
2764 
2765 	trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN;
2766 	return simple_open(inode, file);
2767 }
2768 
iwl_dbgfs_monitor_data_release(struct inode * inode,struct file * file)2769 static int iwl_dbgfs_monitor_data_release(struct inode *inode,
2770 					  struct file *file)
2771 {
2772 	struct iwl_trans_pcie *trans_pcie =
2773 		IWL_TRANS_GET_PCIE_TRANS(inode->i_private);
2774 
2775 	if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN)
2776 		trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
2777 	return 0;
2778 }
2779 
iwl_write_to_user_buf(char __user * user_buf,ssize_t count,void * buf,ssize_t * size,ssize_t * bytes_copied)2780 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count,
2781 				  void *buf, ssize_t *size,
2782 				  ssize_t *bytes_copied)
2783 {
2784 	ssize_t buf_size_left = count - *bytes_copied;
2785 
2786 	buf_size_left = buf_size_left - (buf_size_left % sizeof(u32));
2787 	if (*size > buf_size_left)
2788 		*size = buf_size_left;
2789 
2790 	*size -= copy_to_user(user_buf, buf, *size);
2791 	*bytes_copied += *size;
2792 
2793 	if (buf_size_left == *size)
2794 		return true;
2795 	return false;
2796 }
2797 
iwl_dbgfs_monitor_data_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)2798 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file,
2799 					   char __user *user_buf,
2800 					   size_t count, loff_t *ppos)
2801 {
2802 	struct iwl_trans *trans = file->private_data;
2803 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2804 	u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf;
2805 	struct cont_rec *data = &trans_pcie->fw_mon_data;
2806 	u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt;
2807 	ssize_t size, bytes_copied = 0;
2808 	bool b_full;
2809 
2810 	if (trans->dbg.dest_tlv) {
2811 		write_ptr_addr =
2812 			le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
2813 		wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
2814 	} else {
2815 		write_ptr_addr = MON_BUFF_WRPTR;
2816 		wrap_cnt_addr = MON_BUFF_CYCLE_CNT;
2817 	}
2818 
2819 	if (unlikely(!trans->dbg.rec_on))
2820 		return 0;
2821 
2822 	mutex_lock(&data->mutex);
2823 	if (data->state ==
2824 	    IWL_FW_MON_DBGFS_STATE_DISABLED) {
2825 		mutex_unlock(&data->mutex);
2826 		return 0;
2827 	}
2828 
2829 	/* write_ptr position in bytes rather then DW */
2830 	write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);
2831 	wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);
2832 
2833 	if (data->prev_wrap_cnt == wrap_cnt) {
2834 		size = write_ptr - data->prev_wr_ptr;
2835 		curr_buf = cpu_addr + data->prev_wr_ptr;
2836 		b_full = iwl_write_to_user_buf(user_buf, count,
2837 					       curr_buf, &size,
2838 					       &bytes_copied);
2839 		data->prev_wr_ptr += size;
2840 
2841 	} else if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2842 		   write_ptr < data->prev_wr_ptr) {
2843 		size = trans->dbg.fw_mon.size - data->prev_wr_ptr;
2844 		curr_buf = cpu_addr + data->prev_wr_ptr;
2845 		b_full = iwl_write_to_user_buf(user_buf, count,
2846 					       curr_buf, &size,
2847 					       &bytes_copied);
2848 		data->prev_wr_ptr += size;
2849 
2850 		if (!b_full) {
2851 			size = write_ptr;
2852 			b_full = iwl_write_to_user_buf(user_buf, count,
2853 						       cpu_addr, &size,
2854 						       &bytes_copied);
2855 			data->prev_wr_ptr = size;
2856 			data->prev_wrap_cnt++;
2857 		}
2858 	} else {
2859 		if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2860 		    write_ptr > data->prev_wr_ptr)
2861 			IWL_WARN(trans,
2862 				 "write pointer passed previous write pointer, start copying from the beginning\n");
2863 		else if (!unlikely(data->prev_wrap_cnt == 0 &&
2864 				   data->prev_wr_ptr == 0))
2865 			IWL_WARN(trans,
2866 				 "monitor data is out of sync, start copying from the beginning\n");
2867 
2868 		size = write_ptr;
2869 		b_full = iwl_write_to_user_buf(user_buf, count,
2870 					       cpu_addr, &size,
2871 					       &bytes_copied);
2872 		data->prev_wr_ptr = size;
2873 		data->prev_wrap_cnt = wrap_cnt;
2874 	}
2875 
2876 	mutex_unlock(&data->mutex);
2877 
2878 	return bytes_copied;
2879 }
2880 
iwl_dbgfs_rf_read(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)2881 static ssize_t iwl_dbgfs_rf_read(struct file *file,
2882 				 char __user *user_buf,
2883 				 size_t count, loff_t *ppos)
2884 {
2885 	struct iwl_trans *trans = file->private_data;
2886 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2887 
2888 	if (!trans_pcie->rf_name[0])
2889 		return -ENODEV;
2890 
2891 	return simple_read_from_buffer(user_buf, count, ppos,
2892 				       trans_pcie->rf_name,
2893 				       strlen(trans_pcie->rf_name));
2894 }
2895 
2896 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2897 DEBUGFS_READ_FILE_OPS(fh_reg);
2898 DEBUGFS_READ_FILE_OPS(rx_queue);
2899 DEBUGFS_WRITE_FILE_OPS(csr);
2900 DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
2901 DEBUGFS_READ_FILE_OPS(rf);
2902 
2903 static const struct file_operations iwl_dbgfs_tx_queue_ops = {
2904 	.owner = THIS_MODULE,
2905 	.open = iwl_dbgfs_tx_queue_open,
2906 	.read = seq_read,
2907 	.llseek = seq_lseek,
2908 	.release = seq_release_private,
2909 };
2910 
2911 static const struct file_operations iwl_dbgfs_monitor_data_ops = {
2912 	.read = iwl_dbgfs_monitor_data_read,
2913 	.open = iwl_dbgfs_monitor_data_open,
2914 	.release = iwl_dbgfs_monitor_data_release,
2915 };
2916 
2917 /* Create the debugfs files and directories */
iwl_trans_pcie_dbgfs_register(struct iwl_trans * trans)2918 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2919 {
2920 	struct dentry *dir = trans->dbgfs_dir;
2921 
2922 	DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
2923 	DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
2924 	DEBUGFS_ADD_FILE(interrupt, dir, 0600);
2925 	DEBUGFS_ADD_FILE(csr, dir, 0200);
2926 	DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
2927 	DEBUGFS_ADD_FILE(rfkill, dir, 0600);
2928 	DEBUGFS_ADD_FILE(monitor_data, dir, 0400);
2929 	DEBUGFS_ADD_FILE(rf, dir, 0400);
2930 }
2931 
iwl_trans_pcie_debugfs_cleanup(struct iwl_trans * trans)2932 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans)
2933 {
2934 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2935 	struct cont_rec *data = &trans_pcie->fw_mon_data;
2936 
2937 	mutex_lock(&data->mutex);
2938 	data->state = IWL_FW_MON_DBGFS_STATE_DISABLED;
2939 	mutex_unlock(&data->mutex);
2940 }
2941 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2942 
iwl_trans_pcie_get_cmdlen(struct iwl_trans * trans,void * tfd)2943 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
2944 {
2945 	u32 cmdlen = 0;
2946 	int i;
2947 
2948 	for (i = 0; i < trans->txqs.tfd.max_tbs; i++)
2949 		cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i);
2950 
2951 	return cmdlen;
2952 }
2953 
iwl_trans_pcie_dump_rbs(struct iwl_trans * trans,struct iwl_fw_error_dump_data ** data,int allocated_rb_nums)2954 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2955 				   struct iwl_fw_error_dump_data **data,
2956 				   int allocated_rb_nums)
2957 {
2958 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2959 	int max_len = trans_pcie->rx_buf_bytes;
2960 	/* Dump RBs is supported only for pre-9000 devices (1 queue) */
2961 	struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2962 	u32 i, r, j, rb_len = 0;
2963 
2964 	spin_lock_bh(&rxq->lock);
2965 
2966 	r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
2967 
2968 	for (i = rxq->read, j = 0;
2969 	     i != r && j < allocated_rb_nums;
2970 	     i = (i + 1) & RX_QUEUE_MASK, j++) {
2971 		struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2972 		struct iwl_fw_error_dump_rb *rb;
2973 
2974 		dma_sync_single_for_cpu(trans->dev, rxb->page_dma,
2975 					max_len, DMA_FROM_DEVICE);
2976 
2977 		rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2978 
2979 		(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2980 		(*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2981 		rb = (void *)(*data)->data;
2982 		rb->index = cpu_to_le32(i);
2983 		memcpy(rb->data, page_address(rxb->page), max_len);
2984 
2985 		*data = iwl_fw_error_next_data(*data);
2986 	}
2987 
2988 	spin_unlock_bh(&rxq->lock);
2989 
2990 	return rb_len;
2991 }
2992 #define IWL_CSR_TO_DUMP (0x250)
2993 
iwl_trans_pcie_dump_csr(struct iwl_trans * trans,struct iwl_fw_error_dump_data ** data)2994 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2995 				   struct iwl_fw_error_dump_data **data)
2996 {
2997 	u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2998 	__le32 *val;
2999 	int i;
3000 
3001 	(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
3002 	(*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
3003 	val = (void *)(*data)->data;
3004 
3005 	for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
3006 		*val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3007 
3008 	*data = iwl_fw_error_next_data(*data);
3009 
3010 	return csr_len;
3011 }
3012 
iwl_trans_pcie_fh_regs_dump(struct iwl_trans * trans,struct iwl_fw_error_dump_data ** data)3013 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
3014 				       struct iwl_fw_error_dump_data **data)
3015 {
3016 	u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
3017 	__le32 *val;
3018 	int i;
3019 
3020 	if (!iwl_trans_grab_nic_access(trans))
3021 		return 0;
3022 
3023 	(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
3024 	(*data)->len = cpu_to_le32(fh_regs_len);
3025 	val = (void *)(*data)->data;
3026 
3027 	if (!trans->trans_cfg->gen2)
3028 		for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
3029 		     i += sizeof(u32))
3030 			*val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3031 	else
3032 		for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);
3033 		     i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);
3034 		     i += sizeof(u32))
3035 			*val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
3036 								      i));
3037 
3038 	iwl_trans_release_nic_access(trans);
3039 
3040 	*data = iwl_fw_error_next_data(*data);
3041 
3042 	return sizeof(**data) + fh_regs_len;
3043 }
3044 
3045 static u32
iwl_trans_pci_dump_marbh_monitor(struct iwl_trans * trans,struct iwl_fw_error_dump_fw_mon * fw_mon_data,u32 monitor_len)3046 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
3047 				 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
3048 				 u32 monitor_len)
3049 {
3050 	u32 buf_size_in_dwords = (monitor_len >> 2);
3051 	u32 *buffer = (u32 *)fw_mon_data->data;
3052 	u32 i;
3053 
3054 	if (!iwl_trans_grab_nic_access(trans))
3055 		return 0;
3056 
3057 	iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
3058 	for (i = 0; i < buf_size_in_dwords; i++)
3059 		buffer[i] = iwl_read_umac_prph_no_grab(trans,
3060 						       MON_DMARB_RD_DATA_ADDR);
3061 	iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
3062 
3063 	iwl_trans_release_nic_access(trans);
3064 
3065 	return monitor_len;
3066 }
3067 
3068 static void
iwl_trans_pcie_dump_pointers(struct iwl_trans * trans,struct iwl_fw_error_dump_fw_mon * fw_mon_data)3069 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
3070 			     struct iwl_fw_error_dump_fw_mon *fw_mon_data)
3071 {
3072 	u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt;
3073 
3074 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3075 		base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB;
3076 		base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB;
3077 		write_ptr = DBGC_CUR_DBGBUF_STATUS;
3078 		wrap_cnt = DBGC_DBGBUF_WRAP_AROUND;
3079 	} else if (trans->dbg.dest_tlv) {
3080 		write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
3081 		wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
3082 		base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3083 	} else {
3084 		base = MON_BUFF_BASE_ADDR;
3085 		write_ptr = MON_BUFF_WRPTR;
3086 		wrap_cnt = MON_BUFF_CYCLE_CNT;
3087 	}
3088 
3089 	write_ptr_val = iwl_read_prph(trans, write_ptr);
3090 	fw_mon_data->fw_mon_cycle_cnt =
3091 		cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
3092 	fw_mon_data->fw_mon_base_ptr =
3093 		cpu_to_le32(iwl_read_prph(trans, base));
3094 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3095 		fw_mon_data->fw_mon_base_high_ptr =
3096 			cpu_to_le32(iwl_read_prph(trans, base_high));
3097 		write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;
3098 		/* convert wrtPtr to DWs, to align with all HWs */
3099 		write_ptr_val >>= 2;
3100 	}
3101 	fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val);
3102 }
3103 
3104 static u32
iwl_trans_pcie_dump_monitor(struct iwl_trans * trans,struct iwl_fw_error_dump_data ** data,u32 monitor_len)3105 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
3106 			    struct iwl_fw_error_dump_data **data,
3107 			    u32 monitor_len)
3108 {
3109 	struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
3110 	u32 len = 0;
3111 
3112 	if (trans->dbg.dest_tlv ||
3113 	    (fw_mon->size &&
3114 	     (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 ||
3115 	      trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) {
3116 		struct iwl_fw_error_dump_fw_mon *fw_mon_data;
3117 
3118 		(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
3119 		fw_mon_data = (void *)(*data)->data;
3120 
3121 		iwl_trans_pcie_dump_pointers(trans, fw_mon_data);
3122 
3123 		len += sizeof(**data) + sizeof(*fw_mon_data);
3124 		if (fw_mon->size) {
3125 			memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size);
3126 			monitor_len = fw_mon->size;
3127 		} else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) {
3128 			u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr);
3129 			/*
3130 			 * Update pointers to reflect actual values after
3131 			 * shifting
3132 			 */
3133 			if (trans->dbg.dest_tlv->version) {
3134 				base = (iwl_read_prph(trans, base) &
3135 					IWL_LDBG_M2S_BUF_BA_MSK) <<
3136 				       trans->dbg.dest_tlv->base_shift;
3137 				base *= IWL_M2S_UNIT_SIZE;
3138 				base += trans->cfg->smem_offset;
3139 			} else {
3140 				base = iwl_read_prph(trans, base) <<
3141 				       trans->dbg.dest_tlv->base_shift;
3142 			}
3143 
3144 			iwl_trans_read_mem(trans, base, fw_mon_data->data,
3145 					   monitor_len / sizeof(u32));
3146 		} else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) {
3147 			monitor_len =
3148 				iwl_trans_pci_dump_marbh_monitor(trans,
3149 								 fw_mon_data,
3150 								 monitor_len);
3151 		} else {
3152 			/* Didn't match anything - output no monitor data */
3153 			monitor_len = 0;
3154 		}
3155 
3156 		len += monitor_len;
3157 		(*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
3158 	}
3159 
3160 	return len;
3161 }
3162 
iwl_trans_get_fw_monitor_len(struct iwl_trans * trans,u32 * len)3163 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)
3164 {
3165 	if (trans->dbg.fw_mon.size) {
3166 		*len += sizeof(struct iwl_fw_error_dump_data) +
3167 			sizeof(struct iwl_fw_error_dump_fw_mon) +
3168 			trans->dbg.fw_mon.size;
3169 		return trans->dbg.fw_mon.size;
3170 	} else if (trans->dbg.dest_tlv) {
3171 		u32 base, end, cfg_reg, monitor_len;
3172 
3173 		if (trans->dbg.dest_tlv->version == 1) {
3174 			cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3175 			cfg_reg = iwl_read_prph(trans, cfg_reg);
3176 			base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
3177 				trans->dbg.dest_tlv->base_shift;
3178 			base *= IWL_M2S_UNIT_SIZE;
3179 			base += trans->cfg->smem_offset;
3180 
3181 			monitor_len =
3182 				(cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
3183 				trans->dbg.dest_tlv->end_shift;
3184 			monitor_len *= IWL_M2S_UNIT_SIZE;
3185 		} else {
3186 			base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3187 			end = le32_to_cpu(trans->dbg.dest_tlv->end_reg);
3188 
3189 			base = iwl_read_prph(trans, base) <<
3190 			       trans->dbg.dest_tlv->base_shift;
3191 			end = iwl_read_prph(trans, end) <<
3192 			      trans->dbg.dest_tlv->end_shift;
3193 
3194 			/* Make "end" point to the actual end */
3195 			if (trans->trans_cfg->device_family >=
3196 			    IWL_DEVICE_FAMILY_8000 ||
3197 			    trans->dbg.dest_tlv->monitor_mode == MARBH_MODE)
3198 				end += (1 << trans->dbg.dest_tlv->end_shift);
3199 			monitor_len = end - base;
3200 		}
3201 		*len += sizeof(struct iwl_fw_error_dump_data) +
3202 			sizeof(struct iwl_fw_error_dump_fw_mon) +
3203 			monitor_len;
3204 		return monitor_len;
3205 	}
3206 	return 0;
3207 }
3208 
3209 static struct iwl_trans_dump_data
iwl_trans_pcie_dump_data(struct iwl_trans * trans,u32 dump_mask)3210 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
3211 			  u32 dump_mask)
3212 {
3213 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3214 	struct iwl_fw_error_dump_data *data;
3215 	struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id];
3216 	struct iwl_fw_error_dump_txcmd *txcmd;
3217 	struct iwl_trans_dump_data *dump_data;
3218 	u32 len, num_rbs = 0, monitor_len = 0;
3219 	int i, ptr;
3220 	bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
3221 			!trans->trans_cfg->mq_rx_supported &&
3222 			dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
3223 
3224 	if (!dump_mask)
3225 		return NULL;
3226 
3227 	/* transport dump header */
3228 	len = sizeof(*dump_data);
3229 
3230 	/* host commands */
3231 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq)
3232 		len += sizeof(*data) +
3233 			cmdq->n_window * (sizeof(*txcmd) +
3234 					  TFD_MAX_PAYLOAD_SIZE);
3235 
3236 	/* FW monitor */
3237 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3238 		monitor_len = iwl_trans_get_fw_monitor_len(trans, &len);
3239 
3240 	/* CSR registers */
3241 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3242 		len += sizeof(*data) + IWL_CSR_TO_DUMP;
3243 
3244 	/* FH registers */
3245 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
3246 		if (trans->trans_cfg->gen2)
3247 			len += sizeof(*data) +
3248 			       (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -
3249 				iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));
3250 		else
3251 			len += sizeof(*data) +
3252 			       (FH_MEM_UPPER_BOUND -
3253 				FH_MEM_LOWER_BOUND);
3254 	}
3255 
3256 	if (dump_rbs) {
3257 		/* Dump RBs is supported only for pre-9000 devices (1 queue) */
3258 		struct iwl_rxq *rxq = &trans_pcie->rxq[0];
3259 		/* RBs */
3260 		num_rbs =
3261 			le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq))
3262 			& 0x0FFF;
3263 		num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
3264 		len += num_rbs * (sizeof(*data) +
3265 				  sizeof(struct iwl_fw_error_dump_rb) +
3266 				  (PAGE_SIZE << trans_pcie->rx_page_order));
3267 	}
3268 
3269 	/* Paged memory for gen2 HW */
3270 	if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
3271 		for (i = 0; i < trans->init_dram.paging_cnt; i++)
3272 			len += sizeof(*data) +
3273 			       sizeof(struct iwl_fw_error_dump_paging) +
3274 			       trans->init_dram.paging[i].size;
3275 
3276 	dump_data = vzalloc(len);
3277 	if (!dump_data)
3278 		return NULL;
3279 
3280 	len = 0;
3281 	data = (void *)dump_data->data;
3282 
3283 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) {
3284 		u16 tfd_size = trans->txqs.tfd.size;
3285 
3286 		data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3287 		txcmd = (void *)data->data;
3288 		spin_lock_bh(&cmdq->lock);
3289 		ptr = cmdq->write_ptr;
3290 		for (i = 0; i < cmdq->n_window; i++) {
3291 			u8 idx = iwl_txq_get_cmd_index(cmdq, ptr);
3292 			u8 tfdidx;
3293 			u32 caplen, cmdlen;
3294 
3295 			if (trans->trans_cfg->use_tfh)
3296 				tfdidx = idx;
3297 			else
3298 				tfdidx = ptr;
3299 
3300 			cmdlen = iwl_trans_pcie_get_cmdlen(trans,
3301 							   (u8 *)cmdq->tfds +
3302 							   tfd_size * tfdidx);
3303 			caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3304 
3305 			if (cmdlen) {
3306 				len += sizeof(*txcmd) + caplen;
3307 				txcmd->cmdlen = cpu_to_le32(cmdlen);
3308 				txcmd->caplen = cpu_to_le32(caplen);
3309 				memcpy(txcmd->data, cmdq->entries[idx].cmd,
3310 				       caplen);
3311 				txcmd = (void *)((u8 *)txcmd->data + caplen);
3312 			}
3313 
3314 			ptr = iwl_txq_dec_wrap(trans, ptr);
3315 		}
3316 		spin_unlock_bh(&cmdq->lock);
3317 
3318 		data->len = cpu_to_le32(len);
3319 		len += sizeof(*data);
3320 		data = iwl_fw_error_next_data(data);
3321 	}
3322 
3323 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3324 		len += iwl_trans_pcie_dump_csr(trans, &data);
3325 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
3326 		len += iwl_trans_pcie_fh_regs_dump(trans, &data);
3327 	if (dump_rbs)
3328 		len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
3329 
3330 	/* Paged memory for gen2 HW */
3331 	if (trans->trans_cfg->gen2 &&
3332 	    dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
3333 		for (i = 0; i < trans->init_dram.paging_cnt; i++) {
3334 			struct iwl_fw_error_dump_paging *paging;
3335 			u32 page_len = trans->init_dram.paging[i].size;
3336 
3337 			data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3338 			data->len = cpu_to_le32(sizeof(*paging) + page_len);
3339 			paging = (void *)data->data;
3340 			paging->index = cpu_to_le32(i);
3341 			memcpy(paging->data,
3342 			       trans->init_dram.paging[i].block, page_len);
3343 			data = iwl_fw_error_next_data(data);
3344 
3345 			len += sizeof(*data) + sizeof(*paging) + page_len;
3346 		}
3347 	}
3348 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3349 		len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
3350 
3351 	dump_data->len = len;
3352 
3353 	return dump_data;
3354 }
3355 
iwl_trans_pci_interrupts(struct iwl_trans * trans,bool enable)3356 static void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable)
3357 {
3358 	if (enable)
3359 		iwl_enable_interrupts(trans);
3360 	else
3361 		iwl_disable_interrupts(trans);
3362 }
3363 
iwl_trans_pcie_sync_nmi(struct iwl_trans * trans)3364 static void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans)
3365 {
3366 	u32 inta_addr, sw_err_bit;
3367 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3368 
3369 	if (trans_pcie->msix_enabled) {
3370 		inta_addr = CSR_MSIX_HW_INT_CAUSES_AD;
3371 		sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR;
3372 	} else {
3373 		inta_addr = CSR_INT;
3374 		sw_err_bit = CSR_INT_BIT_SW_ERR;
3375 	}
3376 
3377 	iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit);
3378 }
3379 
3380 #define IWL_TRANS_COMMON_OPS						\
3381 	.op_mode_leave = iwl_trans_pcie_op_mode_leave,			\
3382 	.write8 = iwl_trans_pcie_write8,				\
3383 	.write32 = iwl_trans_pcie_write32,				\
3384 	.read32 = iwl_trans_pcie_read32,				\
3385 	.read_prph = iwl_trans_pcie_read_prph,				\
3386 	.write_prph = iwl_trans_pcie_write_prph,			\
3387 	.read_mem = iwl_trans_pcie_read_mem,				\
3388 	.write_mem = iwl_trans_pcie_write_mem,				\
3389 	.read_config32 = iwl_trans_pcie_read_config32,			\
3390 	.configure = iwl_trans_pcie_configure,				\
3391 	.set_pmi = iwl_trans_pcie_set_pmi,				\
3392 	.sw_reset = iwl_trans_pcie_sw_reset,				\
3393 	.grab_nic_access = iwl_trans_pcie_grab_nic_access,		\
3394 	.release_nic_access = iwl_trans_pcie_release_nic_access,	\
3395 	.set_bits_mask = iwl_trans_pcie_set_bits_mask,			\
3396 	.dump_data = iwl_trans_pcie_dump_data,				\
3397 	.d3_suspend = iwl_trans_pcie_d3_suspend,			\
3398 	.d3_resume = iwl_trans_pcie_d3_resume,				\
3399 	.interrupts = iwl_trans_pci_interrupts,				\
3400 	.sync_nmi = iwl_trans_pcie_sync_nmi				\
3401 
3402 static const struct iwl_trans_ops trans_ops_pcie = {
3403 	IWL_TRANS_COMMON_OPS,
3404 	.start_hw = iwl_trans_pcie_start_hw,
3405 	.fw_alive = iwl_trans_pcie_fw_alive,
3406 	.start_fw = iwl_trans_pcie_start_fw,
3407 	.stop_device = iwl_trans_pcie_stop_device,
3408 
3409 	.send_cmd = iwl_pcie_enqueue_hcmd,
3410 
3411 	.tx = iwl_trans_pcie_tx,
3412 	.reclaim = iwl_txq_reclaim,
3413 
3414 	.txq_disable = iwl_trans_pcie_txq_disable,
3415 	.txq_enable = iwl_trans_pcie_txq_enable,
3416 
3417 	.txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3418 
3419 	.wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3420 
3421 	.freeze_txq_timer = iwl_trans_txq_freeze_timer,
3422 	.block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
3423 #ifdef CONFIG_IWLWIFI_DEBUGFS
3424 	.debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3425 #endif
3426 };
3427 
3428 static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3429 	IWL_TRANS_COMMON_OPS,
3430 	.start_hw = iwl_trans_pcie_start_hw,
3431 	.fw_alive = iwl_trans_pcie_gen2_fw_alive,
3432 	.start_fw = iwl_trans_pcie_gen2_start_fw,
3433 	.stop_device = iwl_trans_pcie_gen2_stop_device,
3434 
3435 	.send_cmd = iwl_pcie_gen2_enqueue_hcmd,
3436 
3437 	.tx = iwl_txq_gen2_tx,
3438 	.reclaim = iwl_txq_reclaim,
3439 
3440 	.set_q_ptrs = iwl_txq_set_q_ptrs,
3441 
3442 	.txq_alloc = iwl_txq_dyn_alloc,
3443 	.txq_free = iwl_txq_dyn_free,
3444 	.wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
3445 	.rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
3446 	.set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm,
3447 	.set_reduce_power = iwl_trans_pcie_ctx_info_gen3_set_reduce_power,
3448 #ifdef CONFIG_IWLWIFI_DEBUGFS
3449 	.debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3450 #endif
3451 };
3452 
iwl_trans_pcie_alloc(struct pci_dev * pdev,const struct pci_device_id * ent,const struct iwl_cfg_trans_params * cfg_trans)3453 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
3454 			       const struct pci_device_id *ent,
3455 			       const struct iwl_cfg_trans_params *cfg_trans)
3456 {
3457 	struct iwl_trans_pcie *trans_pcie;
3458 	struct iwl_trans *trans;
3459 	int ret, addr_size;
3460 	const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2;
3461 	void __iomem * const *table;
3462 
3463 	if (!cfg_trans->gen2)
3464 		ops = &trans_ops_pcie;
3465 
3466 	ret = pcim_enable_device(pdev);
3467 	if (ret)
3468 		return ERR_PTR(ret);
3469 
3470 	trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops,
3471 				cfg_trans);
3472 	if (!trans)
3473 		return ERR_PTR(-ENOMEM);
3474 
3475 	trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3476 
3477 	trans_pcie->trans = trans;
3478 	trans_pcie->opmode_down = true;
3479 	spin_lock_init(&trans_pcie->irq_lock);
3480 	spin_lock_init(&trans_pcie->reg_lock);
3481 	spin_lock_init(&trans_pcie->alloc_page_lock);
3482 	mutex_init(&trans_pcie->mutex);
3483 	init_waitqueue_head(&trans_pcie->ucode_write_waitq);
3484 	init_waitqueue_head(&trans_pcie->fw_reset_waitq);
3485 
3486 	trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3487 						   WQ_HIGHPRI | WQ_UNBOUND, 1);
3488 	if (!trans_pcie->rba.alloc_wq) {
3489 		ret = -ENOMEM;
3490 		goto out_free_trans;
3491 	}
3492 	INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3493 
3494 	trans_pcie->debug_rfkill = -1;
3495 
3496 	if (!cfg_trans->base_params->pcie_l1_allowed) {
3497 		/*
3498 		 * W/A - seems to solve weird behavior. We need to remove this
3499 		 * if we don't want to stay in L1 all the time. This wastes a
3500 		 * lot of power.
3501 		 */
3502 		pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3503 				       PCIE_LINK_STATE_L1 |
3504 				       PCIE_LINK_STATE_CLKPM);
3505 	}
3506 
3507 	trans_pcie->def_rx_queue = 0;
3508 
3509 	pci_set_master(pdev);
3510 
3511 	addr_size = trans->txqs.tfd.addr_size;
3512 	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size));
3513 	if (ret) {
3514 		ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3515 		/* both attempts failed: */
3516 		if (ret) {
3517 			dev_err(&pdev->dev, "No suitable DMA available\n");
3518 			goto out_no_pci;
3519 		}
3520 	}
3521 
3522 	ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
3523 	if (ret) {
3524 		dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3525 		goto out_no_pci;
3526 	}
3527 
3528 	table = pcim_iomap_table(pdev);
3529 	if (!table) {
3530 		dev_err(&pdev->dev, "pcim_iomap_table failed\n");
3531 		ret = -ENOMEM;
3532 		goto out_no_pci;
3533 	}
3534 
3535 	trans_pcie->hw_base = table[0];
3536 	if (!trans_pcie->hw_base) {
3537 		dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n");
3538 		ret = -ENODEV;
3539 		goto out_no_pci;
3540 	}
3541 
3542 	/* We disable the RETRY_TIMEOUT register (0x41) to keep
3543 	 * PCI Tx retries from interfering with C3 CPU state */
3544 	pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3545 
3546 	trans_pcie->pci_dev = pdev;
3547 	iwl_disable_interrupts(trans);
3548 
3549 	trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
3550 	if (trans->hw_rev == 0xffffffff) {
3551 		dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n");
3552 		ret = -EIO;
3553 		goto out_no_pci;
3554 	}
3555 
3556 	/*
3557 	 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3558 	 * changed, and now the revision step also includes bit 0-1 (no more
3559 	 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3560 	 * in the old format.
3561 	 */
3562 	if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000)
3563 		trans->hw_rev = (trans->hw_rev & 0xfff0) |
3564 				(CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
3565 
3566 	IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev);
3567 
3568 	iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans);
3569 	trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
3570 	snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3571 		 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
3572 
3573 	init_waitqueue_head(&trans_pcie->sx_waitq);
3574 
3575 
3576 	if (trans_pcie->msix_enabled) {
3577 		ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3578 		if (ret)
3579 			goto out_no_pci;
3580 	 } else {
3581 		ret = iwl_pcie_alloc_ict(trans);
3582 		if (ret)
3583 			goto out_no_pci;
3584 
3585 		ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3586 						iwl_pcie_isr,
3587 						iwl_pcie_irq_handler,
3588 						IRQF_SHARED, DRV_NAME, trans);
3589 		if (ret) {
3590 			IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3591 			goto out_free_ict;
3592 		}
3593 	 }
3594 
3595 #ifdef CONFIG_IWLWIFI_DEBUGFS
3596 	trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
3597 	mutex_init(&trans_pcie->fw_mon_data.mutex);
3598 #endif
3599 
3600 	iwl_dbg_tlv_init(trans);
3601 
3602 	return trans;
3603 
3604 out_free_ict:
3605 	iwl_pcie_free_ict(trans);
3606 out_no_pci:
3607 	destroy_workqueue(trans_pcie->rba.alloc_wq);
3608 out_free_trans:
3609 	iwl_trans_free(trans);
3610 	return ERR_PTR(ret);
3611 }
3612