1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2018-2021 Intel Corporation
4 */
5 #include "iwl-trans.h"
6 #include "iwl-fh.h"
7 #include "iwl-context-info-gen3.h"
8 #include "internal.h"
9 #include "iwl-prph.h"
10
11 static void
iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans * trans,struct iwl_prph_scratch_hwm_cfg * dbg_cfg,u32 * control_flags)12 iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans,
13 struct iwl_prph_scratch_hwm_cfg *dbg_cfg,
14 u32 *control_flags)
15 {
16 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
17 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg;
18 u32 dbg_flags = 0;
19
20 if (!iwl_trans_dbg_ini_valid(trans)) {
21 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
22
23 iwl_pcie_alloc_fw_monitor(trans, 0);
24
25 if (fw_mon->size) {
26 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
27
28 IWL_DEBUG_FW(trans,
29 "WRT: Applying DRAM buffer destination\n");
30
31 dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical);
32 dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size);
33 }
34
35 goto out;
36 }
37
38 fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id];
39
40 switch (le32_to_cpu(fw_mon_cfg->buf_location)) {
41 case IWL_FW_INI_LOCATION_SRAM_PATH:
42 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL;
43 IWL_DEBUG_FW(trans,
44 "WRT: Applying SMEM buffer destination\n");
45 break;
46
47 case IWL_FW_INI_LOCATION_NPK_PATH:
48 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF;
49 IWL_DEBUG_FW(trans,
50 "WRT: Applying NPK buffer destination\n");
51 break;
52
53 case IWL_FW_INI_LOCATION_DRAM_PATH:
54 if (trans->dbg.fw_mon_ini[alloc_id].num_frags) {
55 struct iwl_dram_data *frag =
56 &trans->dbg.fw_mon_ini[alloc_id].frags[0];
57 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
58 dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical);
59 dbg_cfg->hwm_size = cpu_to_le32(frag->size);
60 IWL_DEBUG_FW(trans,
61 "WRT: Applying DRAM destination (alloc_id=%u, num_frags=%u)\n",
62 alloc_id,
63 trans->dbg.fw_mon_ini[alloc_id].num_frags);
64 }
65 break;
66 default:
67 IWL_ERR(trans, "WRT: Invalid buffer destination\n");
68 }
69 out:
70 if (dbg_flags)
71 *control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags;
72 }
73
iwl_pcie_ctxt_info_gen3_init(struct iwl_trans * trans,const struct fw_img * fw)74 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
75 const struct fw_img *fw)
76 {
77 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
78 struct iwl_context_info_gen3 *ctxt_info_gen3;
79 struct iwl_prph_scratch *prph_scratch;
80 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl;
81 struct iwl_prph_info *prph_info;
82 u32 control_flags = 0;
83 int ret;
84 int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
85 trans->cfg->min_txq_size);
86
87 switch (trans_pcie->rx_buf_size) {
88 case IWL_AMSDU_DEF:
89 return -EINVAL;
90 case IWL_AMSDU_2K:
91 break;
92 case IWL_AMSDU_4K:
93 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
94 break;
95 case IWL_AMSDU_8K:
96 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
97 /* if firmware supports the ext size, tell it */
98 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K;
99 break;
100 case IWL_AMSDU_12K:
101 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
102 /* if firmware supports the ext size, tell it */
103 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K;
104 break;
105 }
106
107 /* Allocate prph scratch */
108 prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch),
109 &trans_pcie->prph_scratch_dma_addr,
110 GFP_KERNEL);
111 if (!prph_scratch)
112 return -ENOMEM;
113
114 prph_sc_ctrl = &prph_scratch->ctrl_cfg;
115
116 prph_sc_ctrl->version.version = 0;
117 prph_sc_ctrl->version.mac_id =
118 cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV));
119 prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4);
120
121 control_flags |= IWL_PRPH_SCRATCH_MTR_MODE;
122 control_flags |= IWL_PRPH_MTR_FORMAT_256B & IWL_PRPH_SCRATCH_MTR_FORMAT;
123
124 /* initialize RX default queue */
125 prph_sc_ctrl->rbd_cfg.free_rbd_addr =
126 cpu_to_le64(trans_pcie->rxq->bd_dma);
127
128 iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg,
129 &control_flags);
130 prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags);
131
132 /* allocate ucode sections in dram and set addresses */
133 ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram);
134 if (ret)
135 goto err_free_prph_scratch;
136
137
138 /* Allocate prph information
139 * currently we don't assign to the prph info anything, but it would get
140 * assigned later
141 *
142 * We also use the second half of this page to give the device some
143 * dummy TR/CR tail pointers - which shouldn't be necessary as we don't
144 * use this, but the hardware still reads/writes there and we can't let
145 * it go do that with a NULL pointer.
146 */
147 BUILD_BUG_ON(sizeof(*prph_info) > PAGE_SIZE / 2);
148 prph_info = dma_alloc_coherent(trans->dev, PAGE_SIZE,
149 &trans_pcie->prph_info_dma_addr,
150 GFP_KERNEL);
151 if (!prph_info) {
152 ret = -ENOMEM;
153 goto err_free_prph_scratch;
154 }
155
156 /* Allocate context info */
157 ctxt_info_gen3 = dma_alloc_coherent(trans->dev,
158 sizeof(*ctxt_info_gen3),
159 &trans_pcie->ctxt_info_dma_addr,
160 GFP_KERNEL);
161 if (!ctxt_info_gen3) {
162 ret = -ENOMEM;
163 goto err_free_prph_info;
164 }
165
166 ctxt_info_gen3->prph_info_base_addr =
167 cpu_to_le64(trans_pcie->prph_info_dma_addr);
168 ctxt_info_gen3->prph_scratch_base_addr =
169 cpu_to_le64(trans_pcie->prph_scratch_dma_addr);
170 ctxt_info_gen3->prph_scratch_size =
171 cpu_to_le32(sizeof(*prph_scratch));
172 ctxt_info_gen3->cr_head_idx_arr_base_addr =
173 cpu_to_le64(trans_pcie->rxq->rb_stts_dma);
174 ctxt_info_gen3->tr_tail_idx_arr_base_addr =
175 cpu_to_le64(trans_pcie->prph_info_dma_addr + PAGE_SIZE / 2);
176 ctxt_info_gen3->cr_tail_idx_arr_base_addr =
177 cpu_to_le64(trans_pcie->prph_info_dma_addr + 3 * PAGE_SIZE / 4);
178 ctxt_info_gen3->mtr_base_addr =
179 cpu_to_le64(trans->txqs.txq[trans->txqs.cmd.q_id]->dma_addr);
180 ctxt_info_gen3->mcr_base_addr =
181 cpu_to_le64(trans_pcie->rxq->used_bd_dma);
182 ctxt_info_gen3->mtr_size =
183 cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size));
184 ctxt_info_gen3->mcr_size =
185 cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds));
186
187 trans_pcie->ctxt_info_gen3 = ctxt_info_gen3;
188 trans_pcie->prph_info = prph_info;
189 trans_pcie->prph_scratch = prph_scratch;
190
191 /* Allocate IML */
192 trans_pcie->iml = dma_alloc_coherent(trans->dev, trans->iml_len,
193 &trans_pcie->iml_dma_addr,
194 GFP_KERNEL);
195 if (!trans_pcie->iml) {
196 ret = -ENOMEM;
197 goto err_free_ctxt_info;
198 }
199
200 memcpy(trans_pcie->iml, trans->iml, trans->iml_len);
201
202 iwl_enable_fw_load_int_ctx_info(trans);
203
204 /* kick FW self load */
205 iwl_write64(trans, CSR_CTXT_INFO_ADDR,
206 trans_pcie->ctxt_info_dma_addr);
207 iwl_write64(trans, CSR_IML_DATA_ADDR,
208 trans_pcie->iml_dma_addr);
209 iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len);
210
211 iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL,
212 CSR_AUTO_FUNC_BOOT_ENA);
213
214 return 0;
215
216 err_free_ctxt_info:
217 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3),
218 trans_pcie->ctxt_info_gen3,
219 trans_pcie->ctxt_info_dma_addr);
220 trans_pcie->ctxt_info_gen3 = NULL;
221 err_free_prph_info:
222 dma_free_coherent(trans->dev, PAGE_SIZE, prph_info,
223 trans_pcie->prph_info_dma_addr);
224
225 err_free_prph_scratch:
226 dma_free_coherent(trans->dev,
227 sizeof(*prph_scratch),
228 prph_scratch,
229 trans_pcie->prph_scratch_dma_addr);
230 return ret;
231
232 }
233
iwl_pcie_ctxt_info_gen3_free(struct iwl_trans * trans,bool alive)234 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans, bool alive)
235 {
236 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
237
238 if (trans_pcie->iml) {
239 dma_free_coherent(trans->dev, trans->iml_len, trans_pcie->iml,
240 trans_pcie->iml_dma_addr);
241 trans_pcie->iml_dma_addr = 0;
242 trans_pcie->iml = NULL;
243 }
244
245 iwl_pcie_ctxt_info_free_fw_img(trans);
246
247 if (alive)
248 return;
249
250 if (!trans_pcie->ctxt_info_gen3)
251 return;
252
253 /* ctxt_info_gen3 and prph_scratch are still needed for PNVM load */
254 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3),
255 trans_pcie->ctxt_info_gen3,
256 trans_pcie->ctxt_info_dma_addr);
257 trans_pcie->ctxt_info_dma_addr = 0;
258 trans_pcie->ctxt_info_gen3 = NULL;
259
260 dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch),
261 trans_pcie->prph_scratch,
262 trans_pcie->prph_scratch_dma_addr);
263 trans_pcie->prph_scratch_dma_addr = 0;
264 trans_pcie->prph_scratch = NULL;
265
266 /* this is needed for the entire lifetime */
267 dma_free_coherent(trans->dev, PAGE_SIZE, trans_pcie->prph_info,
268 trans_pcie->prph_info_dma_addr);
269 trans_pcie->prph_info_dma_addr = 0;
270 trans_pcie->prph_info = NULL;
271 }
272
iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans * trans,const void * data,u32 len)273 int iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans,
274 const void *data, u32 len)
275 {
276 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
277 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
278 &trans_pcie->prph_scratch->ctrl_cfg;
279 int ret;
280
281 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
282 return 0;
283
284 /* only allocate the DRAM if not allocated yet */
285 if (!trans->pnvm_loaded) {
286 if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size))
287 return -EBUSY;
288
289 ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len,
290 &trans_pcie->pnvm_dram);
291 if (ret < 0) {
292 IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA %d.\n",
293 ret);
294 return ret;
295 }
296 }
297
298 prph_sc_ctrl->pnvm_cfg.pnvm_base_addr =
299 cpu_to_le64(trans_pcie->pnvm_dram.physical);
300 prph_sc_ctrl->pnvm_cfg.pnvm_size =
301 cpu_to_le32(trans_pcie->pnvm_dram.size);
302
303 return 0;
304 }
305
iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans * trans,const void * data,u32 len)306 int iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans,
307 const void *data, u32 len)
308 {
309 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
310 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
311 &trans_pcie->prph_scratch->ctrl_cfg;
312 int ret;
313
314 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
315 return 0;
316
317 /* only allocate the DRAM if not allocated yet */
318 if (!trans->reduce_power_loaded) {
319 if (WARN_ON(prph_sc_ctrl->reduce_power_cfg.size))
320 return -EBUSY;
321
322 ret = iwl_pcie_ctxt_info_alloc_dma(trans, data, len,
323 &trans_pcie->reduce_power_dram);
324 if (ret < 0) {
325 IWL_DEBUG_FW(trans,
326 "Failed to allocate reduce power DMA %d.\n",
327 ret);
328 return ret;
329 }
330 }
331
332 prph_sc_ctrl->reduce_power_cfg.base_addr =
333 cpu_to_le64(trans_pcie->reduce_power_dram.physical);
334 prph_sc_ctrl->reduce_power_cfg.size =
335 cpu_to_le32(trans_pcie->reduce_power_dram.size);
336
337 return 0;
338 }
339