1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * This control block defines the PACA which defines the processor
4 * specific data for each logical processor on the system.
5 * There are some pointers defined that are utilized by PLIC.
6 *
7 * C 2001 PPC 64 Team, IBM Corp
8 */
9 #ifndef _ASM_POWERPC_PACA_H
10 #define _ASM_POWERPC_PACA_H
11 #ifdef __KERNEL__
12
13 #ifdef CONFIG_PPC64
14
15 #include <linux/cache.h>
16 #include <linux/string.h>
17 #include <asm/types.h>
18 #include <asm/mmu.h>
19 #include <asm/page.h>
20 #ifdef CONFIG_PPC_BOOK3E
21 #include <asm/exception-64e.h>
22 #else
23 #include <asm/exception-64s.h>
24 #endif
25 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
26 #include <asm/kvm_book3s_asm.h>
27 #endif
28 #include <asm/accounting.h>
29 #include <asm/hmi.h>
30 #include <asm/cpuidle.h>
31 #include <asm/atomic.h>
32 #include <asm/mce.h>
33
34 #include <asm-generic/mmiowb_types.h>
35
36 register struct paca_struct *local_paca asm("r13");
37
38 #if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP)
39 extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
40 /*
41 * Add standard checks that preemption cannot occur when using get_paca():
42 * otherwise the paca_struct it points to may be the wrong one just after.
43 */
44 #define get_paca() ((void) debug_smp_processor_id(), local_paca)
45 #else
46 #define get_paca() local_paca
47 #endif
48
49 #define get_slb_shadow() (get_paca()->slb_shadow_ptr)
50
51 struct task_struct;
52 struct rtas_args;
53 struct lppaca;
54
55 /*
56 * Defines the layout of the paca.
57 *
58 * This structure is not directly accessed by firmware or the service
59 * processor.
60 */
61 struct paca_struct {
62 #ifdef CONFIG_PPC_PSERIES
63 /*
64 * Because hw_cpu_id, unlike other paca fields, is accessed
65 * routinely from other CPUs (from the IRQ code), we stick to
66 * read-only (after boot) fields in the first cacheline to
67 * avoid cacheline bouncing.
68 */
69
70 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
71 #endif /* CONFIG_PPC_PSERIES */
72
73 /*
74 * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c
75 * load lock_token and paca_index with a single lwz
76 * instruction. They must travel together and be properly
77 * aligned.
78 */
79 #ifdef __BIG_ENDIAN__
80 u16 lock_token; /* Constant 0x8000, used in locks */
81 u16 paca_index; /* Logical processor number */
82 #else
83 u16 paca_index; /* Logical processor number */
84 u16 lock_token; /* Constant 0x8000, used in locks */
85 #endif
86
87 u64 kernel_toc; /* Kernel TOC address */
88 u64 kernelbase; /* Base address of kernel */
89 u64 kernel_msr; /* MSR while running in kernel */
90 void *emergency_sp; /* pointer to emergency stack */
91 u64 data_offset; /* per cpu data offset */
92 s16 hw_cpu_id; /* Physical processor number */
93 u8 cpu_start; /* At startup, processor spins until */
94 /* this becomes non-zero. */
95 u8 kexec_state; /* set when kexec down has irqs off */
96 #ifdef CONFIG_PPC_BOOK3S_64
97 struct slb_shadow *slb_shadow_ptr;
98 struct dtl_entry *dispatch_log;
99 struct dtl_entry *dispatch_log_end;
100 #endif
101 u64 dscr_default; /* per-CPU default DSCR */
102
103 #ifdef CONFIG_PPC_BOOK3S_64
104 /*
105 * Now, starting in cacheline 2, the exception save areas
106 */
107 /* used for most interrupts/exceptions */
108 u64 exgen[EX_SIZE] __attribute__((aligned(0x80)));
109
110 /* SLB related definitions */
111 u16 vmalloc_sllp;
112 u8 slb_cache_ptr;
113 u8 stab_rr; /* stab/slb round-robin counter */
114 #ifdef CONFIG_DEBUG_VM
115 u8 in_kernel_slb_handler;
116 #endif
117 u32 slb_used_bitmap; /* Bitmaps for first 32 SLB entries. */
118 u32 slb_kern_bitmap;
119 u32 slb_cache[SLB_CACHE_ENTRIES];
120 #endif /* CONFIG_PPC_BOOK3S_64 */
121
122 #ifdef CONFIG_PPC_BOOK3E
123 u64 exgen[8] __aligned(0x40);
124 /* Keep pgd in the same cacheline as the start of extlb */
125 pgd_t *pgd __aligned(0x40); /* Current PGD */
126 pgd_t *kernel_pgd; /* Kernel PGD */
127
128 /* Shared by all threads of a core -- points to tcd of first thread */
129 struct tlb_core_data *tcd_ptr;
130
131 /*
132 * We can have up to 3 levels of reentrancy in the TLB miss handler,
133 * in each of four exception levels (normal, crit, mcheck, debug).
134 */
135 u64 extlb[12][EX_TLB_SIZE / sizeof(u64)];
136 u64 exmc[8]; /* used for machine checks */
137 u64 excrit[8]; /* used for crit interrupts */
138 u64 exdbg[8]; /* used for debug interrupts */
139
140 /* Kernel stack pointers for use by special exceptions */
141 void *mc_kstack;
142 void *crit_kstack;
143 void *dbg_kstack;
144
145 struct tlb_core_data tcd;
146 #endif /* CONFIG_PPC_BOOK3E */
147
148 #ifdef CONFIG_PPC_BOOK3S
149 #ifdef CONFIG_PPC_MM_SLICES
150 unsigned char mm_ctx_low_slices_psize[BITS_PER_LONG / BITS_PER_BYTE];
151 unsigned char mm_ctx_high_slices_psize[SLICE_ARRAY_SIZE];
152 #else
153 u16 mm_ctx_user_psize;
154 u16 mm_ctx_sllp;
155 #endif
156 #endif
157
158 /*
159 * then miscellaneous read-write fields
160 */
161 struct task_struct *__current; /* Pointer to current */
162 u64 kstack; /* Saved Kernel stack addr */
163 u64 saved_r1; /* r1 save for RTAS calls or PM or EE=0 */
164 u64 saved_msr; /* MSR saved here by enter_rtas */
165 #ifdef CONFIG_PPC64
166 u64 exit_save_r1; /* Syscall/interrupt R1 save */
167 #endif
168 #ifdef CONFIG_PPC_BOOK3E
169 u16 trap_save; /* Used when bad stack is encountered */
170 #endif
171 #ifdef CONFIG_PPC_BOOK3S_64
172 u8 hsrr_valid; /* HSRRs set for HRFID */
173 u8 srr_valid; /* SRRs set for RFID */
174 #endif
175 u8 irq_soft_mask; /* mask for irq soft masking */
176 u8 irq_happened; /* irq happened while soft-disabled */
177 u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */
178 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
179 u8 pmcregs_in_use; /* pseries puts this in lppaca */
180 #endif
181 u64 sprg_vdso; /* Saved user-visible sprg */
182 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
183 u64 tm_scratch; /* TM scratch area for reclaim */
184 #endif
185
186 #ifdef CONFIG_PPC_POWERNV
187 /* PowerNV idle fields */
188 /* PNV_CORE_IDLE_* bits, all siblings work on thread 0 paca */
189 unsigned long idle_state;
190 union {
191 /* P7/P8 specific fields */
192 struct {
193 /* PNV_THREAD_RUNNING/NAP/SLEEP */
194 u8 thread_idle_state;
195 /* Mask to denote subcore sibling threads */
196 u8 subcore_sibling_mask;
197 };
198
199 /* P9 specific fields */
200 struct {
201 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
202 /* The PSSCR value that the kernel requested before going to stop */
203 u64 requested_psscr;
204 /* Flag to request this thread not to stop */
205 atomic_t dont_stop;
206 #endif
207 };
208 };
209 #endif
210
211 #ifdef CONFIG_PPC_BOOK3S_64
212 /* Non-maskable exceptions that are not performance critical */
213 u64 exnmi[EX_SIZE]; /* used for system reset (nmi) */
214 u64 exmc[EX_SIZE]; /* used for machine checks */
215 #endif
216 #ifdef CONFIG_PPC_BOOK3S_64
217 /* Exclusive stacks for system reset and machine check exception. */
218 void *nmi_emergency_sp;
219 void *mc_emergency_sp;
220
221 u16 in_nmi; /* In nmi handler */
222
223 /*
224 * Flag to check whether we are in machine check early handler
225 * and already using emergency stack.
226 */
227 u16 in_mce;
228 u8 hmi_event_available; /* HMI event is available */
229 u8 hmi_p9_special_emu; /* HMI P9 special emulation */
230 u32 hmi_irqs; /* HMI irq stat */
231 #endif
232 u8 ftrace_enabled; /* Hard disable ftrace */
233
234 /* Stuff for accurate time accounting */
235 struct cpu_accounting_data accounting;
236 u64 dtl_ridx; /* read index in dispatch log */
237 struct dtl_entry *dtl_curr; /* pointer corresponding to dtl_ridx */
238
239 #ifdef CONFIG_KVM_BOOK3S_HANDLER
240 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
241 /* We use this to store guest state in */
242 struct kvmppc_book3s_shadow_vcpu shadow_vcpu;
243 #endif
244 struct kvmppc_host_state kvm_hstate;
245 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
246 /*
247 * Bitmap for sibling subcore status. See kvm/book3s_hv_ras.c for
248 * more details
249 */
250 struct sibling_subcore_state *sibling_subcore_state;
251 #endif
252 #endif
253 #ifdef CONFIG_PPC_BOOK3S_64
254 /*
255 * rfi fallback flush must be in its own cacheline to prevent
256 * other paca data leaking into the L1d
257 */
258 u64 exrfi[EX_SIZE] __aligned(0x80);
259 void *rfi_flush_fallback_area;
260 u64 l1d_flush_size;
261 #endif
262 #ifdef CONFIG_PPC_PSERIES
263 u8 *mce_data_buf; /* buffer to hold per cpu rtas errlog */
264 #endif /* CONFIG_PPC_PSERIES */
265
266 #ifdef CONFIG_PPC_BOOK3S_64
267 /* Capture SLB related old contents in MCE handler. */
268 struct slb_entry *mce_faulty_slbs;
269 u16 slb_save_cache_ptr;
270 #endif /* CONFIG_PPC_BOOK3S_64 */
271 #ifdef CONFIG_STACKPROTECTOR
272 unsigned long canary;
273 #endif
274 #ifdef CONFIG_MMIOWB
275 struct mmiowb_state mmiowb_state;
276 #endif
277 #ifdef CONFIG_PPC_BOOK3S_64
278 struct mce_info *mce_info;
279 #endif /* CONFIG_PPC_BOOK3S_64 */
280 } ____cacheline_aligned;
281
282 extern void copy_mm_to_paca(struct mm_struct *mm);
283 extern struct paca_struct **paca_ptrs;
284 extern void initialise_paca(struct paca_struct *new_paca, int cpu);
285 extern void setup_paca(struct paca_struct *new_paca);
286 extern void allocate_paca_ptrs(void);
287 extern void allocate_paca(int cpu);
288 extern void free_unused_pacas(void);
289
290 #else /* CONFIG_PPC64 */
291
allocate_paca_ptrs(void)292 static inline void allocate_paca_ptrs(void) { }
allocate_paca(int cpu)293 static inline void allocate_paca(int cpu) { }
free_unused_pacas(void)294 static inline void free_unused_pacas(void) { }
295
296 #endif /* CONFIG_PPC64 */
297
298 #endif /* __KERNEL__ */
299 #endif /* _ASM_POWERPC_PACA_H */
300