1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/kvm/coproc.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Authors: Rusty Russell <rusty@rustcorp.com.au>
9 * Christoffer Dall <c.dall@virtualopensystems.com>
10 */
11
12 #include <linux/bitfield.h>
13 #include <linux/bsearch.h>
14 #include <linux/kvm_host.h>
15 #include <linux/mm.h>
16 #include <linux/printk.h>
17 #include <linux/uaccess.h>
18
19 #include <asm/cacheflush.h>
20 #include <asm/cputype.h>
21 #include <asm/debug-monitors.h>
22 #include <asm/esr.h>
23 #include <asm/kvm_arm.h>
24 #include <asm/kvm_emulate.h>
25 #include <asm/kvm_hyp.h>
26 #include <asm/kvm_mmu.h>
27 #include <asm/perf_event.h>
28 #include <asm/sysreg.h>
29
30 #include <trace/events/kvm.h>
31
32 #include "sys_regs.h"
33
34 #include "trace.h"
35
36 /*
37 * All of this file is extremely similar to the ARM coproc.c, but the
38 * types are different. My gut feeling is that it should be pretty
39 * easy to merge, but that would be an ABI breakage -- again. VFP
40 * would also need to be abstracted.
41 *
42 * For AArch32, we only take care of what is being trapped. Anything
43 * that has to do with init and userspace access has to go via the
44 * 64bit interface.
45 */
46
read_from_write_only(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)47 static bool read_from_write_only(struct kvm_vcpu *vcpu,
48 struct sys_reg_params *params,
49 const struct sys_reg_desc *r)
50 {
51 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n");
52 print_sys_reg_instr(params);
53 kvm_inject_undefined(vcpu);
54 return false;
55 }
56
write_to_read_only(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)57 static bool write_to_read_only(struct kvm_vcpu *vcpu,
58 struct sys_reg_params *params,
59 const struct sys_reg_desc *r)
60 {
61 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n");
62 print_sys_reg_instr(params);
63 kvm_inject_undefined(vcpu);
64 return false;
65 }
66
67 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
68 static u32 cache_levels;
69
70 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
71 #define CSSELR_MAX 14
72
73 /* Which cache CCSIDR represents depends on CSSELR value. */
get_ccsidr(u32 csselr)74 static u32 get_ccsidr(u32 csselr)
75 {
76 u32 ccsidr;
77
78 /* Make sure noone else changes CSSELR during this! */
79 local_irq_disable();
80 write_sysreg(csselr, csselr_el1);
81 isb();
82 ccsidr = read_sysreg(ccsidr_el1);
83 local_irq_enable();
84
85 return ccsidr;
86 }
87
88 /*
89 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
90 */
access_dcsw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)91 static bool access_dcsw(struct kvm_vcpu *vcpu,
92 struct sys_reg_params *p,
93 const struct sys_reg_desc *r)
94 {
95 if (!p->is_write)
96 return read_from_write_only(vcpu, p, r);
97
98 /*
99 * Only track S/W ops if we don't have FWB. It still indicates
100 * that the guest is a bit broken (S/W operations should only
101 * be done by firmware, knowing that there is only a single
102 * CPU left in the system, and certainly not from non-secure
103 * software).
104 */
105 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
106 kvm_set_way_flush(vcpu);
107
108 return true;
109 }
110
get_access_mask(const struct sys_reg_desc * r,u64 * mask,u64 * shift)111 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift)
112 {
113 switch (r->aarch32_map) {
114 case AA32_LO:
115 *mask = GENMASK_ULL(31, 0);
116 *shift = 0;
117 break;
118 case AA32_HI:
119 *mask = GENMASK_ULL(63, 32);
120 *shift = 32;
121 break;
122 default:
123 *mask = GENMASK_ULL(63, 0);
124 *shift = 0;
125 break;
126 }
127 }
128
129 /*
130 * Generic accessor for VM registers. Only called as long as HCR_TVM
131 * is set. If the guest enables the MMU, we stop trapping the VM
132 * sys_regs and leave it in complete control of the caches.
133 */
access_vm_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)134 static bool access_vm_reg(struct kvm_vcpu *vcpu,
135 struct sys_reg_params *p,
136 const struct sys_reg_desc *r)
137 {
138 bool was_enabled = vcpu_has_cache_enabled(vcpu);
139 u64 val, mask, shift;
140
141 BUG_ON(!p->is_write);
142
143 get_access_mask(r, &mask, &shift);
144
145 if (~mask) {
146 val = vcpu_read_sys_reg(vcpu, r->reg);
147 val &= ~mask;
148 } else {
149 val = 0;
150 }
151
152 val |= (p->regval & (mask >> shift)) << shift;
153 vcpu_write_sys_reg(vcpu, val, r->reg);
154
155 kvm_toggle_cache(vcpu, was_enabled);
156 return true;
157 }
158
access_actlr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)159 static bool access_actlr(struct kvm_vcpu *vcpu,
160 struct sys_reg_params *p,
161 const struct sys_reg_desc *r)
162 {
163 u64 mask, shift;
164
165 if (p->is_write)
166 return ignore_write(vcpu, p);
167
168 get_access_mask(r, &mask, &shift);
169 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift;
170
171 return true;
172 }
173
174 /*
175 * Trap handler for the GICv3 SGI generation system register.
176 * Forward the request to the VGIC emulation.
177 * The cp15_64 code makes sure this automatically works
178 * for both AArch64 and AArch32 accesses.
179 */
access_gic_sgi(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)180 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
181 struct sys_reg_params *p,
182 const struct sys_reg_desc *r)
183 {
184 bool g1;
185
186 if (!p->is_write)
187 return read_from_write_only(vcpu, p, r);
188
189 /*
190 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
191 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
192 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
193 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
194 * group.
195 */
196 if (p->Op0 == 0) { /* AArch32 */
197 switch (p->Op1) {
198 default: /* Keep GCC quiet */
199 case 0: /* ICC_SGI1R */
200 g1 = true;
201 break;
202 case 1: /* ICC_ASGI1R */
203 case 2: /* ICC_SGI0R */
204 g1 = false;
205 break;
206 }
207 } else { /* AArch64 */
208 switch (p->Op2) {
209 default: /* Keep GCC quiet */
210 case 5: /* ICC_SGI1R_EL1 */
211 g1 = true;
212 break;
213 case 6: /* ICC_ASGI1R_EL1 */
214 case 7: /* ICC_SGI0R_EL1 */
215 g1 = false;
216 break;
217 }
218 }
219
220 vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
221
222 return true;
223 }
224
access_gic_sre(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)225 static bool access_gic_sre(struct kvm_vcpu *vcpu,
226 struct sys_reg_params *p,
227 const struct sys_reg_desc *r)
228 {
229 if (p->is_write)
230 return ignore_write(vcpu, p);
231
232 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
233 return true;
234 }
235
trap_raz_wi(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)236 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
237 struct sys_reg_params *p,
238 const struct sys_reg_desc *r)
239 {
240 if (p->is_write)
241 return ignore_write(vcpu, p);
242 else
243 return read_zero(vcpu, p);
244 }
245
246 /*
247 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
248 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
249 * system, these registers should UNDEF. LORID_EL1 being a RO register, we
250 * treat it separately.
251 */
trap_loregion(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)252 static bool trap_loregion(struct kvm_vcpu *vcpu,
253 struct sys_reg_params *p,
254 const struct sys_reg_desc *r)
255 {
256 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
257 u32 sr = reg_to_encoding(r);
258
259 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
260 kvm_inject_undefined(vcpu);
261 return false;
262 }
263
264 if (p->is_write && sr == SYS_LORID_EL1)
265 return write_to_read_only(vcpu, p, r);
266
267 return trap_raz_wi(vcpu, p, r);
268 }
269
trap_oslsr_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)270 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
271 struct sys_reg_params *p,
272 const struct sys_reg_desc *r)
273 {
274 if (p->is_write) {
275 return ignore_write(vcpu, p);
276 } else {
277 p->regval = (1 << 3);
278 return true;
279 }
280 }
281
trap_dbgauthstatus_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)282 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
283 struct sys_reg_params *p,
284 const struct sys_reg_desc *r)
285 {
286 if (p->is_write) {
287 return ignore_write(vcpu, p);
288 } else {
289 p->regval = read_sysreg(dbgauthstatus_el1);
290 return true;
291 }
292 }
293
294 /*
295 * We want to avoid world-switching all the DBG registers all the
296 * time:
297 *
298 * - If we've touched any debug register, it is likely that we're
299 * going to touch more of them. It then makes sense to disable the
300 * traps and start doing the save/restore dance
301 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
302 * then mandatory to save/restore the registers, as the guest
303 * depends on them.
304 *
305 * For this, we use a DIRTY bit, indicating the guest has modified the
306 * debug registers, used as follow:
307 *
308 * On guest entry:
309 * - If the dirty bit is set (because we're coming back from trapping),
310 * disable the traps, save host registers, restore guest registers.
311 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
312 * set the dirty bit, disable the traps, save host registers,
313 * restore guest registers.
314 * - Otherwise, enable the traps
315 *
316 * On guest exit:
317 * - If the dirty bit is set, save guest registers, restore host
318 * registers and clear the dirty bit. This ensure that the host can
319 * now use the debug registers.
320 */
trap_debug_regs(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)321 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
322 struct sys_reg_params *p,
323 const struct sys_reg_desc *r)
324 {
325 if (p->is_write) {
326 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
327 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
328 } else {
329 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
330 }
331
332 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
333
334 return true;
335 }
336
337 /*
338 * reg_to_dbg/dbg_to_reg
339 *
340 * A 32 bit write to a debug register leave top bits alone
341 * A 32 bit read from a debug register only returns the bottom bits
342 *
343 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
344 * hyp.S code switches between host and guest values in future.
345 */
reg_to_dbg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd,u64 * dbg_reg)346 static void reg_to_dbg(struct kvm_vcpu *vcpu,
347 struct sys_reg_params *p,
348 const struct sys_reg_desc *rd,
349 u64 *dbg_reg)
350 {
351 u64 mask, shift, val;
352
353 get_access_mask(rd, &mask, &shift);
354
355 val = *dbg_reg;
356 val &= ~mask;
357 val |= (p->regval & (mask >> shift)) << shift;
358 *dbg_reg = val;
359
360 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
361 }
362
dbg_to_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd,u64 * dbg_reg)363 static void dbg_to_reg(struct kvm_vcpu *vcpu,
364 struct sys_reg_params *p,
365 const struct sys_reg_desc *rd,
366 u64 *dbg_reg)
367 {
368 u64 mask, shift;
369
370 get_access_mask(rd, &mask, &shift);
371 p->regval = (*dbg_reg & mask) >> shift;
372 }
373
trap_bvr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)374 static bool trap_bvr(struct kvm_vcpu *vcpu,
375 struct sys_reg_params *p,
376 const struct sys_reg_desc *rd)
377 {
378 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
379
380 if (p->is_write)
381 reg_to_dbg(vcpu, p, rd, dbg_reg);
382 else
383 dbg_to_reg(vcpu, p, rd, dbg_reg);
384
385 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
386
387 return true;
388 }
389
set_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)390 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
391 const struct kvm_one_reg *reg, void __user *uaddr)
392 {
393 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
394
395 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
396 return -EFAULT;
397 return 0;
398 }
399
get_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)400 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
401 const struct kvm_one_reg *reg, void __user *uaddr)
402 {
403 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
404
405 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
406 return -EFAULT;
407 return 0;
408 }
409
reset_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)410 static void reset_bvr(struct kvm_vcpu *vcpu,
411 const struct sys_reg_desc *rd)
412 {
413 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
414 }
415
trap_bcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)416 static bool trap_bcr(struct kvm_vcpu *vcpu,
417 struct sys_reg_params *p,
418 const struct sys_reg_desc *rd)
419 {
420 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
421
422 if (p->is_write)
423 reg_to_dbg(vcpu, p, rd, dbg_reg);
424 else
425 dbg_to_reg(vcpu, p, rd, dbg_reg);
426
427 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
428
429 return true;
430 }
431
set_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)432 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
433 const struct kvm_one_reg *reg, void __user *uaddr)
434 {
435 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
436
437 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
438 return -EFAULT;
439
440 return 0;
441 }
442
get_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)443 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
444 const struct kvm_one_reg *reg, void __user *uaddr)
445 {
446 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
447
448 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
449 return -EFAULT;
450 return 0;
451 }
452
reset_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)453 static void reset_bcr(struct kvm_vcpu *vcpu,
454 const struct sys_reg_desc *rd)
455 {
456 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
457 }
458
trap_wvr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)459 static bool trap_wvr(struct kvm_vcpu *vcpu,
460 struct sys_reg_params *p,
461 const struct sys_reg_desc *rd)
462 {
463 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
464
465 if (p->is_write)
466 reg_to_dbg(vcpu, p, rd, dbg_reg);
467 else
468 dbg_to_reg(vcpu, p, rd, dbg_reg);
469
470 trace_trap_reg(__func__, rd->CRm, p->is_write,
471 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]);
472
473 return true;
474 }
475
set_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)476 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
477 const struct kvm_one_reg *reg, void __user *uaddr)
478 {
479 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
480
481 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
482 return -EFAULT;
483 return 0;
484 }
485
get_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)486 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
487 const struct kvm_one_reg *reg, void __user *uaddr)
488 {
489 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
490
491 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
492 return -EFAULT;
493 return 0;
494 }
495
reset_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)496 static void reset_wvr(struct kvm_vcpu *vcpu,
497 const struct sys_reg_desc *rd)
498 {
499 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
500 }
501
trap_wcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)502 static bool trap_wcr(struct kvm_vcpu *vcpu,
503 struct sys_reg_params *p,
504 const struct sys_reg_desc *rd)
505 {
506 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
507
508 if (p->is_write)
509 reg_to_dbg(vcpu, p, rd, dbg_reg);
510 else
511 dbg_to_reg(vcpu, p, rd, dbg_reg);
512
513 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
514
515 return true;
516 }
517
set_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)518 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
519 const struct kvm_one_reg *reg, void __user *uaddr)
520 {
521 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
522
523 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
524 return -EFAULT;
525 return 0;
526 }
527
get_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)528 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
529 const struct kvm_one_reg *reg, void __user *uaddr)
530 {
531 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
532
533 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
534 return -EFAULT;
535 return 0;
536 }
537
reset_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)538 static void reset_wcr(struct kvm_vcpu *vcpu,
539 const struct sys_reg_desc *rd)
540 {
541 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
542 }
543
reset_amair_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)544 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
545 {
546 u64 amair = read_sysreg(amair_el1);
547 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
548 }
549
reset_actlr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)550 static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
551 {
552 u64 actlr = read_sysreg(actlr_el1);
553 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1);
554 }
555
reset_mpidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)556 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
557 {
558 vcpu_write_sys_reg(vcpu, calculate_mpidr(vcpu), MPIDR_EL1);
559 }
560
pmu_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)561 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
562 const struct sys_reg_desc *r)
563 {
564 if (kvm_vcpu_has_pmu(vcpu))
565 return 0;
566
567 return REG_HIDDEN;
568 }
569
reset_pmu_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)570 static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
571 {
572 u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX);
573
574 /* No PMU available, any PMU reg may UNDEF... */
575 if (!kvm_arm_support_pmu_v3())
576 return;
577
578 n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT;
579 n &= ARMV8_PMU_PMCR_N_MASK;
580 if (n)
581 mask |= GENMASK(n - 1, 0);
582
583 reset_unknown(vcpu, r);
584 __vcpu_sys_reg(vcpu, r->reg) &= mask;
585 }
586
reset_pmevcntr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)587 static void reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
588 {
589 reset_unknown(vcpu, r);
590 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0);
591 }
592
reset_pmevtyper(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)593 static void reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
594 {
595 reset_unknown(vcpu, r);
596 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_EVTYPE_MASK;
597 }
598
reset_pmselr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)599 static void reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
600 {
601 reset_unknown(vcpu, r);
602 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK;
603 }
604
reset_pmcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)605 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
606 {
607 u64 pmcr, val;
608
609 /* No PMU available, PMCR_EL0 may UNDEF... */
610 if (!kvm_arm_support_pmu_v3())
611 return;
612
613 pmcr = read_sysreg(pmcr_el0);
614 /*
615 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
616 * except PMCR.E resetting to zero.
617 */
618 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
619 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
620 if (!kvm_supports_32bit_el0())
621 val |= ARMV8_PMU_PMCR_LC;
622 __vcpu_sys_reg(vcpu, r->reg) = val;
623 }
624
check_pmu_access_disabled(struct kvm_vcpu * vcpu,u64 flags)625 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
626 {
627 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
628 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
629
630 if (!enabled)
631 kvm_inject_undefined(vcpu);
632
633 return !enabled;
634 }
635
pmu_access_el0_disabled(struct kvm_vcpu * vcpu)636 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
637 {
638 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
639 }
640
pmu_write_swinc_el0_disabled(struct kvm_vcpu * vcpu)641 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
642 {
643 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
644 }
645
pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu * vcpu)646 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
647 {
648 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
649 }
650
pmu_access_event_counter_el0_disabled(struct kvm_vcpu * vcpu)651 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
652 {
653 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
654 }
655
access_pmcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)656 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
657 const struct sys_reg_desc *r)
658 {
659 u64 val;
660
661 if (pmu_access_el0_disabled(vcpu))
662 return false;
663
664 if (p->is_write) {
665 /* Only update writeable bits of PMCR */
666 val = __vcpu_sys_reg(vcpu, PMCR_EL0);
667 val &= ~ARMV8_PMU_PMCR_MASK;
668 val |= p->regval & ARMV8_PMU_PMCR_MASK;
669 if (!kvm_supports_32bit_el0())
670 val |= ARMV8_PMU_PMCR_LC;
671 __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
672 kvm_pmu_handle_pmcr(vcpu, val);
673 } else {
674 /* PMCR.P & PMCR.C are RAZ */
675 val = __vcpu_sys_reg(vcpu, PMCR_EL0)
676 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
677 p->regval = val;
678 }
679
680 return true;
681 }
682
access_pmselr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)683 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
684 const struct sys_reg_desc *r)
685 {
686 if (pmu_access_event_counter_el0_disabled(vcpu))
687 return false;
688
689 if (p->is_write)
690 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
691 else
692 /* return PMSELR.SEL field */
693 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
694 & ARMV8_PMU_COUNTER_MASK;
695
696 return true;
697 }
698
access_pmceid(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)699 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
700 const struct sys_reg_desc *r)
701 {
702 u64 pmceid, mask, shift;
703
704 BUG_ON(p->is_write);
705
706 if (pmu_access_el0_disabled(vcpu))
707 return false;
708
709 get_access_mask(r, &mask, &shift);
710
711 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1));
712 pmceid &= mask;
713 pmceid >>= shift;
714
715 p->regval = pmceid;
716
717 return true;
718 }
719
pmu_counter_idx_valid(struct kvm_vcpu * vcpu,u64 idx)720 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
721 {
722 u64 pmcr, val;
723
724 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);
725 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
726 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
727 kvm_inject_undefined(vcpu);
728 return false;
729 }
730
731 return true;
732 }
733
access_pmu_evcntr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)734 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
735 struct sys_reg_params *p,
736 const struct sys_reg_desc *r)
737 {
738 u64 idx = ~0UL;
739
740 if (r->CRn == 9 && r->CRm == 13) {
741 if (r->Op2 == 2) {
742 /* PMXEVCNTR_EL0 */
743 if (pmu_access_event_counter_el0_disabled(vcpu))
744 return false;
745
746 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
747 & ARMV8_PMU_COUNTER_MASK;
748 } else if (r->Op2 == 0) {
749 /* PMCCNTR_EL0 */
750 if (pmu_access_cycle_counter_el0_disabled(vcpu))
751 return false;
752
753 idx = ARMV8_PMU_CYCLE_IDX;
754 }
755 } else if (r->CRn == 0 && r->CRm == 9) {
756 /* PMCCNTR */
757 if (pmu_access_event_counter_el0_disabled(vcpu))
758 return false;
759
760 idx = ARMV8_PMU_CYCLE_IDX;
761 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
762 /* PMEVCNTRn_EL0 */
763 if (pmu_access_event_counter_el0_disabled(vcpu))
764 return false;
765
766 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
767 }
768
769 /* Catch any decoding mistake */
770 WARN_ON(idx == ~0UL);
771
772 if (!pmu_counter_idx_valid(vcpu, idx))
773 return false;
774
775 if (p->is_write) {
776 if (pmu_access_el0_disabled(vcpu))
777 return false;
778
779 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
780 } else {
781 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
782 }
783
784 return true;
785 }
786
access_pmu_evtyper(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)787 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
788 const struct sys_reg_desc *r)
789 {
790 u64 idx, reg;
791
792 if (pmu_access_el0_disabled(vcpu))
793 return false;
794
795 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
796 /* PMXEVTYPER_EL0 */
797 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
798 reg = PMEVTYPER0_EL0 + idx;
799 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
800 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
801 if (idx == ARMV8_PMU_CYCLE_IDX)
802 reg = PMCCFILTR_EL0;
803 else
804 /* PMEVTYPERn_EL0 */
805 reg = PMEVTYPER0_EL0 + idx;
806 } else {
807 BUG();
808 }
809
810 if (!pmu_counter_idx_valid(vcpu, idx))
811 return false;
812
813 if (p->is_write) {
814 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
815 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
816 kvm_vcpu_pmu_restore_guest(vcpu);
817 } else {
818 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
819 }
820
821 return true;
822 }
823
access_pmcnten(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)824 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
825 const struct sys_reg_desc *r)
826 {
827 u64 val, mask;
828
829 if (pmu_access_el0_disabled(vcpu))
830 return false;
831
832 mask = kvm_pmu_valid_counter_mask(vcpu);
833 if (p->is_write) {
834 val = p->regval & mask;
835 if (r->Op2 & 0x1) {
836 /* accessing PMCNTENSET_EL0 */
837 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
838 kvm_pmu_enable_counter_mask(vcpu, val);
839 kvm_vcpu_pmu_restore_guest(vcpu);
840 } else {
841 /* accessing PMCNTENCLR_EL0 */
842 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
843 kvm_pmu_disable_counter_mask(vcpu, val);
844 }
845 } else {
846 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
847 }
848
849 return true;
850 }
851
access_pminten(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)852 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
853 const struct sys_reg_desc *r)
854 {
855 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
856
857 if (check_pmu_access_disabled(vcpu, 0))
858 return false;
859
860 if (p->is_write) {
861 u64 val = p->regval & mask;
862
863 if (r->Op2 & 0x1)
864 /* accessing PMINTENSET_EL1 */
865 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
866 else
867 /* accessing PMINTENCLR_EL1 */
868 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
869 } else {
870 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1);
871 }
872
873 return true;
874 }
875
access_pmovs(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)876 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
877 const struct sys_reg_desc *r)
878 {
879 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
880
881 if (pmu_access_el0_disabled(vcpu))
882 return false;
883
884 if (p->is_write) {
885 if (r->CRm & 0x2)
886 /* accessing PMOVSSET_EL0 */
887 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
888 else
889 /* accessing PMOVSCLR_EL0 */
890 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
891 } else {
892 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
893 }
894
895 return true;
896 }
897
access_pmswinc(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)898 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
899 const struct sys_reg_desc *r)
900 {
901 u64 mask;
902
903 if (!p->is_write)
904 return read_from_write_only(vcpu, p, r);
905
906 if (pmu_write_swinc_el0_disabled(vcpu))
907 return false;
908
909 mask = kvm_pmu_valid_counter_mask(vcpu);
910 kvm_pmu_software_increment(vcpu, p->regval & mask);
911 return true;
912 }
913
access_pmuserenr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)914 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
915 const struct sys_reg_desc *r)
916 {
917 if (p->is_write) {
918 if (!vcpu_mode_priv(vcpu)) {
919 kvm_inject_undefined(vcpu);
920 return false;
921 }
922
923 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
924 p->regval & ARMV8_PMU_USERENR_MASK;
925 } else {
926 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
927 & ARMV8_PMU_USERENR_MASK;
928 }
929
930 return true;
931 }
932
933 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
934 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \
935 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \
936 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \
937 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \
938 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \
939 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \
940 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \
941 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \
942 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
943
944 #define PMU_SYS_REG(r) \
945 SYS_DESC(r), .reset = reset_pmu_reg, .visibility = pmu_visibility
946
947 /* Macro to expand the PMEVCNTRn_EL0 register */
948 #define PMU_PMEVCNTR_EL0(n) \
949 { PMU_SYS_REG(SYS_PMEVCNTRn_EL0(n)), \
950 .reset = reset_pmevcntr, \
951 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), }
952
953 /* Macro to expand the PMEVTYPERn_EL0 register */
954 #define PMU_PMEVTYPER_EL0(n) \
955 { PMU_SYS_REG(SYS_PMEVTYPERn_EL0(n)), \
956 .reset = reset_pmevtyper, \
957 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), }
958
undef_access(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)959 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
960 const struct sys_reg_desc *r)
961 {
962 kvm_inject_undefined(vcpu);
963
964 return false;
965 }
966
967 /* Macro to expand the AMU counter and type registers*/
968 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access }
969 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access }
970 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access }
971 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access }
972
ptrauth_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)973 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
974 const struct sys_reg_desc *rd)
975 {
976 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN;
977 }
978
979 /*
980 * If we land here on a PtrAuth access, that is because we didn't
981 * fixup the access on exit by allowing the PtrAuth sysregs. The only
982 * way this happens is when the guest does not have PtrAuth support
983 * enabled.
984 */
985 #define __PTRAUTH_KEY(k) \
986 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \
987 .visibility = ptrauth_visibility}
988
989 #define PTRAUTH_KEY(k) \
990 __PTRAUTH_KEY(k ## KEYLO_EL1), \
991 __PTRAUTH_KEY(k ## KEYHI_EL1)
992
access_arch_timer(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)993 static bool access_arch_timer(struct kvm_vcpu *vcpu,
994 struct sys_reg_params *p,
995 const struct sys_reg_desc *r)
996 {
997 enum kvm_arch_timers tmr;
998 enum kvm_arch_timer_regs treg;
999 u64 reg = reg_to_encoding(r);
1000
1001 switch (reg) {
1002 case SYS_CNTP_TVAL_EL0:
1003 case SYS_AARCH32_CNTP_TVAL:
1004 tmr = TIMER_PTIMER;
1005 treg = TIMER_REG_TVAL;
1006 break;
1007 case SYS_CNTP_CTL_EL0:
1008 case SYS_AARCH32_CNTP_CTL:
1009 tmr = TIMER_PTIMER;
1010 treg = TIMER_REG_CTL;
1011 break;
1012 case SYS_CNTP_CVAL_EL0:
1013 case SYS_AARCH32_CNTP_CVAL:
1014 tmr = TIMER_PTIMER;
1015 treg = TIMER_REG_CVAL;
1016 break;
1017 default:
1018 BUG();
1019 }
1020
1021 if (p->is_write)
1022 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
1023 else
1024 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
1025
1026 return true;
1027 }
1028
1029 /* Read a sanitised cpufeature ID register by sys_reg_desc */
read_id_reg(const struct kvm_vcpu * vcpu,struct sys_reg_desc const * r,bool raz)1030 static u64 read_id_reg(const struct kvm_vcpu *vcpu,
1031 struct sys_reg_desc const *r, bool raz)
1032 {
1033 u32 id = reg_to_encoding(r);
1034 u64 val;
1035
1036 if (raz)
1037 return 0;
1038
1039 val = read_sanitised_ftr_reg(id);
1040
1041 switch (id) {
1042 case SYS_ID_AA64PFR0_EL1:
1043 if (!vcpu_has_sve(vcpu))
1044 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_SVE);
1045 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_AMU);
1046 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2);
1047 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2);
1048 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3);
1049 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3);
1050 if (kvm_vgic_global_state.type == VGIC_V3) {
1051 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR0_GIC);
1052 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_GIC), 1);
1053 }
1054 break;
1055 case SYS_ID_AA64PFR1_EL1:
1056 if (!kvm_has_mte(vcpu->kvm))
1057 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE);
1058 break;
1059 case SYS_ID_AA64ISAR1_EL1:
1060 if (!vcpu_has_ptrauth(vcpu))
1061 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_APA) |
1062 ARM64_FEATURE_MASK(ID_AA64ISAR1_API) |
1063 ARM64_FEATURE_MASK(ID_AA64ISAR1_GPA) |
1064 ARM64_FEATURE_MASK(ID_AA64ISAR1_GPI));
1065 break;
1066 case SYS_ID_AA64DFR0_EL1:
1067 /* Limit debug to ARMv8.0 */
1068 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER);
1069 val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64DFR0_DEBUGVER), 6);
1070 /* Limit guests to PMUv3 for ARMv8.4 */
1071 val = cpuid_feature_cap_perfmon_field(val,
1072 ID_AA64DFR0_PMUVER_SHIFT,
1073 kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0);
1074 /* Hide SPE from guests */
1075 val &= ~ARM64_FEATURE_MASK(ID_AA64DFR0_PMSVER);
1076 break;
1077 case SYS_ID_DFR0_EL1:
1078 /* Limit guests to PMUv3 for ARMv8.4 */
1079 val = cpuid_feature_cap_perfmon_field(val,
1080 ID_DFR0_PERFMON_SHIFT,
1081 kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0);
1082 break;
1083 }
1084
1085 return val;
1086 }
1087
id_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1088 static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
1089 const struct sys_reg_desc *r)
1090 {
1091 u32 id = reg_to_encoding(r);
1092
1093 switch (id) {
1094 case SYS_ID_AA64ZFR0_EL1:
1095 if (!vcpu_has_sve(vcpu))
1096 return REG_RAZ;
1097 break;
1098 }
1099
1100 return 0;
1101 }
1102
1103 /* cpufeature ID register access trap handlers */
1104
__access_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r,bool raz)1105 static bool __access_id_reg(struct kvm_vcpu *vcpu,
1106 struct sys_reg_params *p,
1107 const struct sys_reg_desc *r,
1108 bool raz)
1109 {
1110 if (p->is_write)
1111 return write_to_read_only(vcpu, p, r);
1112
1113 p->regval = read_id_reg(vcpu, r, raz);
1114 return true;
1115 }
1116
access_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1117 static bool access_id_reg(struct kvm_vcpu *vcpu,
1118 struct sys_reg_params *p,
1119 const struct sys_reg_desc *r)
1120 {
1121 bool raz = sysreg_visible_as_raz(vcpu, r);
1122
1123 return __access_id_reg(vcpu, p, r, raz);
1124 }
1125
access_raz_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1126 static bool access_raz_id_reg(struct kvm_vcpu *vcpu,
1127 struct sys_reg_params *p,
1128 const struct sys_reg_desc *r)
1129 {
1130 return __access_id_reg(vcpu, p, r, true);
1131 }
1132
1133 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id);
1134 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id);
1135 static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
1136
1137 /* Visibility overrides for SVE-specific control registers */
sve_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1138 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
1139 const struct sys_reg_desc *rd)
1140 {
1141 if (vcpu_has_sve(vcpu))
1142 return 0;
1143
1144 return REG_HIDDEN;
1145 }
1146
set_id_aa64pfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1147 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
1148 const struct sys_reg_desc *rd,
1149 const struct kvm_one_reg *reg, void __user *uaddr)
1150 {
1151 const u64 id = sys_reg_to_index(rd);
1152 u8 csv2, csv3;
1153 int err;
1154 u64 val;
1155
1156 err = reg_from_user(&val, uaddr, id);
1157 if (err)
1158 return err;
1159
1160 /*
1161 * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as
1162 * it doesn't promise more than what is actually provided (the
1163 * guest could otherwise be covered in ectoplasmic residue).
1164 */
1165 csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV2_SHIFT);
1166 if (csv2 > 1 ||
1167 (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED))
1168 return -EINVAL;
1169
1170 /* Same thing for CSV3 */
1171 csv3 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV3_SHIFT);
1172 if (csv3 > 1 ||
1173 (csv3 && arm64_get_meltdown_state() != SPECTRE_UNAFFECTED))
1174 return -EINVAL;
1175
1176 /* We can only differ with CSV[23], and anything else is an error */
1177 val ^= read_id_reg(vcpu, rd, false);
1178 val &= ~((0xFUL << ID_AA64PFR0_CSV2_SHIFT) |
1179 (0xFUL << ID_AA64PFR0_CSV3_SHIFT));
1180 if (val)
1181 return -EINVAL;
1182
1183 vcpu->kvm->arch.pfr0_csv2 = csv2;
1184 vcpu->kvm->arch.pfr0_csv3 = csv3 ;
1185
1186 return 0;
1187 }
1188
1189 /*
1190 * cpufeature ID register user accessors
1191 *
1192 * For now, these registers are immutable for userspace, so no values
1193 * are stored, and for set_id_reg() we don't allow the effective value
1194 * to be changed.
1195 */
__get_id_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,void __user * uaddr,bool raz)1196 static int __get_id_reg(const struct kvm_vcpu *vcpu,
1197 const struct sys_reg_desc *rd, void __user *uaddr,
1198 bool raz)
1199 {
1200 const u64 id = sys_reg_to_index(rd);
1201 const u64 val = read_id_reg(vcpu, rd, raz);
1202
1203 return reg_to_user(uaddr, &val, id);
1204 }
1205
__set_id_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,void __user * uaddr,bool raz)1206 static int __set_id_reg(const struct kvm_vcpu *vcpu,
1207 const struct sys_reg_desc *rd, void __user *uaddr,
1208 bool raz)
1209 {
1210 const u64 id = sys_reg_to_index(rd);
1211 int err;
1212 u64 val;
1213
1214 err = reg_from_user(&val, uaddr, id);
1215 if (err)
1216 return err;
1217
1218 /* This is what we mean by invariant: you can't change it. */
1219 if (val != read_id_reg(vcpu, rd, raz))
1220 return -EINVAL;
1221
1222 return 0;
1223 }
1224
get_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1225 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1226 const struct kvm_one_reg *reg, void __user *uaddr)
1227 {
1228 bool raz = sysreg_visible_as_raz(vcpu, rd);
1229
1230 return __get_id_reg(vcpu, rd, uaddr, raz);
1231 }
1232
set_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1233 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1234 const struct kvm_one_reg *reg, void __user *uaddr)
1235 {
1236 bool raz = sysreg_visible_as_raz(vcpu, rd);
1237
1238 return __set_id_reg(vcpu, rd, uaddr, raz);
1239 }
1240
set_raz_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1241 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1242 const struct kvm_one_reg *reg, void __user *uaddr)
1243 {
1244 return __set_id_reg(vcpu, rd, uaddr, true);
1245 }
1246
get_raz_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1247 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1248 const struct kvm_one_reg *reg, void __user *uaddr)
1249 {
1250 const u64 id = sys_reg_to_index(rd);
1251 const u64 val = 0;
1252
1253 return reg_to_user(uaddr, &val, id);
1254 }
1255
set_wi_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1256 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1257 const struct kvm_one_reg *reg, void __user *uaddr)
1258 {
1259 int err;
1260 u64 val;
1261
1262 /* Perform the access even if we are going to ignore the value */
1263 err = reg_from_user(&val, uaddr, sys_reg_to_index(rd));
1264 if (err)
1265 return err;
1266
1267 return 0;
1268 }
1269
access_ctr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1270 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1271 const struct sys_reg_desc *r)
1272 {
1273 if (p->is_write)
1274 return write_to_read_only(vcpu, p, r);
1275
1276 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0);
1277 return true;
1278 }
1279
access_clidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1280 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1281 const struct sys_reg_desc *r)
1282 {
1283 if (p->is_write)
1284 return write_to_read_only(vcpu, p, r);
1285
1286 p->regval = read_sysreg(clidr_el1);
1287 return true;
1288 }
1289
access_csselr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1290 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1291 const struct sys_reg_desc *r)
1292 {
1293 int reg = r->reg;
1294
1295 if (p->is_write)
1296 vcpu_write_sys_reg(vcpu, p->regval, reg);
1297 else
1298 p->regval = vcpu_read_sys_reg(vcpu, reg);
1299 return true;
1300 }
1301
access_ccsidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1302 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1303 const struct sys_reg_desc *r)
1304 {
1305 u32 csselr;
1306
1307 if (p->is_write)
1308 return write_to_read_only(vcpu, p, r);
1309
1310 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
1311 p->regval = get_ccsidr(csselr);
1312
1313 /*
1314 * Guests should not be doing cache operations by set/way at all, and
1315 * for this reason, we trap them and attempt to infer the intent, so
1316 * that we can flush the entire guest's address space at the appropriate
1317 * time.
1318 * To prevent this trapping from causing performance problems, let's
1319 * expose the geometry of all data and unified caches (which are
1320 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way.
1321 * [If guests should attempt to infer aliasing properties from the
1322 * geometry (which is not permitted by the architecture), they would
1323 * only do so for virtually indexed caches.]
1324 */
1325 if (!(csselr & 1)) // data or unified cache
1326 p->regval &= ~GENMASK(27, 3);
1327 return true;
1328 }
1329
mte_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1330 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu,
1331 const struct sys_reg_desc *rd)
1332 {
1333 if (kvm_has_mte(vcpu->kvm))
1334 return 0;
1335
1336 return REG_HIDDEN;
1337 }
1338
1339 #define MTE_REG(name) { \
1340 SYS_DESC(SYS_##name), \
1341 .access = undef_access, \
1342 .reset = reset_unknown, \
1343 .reg = name, \
1344 .visibility = mte_visibility, \
1345 }
1346
1347 /* sys_reg_desc initialiser for known cpufeature ID registers */
1348 #define ID_SANITISED(name) { \
1349 SYS_DESC(SYS_##name), \
1350 .access = access_id_reg, \
1351 .get_user = get_id_reg, \
1352 .set_user = set_id_reg, \
1353 .visibility = id_visibility, \
1354 }
1355
1356 /*
1357 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
1358 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1359 * (1 <= crm < 8, 0 <= Op2 < 8).
1360 */
1361 #define ID_UNALLOCATED(crm, op2) { \
1362 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1363 .access = access_raz_id_reg, \
1364 .get_user = get_raz_reg, \
1365 .set_user = set_raz_id_reg, \
1366 }
1367
1368 /*
1369 * sys_reg_desc initialiser for known ID registers that we hide from guests.
1370 * For now, these are exposed just like unallocated ID regs: they appear
1371 * RAZ for the guest.
1372 */
1373 #define ID_HIDDEN(name) { \
1374 SYS_DESC(SYS_##name), \
1375 .access = access_raz_id_reg, \
1376 .get_user = get_raz_reg, \
1377 .set_user = set_raz_id_reg, \
1378 }
1379
1380 /*
1381 * Architected system registers.
1382 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
1383 *
1384 * Debug handling: We do trap most, if not all debug related system
1385 * registers. The implementation is good enough to ensure that a guest
1386 * can use these with minimal performance degradation. The drawback is
1387 * that we don't implement any of the external debug, none of the
1388 * OSlock protocol. This should be revisited if we ever encounter a
1389 * more demanding guest...
1390 */
1391 static const struct sys_reg_desc sys_reg_descs[] = {
1392 { SYS_DESC(SYS_DC_ISW), access_dcsw },
1393 { SYS_DESC(SYS_DC_CSW), access_dcsw },
1394 { SYS_DESC(SYS_DC_CISW), access_dcsw },
1395
1396 DBG_BCR_BVR_WCR_WVR_EL1(0),
1397 DBG_BCR_BVR_WCR_WVR_EL1(1),
1398 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1399 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
1400 DBG_BCR_BVR_WCR_WVR_EL1(2),
1401 DBG_BCR_BVR_WCR_WVR_EL1(3),
1402 DBG_BCR_BVR_WCR_WVR_EL1(4),
1403 DBG_BCR_BVR_WCR_WVR_EL1(5),
1404 DBG_BCR_BVR_WCR_WVR_EL1(6),
1405 DBG_BCR_BVR_WCR_WVR_EL1(7),
1406 DBG_BCR_BVR_WCR_WVR_EL1(8),
1407 DBG_BCR_BVR_WCR_WVR_EL1(9),
1408 DBG_BCR_BVR_WCR_WVR_EL1(10),
1409 DBG_BCR_BVR_WCR_WVR_EL1(11),
1410 DBG_BCR_BVR_WCR_WVR_EL1(12),
1411 DBG_BCR_BVR_WCR_WVR_EL1(13),
1412 DBG_BCR_BVR_WCR_WVR_EL1(14),
1413 DBG_BCR_BVR_WCR_WVR_EL1(15),
1414
1415 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
1416 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi },
1417 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 },
1418 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
1419 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
1420 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
1421 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
1422 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
1423
1424 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
1425 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
1426 // DBGDTR[TR]X_EL0 share the same encoding
1427 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
1428
1429 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
1430
1431 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
1432
1433 /*
1434 * ID regs: all ID_SANITISED() entries here must have corresponding
1435 * entries in arm64_ftr_regs[].
1436 */
1437
1438 /* AArch64 mappings of the AArch32 ID registers */
1439 /* CRm=1 */
1440 ID_SANITISED(ID_PFR0_EL1),
1441 ID_SANITISED(ID_PFR1_EL1),
1442 ID_SANITISED(ID_DFR0_EL1),
1443 ID_HIDDEN(ID_AFR0_EL1),
1444 ID_SANITISED(ID_MMFR0_EL1),
1445 ID_SANITISED(ID_MMFR1_EL1),
1446 ID_SANITISED(ID_MMFR2_EL1),
1447 ID_SANITISED(ID_MMFR3_EL1),
1448
1449 /* CRm=2 */
1450 ID_SANITISED(ID_ISAR0_EL1),
1451 ID_SANITISED(ID_ISAR1_EL1),
1452 ID_SANITISED(ID_ISAR2_EL1),
1453 ID_SANITISED(ID_ISAR3_EL1),
1454 ID_SANITISED(ID_ISAR4_EL1),
1455 ID_SANITISED(ID_ISAR5_EL1),
1456 ID_SANITISED(ID_MMFR4_EL1),
1457 ID_SANITISED(ID_ISAR6_EL1),
1458
1459 /* CRm=3 */
1460 ID_SANITISED(MVFR0_EL1),
1461 ID_SANITISED(MVFR1_EL1),
1462 ID_SANITISED(MVFR2_EL1),
1463 ID_UNALLOCATED(3,3),
1464 ID_SANITISED(ID_PFR2_EL1),
1465 ID_HIDDEN(ID_DFR1_EL1),
1466 ID_SANITISED(ID_MMFR5_EL1),
1467 ID_UNALLOCATED(3,7),
1468
1469 /* AArch64 ID registers */
1470 /* CRm=4 */
1471 { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg,
1472 .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, },
1473 ID_SANITISED(ID_AA64PFR1_EL1),
1474 ID_UNALLOCATED(4,2),
1475 ID_UNALLOCATED(4,3),
1476 ID_SANITISED(ID_AA64ZFR0_EL1),
1477 ID_UNALLOCATED(4,5),
1478 ID_UNALLOCATED(4,6),
1479 ID_UNALLOCATED(4,7),
1480
1481 /* CRm=5 */
1482 ID_SANITISED(ID_AA64DFR0_EL1),
1483 ID_SANITISED(ID_AA64DFR1_EL1),
1484 ID_UNALLOCATED(5,2),
1485 ID_UNALLOCATED(5,3),
1486 ID_HIDDEN(ID_AA64AFR0_EL1),
1487 ID_HIDDEN(ID_AA64AFR1_EL1),
1488 ID_UNALLOCATED(5,6),
1489 ID_UNALLOCATED(5,7),
1490
1491 /* CRm=6 */
1492 ID_SANITISED(ID_AA64ISAR0_EL1),
1493 ID_SANITISED(ID_AA64ISAR1_EL1),
1494 ID_SANITISED(ID_AA64ISAR2_EL1),
1495 ID_UNALLOCATED(6,3),
1496 ID_UNALLOCATED(6,4),
1497 ID_UNALLOCATED(6,5),
1498 ID_UNALLOCATED(6,6),
1499 ID_UNALLOCATED(6,7),
1500
1501 /* CRm=7 */
1502 ID_SANITISED(ID_AA64MMFR0_EL1),
1503 ID_SANITISED(ID_AA64MMFR1_EL1),
1504 ID_SANITISED(ID_AA64MMFR2_EL1),
1505 ID_UNALLOCATED(7,3),
1506 ID_UNALLOCATED(7,4),
1507 ID_UNALLOCATED(7,5),
1508 ID_UNALLOCATED(7,6),
1509 ID_UNALLOCATED(7,7),
1510
1511 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
1512 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
1513 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
1514
1515 MTE_REG(RGSR_EL1),
1516 MTE_REG(GCR_EL1),
1517
1518 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
1519 { SYS_DESC(SYS_TRFCR_EL1), undef_access },
1520 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
1521 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
1522 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
1523
1524 PTRAUTH_KEY(APIA),
1525 PTRAUTH_KEY(APIB),
1526 PTRAUTH_KEY(APDA),
1527 PTRAUTH_KEY(APDB),
1528 PTRAUTH_KEY(APGA),
1529
1530 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
1531 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
1532 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
1533
1534 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
1535 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
1536 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
1537 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
1538 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
1539 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
1540 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
1541 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
1542
1543 MTE_REG(TFSR_EL1),
1544 MTE_REG(TFSRE0_EL1),
1545
1546 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
1547 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
1548
1549 { SYS_DESC(SYS_PMSCR_EL1), undef_access },
1550 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access },
1551 { SYS_DESC(SYS_PMSICR_EL1), undef_access },
1552 { SYS_DESC(SYS_PMSIRR_EL1), undef_access },
1553 { SYS_DESC(SYS_PMSFCR_EL1), undef_access },
1554 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access },
1555 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access },
1556 { SYS_DESC(SYS_PMSIDR_EL1), undef_access },
1557 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access },
1558 { SYS_DESC(SYS_PMBPTR_EL1), undef_access },
1559 { SYS_DESC(SYS_PMBSR_EL1), undef_access },
1560 /* PMBIDR_EL1 is not trapped */
1561
1562 { PMU_SYS_REG(SYS_PMINTENSET_EL1),
1563 .access = access_pminten, .reg = PMINTENSET_EL1 },
1564 { PMU_SYS_REG(SYS_PMINTENCLR_EL1),
1565 .access = access_pminten, .reg = PMINTENSET_EL1 },
1566 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi },
1567
1568 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
1569 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
1570
1571 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
1572 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
1573 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
1574 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
1575 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
1576
1577 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
1578 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
1579
1580 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
1581 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
1582 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
1583 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
1584 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
1585 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
1586 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
1587 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
1588 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
1589 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
1590 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
1591 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
1592
1593 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
1594 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
1595
1596 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access },
1597
1598 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
1599
1600 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
1601 { SYS_DESC(SYS_CLIDR_EL1), access_clidr },
1602 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
1603 { SYS_DESC(SYS_CTR_EL0), access_ctr },
1604
1605 { PMU_SYS_REG(SYS_PMCR_EL0), .access = access_pmcr,
1606 .reset = reset_pmcr, .reg = PMCR_EL0 },
1607 { PMU_SYS_REG(SYS_PMCNTENSET_EL0),
1608 .access = access_pmcnten, .reg = PMCNTENSET_EL0 },
1609 { PMU_SYS_REG(SYS_PMCNTENCLR_EL0),
1610 .access = access_pmcnten, .reg = PMCNTENSET_EL0 },
1611 { PMU_SYS_REG(SYS_PMOVSCLR_EL0),
1612 .access = access_pmovs, .reg = PMOVSSET_EL0 },
1613 /*
1614 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was
1615 * previously (and pointlessly) advertised in the past...
1616 */
1617 { PMU_SYS_REG(SYS_PMSWINC_EL0),
1618 .get_user = get_raz_reg, .set_user = set_wi_reg,
1619 .access = access_pmswinc, .reset = NULL },
1620 { PMU_SYS_REG(SYS_PMSELR_EL0),
1621 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 },
1622 { PMU_SYS_REG(SYS_PMCEID0_EL0),
1623 .access = access_pmceid, .reset = NULL },
1624 { PMU_SYS_REG(SYS_PMCEID1_EL0),
1625 .access = access_pmceid, .reset = NULL },
1626 { PMU_SYS_REG(SYS_PMCCNTR_EL0),
1627 .access = access_pmu_evcntr, .reset = reset_unknown, .reg = PMCCNTR_EL0 },
1628 { PMU_SYS_REG(SYS_PMXEVTYPER_EL0),
1629 .access = access_pmu_evtyper, .reset = NULL },
1630 { PMU_SYS_REG(SYS_PMXEVCNTR_EL0),
1631 .access = access_pmu_evcntr, .reset = NULL },
1632 /*
1633 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
1634 * in 32bit mode. Here we choose to reset it as zero for consistency.
1635 */
1636 { PMU_SYS_REG(SYS_PMUSERENR_EL0), .access = access_pmuserenr,
1637 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },
1638 { PMU_SYS_REG(SYS_PMOVSSET_EL0),
1639 .access = access_pmovs, .reg = PMOVSSET_EL0 },
1640
1641 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
1642 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
1643
1644 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access },
1645
1646 { SYS_DESC(SYS_AMCR_EL0), undef_access },
1647 { SYS_DESC(SYS_AMCFGR_EL0), undef_access },
1648 { SYS_DESC(SYS_AMCGCR_EL0), undef_access },
1649 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access },
1650 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },
1651 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },
1652 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },
1653 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },
1654 AMU_AMEVCNTR0_EL0(0),
1655 AMU_AMEVCNTR0_EL0(1),
1656 AMU_AMEVCNTR0_EL0(2),
1657 AMU_AMEVCNTR0_EL0(3),
1658 AMU_AMEVCNTR0_EL0(4),
1659 AMU_AMEVCNTR0_EL0(5),
1660 AMU_AMEVCNTR0_EL0(6),
1661 AMU_AMEVCNTR0_EL0(7),
1662 AMU_AMEVCNTR0_EL0(8),
1663 AMU_AMEVCNTR0_EL0(9),
1664 AMU_AMEVCNTR0_EL0(10),
1665 AMU_AMEVCNTR0_EL0(11),
1666 AMU_AMEVCNTR0_EL0(12),
1667 AMU_AMEVCNTR0_EL0(13),
1668 AMU_AMEVCNTR0_EL0(14),
1669 AMU_AMEVCNTR0_EL0(15),
1670 AMU_AMEVTYPER0_EL0(0),
1671 AMU_AMEVTYPER0_EL0(1),
1672 AMU_AMEVTYPER0_EL0(2),
1673 AMU_AMEVTYPER0_EL0(3),
1674 AMU_AMEVTYPER0_EL0(4),
1675 AMU_AMEVTYPER0_EL0(5),
1676 AMU_AMEVTYPER0_EL0(6),
1677 AMU_AMEVTYPER0_EL0(7),
1678 AMU_AMEVTYPER0_EL0(8),
1679 AMU_AMEVTYPER0_EL0(9),
1680 AMU_AMEVTYPER0_EL0(10),
1681 AMU_AMEVTYPER0_EL0(11),
1682 AMU_AMEVTYPER0_EL0(12),
1683 AMU_AMEVTYPER0_EL0(13),
1684 AMU_AMEVTYPER0_EL0(14),
1685 AMU_AMEVTYPER0_EL0(15),
1686 AMU_AMEVCNTR1_EL0(0),
1687 AMU_AMEVCNTR1_EL0(1),
1688 AMU_AMEVCNTR1_EL0(2),
1689 AMU_AMEVCNTR1_EL0(3),
1690 AMU_AMEVCNTR1_EL0(4),
1691 AMU_AMEVCNTR1_EL0(5),
1692 AMU_AMEVCNTR1_EL0(6),
1693 AMU_AMEVCNTR1_EL0(7),
1694 AMU_AMEVCNTR1_EL0(8),
1695 AMU_AMEVCNTR1_EL0(9),
1696 AMU_AMEVCNTR1_EL0(10),
1697 AMU_AMEVCNTR1_EL0(11),
1698 AMU_AMEVCNTR1_EL0(12),
1699 AMU_AMEVCNTR1_EL0(13),
1700 AMU_AMEVCNTR1_EL0(14),
1701 AMU_AMEVCNTR1_EL0(15),
1702 AMU_AMEVTYPER1_EL0(0),
1703 AMU_AMEVTYPER1_EL0(1),
1704 AMU_AMEVTYPER1_EL0(2),
1705 AMU_AMEVTYPER1_EL0(3),
1706 AMU_AMEVTYPER1_EL0(4),
1707 AMU_AMEVTYPER1_EL0(5),
1708 AMU_AMEVTYPER1_EL0(6),
1709 AMU_AMEVTYPER1_EL0(7),
1710 AMU_AMEVTYPER1_EL0(8),
1711 AMU_AMEVTYPER1_EL0(9),
1712 AMU_AMEVTYPER1_EL0(10),
1713 AMU_AMEVTYPER1_EL0(11),
1714 AMU_AMEVTYPER1_EL0(12),
1715 AMU_AMEVTYPER1_EL0(13),
1716 AMU_AMEVTYPER1_EL0(14),
1717 AMU_AMEVTYPER1_EL0(15),
1718
1719 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
1720 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
1721 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
1722
1723 /* PMEVCNTRn_EL0 */
1724 PMU_PMEVCNTR_EL0(0),
1725 PMU_PMEVCNTR_EL0(1),
1726 PMU_PMEVCNTR_EL0(2),
1727 PMU_PMEVCNTR_EL0(3),
1728 PMU_PMEVCNTR_EL0(4),
1729 PMU_PMEVCNTR_EL0(5),
1730 PMU_PMEVCNTR_EL0(6),
1731 PMU_PMEVCNTR_EL0(7),
1732 PMU_PMEVCNTR_EL0(8),
1733 PMU_PMEVCNTR_EL0(9),
1734 PMU_PMEVCNTR_EL0(10),
1735 PMU_PMEVCNTR_EL0(11),
1736 PMU_PMEVCNTR_EL0(12),
1737 PMU_PMEVCNTR_EL0(13),
1738 PMU_PMEVCNTR_EL0(14),
1739 PMU_PMEVCNTR_EL0(15),
1740 PMU_PMEVCNTR_EL0(16),
1741 PMU_PMEVCNTR_EL0(17),
1742 PMU_PMEVCNTR_EL0(18),
1743 PMU_PMEVCNTR_EL0(19),
1744 PMU_PMEVCNTR_EL0(20),
1745 PMU_PMEVCNTR_EL0(21),
1746 PMU_PMEVCNTR_EL0(22),
1747 PMU_PMEVCNTR_EL0(23),
1748 PMU_PMEVCNTR_EL0(24),
1749 PMU_PMEVCNTR_EL0(25),
1750 PMU_PMEVCNTR_EL0(26),
1751 PMU_PMEVCNTR_EL0(27),
1752 PMU_PMEVCNTR_EL0(28),
1753 PMU_PMEVCNTR_EL0(29),
1754 PMU_PMEVCNTR_EL0(30),
1755 /* PMEVTYPERn_EL0 */
1756 PMU_PMEVTYPER_EL0(0),
1757 PMU_PMEVTYPER_EL0(1),
1758 PMU_PMEVTYPER_EL0(2),
1759 PMU_PMEVTYPER_EL0(3),
1760 PMU_PMEVTYPER_EL0(4),
1761 PMU_PMEVTYPER_EL0(5),
1762 PMU_PMEVTYPER_EL0(6),
1763 PMU_PMEVTYPER_EL0(7),
1764 PMU_PMEVTYPER_EL0(8),
1765 PMU_PMEVTYPER_EL0(9),
1766 PMU_PMEVTYPER_EL0(10),
1767 PMU_PMEVTYPER_EL0(11),
1768 PMU_PMEVTYPER_EL0(12),
1769 PMU_PMEVTYPER_EL0(13),
1770 PMU_PMEVTYPER_EL0(14),
1771 PMU_PMEVTYPER_EL0(15),
1772 PMU_PMEVTYPER_EL0(16),
1773 PMU_PMEVTYPER_EL0(17),
1774 PMU_PMEVTYPER_EL0(18),
1775 PMU_PMEVTYPER_EL0(19),
1776 PMU_PMEVTYPER_EL0(20),
1777 PMU_PMEVTYPER_EL0(21),
1778 PMU_PMEVTYPER_EL0(22),
1779 PMU_PMEVTYPER_EL0(23),
1780 PMU_PMEVTYPER_EL0(24),
1781 PMU_PMEVTYPER_EL0(25),
1782 PMU_PMEVTYPER_EL0(26),
1783 PMU_PMEVTYPER_EL0(27),
1784 PMU_PMEVTYPER_EL0(28),
1785 PMU_PMEVTYPER_EL0(29),
1786 PMU_PMEVTYPER_EL0(30),
1787 /*
1788 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
1789 * in 32bit mode. Here we choose to reset it as zero for consistency.
1790 */
1791 { PMU_SYS_REG(SYS_PMCCFILTR_EL0), .access = access_pmu_evtyper,
1792 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 },
1793
1794 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
1795 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
1796 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
1797 };
1798
trap_dbgdidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1799 static bool trap_dbgdidr(struct kvm_vcpu *vcpu,
1800 struct sys_reg_params *p,
1801 const struct sys_reg_desc *r)
1802 {
1803 if (p->is_write) {
1804 return ignore_write(vcpu, p);
1805 } else {
1806 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1807 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1808 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
1809
1810 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1811 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1812 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1813 | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12));
1814 return true;
1815 }
1816 }
1817
1818 /*
1819 * AArch32 debug register mappings
1820 *
1821 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1822 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1823 *
1824 * None of the other registers share their location, so treat them as
1825 * if they were 64bit.
1826 */
1827 #define DBG_BCR_BVR_WCR_WVR(n) \
1828 /* DBGBVRn */ \
1829 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1830 /* DBGBCRn */ \
1831 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1832 /* DBGWVRn */ \
1833 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1834 /* DBGWCRn */ \
1835 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1836
1837 #define DBGBXVR(n) \
1838 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n }
1839
1840 /*
1841 * Trapped cp14 registers. We generally ignore most of the external
1842 * debug, on the principle that they don't really make sense to a
1843 * guest. Revisit this one day, would this principle change.
1844 */
1845 static const struct sys_reg_desc cp14_regs[] = {
1846 /* DBGDIDR */
1847 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },
1848 /* DBGDTRRXext */
1849 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1850
1851 DBG_BCR_BVR_WCR_WVR(0),
1852 /* DBGDSCRint */
1853 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1854 DBG_BCR_BVR_WCR_WVR(1),
1855 /* DBGDCCINT */
1856 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 },
1857 /* DBGDSCRext */
1858 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 },
1859 DBG_BCR_BVR_WCR_WVR(2),
1860 /* DBGDTR[RT]Xint */
1861 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1862 /* DBGDTR[RT]Xext */
1863 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1864 DBG_BCR_BVR_WCR_WVR(3),
1865 DBG_BCR_BVR_WCR_WVR(4),
1866 DBG_BCR_BVR_WCR_WVR(5),
1867 /* DBGWFAR */
1868 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1869 /* DBGOSECCR */
1870 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1871 DBG_BCR_BVR_WCR_WVR(6),
1872 /* DBGVCR */
1873 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 },
1874 DBG_BCR_BVR_WCR_WVR(7),
1875 DBG_BCR_BVR_WCR_WVR(8),
1876 DBG_BCR_BVR_WCR_WVR(9),
1877 DBG_BCR_BVR_WCR_WVR(10),
1878 DBG_BCR_BVR_WCR_WVR(11),
1879 DBG_BCR_BVR_WCR_WVR(12),
1880 DBG_BCR_BVR_WCR_WVR(13),
1881 DBG_BCR_BVR_WCR_WVR(14),
1882 DBG_BCR_BVR_WCR_WVR(15),
1883
1884 /* DBGDRAR (32bit) */
1885 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1886
1887 DBGBXVR(0),
1888 /* DBGOSLAR */
1889 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1890 DBGBXVR(1),
1891 /* DBGOSLSR */
1892 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1893 DBGBXVR(2),
1894 DBGBXVR(3),
1895 /* DBGOSDLR */
1896 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1897 DBGBXVR(4),
1898 /* DBGPRCR */
1899 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1900 DBGBXVR(5),
1901 DBGBXVR(6),
1902 DBGBXVR(7),
1903 DBGBXVR(8),
1904 DBGBXVR(9),
1905 DBGBXVR(10),
1906 DBGBXVR(11),
1907 DBGBXVR(12),
1908 DBGBXVR(13),
1909 DBGBXVR(14),
1910 DBGBXVR(15),
1911
1912 /* DBGDSAR (32bit) */
1913 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1914
1915 /* DBGDEVID2 */
1916 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1917 /* DBGDEVID1 */
1918 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1919 /* DBGDEVID */
1920 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1921 /* DBGCLAIMSET */
1922 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1923 /* DBGCLAIMCLR */
1924 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1925 /* DBGAUTHSTATUS */
1926 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1927 };
1928
1929 /* Trapped cp14 64bit registers */
1930 static const struct sys_reg_desc cp14_64_regs[] = {
1931 /* DBGDRAR (64bit) */
1932 { Op1( 0), CRm( 1), .access = trap_raz_wi },
1933
1934 /* DBGDSAR (64bit) */
1935 { Op1( 0), CRm( 2), .access = trap_raz_wi },
1936 };
1937
1938 /* Macro to expand the PMEVCNTRn register */
1939 #define PMU_PMEVCNTR(n) \
1940 /* PMEVCNTRn */ \
1941 { Op1(0), CRn(0b1110), \
1942 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1943 access_pmu_evcntr }
1944
1945 /* Macro to expand the PMEVTYPERn register */
1946 #define PMU_PMEVTYPER(n) \
1947 /* PMEVTYPERn */ \
1948 { Op1(0), CRn(0b1110), \
1949 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1950 access_pmu_evtyper }
1951
1952 /*
1953 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1954 * depending on the way they are accessed (as a 32bit or a 64bit
1955 * register).
1956 */
1957 static const struct sys_reg_desc cp15_regs[] = {
1958 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
1959 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 },
1960 /* ACTLR */
1961 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 },
1962 /* ACTLR2 */
1963 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 },
1964 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
1965 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 },
1966 /* TTBCR */
1967 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },
1968 /* TTBCR2 */
1969 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },
1970 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 },
1971 /* DFSR */
1972 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 },
1973 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 },
1974 /* ADFSR */
1975 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 },
1976 /* AIFSR */
1977 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 },
1978 /* DFAR */
1979 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 },
1980 /* IFAR */
1981 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 },
1982
1983 /*
1984 * DC{C,I,CI}SW operations:
1985 */
1986 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1987 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1988 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
1989
1990 /* PMU */
1991 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
1992 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1993 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
1994 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
1995 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
1996 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
1997 { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1998 { AA32(LO), Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
1999 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
2000 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
2001 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
2002 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
2003 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
2004 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
2005 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
2006 { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 4), access_pmceid },
2007 { AA32(HI), Op1( 0), CRn( 9), CRm(14), Op2( 5), access_pmceid },
2008 /* PMMIR */
2009 { Op1( 0), CRn( 9), CRm(14), Op2( 6), trap_raz_wi },
2010
2011 /* PRRR/MAIR0 */
2012 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
2013 /* NMRR/MAIR1 */
2014 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 },
2015 /* AMAIR0 */
2016 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },
2017 /* AMAIR1 */
2018 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 },
2019
2020 /* ICC_SRE */
2021 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
2022
2023 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 },
2024
2025 /* Arch Tmers */
2026 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
2027 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
2028
2029 /* PMEVCNTRn */
2030 PMU_PMEVCNTR(0),
2031 PMU_PMEVCNTR(1),
2032 PMU_PMEVCNTR(2),
2033 PMU_PMEVCNTR(3),
2034 PMU_PMEVCNTR(4),
2035 PMU_PMEVCNTR(5),
2036 PMU_PMEVCNTR(6),
2037 PMU_PMEVCNTR(7),
2038 PMU_PMEVCNTR(8),
2039 PMU_PMEVCNTR(9),
2040 PMU_PMEVCNTR(10),
2041 PMU_PMEVCNTR(11),
2042 PMU_PMEVCNTR(12),
2043 PMU_PMEVCNTR(13),
2044 PMU_PMEVCNTR(14),
2045 PMU_PMEVCNTR(15),
2046 PMU_PMEVCNTR(16),
2047 PMU_PMEVCNTR(17),
2048 PMU_PMEVCNTR(18),
2049 PMU_PMEVCNTR(19),
2050 PMU_PMEVCNTR(20),
2051 PMU_PMEVCNTR(21),
2052 PMU_PMEVCNTR(22),
2053 PMU_PMEVCNTR(23),
2054 PMU_PMEVCNTR(24),
2055 PMU_PMEVCNTR(25),
2056 PMU_PMEVCNTR(26),
2057 PMU_PMEVCNTR(27),
2058 PMU_PMEVCNTR(28),
2059 PMU_PMEVCNTR(29),
2060 PMU_PMEVCNTR(30),
2061 /* PMEVTYPERn */
2062 PMU_PMEVTYPER(0),
2063 PMU_PMEVTYPER(1),
2064 PMU_PMEVTYPER(2),
2065 PMU_PMEVTYPER(3),
2066 PMU_PMEVTYPER(4),
2067 PMU_PMEVTYPER(5),
2068 PMU_PMEVTYPER(6),
2069 PMU_PMEVTYPER(7),
2070 PMU_PMEVTYPER(8),
2071 PMU_PMEVTYPER(9),
2072 PMU_PMEVTYPER(10),
2073 PMU_PMEVTYPER(11),
2074 PMU_PMEVTYPER(12),
2075 PMU_PMEVTYPER(13),
2076 PMU_PMEVTYPER(14),
2077 PMU_PMEVTYPER(15),
2078 PMU_PMEVTYPER(16),
2079 PMU_PMEVTYPER(17),
2080 PMU_PMEVTYPER(18),
2081 PMU_PMEVTYPER(19),
2082 PMU_PMEVTYPER(20),
2083 PMU_PMEVTYPER(21),
2084 PMU_PMEVTYPER(22),
2085 PMU_PMEVTYPER(23),
2086 PMU_PMEVTYPER(24),
2087 PMU_PMEVTYPER(25),
2088 PMU_PMEVTYPER(26),
2089 PMU_PMEVTYPER(27),
2090 PMU_PMEVTYPER(28),
2091 PMU_PMEVTYPER(29),
2092 PMU_PMEVTYPER(30),
2093 /* PMCCFILTR */
2094 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
2095
2096 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2097 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
2098 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 },
2099 };
2100
2101 static const struct sys_reg_desc cp15_64_regs[] = {
2102 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
2103 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
2104 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
2105 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },
2106 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2107 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
2108 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },
2109 };
2110
check_sysreg_table(const struct sys_reg_desc * table,unsigned int n,bool is_32)2111 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,
2112 bool is_32)
2113 {
2114 unsigned int i;
2115
2116 for (i = 0; i < n; i++) {
2117 if (!is_32 && table[i].reg && !table[i].reset) {
2118 kvm_err("sys_reg table %p entry %d has lacks reset\n",
2119 table, i);
2120 return 1;
2121 }
2122
2123 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2124 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2125 return 1;
2126 }
2127 }
2128
2129 return 0;
2130 }
2131
kvm_handle_cp14_load_store(struct kvm_vcpu * vcpu)2132 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
2133 {
2134 kvm_inject_undefined(vcpu);
2135 return 1;
2136 }
2137
perform_access(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)2138 static void perform_access(struct kvm_vcpu *vcpu,
2139 struct sys_reg_params *params,
2140 const struct sys_reg_desc *r)
2141 {
2142 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
2143
2144 /* Check for regs disabled by runtime config */
2145 if (sysreg_hidden(vcpu, r)) {
2146 kvm_inject_undefined(vcpu);
2147 return;
2148 }
2149
2150 /*
2151 * Not having an accessor means that we have configured a trap
2152 * that we don't know how to handle. This certainly qualifies
2153 * as a gross bug that should be fixed right away.
2154 */
2155 BUG_ON(!r->access);
2156
2157 /* Skip instruction if instructed so */
2158 if (likely(r->access(vcpu, params, r)))
2159 kvm_incr_pc(vcpu);
2160 }
2161
2162 /*
2163 * emulate_cp -- tries to match a sys_reg access in a handling table, and
2164 * call the corresponding trap handler.
2165 *
2166 * @params: pointer to the descriptor of the access
2167 * @table: array of trap descriptors
2168 * @num: size of the trap descriptor array
2169 *
2170 * Return 0 if the access has been handled, and -1 if not.
2171 */
emulate_cp(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * table,size_t num)2172 static int emulate_cp(struct kvm_vcpu *vcpu,
2173 struct sys_reg_params *params,
2174 const struct sys_reg_desc *table,
2175 size_t num)
2176 {
2177 const struct sys_reg_desc *r;
2178
2179 if (!table)
2180 return -1; /* Not handled */
2181
2182 r = find_reg(params, table, num);
2183
2184 if (r) {
2185 perform_access(vcpu, params, r);
2186 return 0;
2187 }
2188
2189 /* Not handled */
2190 return -1;
2191 }
2192
unhandled_cp_access(struct kvm_vcpu * vcpu,struct sys_reg_params * params)2193 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
2194 struct sys_reg_params *params)
2195 {
2196 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
2197 int cp = -1;
2198
2199 switch (esr_ec) {
2200 case ESR_ELx_EC_CP15_32:
2201 case ESR_ELx_EC_CP15_64:
2202 cp = 15;
2203 break;
2204 case ESR_ELx_EC_CP14_MR:
2205 case ESR_ELx_EC_CP14_64:
2206 cp = 14;
2207 break;
2208 default:
2209 WARN_ON(1);
2210 }
2211
2212 print_sys_reg_msg(params,
2213 "Unsupported guest CP%d access at: %08lx [%08lx]\n",
2214 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2215 kvm_inject_undefined(vcpu);
2216 }
2217
2218 /**
2219 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
2220 * @vcpu: The VCPU pointer
2221 * @run: The kvm_run struct
2222 */
kvm_handle_cp_64(struct kvm_vcpu * vcpu,const struct sys_reg_desc * global,size_t nr_global)2223 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
2224 const struct sys_reg_desc *global,
2225 size_t nr_global)
2226 {
2227 struct sys_reg_params params;
2228 u32 esr = kvm_vcpu_get_esr(vcpu);
2229 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2230 int Rt2 = (esr >> 10) & 0x1f;
2231
2232 params.CRm = (esr >> 1) & 0xf;
2233 params.is_write = ((esr & 1) == 0);
2234
2235 params.Op0 = 0;
2236 params.Op1 = (esr >> 16) & 0xf;
2237 params.Op2 = 0;
2238 params.CRn = 0;
2239
2240 /*
2241 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
2242 * backends between AArch32 and AArch64, we get away with it.
2243 */
2244 if (params.is_write) {
2245 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
2246 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
2247 }
2248
2249 /*
2250 * If the table contains a handler, handle the
2251 * potential register operation in the case of a read and return
2252 * with success.
2253 */
2254 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) {
2255 /* Split up the value between registers for the read side */
2256 if (!params.is_write) {
2257 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
2258 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
2259 }
2260
2261 return 1;
2262 }
2263
2264 unhandled_cp_access(vcpu, ¶ms);
2265 return 1;
2266 }
2267
2268 /**
2269 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
2270 * @vcpu: The VCPU pointer
2271 * @run: The kvm_run struct
2272 */
kvm_handle_cp_32(struct kvm_vcpu * vcpu,const struct sys_reg_desc * global,size_t nr_global)2273 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
2274 const struct sys_reg_desc *global,
2275 size_t nr_global)
2276 {
2277 struct sys_reg_params params;
2278 u32 esr = kvm_vcpu_get_esr(vcpu);
2279 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2280
2281 params.CRm = (esr >> 1) & 0xf;
2282 params.regval = vcpu_get_reg(vcpu, Rt);
2283 params.is_write = ((esr & 1) == 0);
2284 params.CRn = (esr >> 10) & 0xf;
2285 params.Op0 = 0;
2286 params.Op1 = (esr >> 14) & 0x7;
2287 params.Op2 = (esr >> 17) & 0x7;
2288
2289 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) {
2290 if (!params.is_write)
2291 vcpu_set_reg(vcpu, Rt, params.regval);
2292 return 1;
2293 }
2294
2295 unhandled_cp_access(vcpu, ¶ms);
2296 return 1;
2297 }
2298
kvm_handle_cp15_64(struct kvm_vcpu * vcpu)2299 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu)
2300 {
2301 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs));
2302 }
2303
kvm_handle_cp15_32(struct kvm_vcpu * vcpu)2304 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu)
2305 {
2306 return kvm_handle_cp_32(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
2307 }
2308
kvm_handle_cp14_64(struct kvm_vcpu * vcpu)2309 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu)
2310 {
2311 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs));
2312 }
2313
kvm_handle_cp14_32(struct kvm_vcpu * vcpu)2314 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu)
2315 {
2316 return kvm_handle_cp_32(vcpu, cp14_regs, ARRAY_SIZE(cp14_regs));
2317 }
2318
is_imp_def_sys_reg(struct sys_reg_params * params)2319 static bool is_imp_def_sys_reg(struct sys_reg_params *params)
2320 {
2321 // See ARM DDI 0487E.a, section D12.3.2
2322 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011;
2323 }
2324
emulate_sys_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * params)2325 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
2326 struct sys_reg_params *params)
2327 {
2328 const struct sys_reg_desc *r;
2329
2330 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2331
2332 if (likely(r)) {
2333 perform_access(vcpu, params, r);
2334 } else if (is_imp_def_sys_reg(params)) {
2335 kvm_inject_undefined(vcpu);
2336 } else {
2337 print_sys_reg_msg(params,
2338 "Unsupported guest sys_reg access at: %lx [%08lx]\n",
2339 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2340 kvm_inject_undefined(vcpu);
2341 }
2342 return 1;
2343 }
2344
2345 /**
2346 * kvm_reset_sys_regs - sets system registers to reset value
2347 * @vcpu: The VCPU pointer
2348 *
2349 * This function finds the right table above and sets the registers on the
2350 * virtual CPU struct to their architecturally defined reset values.
2351 */
kvm_reset_sys_regs(struct kvm_vcpu * vcpu)2352 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2353 {
2354 unsigned long i;
2355
2356 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++)
2357 if (sys_reg_descs[i].reset)
2358 sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]);
2359 }
2360
2361 /**
2362 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
2363 * @vcpu: The VCPU pointer
2364 */
kvm_handle_sys_reg(struct kvm_vcpu * vcpu)2365 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
2366 {
2367 struct sys_reg_params params;
2368 unsigned long esr = kvm_vcpu_get_esr(vcpu);
2369 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2370 int ret;
2371
2372 trace_kvm_handle_sys_reg(esr);
2373
2374 params = esr_sys64_to_params(esr);
2375 params.regval = vcpu_get_reg(vcpu, Rt);
2376
2377 ret = emulate_sys_reg(vcpu, ¶ms);
2378
2379 if (!params.is_write)
2380 vcpu_set_reg(vcpu, Rt, params.regval);
2381 return ret;
2382 }
2383
2384 /******************************************************************************
2385 * Userspace API
2386 *****************************************************************************/
2387
index_to_params(u64 id,struct sys_reg_params * params)2388 static bool index_to_params(u64 id, struct sys_reg_params *params)
2389 {
2390 switch (id & KVM_REG_SIZE_MASK) {
2391 case KVM_REG_SIZE_U64:
2392 /* Any unused index bits means it's not valid. */
2393 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
2394 | KVM_REG_ARM_COPROC_MASK
2395 | KVM_REG_ARM64_SYSREG_OP0_MASK
2396 | KVM_REG_ARM64_SYSREG_OP1_MASK
2397 | KVM_REG_ARM64_SYSREG_CRN_MASK
2398 | KVM_REG_ARM64_SYSREG_CRM_MASK
2399 | KVM_REG_ARM64_SYSREG_OP2_MASK))
2400 return false;
2401 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
2402 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
2403 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
2404 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
2405 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
2406 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
2407 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
2408 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
2409 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
2410 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
2411 return true;
2412 default:
2413 return false;
2414 }
2415 }
2416
find_reg_by_id(u64 id,struct sys_reg_params * params,const struct sys_reg_desc table[],unsigned int num)2417 const struct sys_reg_desc *find_reg_by_id(u64 id,
2418 struct sys_reg_params *params,
2419 const struct sys_reg_desc table[],
2420 unsigned int num)
2421 {
2422 if (!index_to_params(id, params))
2423 return NULL;
2424
2425 return find_reg(params, table, num);
2426 }
2427
2428 /* Decode an index value, and find the sys_reg_desc entry. */
index_to_sys_reg_desc(struct kvm_vcpu * vcpu,u64 id)2429 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
2430 u64 id)
2431 {
2432 const struct sys_reg_desc *r;
2433 struct sys_reg_params params;
2434
2435 /* We only do sys_reg for now. */
2436 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
2437 return NULL;
2438
2439 if (!index_to_params(id, ¶ms))
2440 return NULL;
2441
2442 r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2443
2444 /* Not saved in the sys_reg array and not otherwise accessible? */
2445 if (r && !(r->reg || r->get_user))
2446 r = NULL;
2447
2448 return r;
2449 }
2450
2451 /*
2452 * These are the invariant sys_reg registers: we let the guest see the
2453 * host versions of these, so they're part of the guest state.
2454 *
2455 * A future CPU may provide a mechanism to present different values to
2456 * the guest, or a future kvm may trap them.
2457 */
2458
2459 #define FUNCTION_INVARIANT(reg) \
2460 static void get_##reg(struct kvm_vcpu *v, \
2461 const struct sys_reg_desc *r) \
2462 { \
2463 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
2464 }
2465
2466 FUNCTION_INVARIANT(midr_el1)
FUNCTION_INVARIANT(revidr_el1)2467 FUNCTION_INVARIANT(revidr_el1)
2468 FUNCTION_INVARIANT(clidr_el1)
2469 FUNCTION_INVARIANT(aidr_el1)
2470
2471 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
2472 {
2473 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
2474 }
2475
2476 /* ->val is filled in by kvm_sys_reg_table_init() */
2477 static struct sys_reg_desc invariant_sys_regs[] = {
2478 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
2479 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
2480 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 },
2481 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
2482 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
2483 };
2484
reg_from_user(u64 * val,const void __user * uaddr,u64 id)2485 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
2486 {
2487 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
2488 return -EFAULT;
2489 return 0;
2490 }
2491
reg_to_user(void __user * uaddr,const u64 * val,u64 id)2492 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
2493 {
2494 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
2495 return -EFAULT;
2496 return 0;
2497 }
2498
get_invariant_sys_reg(u64 id,void __user * uaddr)2499 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
2500 {
2501 struct sys_reg_params params;
2502 const struct sys_reg_desc *r;
2503
2504 r = find_reg_by_id(id, ¶ms, invariant_sys_regs,
2505 ARRAY_SIZE(invariant_sys_regs));
2506 if (!r)
2507 return -ENOENT;
2508
2509 return reg_to_user(uaddr, &r->val, id);
2510 }
2511
set_invariant_sys_reg(u64 id,void __user * uaddr)2512 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
2513 {
2514 struct sys_reg_params params;
2515 const struct sys_reg_desc *r;
2516 int err;
2517 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
2518
2519 r = find_reg_by_id(id, ¶ms, invariant_sys_regs,
2520 ARRAY_SIZE(invariant_sys_regs));
2521 if (!r)
2522 return -ENOENT;
2523
2524 err = reg_from_user(&val, uaddr, id);
2525 if (err)
2526 return err;
2527
2528 /* This is what we mean by invariant: you can't change it. */
2529 if (r->val != val)
2530 return -EINVAL;
2531
2532 return 0;
2533 }
2534
is_valid_cache(u32 val)2535 static bool is_valid_cache(u32 val)
2536 {
2537 u32 level, ctype;
2538
2539 if (val >= CSSELR_MAX)
2540 return false;
2541
2542 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
2543 level = (val >> 1);
2544 ctype = (cache_levels >> (level * 3)) & 7;
2545
2546 switch (ctype) {
2547 case 0: /* No cache */
2548 return false;
2549 case 1: /* Instruction cache only */
2550 return (val & 1);
2551 case 2: /* Data cache only */
2552 case 4: /* Unified cache */
2553 return !(val & 1);
2554 case 3: /* Separate instruction and data caches */
2555 return true;
2556 default: /* Reserved: we can't know instruction or data. */
2557 return false;
2558 }
2559 }
2560
demux_c15_get(u64 id,void __user * uaddr)2561 static int demux_c15_get(u64 id, void __user *uaddr)
2562 {
2563 u32 val;
2564 u32 __user *uval = uaddr;
2565
2566 /* Fail if we have unknown bits set. */
2567 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2568 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2569 return -ENOENT;
2570
2571 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2572 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2573 if (KVM_REG_SIZE(id) != 4)
2574 return -ENOENT;
2575 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2576 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2577 if (!is_valid_cache(val))
2578 return -ENOENT;
2579
2580 return put_user(get_ccsidr(val), uval);
2581 default:
2582 return -ENOENT;
2583 }
2584 }
2585
demux_c15_set(u64 id,void __user * uaddr)2586 static int demux_c15_set(u64 id, void __user *uaddr)
2587 {
2588 u32 val, newval;
2589 u32 __user *uval = uaddr;
2590
2591 /* Fail if we have unknown bits set. */
2592 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2593 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2594 return -ENOENT;
2595
2596 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2597 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2598 if (KVM_REG_SIZE(id) != 4)
2599 return -ENOENT;
2600 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2601 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2602 if (!is_valid_cache(val))
2603 return -ENOENT;
2604
2605 if (get_user(newval, uval))
2606 return -EFAULT;
2607
2608 /* This is also invariant: you can't change it. */
2609 if (newval != get_ccsidr(val))
2610 return -EINVAL;
2611 return 0;
2612 default:
2613 return -ENOENT;
2614 }
2615 }
2616
kvm_arm_sys_reg_get_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)2617 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2618 {
2619 const struct sys_reg_desc *r;
2620 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2621
2622 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2623 return demux_c15_get(reg->id, uaddr);
2624
2625 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2626 return -ENOENT;
2627
2628 r = index_to_sys_reg_desc(vcpu, reg->id);
2629 if (!r)
2630 return get_invariant_sys_reg(reg->id, uaddr);
2631
2632 /* Check for regs disabled by runtime config */
2633 if (sysreg_hidden(vcpu, r))
2634 return -ENOENT;
2635
2636 if (r->get_user)
2637 return (r->get_user)(vcpu, r, reg, uaddr);
2638
2639 return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id);
2640 }
2641
kvm_arm_sys_reg_set_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)2642 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2643 {
2644 const struct sys_reg_desc *r;
2645 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2646
2647 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2648 return demux_c15_set(reg->id, uaddr);
2649
2650 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2651 return -ENOENT;
2652
2653 r = index_to_sys_reg_desc(vcpu, reg->id);
2654 if (!r)
2655 return set_invariant_sys_reg(reg->id, uaddr);
2656
2657 /* Check for regs disabled by runtime config */
2658 if (sysreg_hidden(vcpu, r))
2659 return -ENOENT;
2660
2661 if (r->set_user)
2662 return (r->set_user)(vcpu, r, reg, uaddr);
2663
2664 return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2665 }
2666
num_demux_regs(void)2667 static unsigned int num_demux_regs(void)
2668 {
2669 unsigned int i, count = 0;
2670
2671 for (i = 0; i < CSSELR_MAX; i++)
2672 if (is_valid_cache(i))
2673 count++;
2674
2675 return count;
2676 }
2677
write_demux_regids(u64 __user * uindices)2678 static int write_demux_regids(u64 __user *uindices)
2679 {
2680 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
2681 unsigned int i;
2682
2683 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2684 for (i = 0; i < CSSELR_MAX; i++) {
2685 if (!is_valid_cache(i))
2686 continue;
2687 if (put_user(val | i, uindices))
2688 return -EFAULT;
2689 uindices++;
2690 }
2691 return 0;
2692 }
2693
sys_reg_to_index(const struct sys_reg_desc * reg)2694 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2695 {
2696 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2697 KVM_REG_ARM64_SYSREG |
2698 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2699 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2700 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2701 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2702 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2703 }
2704
copy_reg_to_user(const struct sys_reg_desc * reg,u64 __user ** uind)2705 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2706 {
2707 if (!*uind)
2708 return true;
2709
2710 if (put_user(sys_reg_to_index(reg), *uind))
2711 return false;
2712
2713 (*uind)++;
2714 return true;
2715 }
2716
walk_one_sys_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 __user ** uind,unsigned int * total)2717 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
2718 const struct sys_reg_desc *rd,
2719 u64 __user **uind,
2720 unsigned int *total)
2721 {
2722 /*
2723 * Ignore registers we trap but don't save,
2724 * and for which no custom user accessor is provided.
2725 */
2726 if (!(rd->reg || rd->get_user))
2727 return 0;
2728
2729 if (sysreg_hidden(vcpu, rd))
2730 return 0;
2731
2732 if (!copy_reg_to_user(rd, uind))
2733 return -EFAULT;
2734
2735 (*total)++;
2736 return 0;
2737 }
2738
2739 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
walk_sys_regs(struct kvm_vcpu * vcpu,u64 __user * uind)2740 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2741 {
2742 const struct sys_reg_desc *i2, *end2;
2743 unsigned int total = 0;
2744 int err;
2745
2746 i2 = sys_reg_descs;
2747 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2748
2749 while (i2 != end2) {
2750 err = walk_one_sys_reg(vcpu, i2++, &uind, &total);
2751 if (err)
2752 return err;
2753 }
2754 return total;
2755 }
2756
kvm_arm_num_sys_reg_descs(struct kvm_vcpu * vcpu)2757 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2758 {
2759 return ARRAY_SIZE(invariant_sys_regs)
2760 + num_demux_regs()
2761 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2762 }
2763
kvm_arm_copy_sys_reg_indices(struct kvm_vcpu * vcpu,u64 __user * uindices)2764 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2765 {
2766 unsigned int i;
2767 int err;
2768
2769 /* Then give them all the invariant registers' indices. */
2770 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2771 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2772 return -EFAULT;
2773 uindices++;
2774 }
2775
2776 err = walk_sys_regs(vcpu, uindices);
2777 if (err < 0)
2778 return err;
2779 uindices += err;
2780
2781 return write_demux_regids(uindices);
2782 }
2783
kvm_sys_reg_table_init(void)2784 void kvm_sys_reg_table_init(void)
2785 {
2786 unsigned int i;
2787 struct sys_reg_desc clidr;
2788
2789 /* Make sure tables are unique and in order. */
2790 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false));
2791 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true));
2792 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true));
2793 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true));
2794 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true));
2795 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false));
2796
2797 /* We abuse the reset function to overwrite the table itself. */
2798 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2799 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2800
2801 /*
2802 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
2803 *
2804 * If software reads the Cache Type fields from Ctype1
2805 * upwards, once it has seen a value of 0b000, no caches
2806 * exist at further-out levels of the hierarchy. So, for
2807 * example, if Ctype3 is the first Cache Type field with a
2808 * value of 0b000, the values of Ctype4 to Ctype7 must be
2809 * ignored.
2810 */
2811 get_clidr_el1(NULL, &clidr); /* Ugly... */
2812 cache_levels = clidr.val;
2813 for (i = 0; i < 7; i++)
2814 if (((cache_levels >> (i*3)) & 7) == 0)
2815 break;
2816 /* Clear all higher bits. */
2817 cache_levels &= (1 << (i*3))-1;
2818 }
2819