1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7 #include <linux/delay.h>
8
9 #include <drm/drm_vblank.h>
10
11 #include "msm_drv.h"
12 #include "msm_gem.h"
13 #include "msm_mmu.h"
14 #include "mdp4_kms.h"
15
16 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev);
17
mdp4_hw_init(struct msm_kms * kms)18 static int mdp4_hw_init(struct msm_kms *kms)
19 {
20 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
21 struct drm_device *dev = mdp4_kms->dev;
22 u32 dmap_cfg, vg_cfg;
23 unsigned long clk;
24 int ret = 0;
25
26 pm_runtime_get_sync(dev->dev);
27
28 if (mdp4_kms->rev > 1) {
29 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
30 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
31 }
32
33 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
34
35 /* max read pending cmd config, 3 pending requests: */
36 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
37
38 clk = clk_get_rate(mdp4_kms->clk);
39
40 if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
41 dmap_cfg = 0x47; /* 16 bytes-burst x 8 req */
42 vg_cfg = 0x47; /* 16 bytes-burs x 8 req */
43 } else {
44 dmap_cfg = 0x27; /* 8 bytes-burst x 8 req */
45 vg_cfg = 0x43; /* 16 bytes-burst x 4 req */
46 }
47
48 DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
49
50 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
51 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
52
53 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
54 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
55 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
56 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
57
58 if (mdp4_kms->rev >= 2)
59 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
60 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0);
61
62 /* disable CSC matrix / YUV by default: */
63 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
64 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
65 mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
66 mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
67 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
68 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
69
70 if (mdp4_kms->rev > 1)
71 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
72
73 pm_runtime_put_sync(dev->dev);
74
75 return ret;
76 }
77
mdp4_enable_commit(struct msm_kms * kms)78 static void mdp4_enable_commit(struct msm_kms *kms)
79 {
80 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
81 mdp4_enable(mdp4_kms);
82 }
83
mdp4_disable_commit(struct msm_kms * kms)84 static void mdp4_disable_commit(struct msm_kms *kms)
85 {
86 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
87 mdp4_disable(mdp4_kms);
88 }
89
mdp4_prepare_commit(struct msm_kms * kms,struct drm_atomic_state * state)90 static void mdp4_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
91 {
92 }
93
mdp4_flush_commit(struct msm_kms * kms,unsigned crtc_mask)94 static void mdp4_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
95 {
96 /* TODO */
97 }
98
mdp4_wait_flush(struct msm_kms * kms,unsigned crtc_mask)99 static void mdp4_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
100 {
101 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
102 struct drm_crtc *crtc;
103
104 for_each_crtc_mask(mdp4_kms->dev, crtc, crtc_mask)
105 mdp4_crtc_wait_for_commit_done(crtc);
106 }
107
mdp4_complete_commit(struct msm_kms * kms,unsigned crtc_mask)108 static void mdp4_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
109 {
110 }
111
mdp4_round_pixclk(struct msm_kms * kms,unsigned long rate,struct drm_encoder * encoder)112 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
113 struct drm_encoder *encoder)
114 {
115 /* if we had >1 encoder, we'd need something more clever: */
116 switch (encoder->encoder_type) {
117 case DRM_MODE_ENCODER_TMDS:
118 return mdp4_dtv_round_pixclk(encoder, rate);
119 case DRM_MODE_ENCODER_LVDS:
120 case DRM_MODE_ENCODER_DSI:
121 default:
122 return rate;
123 }
124 }
125
mdp4_destroy(struct msm_kms * kms)126 static void mdp4_destroy(struct msm_kms *kms)
127 {
128 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
129 struct device *dev = mdp4_kms->dev->dev;
130 struct msm_gem_address_space *aspace = kms->aspace;
131
132 if (mdp4_kms->blank_cursor_iova)
133 msm_gem_unpin_iova(mdp4_kms->blank_cursor_bo, kms->aspace);
134 drm_gem_object_put(mdp4_kms->blank_cursor_bo);
135
136 if (aspace) {
137 aspace->mmu->funcs->detach(aspace->mmu);
138 msm_gem_address_space_put(aspace);
139 }
140
141 if (mdp4_kms->rpm_enabled)
142 pm_runtime_disable(dev);
143
144 mdp_kms_destroy(&mdp4_kms->base);
145
146 kfree(mdp4_kms);
147 }
148
149 static const struct mdp_kms_funcs kms_funcs = {
150 .base = {
151 .hw_init = mdp4_hw_init,
152 .irq_preinstall = mdp4_irq_preinstall,
153 .irq_postinstall = mdp4_irq_postinstall,
154 .irq_uninstall = mdp4_irq_uninstall,
155 .irq = mdp4_irq,
156 .enable_vblank = mdp4_enable_vblank,
157 .disable_vblank = mdp4_disable_vblank,
158 .enable_commit = mdp4_enable_commit,
159 .disable_commit = mdp4_disable_commit,
160 .prepare_commit = mdp4_prepare_commit,
161 .flush_commit = mdp4_flush_commit,
162 .wait_flush = mdp4_wait_flush,
163 .complete_commit = mdp4_complete_commit,
164 .get_format = mdp_get_format,
165 .round_pixclk = mdp4_round_pixclk,
166 .destroy = mdp4_destroy,
167 },
168 .set_irqmask = mdp4_set_irqmask,
169 };
170
mdp4_disable(struct mdp4_kms * mdp4_kms)171 int mdp4_disable(struct mdp4_kms *mdp4_kms)
172 {
173 DBG("");
174
175 clk_disable_unprepare(mdp4_kms->clk);
176 if (mdp4_kms->pclk)
177 clk_disable_unprepare(mdp4_kms->pclk);
178 if (mdp4_kms->lut_clk)
179 clk_disable_unprepare(mdp4_kms->lut_clk);
180 if (mdp4_kms->axi_clk)
181 clk_disable_unprepare(mdp4_kms->axi_clk);
182
183 return 0;
184 }
185
mdp4_enable(struct mdp4_kms * mdp4_kms)186 int mdp4_enable(struct mdp4_kms *mdp4_kms)
187 {
188 DBG("");
189
190 clk_prepare_enable(mdp4_kms->clk);
191 if (mdp4_kms->pclk)
192 clk_prepare_enable(mdp4_kms->pclk);
193 if (mdp4_kms->lut_clk)
194 clk_prepare_enable(mdp4_kms->lut_clk);
195 if (mdp4_kms->axi_clk)
196 clk_prepare_enable(mdp4_kms->axi_clk);
197
198 return 0;
199 }
200
201
mdp4_modeset_init_intf(struct mdp4_kms * mdp4_kms,int intf_type)202 static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms,
203 int intf_type)
204 {
205 struct drm_device *dev = mdp4_kms->dev;
206 struct msm_drm_private *priv = dev->dev_private;
207 struct drm_encoder *encoder;
208 struct drm_connector *connector;
209 struct device_node *panel_node;
210 int dsi_id;
211 int ret;
212
213 switch (intf_type) {
214 case DRM_MODE_ENCODER_LVDS:
215 /*
216 * bail out early if there is no panel node (no need to
217 * initialize LCDC encoder and LVDS connector)
218 */
219 panel_node = of_graph_get_remote_node(dev->dev->of_node, 0, 0);
220 if (!panel_node)
221 return 0;
222
223 encoder = mdp4_lcdc_encoder_init(dev, panel_node);
224 if (IS_ERR(encoder)) {
225 DRM_DEV_ERROR(dev->dev, "failed to construct LCDC encoder\n");
226 of_node_put(panel_node);
227 return PTR_ERR(encoder);
228 }
229
230 /* LCDC can be hooked to DMA_P (TODO: Add DMA_S later?) */
231 encoder->possible_crtcs = 1 << DMA_P;
232
233 connector = mdp4_lvds_connector_init(dev, panel_node, encoder);
234 if (IS_ERR(connector)) {
235 DRM_DEV_ERROR(dev->dev, "failed to initialize LVDS connector\n");
236 of_node_put(panel_node);
237 return PTR_ERR(connector);
238 }
239
240 priv->encoders[priv->num_encoders++] = encoder;
241 priv->connectors[priv->num_connectors++] = connector;
242
243 break;
244 case DRM_MODE_ENCODER_TMDS:
245 encoder = mdp4_dtv_encoder_init(dev);
246 if (IS_ERR(encoder)) {
247 DRM_DEV_ERROR(dev->dev, "failed to construct DTV encoder\n");
248 return PTR_ERR(encoder);
249 }
250
251 /* DTV can be hooked to DMA_E: */
252 encoder->possible_crtcs = 1 << 1;
253
254 if (priv->hdmi) {
255 /* Construct bridge/connector for HDMI: */
256 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
257 if (ret) {
258 DRM_DEV_ERROR(dev->dev, "failed to initialize HDMI: %d\n", ret);
259 return ret;
260 }
261 }
262
263 priv->encoders[priv->num_encoders++] = encoder;
264
265 break;
266 case DRM_MODE_ENCODER_DSI:
267 /* only DSI1 supported for now */
268 dsi_id = 0;
269
270 if (!priv->dsi[dsi_id])
271 break;
272
273 encoder = mdp4_dsi_encoder_init(dev);
274 if (IS_ERR(encoder)) {
275 ret = PTR_ERR(encoder);
276 DRM_DEV_ERROR(dev->dev,
277 "failed to construct DSI encoder: %d\n", ret);
278 return ret;
279 }
280
281 /* TODO: Add DMA_S later? */
282 encoder->possible_crtcs = 1 << DMA_P;
283 priv->encoders[priv->num_encoders++] = encoder;
284
285 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder);
286 if (ret) {
287 DRM_DEV_ERROR(dev->dev, "failed to initialize DSI: %d\n",
288 ret);
289 return ret;
290 }
291
292 break;
293 default:
294 DRM_DEV_ERROR(dev->dev, "Invalid or unsupported interface\n");
295 return -EINVAL;
296 }
297
298 return 0;
299 }
300
modeset_init(struct mdp4_kms * mdp4_kms)301 static int modeset_init(struct mdp4_kms *mdp4_kms)
302 {
303 struct drm_device *dev = mdp4_kms->dev;
304 struct msm_drm_private *priv = dev->dev_private;
305 struct drm_plane *plane;
306 struct drm_crtc *crtc;
307 int i, ret;
308 static const enum mdp4_pipe rgb_planes[] = {
309 RGB1, RGB2,
310 };
311 static const enum mdp4_pipe vg_planes[] = {
312 VG1, VG2,
313 };
314 static const enum mdp4_dma mdp4_crtcs[] = {
315 DMA_P, DMA_E,
316 };
317 static const char * const mdp4_crtc_names[] = {
318 "DMA_P", "DMA_E",
319 };
320 static const int mdp4_intfs[] = {
321 DRM_MODE_ENCODER_LVDS,
322 DRM_MODE_ENCODER_DSI,
323 DRM_MODE_ENCODER_TMDS,
324 };
325
326 /* construct non-private planes: */
327 for (i = 0; i < ARRAY_SIZE(vg_planes); i++) {
328 plane = mdp4_plane_init(dev, vg_planes[i], false);
329 if (IS_ERR(plane)) {
330 DRM_DEV_ERROR(dev->dev,
331 "failed to construct plane for VG%d\n", i + 1);
332 ret = PTR_ERR(plane);
333 goto fail;
334 }
335 priv->planes[priv->num_planes++] = plane;
336 }
337
338 for (i = 0; i < ARRAY_SIZE(mdp4_crtcs); i++) {
339 plane = mdp4_plane_init(dev, rgb_planes[i], true);
340 if (IS_ERR(plane)) {
341 DRM_DEV_ERROR(dev->dev,
342 "failed to construct plane for RGB%d\n", i + 1);
343 ret = PTR_ERR(plane);
344 goto fail;
345 }
346
347 crtc = mdp4_crtc_init(dev, plane, priv->num_crtcs, i,
348 mdp4_crtcs[i]);
349 if (IS_ERR(crtc)) {
350 DRM_DEV_ERROR(dev->dev, "failed to construct crtc for %s\n",
351 mdp4_crtc_names[i]);
352 ret = PTR_ERR(crtc);
353 goto fail;
354 }
355
356 priv->crtcs[priv->num_crtcs++] = crtc;
357 }
358
359 /*
360 * we currently set up two relatively fixed paths:
361 *
362 * LCDC/LVDS path: RGB1 -> DMA_P -> LCDC -> LVDS
363 * or
364 * DSI path: RGB1 -> DMA_P -> DSI1 -> DSI Panel
365 *
366 * DTV/HDMI path: RGB2 -> DMA_E -> DTV -> HDMI
367 */
368
369 for (i = 0; i < ARRAY_SIZE(mdp4_intfs); i++) {
370 ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]);
371 if (ret) {
372 DRM_DEV_ERROR(dev->dev, "failed to initialize intf: %d, %d\n",
373 i, ret);
374 goto fail;
375 }
376 }
377
378 return 0;
379
380 fail:
381 return ret;
382 }
383
read_mdp_hw_revision(struct mdp4_kms * mdp4_kms,u32 * major,u32 * minor)384 static void read_mdp_hw_revision(struct mdp4_kms *mdp4_kms,
385 u32 *major, u32 *minor)
386 {
387 struct drm_device *dev = mdp4_kms->dev;
388 u32 version;
389
390 mdp4_enable(mdp4_kms);
391 version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
392 mdp4_disable(mdp4_kms);
393
394 *major = FIELD(version, MDP4_VERSION_MAJOR);
395 *minor = FIELD(version, MDP4_VERSION_MINOR);
396
397 DRM_DEV_INFO(dev->dev, "MDP4 version v%d.%d", *major, *minor);
398 }
399
mdp4_kms_init(struct drm_device * dev)400 struct msm_kms *mdp4_kms_init(struct drm_device *dev)
401 {
402 struct platform_device *pdev = to_platform_device(dev->dev);
403 struct mdp4_platform_config *config = mdp4_get_config(pdev);
404 struct msm_drm_private *priv = dev->dev_private;
405 struct mdp4_kms *mdp4_kms;
406 struct msm_kms *kms = NULL;
407 struct msm_gem_address_space *aspace;
408 int irq, ret;
409 u32 major, minor;
410
411 mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
412 if (!mdp4_kms) {
413 DRM_DEV_ERROR(dev->dev, "failed to allocate kms\n");
414 ret = -ENOMEM;
415 goto fail;
416 }
417
418 ret = mdp_kms_init(&mdp4_kms->base, &kms_funcs);
419 if (ret) {
420 DRM_DEV_ERROR(dev->dev, "failed to init kms\n");
421 goto fail;
422 }
423
424 priv->kms = &mdp4_kms->base.base;
425 kms = priv->kms;
426
427 mdp4_kms->dev = dev;
428
429 mdp4_kms->mmio = msm_ioremap(pdev, NULL, "MDP4");
430 if (IS_ERR(mdp4_kms->mmio)) {
431 ret = PTR_ERR(mdp4_kms->mmio);
432 goto fail;
433 }
434
435 irq = platform_get_irq(pdev, 0);
436 if (irq < 0) {
437 ret = irq;
438 DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret);
439 goto fail;
440 }
441
442 kms->irq = irq;
443
444 /* NOTE: driver for this regulator still missing upstream.. use
445 * _get_exclusive() and ignore the error if it does not exist
446 * (and hope that the bootloader left it on for us)
447 */
448 mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd");
449 if (IS_ERR(mdp4_kms->vdd))
450 mdp4_kms->vdd = NULL;
451
452 if (mdp4_kms->vdd) {
453 ret = regulator_enable(mdp4_kms->vdd);
454 if (ret) {
455 DRM_DEV_ERROR(dev->dev, "failed to enable regulator vdd: %d\n", ret);
456 goto fail;
457 }
458 }
459
460 mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
461 if (IS_ERR(mdp4_kms->clk)) {
462 DRM_DEV_ERROR(dev->dev, "failed to get core_clk\n");
463 ret = PTR_ERR(mdp4_kms->clk);
464 goto fail;
465 }
466
467 mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
468 if (IS_ERR(mdp4_kms->pclk))
469 mdp4_kms->pclk = NULL;
470
471 mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk");
472 if (IS_ERR(mdp4_kms->axi_clk)) {
473 DRM_DEV_ERROR(dev->dev, "failed to get axi_clk\n");
474 ret = PTR_ERR(mdp4_kms->axi_clk);
475 goto fail;
476 }
477
478 clk_set_rate(mdp4_kms->clk, config->max_clk);
479
480 read_mdp_hw_revision(mdp4_kms, &major, &minor);
481
482 if (major != 4) {
483 DRM_DEV_ERROR(dev->dev, "unexpected MDP version: v%d.%d\n",
484 major, minor);
485 ret = -ENXIO;
486 goto fail;
487 }
488
489 mdp4_kms->rev = minor;
490
491 if (mdp4_kms->rev >= 2) {
492 mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk");
493 if (IS_ERR(mdp4_kms->lut_clk)) {
494 DRM_DEV_ERROR(dev->dev, "failed to get lut_clk\n");
495 ret = PTR_ERR(mdp4_kms->lut_clk);
496 goto fail;
497 }
498 clk_set_rate(mdp4_kms->lut_clk, config->max_clk);
499 }
500
501 pm_runtime_enable(dev->dev);
502 mdp4_kms->rpm_enabled = true;
503
504 /* make sure things are off before attaching iommu (bootloader could
505 * have left things on, in which case we'll start getting faults if
506 * we don't disable):
507 */
508 mdp4_enable(mdp4_kms);
509 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
510 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
511 mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
512 mdp4_disable(mdp4_kms);
513 mdelay(16);
514
515 if (config->iommu) {
516 struct msm_mmu *mmu = msm_iommu_new(&pdev->dev,
517 config->iommu);
518
519 aspace = msm_gem_address_space_create(mmu,
520 "mdp4", 0x1000, 0x100000000 - 0x1000);
521
522 if (IS_ERR(aspace)) {
523 if (!IS_ERR(mmu))
524 mmu->funcs->destroy(mmu);
525 ret = PTR_ERR(aspace);
526 goto fail;
527 }
528
529 kms->aspace = aspace;
530 } else {
531 DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys "
532 "contig buffers for scanout\n");
533 aspace = NULL;
534 }
535
536 ret = modeset_init(mdp4_kms);
537 if (ret) {
538 DRM_DEV_ERROR(dev->dev, "modeset_init failed: %d\n", ret);
539 goto fail;
540 }
541
542 mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC | MSM_BO_SCANOUT);
543 if (IS_ERR(mdp4_kms->blank_cursor_bo)) {
544 ret = PTR_ERR(mdp4_kms->blank_cursor_bo);
545 DRM_DEV_ERROR(dev->dev, "could not allocate blank-cursor bo: %d\n", ret);
546 mdp4_kms->blank_cursor_bo = NULL;
547 goto fail;
548 }
549
550 ret = msm_gem_get_and_pin_iova(mdp4_kms->blank_cursor_bo, kms->aspace,
551 &mdp4_kms->blank_cursor_iova);
552 if (ret) {
553 DRM_DEV_ERROR(dev->dev, "could not pin blank-cursor bo: %d\n", ret);
554 goto fail;
555 }
556
557 dev->mode_config.min_width = 0;
558 dev->mode_config.min_height = 0;
559 dev->mode_config.max_width = 2048;
560 dev->mode_config.max_height = 2048;
561
562 return kms;
563
564 fail:
565 if (kms)
566 mdp4_destroy(kms);
567 return ERR_PTR(ret);
568 }
569
mdp4_get_config(struct platform_device * dev)570 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev)
571 {
572 static struct mdp4_platform_config config = {};
573
574 /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */
575 config.max_clk = 266667000;
576 config.iommu = iommu_domain_alloc(&platform_bus_type);
577
578 return &config;
579 }
580