1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
4 */
5
6 #include "mdp5_kms.h"
7 #include "mdp5_cfg.h"
8
9 struct mdp5_cfg_handler {
10 int revision;
11 struct mdp5_cfg config;
12 };
13
14 /* mdp5_cfg must be exposed (used in mdp5.xml.h) */
15 const struct mdp5_cfg_hw *mdp5_cfg = NULL;
16
17 static const struct mdp5_cfg_hw msm8x74v1_config = {
18 .name = "msm8x74v1",
19 .mdp = {
20 .count = 1,
21 .caps = MDP_CAP_SMP |
22 0,
23 },
24 .smp = {
25 .mmb_count = 22,
26 .mmb_size = 4096,
27 .clients = {
28 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
29 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
30 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
31 },
32 },
33 .ctl = {
34 .count = 5,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
37 },
38 .pipe_vig = {
39 .count = 3,
40 .base = { 0x01100, 0x01500, 0x01900 },
41 .caps = MDP_PIPE_CAP_HFLIP |
42 MDP_PIPE_CAP_VFLIP |
43 MDP_PIPE_CAP_SCALE |
44 MDP_PIPE_CAP_CSC |
45 0,
46 },
47 .pipe_rgb = {
48 .count = 3,
49 .base = { 0x01d00, 0x02100, 0x02500 },
50 .caps = MDP_PIPE_CAP_HFLIP |
51 MDP_PIPE_CAP_VFLIP |
52 MDP_PIPE_CAP_SCALE |
53 0,
54 },
55 .pipe_dma = {
56 .count = 2,
57 .base = { 0x02900, 0x02d00 },
58 .caps = MDP_PIPE_CAP_HFLIP |
59 MDP_PIPE_CAP_VFLIP |
60 0,
61 },
62 .lm = {
63 .count = 5,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
65 .instances = {
66 { .id = 0, .pp = 0, .dspp = 0,
67 .caps = MDP_LM_CAP_DISPLAY, },
68 { .id = 1, .pp = 1, .dspp = 1,
69 .caps = MDP_LM_CAP_DISPLAY, },
70 { .id = 2, .pp = 2, .dspp = 2,
71 .caps = MDP_LM_CAP_DISPLAY, },
72 { .id = 3, .pp = -1, .dspp = -1,
73 .caps = MDP_LM_CAP_WB },
74 { .id = 4, .pp = -1, .dspp = -1,
75 .caps = MDP_LM_CAP_WB },
76 },
77 .nb_stages = 5,
78 .max_width = 2048,
79 .max_height = 0xFFFF,
80 },
81 .dspp = {
82 .count = 3,
83 .base = { 0x04500, 0x04900, 0x04d00 },
84 },
85 .pp = {
86 .count = 3,
87 .base = { 0x21a00, 0x21b00, 0x21c00 },
88 },
89 .intf = {
90 .base = { 0x21000, 0x21200, 0x21400, 0x21600 },
91 .connect = {
92 [0] = INTF_eDP,
93 [1] = INTF_DSI,
94 [2] = INTF_DSI,
95 [3] = INTF_HDMI,
96 },
97 },
98 .perf = {
99 .ab_inefficiency = 200,
100 .ib_inefficiency = 120,
101 .clk_inefficiency = 125
102 },
103 .max_clk = 200000000,
104 };
105
106 static const struct mdp5_cfg_hw msm8x74v2_config = {
107 .name = "msm8x74",
108 .mdp = {
109 .count = 1,
110 .caps = MDP_CAP_SMP |
111 0,
112 },
113 .smp = {
114 .mmb_count = 22,
115 .mmb_size = 4096,
116 .clients = {
117 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
118 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
119 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
120 },
121 },
122 .ctl = {
123 .count = 5,
124 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
125 .flush_hw_mask = 0x0003ffff,
126 },
127 .pipe_vig = {
128 .count = 3,
129 .base = { 0x01100, 0x01500, 0x01900 },
130 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
131 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
132 MDP_PIPE_CAP_DECIMATION,
133 },
134 .pipe_rgb = {
135 .count = 3,
136 .base = { 0x01d00, 0x02100, 0x02500 },
137 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
138 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
139 },
140 .pipe_dma = {
141 .count = 2,
142 .base = { 0x02900, 0x02d00 },
143 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
144 },
145 .lm = {
146 .count = 5,
147 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
148 .instances = {
149 { .id = 0, .pp = 0, .dspp = 0,
150 .caps = MDP_LM_CAP_DISPLAY, },
151 { .id = 1, .pp = 1, .dspp = 1,
152 .caps = MDP_LM_CAP_DISPLAY, },
153 { .id = 2, .pp = 2, .dspp = 2,
154 .caps = MDP_LM_CAP_DISPLAY, },
155 { .id = 3, .pp = -1, .dspp = -1,
156 .caps = MDP_LM_CAP_WB, },
157 { .id = 4, .pp = -1, .dspp = -1,
158 .caps = MDP_LM_CAP_WB, },
159 },
160 .nb_stages = 5,
161 .max_width = 2048,
162 .max_height = 0xFFFF,
163 },
164 .dspp = {
165 .count = 3,
166 .base = { 0x04500, 0x04900, 0x04d00 },
167 },
168 .ad = {
169 .count = 2,
170 .base = { 0x13000, 0x13200 },
171 },
172 .pp = {
173 .count = 3,
174 .base = { 0x12c00, 0x12d00, 0x12e00 },
175 },
176 .intf = {
177 .base = { 0x12400, 0x12600, 0x12800, 0x12a00 },
178 .connect = {
179 [0] = INTF_eDP,
180 [1] = INTF_DSI,
181 [2] = INTF_DSI,
182 [3] = INTF_HDMI,
183 },
184 },
185 .perf = {
186 .ab_inefficiency = 200,
187 .ib_inefficiency = 120,
188 .clk_inefficiency = 125
189 },
190 .max_clk = 320000000,
191 };
192
193 static const struct mdp5_cfg_hw apq8084_config = {
194 .name = "apq8084",
195 .mdp = {
196 .count = 1,
197 .caps = MDP_CAP_SMP |
198 MDP_CAP_SRC_SPLIT |
199 0,
200 },
201 .smp = {
202 .mmb_count = 44,
203 .mmb_size = 8192,
204 .clients = {
205 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
206 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
207 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
208 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
209 [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
210 },
211 .reserved_state[0] = GENMASK(7, 0), /* first 8 MMBs */
212 .reserved = {
213 /* Two SMP blocks are statically tied to RGB pipes: */
214 [16] = 2, [17] = 2, [18] = 2, [22] = 2,
215 },
216 },
217 .ctl = {
218 .count = 5,
219 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
220 .flush_hw_mask = 0x003fffff,
221 },
222 .pipe_vig = {
223 .count = 4,
224 .base = { 0x01100, 0x01500, 0x01900, 0x01d00 },
225 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
226 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
227 MDP_PIPE_CAP_DECIMATION,
228 },
229 .pipe_rgb = {
230 .count = 4,
231 .base = { 0x02100, 0x02500, 0x02900, 0x02d00 },
232 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
233 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
234 },
235 .pipe_dma = {
236 .count = 2,
237 .base = { 0x03100, 0x03500 },
238 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
239 },
240 .lm = {
241 .count = 6,
242 .base = { 0x03900, 0x03d00, 0x04100, 0x04500, 0x04900, 0x04d00 },
243 .instances = {
244 { .id = 0, .pp = 0, .dspp = 0,
245 .caps = MDP_LM_CAP_DISPLAY |
246 MDP_LM_CAP_PAIR, },
247 { .id = 1, .pp = 1, .dspp = 1,
248 .caps = MDP_LM_CAP_DISPLAY, },
249 { .id = 2, .pp = 2, .dspp = 2,
250 .caps = MDP_LM_CAP_DISPLAY |
251 MDP_LM_CAP_PAIR, },
252 { .id = 3, .pp = -1, .dspp = -1,
253 .caps = MDP_LM_CAP_WB, },
254 { .id = 4, .pp = -1, .dspp = -1,
255 .caps = MDP_LM_CAP_WB, },
256 { .id = 5, .pp = 3, .dspp = 3,
257 .caps = MDP_LM_CAP_DISPLAY, },
258 },
259 .nb_stages = 5,
260 .max_width = 2048,
261 .max_height = 0xFFFF,
262 },
263 .dspp = {
264 .count = 4,
265 .base = { 0x05100, 0x05500, 0x05900, 0x05d00 },
266
267 },
268 .ad = {
269 .count = 3,
270 .base = { 0x13400, 0x13600, 0x13800 },
271 },
272 .pp = {
273 .count = 4,
274 .base = { 0x12e00, 0x12f00, 0x13000, 0x13100 },
275 },
276 .intf = {
277 .base = { 0x12400, 0x12600, 0x12800, 0x12a00, 0x12c00 },
278 .connect = {
279 [0] = INTF_eDP,
280 [1] = INTF_DSI,
281 [2] = INTF_DSI,
282 [3] = INTF_HDMI,
283 },
284 },
285 .perf = {
286 .ab_inefficiency = 200,
287 .ib_inefficiency = 120,
288 .clk_inefficiency = 105
289 },
290 .max_clk = 320000000,
291 };
292
293 static const struct mdp5_cfg_hw msm8x16_config = {
294 .name = "msm8x16",
295 .mdp = {
296 .count = 1,
297 .base = { 0x0 },
298 .caps = MDP_CAP_SMP |
299 0,
300 },
301 .smp = {
302 .mmb_count = 8,
303 .mmb_size = 8192,
304 .clients = {
305 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
306 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
307 },
308 },
309 .ctl = {
310 .count = 5,
311 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
312 .flush_hw_mask = 0x4003ffff,
313 },
314 .pipe_vig = {
315 .count = 1,
316 .base = { 0x04000 },
317 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
318 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
319 MDP_PIPE_CAP_DECIMATION,
320 },
321 .pipe_rgb = {
322 .count = 2,
323 .base = { 0x14000, 0x16000 },
324 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
325 MDP_PIPE_CAP_DECIMATION,
326 },
327 .pipe_dma = {
328 .count = 1,
329 .base = { 0x24000 },
330 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
331 },
332 .lm = {
333 .count = 2, /* LM0 and LM3 */
334 .base = { 0x44000, 0x47000 },
335 .instances = {
336 { .id = 0, .pp = 0, .dspp = 0,
337 .caps = MDP_LM_CAP_DISPLAY, },
338 { .id = 3, .pp = -1, .dspp = -1,
339 .caps = MDP_LM_CAP_WB },
340 },
341 .nb_stages = 8,
342 .max_width = 2048,
343 .max_height = 0xFFFF,
344 },
345 .dspp = {
346 .count = 1,
347 .base = { 0x54000 },
348
349 },
350 .intf = {
351 .base = { 0x00000, 0x6a800 },
352 .connect = {
353 [0] = INTF_DISABLED,
354 [1] = INTF_DSI,
355 },
356 },
357 .perf = {
358 .ab_inefficiency = 100,
359 .ib_inefficiency = 200,
360 .clk_inefficiency = 105
361 },
362 .max_clk = 320000000,
363 };
364
365 static const struct mdp5_cfg_hw msm8x36_config = {
366 .name = "msm8x36",
367 .mdp = {
368 .count = 1,
369 .base = { 0x0 },
370 .caps = MDP_CAP_SMP |
371 0,
372 },
373 .smp = {
374 .mmb_count = 8,
375 .mmb_size = 10240,
376 .clients = {
377 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
378 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
379 },
380 },
381 .ctl = {
382 .count = 3,
383 .base = { 0x01000, 0x01200, 0x01400 },
384 .flush_hw_mask = 0x4003ffff,
385 },
386 .pipe_vig = {
387 .count = 1,
388 .base = { 0x04000 },
389 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
390 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
391 MDP_PIPE_CAP_DECIMATION,
392 },
393 .pipe_rgb = {
394 .count = 2,
395 .base = { 0x14000, 0x16000 },
396 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
397 MDP_PIPE_CAP_DECIMATION,
398 },
399 .pipe_dma = {
400 .count = 1,
401 .base = { 0x24000 },
402 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
403 },
404 .lm = {
405 .count = 2,
406 .base = { 0x44000, 0x47000 },
407 .instances = {
408 { .id = 0, .pp = 0, .dspp = 0,
409 .caps = MDP_LM_CAP_DISPLAY, },
410 { .id = 1, .pp = -1, .dspp = -1,
411 .caps = MDP_LM_CAP_WB, },
412 },
413 .nb_stages = 8,
414 .max_width = 2560,
415 .max_height = 0xFFFF,
416 },
417 .pp = {
418 .count = 1,
419 .base = { 0x70000 },
420 },
421 .ad = {
422 .count = 1,
423 .base = { 0x78000 },
424 },
425 .dspp = {
426 .count = 1,
427 .base = { 0x54000 },
428 },
429 .intf = {
430 .base = { 0x00000, 0x6a800, 0x6b000 },
431 .connect = {
432 [0] = INTF_DISABLED,
433 [1] = INTF_DSI,
434 [2] = INTF_DSI,
435 },
436 },
437 .perf = {
438 .ab_inefficiency = 100,
439 .ib_inefficiency = 200,
440 .clk_inefficiency = 105
441 },
442 .max_clk = 366670000,
443 };
444
445 static const struct mdp5_cfg_hw msm8x94_config = {
446 .name = "msm8x94",
447 .mdp = {
448 .count = 1,
449 .caps = MDP_CAP_SMP |
450 MDP_CAP_SRC_SPLIT |
451 0,
452 },
453 .smp = {
454 .mmb_count = 44,
455 .mmb_size = 8192,
456 .clients = {
457 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
458 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
459 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
460 [SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
461 [SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
462 },
463 .reserved_state[0] = GENMASK(23, 0), /* first 24 MMBs */
464 .reserved = {
465 [1] = 1, [4] = 1, [7] = 1, [19] = 1,
466 [16] = 5, [17] = 5, [18] = 5, [22] = 5,
467 },
468 },
469 .ctl = {
470 .count = 5,
471 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
472 .flush_hw_mask = 0xf0ffffff,
473 },
474 .pipe_vig = {
475 .count = 4,
476 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
477 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
478 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
479 MDP_PIPE_CAP_DECIMATION,
480 },
481 .pipe_rgb = {
482 .count = 4,
483 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
484 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
485 MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
486 },
487 .pipe_dma = {
488 .count = 2,
489 .base = { 0x24000, 0x26000 },
490 .caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
491 },
492 .lm = {
493 .count = 6,
494 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
495 .instances = {
496 { .id = 0, .pp = 0, .dspp = 0,
497 .caps = MDP_LM_CAP_DISPLAY |
498 MDP_LM_CAP_PAIR, },
499 { .id = 1, .pp = 1, .dspp = 1,
500 .caps = MDP_LM_CAP_DISPLAY, },
501 { .id = 2, .pp = 2, .dspp = 2,
502 .caps = MDP_LM_CAP_DISPLAY |
503 MDP_LM_CAP_PAIR, },
504 { .id = 3, .pp = -1, .dspp = -1,
505 .caps = MDP_LM_CAP_WB, },
506 { .id = 4, .pp = -1, .dspp = -1,
507 .caps = MDP_LM_CAP_WB, },
508 { .id = 5, .pp = 3, .dspp = 3,
509 .caps = MDP_LM_CAP_DISPLAY, },
510 },
511 .nb_stages = 8,
512 .max_width = 2048,
513 .max_height = 0xFFFF,
514 },
515 .dspp = {
516 .count = 4,
517 .base = { 0x54000, 0x56000, 0x58000, 0x5a000 },
518
519 },
520 .ad = {
521 .count = 3,
522 .base = { 0x78000, 0x78800, 0x79000 },
523 },
524 .pp = {
525 .count = 4,
526 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
527 },
528 .intf = {
529 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
530 .connect = {
531 [0] = INTF_DISABLED,
532 [1] = INTF_DSI,
533 [2] = INTF_DSI,
534 [3] = INTF_HDMI,
535 },
536 },
537 .perf = {
538 .ab_inefficiency = 100,
539 .ib_inefficiency = 100,
540 .clk_inefficiency = 105
541 },
542 .max_clk = 400000000,
543 };
544
545 static const struct mdp5_cfg_hw msm8x96_config = {
546 .name = "msm8x96",
547 .mdp = {
548 .count = 1,
549 .caps = MDP_CAP_DSC |
550 MDP_CAP_CDM |
551 MDP_CAP_SRC_SPLIT |
552 0,
553 },
554 .ctl = {
555 .count = 5,
556 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
557 .flush_hw_mask = 0xf4ffffff,
558 },
559 .pipe_vig = {
560 .count = 4,
561 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
562 .caps = MDP_PIPE_CAP_HFLIP |
563 MDP_PIPE_CAP_VFLIP |
564 MDP_PIPE_CAP_SCALE |
565 MDP_PIPE_CAP_CSC |
566 MDP_PIPE_CAP_DECIMATION |
567 MDP_PIPE_CAP_SW_PIX_EXT |
568 0,
569 },
570 .pipe_rgb = {
571 .count = 4,
572 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
573 .caps = MDP_PIPE_CAP_HFLIP |
574 MDP_PIPE_CAP_VFLIP |
575 MDP_PIPE_CAP_SCALE |
576 MDP_PIPE_CAP_DECIMATION |
577 MDP_PIPE_CAP_SW_PIX_EXT |
578 0,
579 },
580 .pipe_dma = {
581 .count = 2,
582 .base = { 0x24000, 0x26000 },
583 .caps = MDP_PIPE_CAP_HFLIP |
584 MDP_PIPE_CAP_VFLIP |
585 MDP_PIPE_CAP_SW_PIX_EXT |
586 0,
587 },
588 .pipe_cursor = {
589 .count = 2,
590 .base = { 0x34000, 0x36000 },
591 .caps = MDP_PIPE_CAP_HFLIP |
592 MDP_PIPE_CAP_VFLIP |
593 MDP_PIPE_CAP_SW_PIX_EXT |
594 MDP_PIPE_CAP_CURSOR |
595 0,
596 },
597
598 .lm = {
599 .count = 6,
600 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
601 .instances = {
602 { .id = 0, .pp = 0, .dspp = 0,
603 .caps = MDP_LM_CAP_DISPLAY |
604 MDP_LM_CAP_PAIR, },
605 { .id = 1, .pp = 1, .dspp = 1,
606 .caps = MDP_LM_CAP_DISPLAY, },
607 { .id = 2, .pp = 2, .dspp = -1,
608 .caps = MDP_LM_CAP_DISPLAY |
609 MDP_LM_CAP_PAIR, },
610 { .id = 3, .pp = -1, .dspp = -1,
611 .caps = MDP_LM_CAP_WB, },
612 { .id = 4, .pp = -1, .dspp = -1,
613 .caps = MDP_LM_CAP_WB, },
614 { .id = 5, .pp = 3, .dspp = -1,
615 .caps = MDP_LM_CAP_DISPLAY, },
616 },
617 .nb_stages = 8,
618 .max_width = 2560,
619 .max_height = 0xFFFF,
620 },
621 .dspp = {
622 .count = 2,
623 .base = { 0x54000, 0x56000 },
624 },
625 .ad = {
626 .count = 3,
627 .base = { 0x78000, 0x78800, 0x79000 },
628 },
629 .pp = {
630 .count = 4,
631 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
632 },
633 .cdm = {
634 .count = 1,
635 .base = { 0x79200 },
636 },
637 .dsc = {
638 .count = 2,
639 .base = { 0x80000, 0x80400 },
640 },
641 .intf = {
642 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
643 .connect = {
644 [0] = INTF_DISABLED,
645 [1] = INTF_DSI,
646 [2] = INTF_DSI,
647 [3] = INTF_HDMI,
648 },
649 },
650 .perf = {
651 .ab_inefficiency = 100,
652 .ib_inefficiency = 200,
653 .clk_inefficiency = 105
654 },
655 .max_clk = 412500000,
656 };
657
658 const struct mdp5_cfg_hw msm8x76_config = {
659 .name = "msm8x76",
660 .mdp = {
661 .count = 1,
662 .caps = MDP_CAP_SMP |
663 MDP_CAP_DSC |
664 MDP_CAP_SRC_SPLIT |
665 0,
666 },
667 .ctl = {
668 .count = 3,
669 .base = { 0x01000, 0x01200, 0x01400 },
670 .flush_hw_mask = 0xffffffff,
671 },
672 .smp = {
673 .mmb_count = 10,
674 .mmb_size = 10240,
675 .clients = {
676 [SSPP_VIG0] = 1, [SSPP_VIG1] = 9,
677 [SSPP_DMA0] = 4,
678 [SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
679 },
680 },
681 .pipe_vig = {
682 .count = 2,
683 .base = { 0x04000, 0x06000 },
684 .caps = MDP_PIPE_CAP_HFLIP |
685 MDP_PIPE_CAP_VFLIP |
686 MDP_PIPE_CAP_SCALE |
687 MDP_PIPE_CAP_CSC |
688 MDP_PIPE_CAP_DECIMATION |
689 MDP_PIPE_CAP_SW_PIX_EXT |
690 0,
691 },
692 .pipe_rgb = {
693 .count = 2,
694 .base = { 0x14000, 0x16000 },
695 .caps = MDP_PIPE_CAP_HFLIP |
696 MDP_PIPE_CAP_VFLIP |
697 MDP_PIPE_CAP_DECIMATION |
698 MDP_PIPE_CAP_SW_PIX_EXT |
699 0,
700 },
701 .pipe_dma = {
702 .count = 1,
703 .base = { 0x24000 },
704 .caps = MDP_PIPE_CAP_HFLIP |
705 MDP_PIPE_CAP_VFLIP |
706 MDP_PIPE_CAP_SW_PIX_EXT |
707 0,
708 },
709 .pipe_cursor = {
710 .count = 1,
711 .base = { 0x440DC },
712 .caps = MDP_PIPE_CAP_HFLIP |
713 MDP_PIPE_CAP_VFLIP |
714 MDP_PIPE_CAP_SW_PIX_EXT |
715 MDP_PIPE_CAP_CURSOR |
716 0,
717 },
718 .lm = {
719 .count = 2,
720 .base = { 0x44000, 0x45000 },
721 .instances = {
722 { .id = 0, .pp = 0, .dspp = 0,
723 .caps = MDP_LM_CAP_DISPLAY, },
724 { .id = 1, .pp = -1, .dspp = -1,
725 .caps = MDP_LM_CAP_WB },
726 },
727 .nb_stages = 8,
728 .max_width = 2560,
729 .max_height = 0xFFFF,
730 },
731 .dspp = {
732 .count = 1,
733 .base = { 0x54000 },
734
735 },
736 .pp = {
737 .count = 3,
738 .base = { 0x70000, 0x70800, 0x72000 },
739 },
740 .dsc = {
741 .count = 2,
742 .base = { 0x80000, 0x80400 },
743 },
744 .intf = {
745 .base = { 0x6a000, 0x6a800, 0x6b000 },
746 .connect = {
747 [0] = INTF_DISABLED,
748 [1] = INTF_DSI,
749 [2] = INTF_DSI,
750 },
751 },
752 .max_clk = 360000000,
753 };
754
755 static const struct mdp5_cfg_hw msm8917_config = {
756 .name = "msm8917",
757 .mdp = {
758 .count = 1,
759 .caps = MDP_CAP_CDM,
760 },
761 .ctl = {
762 .count = 3,
763 .base = { 0x01000, 0x01200, 0x01400 },
764 .flush_hw_mask = 0xffffffff,
765 },
766 .pipe_vig = {
767 .count = 1,
768 .base = { 0x04000 },
769 .caps = MDP_PIPE_CAP_HFLIP |
770 MDP_PIPE_CAP_VFLIP |
771 MDP_PIPE_CAP_SCALE |
772 MDP_PIPE_CAP_CSC |
773 MDP_PIPE_CAP_DECIMATION |
774 MDP_PIPE_CAP_SW_PIX_EXT |
775 0,
776 },
777 .pipe_rgb = {
778 .count = 2,
779 .base = { 0x14000, 0x16000 },
780 .caps = MDP_PIPE_CAP_HFLIP |
781 MDP_PIPE_CAP_VFLIP |
782 MDP_PIPE_CAP_DECIMATION |
783 MDP_PIPE_CAP_SW_PIX_EXT |
784 0,
785 },
786 .pipe_dma = {
787 .count = 1,
788 .base = { 0x24000 },
789 .caps = MDP_PIPE_CAP_HFLIP |
790 MDP_PIPE_CAP_VFLIP |
791 MDP_PIPE_CAP_SW_PIX_EXT |
792 0,
793 },
794 .pipe_cursor = {
795 .count = 1,
796 .base = { 0x34000 },
797 .caps = MDP_PIPE_CAP_HFLIP |
798 MDP_PIPE_CAP_VFLIP |
799 MDP_PIPE_CAP_SW_PIX_EXT |
800 MDP_PIPE_CAP_CURSOR |
801 0,
802 },
803
804 .lm = {
805 .count = 2,
806 .base = { 0x44000, 0x45000 },
807 .instances = {
808 { .id = 0, .pp = 0, .dspp = 0,
809 .caps = MDP_LM_CAP_DISPLAY, },
810 { .id = 1, .pp = -1, .dspp = -1,
811 .caps = MDP_LM_CAP_WB },
812 },
813 .nb_stages = 8,
814 .max_width = 2048,
815 .max_height = 0xFFFF,
816 },
817 .dspp = {
818 .count = 1,
819 .base = { 0x54000 },
820
821 },
822 .pp = {
823 .count = 1,
824 .base = { 0x70000 },
825 },
826 .cdm = {
827 .count = 1,
828 .base = { 0x79200 },
829 },
830 .intf = {
831 .base = { 0x6a000, 0x6a800 },
832 .connect = {
833 [0] = INTF_DISABLED,
834 [1] = INTF_DSI,
835 },
836 },
837 .max_clk = 320000000,
838 };
839
840 static const struct mdp5_cfg_hw msm8998_config = {
841 .name = "msm8998",
842 .mdp = {
843 .count = 1,
844 .caps = MDP_CAP_DSC |
845 MDP_CAP_CDM |
846 MDP_CAP_SRC_SPLIT |
847 0,
848 },
849 .ctl = {
850 .count = 5,
851 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
852 .flush_hw_mask = 0xf7ffffff,
853 },
854 .pipe_vig = {
855 .count = 4,
856 .base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
857 .caps = MDP_PIPE_CAP_HFLIP |
858 MDP_PIPE_CAP_VFLIP |
859 MDP_PIPE_CAP_SCALE |
860 MDP_PIPE_CAP_CSC |
861 MDP_PIPE_CAP_DECIMATION |
862 MDP_PIPE_CAP_SW_PIX_EXT |
863 0,
864 },
865 .pipe_rgb = {
866 .count = 4,
867 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
868 .caps = MDP_PIPE_CAP_HFLIP |
869 MDP_PIPE_CAP_VFLIP |
870 MDP_PIPE_CAP_SCALE |
871 MDP_PIPE_CAP_DECIMATION |
872 MDP_PIPE_CAP_SW_PIX_EXT |
873 0,
874 },
875 .pipe_dma = {
876 .count = 2, /* driver supports max of 2 currently */
877 .base = { 0x24000, 0x26000, 0x28000, 0x2a000 },
878 .caps = MDP_PIPE_CAP_HFLIP |
879 MDP_PIPE_CAP_VFLIP |
880 MDP_PIPE_CAP_SW_PIX_EXT |
881 0,
882 },
883 .pipe_cursor = {
884 .count = 2,
885 .base = { 0x34000, 0x36000 },
886 .caps = MDP_PIPE_CAP_HFLIP |
887 MDP_PIPE_CAP_VFLIP |
888 MDP_PIPE_CAP_SW_PIX_EXT |
889 MDP_PIPE_CAP_CURSOR |
890 0,
891 },
892
893 .lm = {
894 .count = 6,
895 .base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
896 .instances = {
897 { .id = 0, .pp = 0, .dspp = 0,
898 .caps = MDP_LM_CAP_DISPLAY |
899 MDP_LM_CAP_PAIR, },
900 { .id = 1, .pp = 1, .dspp = 1,
901 .caps = MDP_LM_CAP_DISPLAY, },
902 { .id = 2, .pp = 2, .dspp = -1,
903 .caps = MDP_LM_CAP_DISPLAY |
904 MDP_LM_CAP_PAIR, },
905 { .id = 3, .pp = -1, .dspp = -1,
906 .caps = MDP_LM_CAP_WB, },
907 { .id = 4, .pp = -1, .dspp = -1,
908 .caps = MDP_LM_CAP_WB, },
909 { .id = 5, .pp = 3, .dspp = -1,
910 .caps = MDP_LM_CAP_DISPLAY, },
911 },
912 .nb_stages = 8,
913 .max_width = 2560,
914 .max_height = 0xFFFF,
915 },
916 .dspp = {
917 .count = 2,
918 .base = { 0x54000, 0x56000 },
919 },
920 .ad = {
921 .count = 3,
922 .base = { 0x78000, 0x78800, 0x79000 },
923 },
924 .pp = {
925 .count = 4,
926 .base = { 0x70000, 0x70800, 0x71000, 0x71800 },
927 },
928 .cdm = {
929 .count = 1,
930 .base = { 0x79200 },
931 },
932 .dsc = {
933 .count = 2,
934 .base = { 0x80000, 0x80400 },
935 },
936 .intf = {
937 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
938 .connect = {
939 [0] = INTF_eDP,
940 [1] = INTF_DSI,
941 [2] = INTF_DSI,
942 [3] = INTF_HDMI,
943 },
944 },
945 .max_clk = 412500000,
946 };
947
948 static const struct mdp5_cfg_hw sdm630_config = {
949 .name = "sdm630",
950 .mdp = {
951 .count = 1,
952 .caps = MDP_CAP_CDM |
953 MDP_CAP_SRC_SPLIT |
954 0,
955 },
956 .ctl = {
957 .count = 5,
958 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
959 .flush_hw_mask = 0xf4ffffff,
960 },
961 .pipe_vig = {
962 .count = 1,
963 .base = { 0x04000 },
964 .caps = MDP_PIPE_CAP_HFLIP |
965 MDP_PIPE_CAP_VFLIP |
966 MDP_PIPE_CAP_SCALE |
967 MDP_PIPE_CAP_CSC |
968 MDP_PIPE_CAP_DECIMATION |
969 MDP_PIPE_CAP_SW_PIX_EXT |
970 0,
971 },
972 .pipe_rgb = {
973 .count = 4,
974 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
975 .caps = MDP_PIPE_CAP_HFLIP |
976 MDP_PIPE_CAP_VFLIP |
977 MDP_PIPE_CAP_SCALE |
978 MDP_PIPE_CAP_DECIMATION |
979 MDP_PIPE_CAP_SW_PIX_EXT |
980 0,
981 },
982 .pipe_dma = {
983 .count = 2, /* driver supports max of 2 currently */
984 .base = { 0x24000, 0x26000, 0x28000 },
985 .caps = MDP_PIPE_CAP_HFLIP |
986 MDP_PIPE_CAP_VFLIP |
987 MDP_PIPE_CAP_SW_PIX_EXT |
988 0,
989 },
990 .pipe_cursor = {
991 .count = 1,
992 .base = { 0x34000 },
993 .caps = MDP_PIPE_CAP_HFLIP |
994 MDP_PIPE_CAP_VFLIP |
995 MDP_PIPE_CAP_SW_PIX_EXT |
996 MDP_PIPE_CAP_CURSOR |
997 0,
998 },
999
1000 .lm = {
1001 .count = 2,
1002 .base = { 0x44000, 0x46000 },
1003 .instances = {
1004 { .id = 0, .pp = 0, .dspp = 0,
1005 .caps = MDP_LM_CAP_DISPLAY |
1006 MDP_LM_CAP_PAIR, },
1007 { .id = 1, .pp = 1, .dspp = -1,
1008 .caps = MDP_LM_CAP_WB, },
1009 },
1010 .nb_stages = 8,
1011 .max_width = 2048,
1012 .max_height = 0xFFFF,
1013 },
1014 .dspp = {
1015 .count = 1,
1016 .base = { 0x54000 },
1017 },
1018 .ad = {
1019 .count = 2,
1020 .base = { 0x78000, 0x78800 },
1021 },
1022 .pp = {
1023 .count = 3,
1024 .base = { 0x70000, 0x71000, 0x72000 },
1025 },
1026 .cdm = {
1027 .count = 1,
1028 .base = { 0x79200 },
1029 },
1030 .intf = {
1031 .base = { 0x6a000, 0x6a800 },
1032 .connect = {
1033 [0] = INTF_DISABLED,
1034 [1] = INTF_DSI,
1035 },
1036 },
1037 .max_clk = 412500000,
1038 };
1039
1040 static const struct mdp5_cfg_hw sdm660_config = {
1041 .name = "sdm660",
1042 .mdp = {
1043 .count = 1,
1044 .caps = MDP_CAP_DSC |
1045 MDP_CAP_CDM |
1046 MDP_CAP_SRC_SPLIT |
1047 0,
1048 },
1049 .ctl = {
1050 .count = 5,
1051 .base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
1052 .flush_hw_mask = 0xf4ffffff,
1053 },
1054 .pipe_vig = {
1055 .count = 2,
1056 .base = { 0x04000, 0x6000 },
1057 .caps = MDP_PIPE_CAP_HFLIP |
1058 MDP_PIPE_CAP_VFLIP |
1059 MDP_PIPE_CAP_SCALE |
1060 MDP_PIPE_CAP_CSC |
1061 MDP_PIPE_CAP_DECIMATION |
1062 MDP_PIPE_CAP_SW_PIX_EXT |
1063 0,
1064 },
1065 .pipe_rgb = {
1066 .count = 4,
1067 .base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
1068 .caps = MDP_PIPE_CAP_HFLIP |
1069 MDP_PIPE_CAP_VFLIP |
1070 MDP_PIPE_CAP_SCALE |
1071 MDP_PIPE_CAP_DECIMATION |
1072 MDP_PIPE_CAP_SW_PIX_EXT |
1073 0,
1074 },
1075 .pipe_dma = {
1076 .count = 2, /* driver supports max of 2 currently */
1077 .base = { 0x24000, 0x26000, 0x28000 },
1078 .caps = MDP_PIPE_CAP_HFLIP |
1079 MDP_PIPE_CAP_VFLIP |
1080 MDP_PIPE_CAP_SW_PIX_EXT |
1081 0,
1082 },
1083 .pipe_cursor = {
1084 .count = 1,
1085 .base = { 0x34000 },
1086 .caps = MDP_PIPE_CAP_HFLIP |
1087 MDP_PIPE_CAP_VFLIP |
1088 MDP_PIPE_CAP_SW_PIX_EXT |
1089 MDP_PIPE_CAP_CURSOR |
1090 0,
1091 },
1092
1093 .lm = {
1094 .count = 4,
1095 .base = { 0x44000, 0x45000, 0x46000, 0x49000 },
1096 .instances = {
1097 { .id = 0, .pp = 0, .dspp = 0,
1098 .caps = MDP_LM_CAP_DISPLAY |
1099 MDP_LM_CAP_PAIR, },
1100 { .id = 1, .pp = 1, .dspp = 1,
1101 .caps = MDP_LM_CAP_DISPLAY, },
1102 { .id = 2, .pp = 2, .dspp = -1,
1103 .caps = MDP_LM_CAP_DISPLAY |
1104 MDP_LM_CAP_PAIR, },
1105 { .id = 3, .pp = 3, .dspp = -1,
1106 .caps = MDP_LM_CAP_WB, },
1107 },
1108 .nb_stages = 8,
1109 .max_width = 2560,
1110 .max_height = 0xFFFF,
1111 },
1112 .dspp = {
1113 .count = 2,
1114 .base = { 0x54000, 0x56000 },
1115 },
1116 .ad = {
1117 .count = 2,
1118 .base = { 0x78000, 0x78800 },
1119 },
1120 .pp = {
1121 .count = 5,
1122 .base = { 0x70000, 0x70800, 0x71000, 0x71800, 0x72000 },
1123 },
1124 .cdm = {
1125 .count = 1,
1126 .base = { 0x79200 },
1127 },
1128 .dsc = {
1129 .count = 2,
1130 .base = { 0x80000, 0x80400 },
1131 },
1132 .intf = {
1133 .base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800 },
1134 .connect = {
1135 [0] = INTF_DISABLED,
1136 [1] = INTF_DSI,
1137 [2] = INTF_DSI,
1138 [3] = INTF_HDMI,
1139 },
1140 },
1141 .max_clk = 412500000,
1142 };
1143
1144 static const struct mdp5_cfg_handler cfg_handlers_v1[] = {
1145 { .revision = 0, .config = { .hw = &msm8x74v1_config } },
1146 { .revision = 2, .config = { .hw = &msm8x74v2_config } },
1147 { .revision = 3, .config = { .hw = &apq8084_config } },
1148 { .revision = 6, .config = { .hw = &msm8x16_config } },
1149 { .revision = 8, .config = { .hw = &msm8x36_config } },
1150 { .revision = 9, .config = { .hw = &msm8x94_config } },
1151 { .revision = 7, .config = { .hw = &msm8x96_config } },
1152 { .revision = 11, .config = { .hw = &msm8x76_config } },
1153 { .revision = 15, .config = { .hw = &msm8917_config } },
1154 };
1155
1156 static const struct mdp5_cfg_handler cfg_handlers_v3[] = {
1157 { .revision = 0, .config = { .hw = &msm8998_config } },
1158 { .revision = 2, .config = { .hw = &sdm660_config } },
1159 { .revision = 3, .config = { .hw = &sdm630_config } },
1160 };
1161
1162 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev);
1163
mdp5_cfg_get_hw_config(struct mdp5_cfg_handler * cfg_handler)1164 const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_handler)
1165 {
1166 return cfg_handler->config.hw;
1167 }
1168
mdp5_cfg_get_config(struct mdp5_cfg_handler * cfg_handler)1169 struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_handler)
1170 {
1171 return &cfg_handler->config;
1172 }
1173
mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler * cfg_handler)1174 int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_handler)
1175 {
1176 return cfg_handler->revision;
1177 }
1178
mdp5_cfg_destroy(struct mdp5_cfg_handler * cfg_handler)1179 void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_handler)
1180 {
1181 kfree(cfg_handler);
1182 }
1183
mdp5_cfg_init(struct mdp5_kms * mdp5_kms,uint32_t major,uint32_t minor)1184 struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
1185 uint32_t major, uint32_t minor)
1186 {
1187 struct drm_device *dev = mdp5_kms->dev;
1188 struct platform_device *pdev = to_platform_device(dev->dev);
1189 struct mdp5_cfg_handler *cfg_handler;
1190 const struct mdp5_cfg_handler *cfg_handlers;
1191 struct mdp5_cfg_platform *pconfig;
1192 int i, ret = 0, num_handlers;
1193
1194 cfg_handler = kzalloc(sizeof(*cfg_handler), GFP_KERNEL);
1195 if (unlikely(!cfg_handler)) {
1196 ret = -ENOMEM;
1197 goto fail;
1198 }
1199
1200 switch (major) {
1201 case 1:
1202 cfg_handlers = cfg_handlers_v1;
1203 num_handlers = ARRAY_SIZE(cfg_handlers_v1);
1204 break;
1205 case 3:
1206 cfg_handlers = cfg_handlers_v3;
1207 num_handlers = ARRAY_SIZE(cfg_handlers_v3);
1208 break;
1209 default:
1210 DRM_DEV_ERROR(dev->dev, "unexpected MDP major version: v%d.%d\n",
1211 major, minor);
1212 ret = -ENXIO;
1213 goto fail;
1214 }
1215
1216 /* only after mdp5_cfg global pointer's init can we access the hw */
1217 for (i = 0; i < num_handlers; i++) {
1218 if (cfg_handlers[i].revision != minor)
1219 continue;
1220 mdp5_cfg = cfg_handlers[i].config.hw;
1221
1222 break;
1223 }
1224 if (unlikely(!mdp5_cfg)) {
1225 DRM_DEV_ERROR(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
1226 major, minor);
1227 ret = -ENXIO;
1228 goto fail;
1229 }
1230
1231 cfg_handler->revision = minor;
1232 cfg_handler->config.hw = mdp5_cfg;
1233
1234 pconfig = mdp5_get_config(pdev);
1235 memcpy(&cfg_handler->config.platform, pconfig, sizeof(*pconfig));
1236
1237 DBG("MDP5: %s hw config selected", mdp5_cfg->name);
1238
1239 return cfg_handler;
1240
1241 fail:
1242 if (cfg_handler)
1243 mdp5_cfg_destroy(cfg_handler);
1244
1245 return ERR_PTR(ret);
1246 }
1247
mdp5_get_config(struct platform_device * dev)1248 static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev)
1249 {
1250 static struct mdp5_cfg_platform config = {};
1251
1252 config.iommu = iommu_domain_alloc(&platform_bus_type);
1253
1254 return &config;
1255 }
1256