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1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
4  *
5  */
6 
7 #include <linux/delay.h>
8 #include <linux/device.h>
9 #include <linux/dma-direction.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/interrupt.h>
12 #include <linux/list.h>
13 #include <linux/mhi.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/wait.h>
17 #include "internal.h"
18 
19 /*
20  * Not all MHI state transitions are synchronous. Transitions like Linkdown,
21  * SYS_ERR, and shutdown can happen anytime asynchronously. This function will
22  * transition to a new state only if we're allowed to.
23  *
24  * Priority increases as we go down. For instance, from any state in L0, the
25  * transition can be made to states in L1, L2 and L3. A notable exception to
26  * this rule is state DISABLE.  From DISABLE state we can only transition to
27  * POR state. Also, while in L2 state, user cannot jump back to previous
28  * L1 or L0 states.
29  *
30  * Valid transitions:
31  * L0: DISABLE <--> POR
32  *     POR <--> POR
33  *     POR -> M0 -> M2 --> M0
34  *     POR -> FW_DL_ERR
35  *     FW_DL_ERR <--> FW_DL_ERR
36  *     M0 <--> M0
37  *     M0 -> FW_DL_ERR
38  *     M0 -> M3_ENTER -> M3 -> M3_EXIT --> M0
39  * L1: SYS_ERR_DETECT -> SYS_ERR_PROCESS --> POR
40  * L2: SHUTDOWN_PROCESS -> LD_ERR_FATAL_DETECT
41  *     SHUTDOWN_PROCESS -> DISABLE
42  * L3: LD_ERR_FATAL_DETECT <--> LD_ERR_FATAL_DETECT
43  *     LD_ERR_FATAL_DETECT -> DISABLE
44  */
45 static struct mhi_pm_transitions const dev_state_transitions[] = {
46 	/* L0 States */
47 	{
48 		MHI_PM_DISABLE,
49 		MHI_PM_POR
50 	},
51 	{
52 		MHI_PM_POR,
53 		MHI_PM_POR | MHI_PM_DISABLE | MHI_PM_M0 |
54 		MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
55 		MHI_PM_LD_ERR_FATAL_DETECT | MHI_PM_FW_DL_ERR
56 	},
57 	{
58 		MHI_PM_M0,
59 		MHI_PM_M0 | MHI_PM_M2 | MHI_PM_M3_ENTER |
60 		MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
61 		MHI_PM_LD_ERR_FATAL_DETECT | MHI_PM_FW_DL_ERR
62 	},
63 	{
64 		MHI_PM_M2,
65 		MHI_PM_M0 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
66 		MHI_PM_LD_ERR_FATAL_DETECT
67 	},
68 	{
69 		MHI_PM_M3_ENTER,
70 		MHI_PM_M3 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
71 		MHI_PM_LD_ERR_FATAL_DETECT
72 	},
73 	{
74 		MHI_PM_M3,
75 		MHI_PM_M3_EXIT | MHI_PM_SYS_ERR_DETECT |
76 		MHI_PM_LD_ERR_FATAL_DETECT
77 	},
78 	{
79 		MHI_PM_M3_EXIT,
80 		MHI_PM_M0 | MHI_PM_SYS_ERR_DETECT | MHI_PM_SHUTDOWN_PROCESS |
81 		MHI_PM_LD_ERR_FATAL_DETECT
82 	},
83 	{
84 		MHI_PM_FW_DL_ERR,
85 		MHI_PM_FW_DL_ERR | MHI_PM_SYS_ERR_DETECT |
86 		MHI_PM_SHUTDOWN_PROCESS | MHI_PM_LD_ERR_FATAL_DETECT
87 	},
88 	/* L1 States */
89 	{
90 		MHI_PM_SYS_ERR_DETECT,
91 		MHI_PM_SYS_ERR_PROCESS | MHI_PM_SHUTDOWN_PROCESS |
92 		MHI_PM_LD_ERR_FATAL_DETECT
93 	},
94 	{
95 		MHI_PM_SYS_ERR_PROCESS,
96 		MHI_PM_POR | MHI_PM_SHUTDOWN_PROCESS |
97 		MHI_PM_LD_ERR_FATAL_DETECT
98 	},
99 	/* L2 States */
100 	{
101 		MHI_PM_SHUTDOWN_PROCESS,
102 		MHI_PM_DISABLE | MHI_PM_LD_ERR_FATAL_DETECT
103 	},
104 	/* L3 States */
105 	{
106 		MHI_PM_LD_ERR_FATAL_DETECT,
107 		MHI_PM_LD_ERR_FATAL_DETECT | MHI_PM_DISABLE
108 	},
109 };
110 
mhi_tryset_pm_state(struct mhi_controller * mhi_cntrl,enum mhi_pm_state state)111 enum mhi_pm_state __must_check mhi_tryset_pm_state(struct mhi_controller *mhi_cntrl,
112 						   enum mhi_pm_state state)
113 {
114 	unsigned long cur_state = mhi_cntrl->pm_state;
115 	int index = find_last_bit(&cur_state, 32);
116 
117 	if (unlikely(index >= ARRAY_SIZE(dev_state_transitions)))
118 		return cur_state;
119 
120 	if (unlikely(dev_state_transitions[index].from_state != cur_state))
121 		return cur_state;
122 
123 	if (unlikely(!(dev_state_transitions[index].to_states & state)))
124 		return cur_state;
125 
126 	mhi_cntrl->pm_state = state;
127 	return mhi_cntrl->pm_state;
128 }
129 
mhi_set_mhi_state(struct mhi_controller * mhi_cntrl,enum mhi_state state)130 void mhi_set_mhi_state(struct mhi_controller *mhi_cntrl, enum mhi_state state)
131 {
132 	if (state == MHI_STATE_RESET) {
133 		mhi_write_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
134 				    MHICTRL_RESET_MASK, MHICTRL_RESET_SHIFT, 1);
135 	} else {
136 		mhi_write_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
137 				    MHICTRL_MHISTATE_MASK,
138 				    MHICTRL_MHISTATE_SHIFT, state);
139 	}
140 }
141 
142 /* NOP for backward compatibility, host allowed to ring DB in M2 state */
mhi_toggle_dev_wake_nop(struct mhi_controller * mhi_cntrl)143 static void mhi_toggle_dev_wake_nop(struct mhi_controller *mhi_cntrl)
144 {
145 }
146 
mhi_toggle_dev_wake(struct mhi_controller * mhi_cntrl)147 static void mhi_toggle_dev_wake(struct mhi_controller *mhi_cntrl)
148 {
149 	mhi_cntrl->wake_get(mhi_cntrl, false);
150 	mhi_cntrl->wake_put(mhi_cntrl, true);
151 }
152 
153 /* Handle device ready state transition */
mhi_ready_state_transition(struct mhi_controller * mhi_cntrl)154 int mhi_ready_state_transition(struct mhi_controller *mhi_cntrl)
155 {
156 	struct mhi_event *mhi_event;
157 	enum mhi_pm_state cur_state;
158 	struct device *dev = &mhi_cntrl->mhi_dev->dev;
159 	u32 interval_us = 25000; /* poll register field every 25 milliseconds */
160 	int ret, i;
161 
162 	/* Check if device entered error state */
163 	if (MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state)) {
164 		dev_err(dev, "Device link is not accessible\n");
165 		return -EIO;
166 	}
167 
168 	/* Wait for RESET to be cleared and READY bit to be set by the device */
169 	ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
170 				 MHICTRL_RESET_MASK, MHICTRL_RESET_SHIFT, 0,
171 				 interval_us);
172 	if (ret) {
173 		dev_err(dev, "Device failed to clear MHI Reset\n");
174 		return ret;
175 	}
176 
177 	ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHISTATUS,
178 				 MHISTATUS_READY_MASK, MHISTATUS_READY_SHIFT, 1,
179 				 interval_us);
180 	if (ret) {
181 		dev_err(dev, "Device failed to enter MHI Ready\n");
182 		return ret;
183 	}
184 
185 	dev_dbg(dev, "Device in READY State\n");
186 	write_lock_irq(&mhi_cntrl->pm_lock);
187 	cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_POR);
188 	mhi_cntrl->dev_state = MHI_STATE_READY;
189 	write_unlock_irq(&mhi_cntrl->pm_lock);
190 
191 	if (cur_state != MHI_PM_POR) {
192 		dev_err(dev, "Error moving to state %s from %s\n",
193 			to_mhi_pm_state_str(MHI_PM_POR),
194 			to_mhi_pm_state_str(cur_state));
195 		return -EIO;
196 	}
197 
198 	read_lock_bh(&mhi_cntrl->pm_lock);
199 	if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) {
200 		dev_err(dev, "Device registers not accessible\n");
201 		goto error_mmio;
202 	}
203 
204 	/* Configure MMIO registers */
205 	ret = mhi_init_mmio(mhi_cntrl);
206 	if (ret) {
207 		dev_err(dev, "Error configuring MMIO registers\n");
208 		goto error_mmio;
209 	}
210 
211 	/* Add elements to all SW event rings */
212 	mhi_event = mhi_cntrl->mhi_event;
213 	for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
214 		struct mhi_ring *ring = &mhi_event->ring;
215 
216 		/* Skip if this is an offload or HW event */
217 		if (mhi_event->offload_ev || mhi_event->hw_ring)
218 			continue;
219 
220 		ring->wp = ring->base + ring->len - ring->el_size;
221 		*ring->ctxt_wp = cpu_to_le64(ring->iommu_base + ring->len - ring->el_size);
222 		/* Update all cores */
223 		smp_wmb();
224 
225 		/* Ring the event ring db */
226 		spin_lock_irq(&mhi_event->lock);
227 		mhi_ring_er_db(mhi_event);
228 		spin_unlock_irq(&mhi_event->lock);
229 	}
230 
231 	/* Set MHI to M0 state */
232 	mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M0);
233 	read_unlock_bh(&mhi_cntrl->pm_lock);
234 
235 	return 0;
236 
237 error_mmio:
238 	read_unlock_bh(&mhi_cntrl->pm_lock);
239 
240 	return -EIO;
241 }
242 
mhi_pm_m0_transition(struct mhi_controller * mhi_cntrl)243 int mhi_pm_m0_transition(struct mhi_controller *mhi_cntrl)
244 {
245 	enum mhi_pm_state cur_state;
246 	struct mhi_chan *mhi_chan;
247 	struct device *dev = &mhi_cntrl->mhi_dev->dev;
248 	int i;
249 
250 	write_lock_irq(&mhi_cntrl->pm_lock);
251 	mhi_cntrl->dev_state = MHI_STATE_M0;
252 	cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M0);
253 	write_unlock_irq(&mhi_cntrl->pm_lock);
254 	if (unlikely(cur_state != MHI_PM_M0)) {
255 		dev_err(dev, "Unable to transition to M0 state\n");
256 		return -EIO;
257 	}
258 	mhi_cntrl->M0++;
259 
260 	/* Wake up the device */
261 	read_lock_bh(&mhi_cntrl->pm_lock);
262 	mhi_cntrl->wake_get(mhi_cntrl, true);
263 
264 	/* Ring all event rings and CMD ring only if we're in mission mode */
265 	if (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) {
266 		struct mhi_event *mhi_event = mhi_cntrl->mhi_event;
267 		struct mhi_cmd *mhi_cmd =
268 			&mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING];
269 
270 		for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
271 			if (mhi_event->offload_ev)
272 				continue;
273 
274 			spin_lock_irq(&mhi_event->lock);
275 			mhi_ring_er_db(mhi_event);
276 			spin_unlock_irq(&mhi_event->lock);
277 		}
278 
279 		/* Only ring primary cmd ring if ring is not empty */
280 		spin_lock_irq(&mhi_cmd->lock);
281 		if (mhi_cmd->ring.rp != mhi_cmd->ring.wp)
282 			mhi_ring_cmd_db(mhi_cntrl, mhi_cmd);
283 		spin_unlock_irq(&mhi_cmd->lock);
284 	}
285 
286 	/* Ring channel DB registers */
287 	mhi_chan = mhi_cntrl->mhi_chan;
288 	for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) {
289 		struct mhi_ring *tre_ring = &mhi_chan->tre_ring;
290 
291 		if (mhi_chan->db_cfg.reset_req) {
292 			write_lock_irq(&mhi_chan->lock);
293 			mhi_chan->db_cfg.db_mode = true;
294 			write_unlock_irq(&mhi_chan->lock);
295 		}
296 
297 		read_lock_irq(&mhi_chan->lock);
298 
299 		/* Only ring DB if ring is not empty */
300 		if (tre_ring->base && tre_ring->wp  != tre_ring->rp &&
301 		    mhi_chan->ch_state == MHI_CH_STATE_ENABLED)
302 			mhi_ring_chan_db(mhi_cntrl, mhi_chan);
303 		read_unlock_irq(&mhi_chan->lock);
304 	}
305 
306 	mhi_cntrl->wake_put(mhi_cntrl, false);
307 	read_unlock_bh(&mhi_cntrl->pm_lock);
308 	wake_up_all(&mhi_cntrl->state_event);
309 
310 	return 0;
311 }
312 
313 /*
314  * After receiving the MHI state change event from the device indicating the
315  * transition to M1 state, the host can transition the device to M2 state
316  * for keeping it in low power state.
317  */
mhi_pm_m1_transition(struct mhi_controller * mhi_cntrl)318 void mhi_pm_m1_transition(struct mhi_controller *mhi_cntrl)
319 {
320 	enum mhi_pm_state state;
321 	struct device *dev = &mhi_cntrl->mhi_dev->dev;
322 
323 	write_lock_irq(&mhi_cntrl->pm_lock);
324 	state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M2);
325 	if (state == MHI_PM_M2) {
326 		mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M2);
327 		mhi_cntrl->dev_state = MHI_STATE_M2;
328 
329 		write_unlock_irq(&mhi_cntrl->pm_lock);
330 
331 		mhi_cntrl->M2++;
332 		wake_up_all(&mhi_cntrl->state_event);
333 
334 		/* If there are any pending resources, exit M2 immediately */
335 		if (unlikely(atomic_read(&mhi_cntrl->pending_pkts) ||
336 			     atomic_read(&mhi_cntrl->dev_wake))) {
337 			dev_dbg(dev,
338 				"Exiting M2, pending_pkts: %d dev_wake: %d\n",
339 				atomic_read(&mhi_cntrl->pending_pkts),
340 				atomic_read(&mhi_cntrl->dev_wake));
341 			read_lock_bh(&mhi_cntrl->pm_lock);
342 			mhi_cntrl->wake_get(mhi_cntrl, true);
343 			mhi_cntrl->wake_put(mhi_cntrl, true);
344 			read_unlock_bh(&mhi_cntrl->pm_lock);
345 		} else {
346 			mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_IDLE);
347 		}
348 	} else {
349 		write_unlock_irq(&mhi_cntrl->pm_lock);
350 	}
351 }
352 
353 /* MHI M3 completion handler */
mhi_pm_m3_transition(struct mhi_controller * mhi_cntrl)354 int mhi_pm_m3_transition(struct mhi_controller *mhi_cntrl)
355 {
356 	enum mhi_pm_state state;
357 	struct device *dev = &mhi_cntrl->mhi_dev->dev;
358 
359 	write_lock_irq(&mhi_cntrl->pm_lock);
360 	mhi_cntrl->dev_state = MHI_STATE_M3;
361 	state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3);
362 	write_unlock_irq(&mhi_cntrl->pm_lock);
363 	if (state != MHI_PM_M3) {
364 		dev_err(dev, "Unable to transition to M3 state\n");
365 		return -EIO;
366 	}
367 
368 	mhi_cntrl->M3++;
369 	wake_up_all(&mhi_cntrl->state_event);
370 
371 	return 0;
372 }
373 
374 /* Handle device Mission Mode transition */
mhi_pm_mission_mode_transition(struct mhi_controller * mhi_cntrl)375 static int mhi_pm_mission_mode_transition(struct mhi_controller *mhi_cntrl)
376 {
377 	struct mhi_event *mhi_event;
378 	struct device *dev = &mhi_cntrl->mhi_dev->dev;
379 	enum mhi_ee_type ee = MHI_EE_MAX, current_ee = mhi_cntrl->ee;
380 	int i, ret;
381 
382 	dev_dbg(dev, "Processing Mission Mode transition\n");
383 
384 	write_lock_irq(&mhi_cntrl->pm_lock);
385 	if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state))
386 		ee = mhi_get_exec_env(mhi_cntrl);
387 
388 	if (!MHI_IN_MISSION_MODE(ee)) {
389 		mhi_cntrl->pm_state = MHI_PM_LD_ERR_FATAL_DETECT;
390 		write_unlock_irq(&mhi_cntrl->pm_lock);
391 		wake_up_all(&mhi_cntrl->state_event);
392 		return -EIO;
393 	}
394 	mhi_cntrl->ee = ee;
395 	write_unlock_irq(&mhi_cntrl->pm_lock);
396 
397 	wake_up_all(&mhi_cntrl->state_event);
398 
399 	device_for_each_child(&mhi_cntrl->mhi_dev->dev, &current_ee,
400 			      mhi_destroy_device);
401 	mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_EE_MISSION_MODE);
402 
403 	/* Force MHI to be in M0 state before continuing */
404 	ret = __mhi_device_get_sync(mhi_cntrl);
405 	if (ret)
406 		return ret;
407 
408 	read_lock_bh(&mhi_cntrl->pm_lock);
409 
410 	if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
411 		ret = -EIO;
412 		goto error_mission_mode;
413 	}
414 
415 	/* Add elements to all HW event rings */
416 	mhi_event = mhi_cntrl->mhi_event;
417 	for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
418 		struct mhi_ring *ring = &mhi_event->ring;
419 
420 		if (mhi_event->offload_ev || !mhi_event->hw_ring)
421 			continue;
422 
423 		ring->wp = ring->base + ring->len - ring->el_size;
424 		*ring->ctxt_wp = cpu_to_le64(ring->iommu_base + ring->len - ring->el_size);
425 		/* Update to all cores */
426 		smp_wmb();
427 
428 		spin_lock_irq(&mhi_event->lock);
429 		if (MHI_DB_ACCESS_VALID(mhi_cntrl))
430 			mhi_ring_er_db(mhi_event);
431 		spin_unlock_irq(&mhi_event->lock);
432 	}
433 
434 	read_unlock_bh(&mhi_cntrl->pm_lock);
435 
436 	/*
437 	 * The MHI devices are only created when the client device switches its
438 	 * Execution Environment (EE) to either SBL or AMSS states
439 	 */
440 	mhi_create_devices(mhi_cntrl);
441 
442 	read_lock_bh(&mhi_cntrl->pm_lock);
443 
444 error_mission_mode:
445 	mhi_cntrl->wake_put(mhi_cntrl, false);
446 	read_unlock_bh(&mhi_cntrl->pm_lock);
447 
448 	return ret;
449 }
450 
451 /* Handle shutdown transitions */
mhi_pm_disable_transition(struct mhi_controller * mhi_cntrl)452 static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl)
453 {
454 	enum mhi_pm_state cur_state;
455 	struct mhi_event *mhi_event;
456 	struct mhi_cmd_ctxt *cmd_ctxt;
457 	struct mhi_cmd *mhi_cmd;
458 	struct mhi_event_ctxt *er_ctxt;
459 	struct device *dev = &mhi_cntrl->mhi_dev->dev;
460 	int ret, i;
461 
462 	dev_dbg(dev, "Processing disable transition with PM state: %s\n",
463 		to_mhi_pm_state_str(mhi_cntrl->pm_state));
464 
465 	mutex_lock(&mhi_cntrl->pm_mutex);
466 
467 	/* Trigger MHI RESET so that the device will not access host memory */
468 	if (!MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state)) {
469 		/* Skip MHI RESET if in RDDM state */
470 		if (mhi_cntrl->rddm_image && mhi_get_exec_env(mhi_cntrl) == MHI_EE_RDDM)
471 			goto skip_mhi_reset;
472 
473 		dev_dbg(dev, "Triggering MHI Reset in device\n");
474 		mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
475 
476 		/* Wait for the reset bit to be cleared by the device */
477 		ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
478 				 MHICTRL_RESET_MASK, MHICTRL_RESET_SHIFT, 0,
479 				 25000);
480 		if (ret)
481 			dev_err(dev, "Device failed to clear MHI Reset\n");
482 
483 		/*
484 		 * Device will clear BHI_INTVEC as a part of RESET processing,
485 		 * hence re-program it
486 		 */
487 		mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
488 	}
489 
490 skip_mhi_reset:
491 	dev_dbg(dev,
492 		 "Waiting for all pending event ring processing to complete\n");
493 	mhi_event = mhi_cntrl->mhi_event;
494 	for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
495 		if (mhi_event->offload_ev)
496 			continue;
497 		free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event);
498 		tasklet_kill(&mhi_event->task);
499 	}
500 
501 	/* Release lock and wait for all pending threads to complete */
502 	mutex_unlock(&mhi_cntrl->pm_mutex);
503 	dev_dbg(dev, "Waiting for all pending threads to complete\n");
504 	wake_up_all(&mhi_cntrl->state_event);
505 
506 	dev_dbg(dev, "Reset all active channels and remove MHI devices\n");
507 	device_for_each_child(&mhi_cntrl->mhi_dev->dev, NULL, mhi_destroy_device);
508 
509 	mutex_lock(&mhi_cntrl->pm_mutex);
510 
511 	WARN_ON(atomic_read(&mhi_cntrl->dev_wake));
512 	WARN_ON(atomic_read(&mhi_cntrl->pending_pkts));
513 
514 	/* Reset the ev rings and cmd rings */
515 	dev_dbg(dev, "Resetting EV CTXT and CMD CTXT\n");
516 	mhi_cmd = mhi_cntrl->mhi_cmd;
517 	cmd_ctxt = mhi_cntrl->mhi_ctxt->cmd_ctxt;
518 	for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++, cmd_ctxt++) {
519 		struct mhi_ring *ring = &mhi_cmd->ring;
520 
521 		ring->rp = ring->base;
522 		ring->wp = ring->base;
523 		cmd_ctxt->rp = cmd_ctxt->rbase;
524 		cmd_ctxt->wp = cmd_ctxt->rbase;
525 	}
526 
527 	mhi_event = mhi_cntrl->mhi_event;
528 	er_ctxt = mhi_cntrl->mhi_ctxt->er_ctxt;
529 	for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++,
530 		     mhi_event++) {
531 		struct mhi_ring *ring = &mhi_event->ring;
532 
533 		/* Skip offload events */
534 		if (mhi_event->offload_ev)
535 			continue;
536 
537 		ring->rp = ring->base;
538 		ring->wp = ring->base;
539 		er_ctxt->rp = er_ctxt->rbase;
540 		er_ctxt->wp = er_ctxt->rbase;
541 	}
542 
543 	/* Move to disable state */
544 	write_lock_irq(&mhi_cntrl->pm_lock);
545 	cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_DISABLE);
546 	write_unlock_irq(&mhi_cntrl->pm_lock);
547 	if (unlikely(cur_state != MHI_PM_DISABLE))
548 		dev_err(dev, "Error moving from PM state: %s to: %s\n",
549 			to_mhi_pm_state_str(cur_state),
550 			to_mhi_pm_state_str(MHI_PM_DISABLE));
551 
552 	dev_dbg(dev, "Exiting with PM state: %s, MHI state: %s\n",
553 		to_mhi_pm_state_str(mhi_cntrl->pm_state),
554 		TO_MHI_STATE_STR(mhi_cntrl->dev_state));
555 
556 	mutex_unlock(&mhi_cntrl->pm_mutex);
557 }
558 
559 /* Handle system error transitions */
mhi_pm_sys_error_transition(struct mhi_controller * mhi_cntrl)560 static void mhi_pm_sys_error_transition(struct mhi_controller *mhi_cntrl)
561 {
562 	enum mhi_pm_state cur_state, prev_state;
563 	enum dev_st_transition next_state;
564 	struct mhi_event *mhi_event;
565 	struct mhi_cmd_ctxt *cmd_ctxt;
566 	struct mhi_cmd *mhi_cmd;
567 	struct mhi_event_ctxt *er_ctxt;
568 	struct device *dev = &mhi_cntrl->mhi_dev->dev;
569 	int ret, i;
570 
571 	dev_dbg(dev, "Transitioning from PM state: %s to: %s\n",
572 		to_mhi_pm_state_str(mhi_cntrl->pm_state),
573 		to_mhi_pm_state_str(MHI_PM_SYS_ERR_PROCESS));
574 
575 	/* We must notify MHI control driver so it can clean up first */
576 	mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_SYS_ERROR);
577 
578 	mutex_lock(&mhi_cntrl->pm_mutex);
579 	write_lock_irq(&mhi_cntrl->pm_lock);
580 	prev_state = mhi_cntrl->pm_state;
581 	cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_SYS_ERR_PROCESS);
582 	write_unlock_irq(&mhi_cntrl->pm_lock);
583 
584 	if (cur_state != MHI_PM_SYS_ERR_PROCESS) {
585 		dev_err(dev, "Failed to transition from PM state: %s to: %s\n",
586 			to_mhi_pm_state_str(cur_state),
587 			to_mhi_pm_state_str(MHI_PM_SYS_ERR_PROCESS));
588 		goto exit_sys_error_transition;
589 	}
590 
591 	mhi_cntrl->ee = MHI_EE_DISABLE_TRANSITION;
592 	mhi_cntrl->dev_state = MHI_STATE_RESET;
593 
594 	/* Wake up threads waiting for state transition */
595 	wake_up_all(&mhi_cntrl->state_event);
596 
597 	/* Trigger MHI RESET so that the device will not access host memory */
598 	if (MHI_REG_ACCESS_VALID(prev_state)) {
599 		u32 in_reset = -1;
600 		unsigned long timeout = msecs_to_jiffies(mhi_cntrl->timeout_ms);
601 
602 		dev_dbg(dev, "Triggering MHI Reset in device\n");
603 		mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
604 
605 		/* Wait for the reset bit to be cleared by the device */
606 		ret = wait_event_timeout(mhi_cntrl->state_event,
607 					 mhi_read_reg_field(mhi_cntrl,
608 							    mhi_cntrl->regs,
609 							    MHICTRL,
610 							    MHICTRL_RESET_MASK,
611 							    MHICTRL_RESET_SHIFT,
612 							    &in_reset) ||
613 					!in_reset, timeout);
614 		if (!ret || in_reset) {
615 			dev_err(dev, "Device failed to exit MHI Reset state\n");
616 			goto exit_sys_error_transition;
617 		}
618 
619 		/*
620 		 * Device will clear BHI_INTVEC as a part of RESET processing,
621 		 * hence re-program it
622 		 */
623 		mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
624 	}
625 
626 	dev_dbg(dev,
627 		"Waiting for all pending event ring processing to complete\n");
628 	mhi_event = mhi_cntrl->mhi_event;
629 	for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) {
630 		if (mhi_event->offload_ev)
631 			continue;
632 		tasklet_kill(&mhi_event->task);
633 	}
634 
635 	/* Release lock and wait for all pending threads to complete */
636 	mutex_unlock(&mhi_cntrl->pm_mutex);
637 	dev_dbg(dev, "Waiting for all pending threads to complete\n");
638 	wake_up_all(&mhi_cntrl->state_event);
639 
640 	dev_dbg(dev, "Reset all active channels and remove MHI devices\n");
641 	device_for_each_child(&mhi_cntrl->mhi_dev->dev, NULL, mhi_destroy_device);
642 
643 	mutex_lock(&mhi_cntrl->pm_mutex);
644 
645 	WARN_ON(atomic_read(&mhi_cntrl->dev_wake));
646 	WARN_ON(atomic_read(&mhi_cntrl->pending_pkts));
647 
648 	/* Reset the ev rings and cmd rings */
649 	dev_dbg(dev, "Resetting EV CTXT and CMD CTXT\n");
650 	mhi_cmd = mhi_cntrl->mhi_cmd;
651 	cmd_ctxt = mhi_cntrl->mhi_ctxt->cmd_ctxt;
652 	for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++, cmd_ctxt++) {
653 		struct mhi_ring *ring = &mhi_cmd->ring;
654 
655 		ring->rp = ring->base;
656 		ring->wp = ring->base;
657 		cmd_ctxt->rp = cmd_ctxt->rbase;
658 		cmd_ctxt->wp = cmd_ctxt->rbase;
659 	}
660 
661 	mhi_event = mhi_cntrl->mhi_event;
662 	er_ctxt = mhi_cntrl->mhi_ctxt->er_ctxt;
663 	for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++,
664 	     mhi_event++) {
665 		struct mhi_ring *ring = &mhi_event->ring;
666 
667 		/* Skip offload events */
668 		if (mhi_event->offload_ev)
669 			continue;
670 
671 		ring->rp = ring->base;
672 		ring->wp = ring->base;
673 		er_ctxt->rp = er_ctxt->rbase;
674 		er_ctxt->wp = er_ctxt->rbase;
675 	}
676 
677 	/* Transition to next state */
678 	if (MHI_IN_PBL(mhi_get_exec_env(mhi_cntrl))) {
679 		write_lock_irq(&mhi_cntrl->pm_lock);
680 		cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_POR);
681 		write_unlock_irq(&mhi_cntrl->pm_lock);
682 		if (cur_state != MHI_PM_POR) {
683 			dev_err(dev, "Error moving to state %s from %s\n",
684 				to_mhi_pm_state_str(MHI_PM_POR),
685 				to_mhi_pm_state_str(cur_state));
686 			goto exit_sys_error_transition;
687 		}
688 		next_state = DEV_ST_TRANSITION_PBL;
689 	} else {
690 		next_state = DEV_ST_TRANSITION_READY;
691 	}
692 
693 	mhi_queue_state_transition(mhi_cntrl, next_state);
694 
695 exit_sys_error_transition:
696 	dev_dbg(dev, "Exiting with PM state: %s, MHI state: %s\n",
697 		to_mhi_pm_state_str(mhi_cntrl->pm_state),
698 		TO_MHI_STATE_STR(mhi_cntrl->dev_state));
699 
700 	mutex_unlock(&mhi_cntrl->pm_mutex);
701 }
702 
703 /* Queue a new work item and schedule work */
mhi_queue_state_transition(struct mhi_controller * mhi_cntrl,enum dev_st_transition state)704 int mhi_queue_state_transition(struct mhi_controller *mhi_cntrl,
705 			       enum dev_st_transition state)
706 {
707 	struct state_transition *item = kmalloc(sizeof(*item), GFP_ATOMIC);
708 	unsigned long flags;
709 
710 	if (!item)
711 		return -ENOMEM;
712 
713 	item->state = state;
714 	spin_lock_irqsave(&mhi_cntrl->transition_lock, flags);
715 	list_add_tail(&item->node, &mhi_cntrl->transition_list);
716 	spin_unlock_irqrestore(&mhi_cntrl->transition_lock, flags);
717 
718 	queue_work(mhi_cntrl->hiprio_wq, &mhi_cntrl->st_worker);
719 
720 	return 0;
721 }
722 
723 /* SYS_ERR worker */
mhi_pm_sys_err_handler(struct mhi_controller * mhi_cntrl)724 void mhi_pm_sys_err_handler(struct mhi_controller *mhi_cntrl)
725 {
726 	struct device *dev = &mhi_cntrl->mhi_dev->dev;
727 
728 	/* skip if controller supports RDDM */
729 	if (mhi_cntrl->rddm_image) {
730 		dev_dbg(dev, "Controller supports RDDM, skip SYS_ERROR\n");
731 		return;
732 	}
733 
734 	mhi_queue_state_transition(mhi_cntrl, DEV_ST_TRANSITION_SYS_ERR);
735 }
736 
737 /* Device State Transition worker */
mhi_pm_st_worker(struct work_struct * work)738 void mhi_pm_st_worker(struct work_struct *work)
739 {
740 	struct state_transition *itr, *tmp;
741 	LIST_HEAD(head);
742 	struct mhi_controller *mhi_cntrl = container_of(work,
743 							struct mhi_controller,
744 							st_worker);
745 	struct device *dev = &mhi_cntrl->mhi_dev->dev;
746 
747 	spin_lock_irq(&mhi_cntrl->transition_lock);
748 	list_splice_tail_init(&mhi_cntrl->transition_list, &head);
749 	spin_unlock_irq(&mhi_cntrl->transition_lock);
750 
751 	list_for_each_entry_safe(itr, tmp, &head, node) {
752 		list_del(&itr->node);
753 		dev_dbg(dev, "Handling state transition: %s\n",
754 			TO_DEV_STATE_TRANS_STR(itr->state));
755 
756 		switch (itr->state) {
757 		case DEV_ST_TRANSITION_PBL:
758 			write_lock_irq(&mhi_cntrl->pm_lock);
759 			if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state))
760 				mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl);
761 			write_unlock_irq(&mhi_cntrl->pm_lock);
762 			mhi_fw_load_handler(mhi_cntrl);
763 			break;
764 		case DEV_ST_TRANSITION_SBL:
765 			write_lock_irq(&mhi_cntrl->pm_lock);
766 			mhi_cntrl->ee = MHI_EE_SBL;
767 			write_unlock_irq(&mhi_cntrl->pm_lock);
768 			/*
769 			 * The MHI devices are only created when the client
770 			 * device switches its Execution Environment (EE) to
771 			 * either SBL or AMSS states
772 			 */
773 			mhi_create_devices(mhi_cntrl);
774 			if (mhi_cntrl->fbc_download)
775 				mhi_download_amss_image(mhi_cntrl);
776 			break;
777 		case DEV_ST_TRANSITION_MISSION_MODE:
778 			mhi_pm_mission_mode_transition(mhi_cntrl);
779 			break;
780 		case DEV_ST_TRANSITION_FP:
781 			write_lock_irq(&mhi_cntrl->pm_lock);
782 			mhi_cntrl->ee = MHI_EE_FP;
783 			write_unlock_irq(&mhi_cntrl->pm_lock);
784 			mhi_create_devices(mhi_cntrl);
785 			break;
786 		case DEV_ST_TRANSITION_READY:
787 			mhi_ready_state_transition(mhi_cntrl);
788 			break;
789 		case DEV_ST_TRANSITION_SYS_ERR:
790 			mhi_pm_sys_error_transition(mhi_cntrl);
791 			break;
792 		case DEV_ST_TRANSITION_DISABLE:
793 			mhi_pm_disable_transition(mhi_cntrl);
794 			break;
795 		default:
796 			break;
797 		}
798 		kfree(itr);
799 	}
800 }
801 
mhi_pm_suspend(struct mhi_controller * mhi_cntrl)802 int mhi_pm_suspend(struct mhi_controller *mhi_cntrl)
803 {
804 	struct mhi_chan *itr, *tmp;
805 	struct device *dev = &mhi_cntrl->mhi_dev->dev;
806 	enum mhi_pm_state new_state;
807 	int ret;
808 
809 	if (mhi_cntrl->pm_state == MHI_PM_DISABLE)
810 		return -EINVAL;
811 
812 	if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))
813 		return -EIO;
814 
815 	/* Return busy if there are any pending resources */
816 	if (atomic_read(&mhi_cntrl->dev_wake) ||
817 	    atomic_read(&mhi_cntrl->pending_pkts))
818 		return -EBUSY;
819 
820 	/* Take MHI out of M2 state */
821 	read_lock_bh(&mhi_cntrl->pm_lock);
822 	mhi_cntrl->wake_get(mhi_cntrl, false);
823 	read_unlock_bh(&mhi_cntrl->pm_lock);
824 
825 	ret = wait_event_timeout(mhi_cntrl->state_event,
826 				 mhi_cntrl->dev_state == MHI_STATE_M0 ||
827 				 mhi_cntrl->dev_state == MHI_STATE_M1 ||
828 				 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
829 				 msecs_to_jiffies(mhi_cntrl->timeout_ms));
830 
831 	read_lock_bh(&mhi_cntrl->pm_lock);
832 	mhi_cntrl->wake_put(mhi_cntrl, false);
833 	read_unlock_bh(&mhi_cntrl->pm_lock);
834 
835 	if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
836 		dev_err(dev,
837 			"Could not enter M0/M1 state");
838 		return -EIO;
839 	}
840 
841 	write_lock_irq(&mhi_cntrl->pm_lock);
842 
843 	if (atomic_read(&mhi_cntrl->dev_wake) ||
844 	    atomic_read(&mhi_cntrl->pending_pkts)) {
845 		write_unlock_irq(&mhi_cntrl->pm_lock);
846 		return -EBUSY;
847 	}
848 
849 	dev_dbg(dev, "Allowing M3 transition\n");
850 	new_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_ENTER);
851 	if (new_state != MHI_PM_M3_ENTER) {
852 		write_unlock_irq(&mhi_cntrl->pm_lock);
853 		dev_err(dev,
854 			"Error setting to PM state: %s from: %s\n",
855 			to_mhi_pm_state_str(MHI_PM_M3_ENTER),
856 			to_mhi_pm_state_str(mhi_cntrl->pm_state));
857 		return -EIO;
858 	}
859 
860 	/* Set MHI to M3 and wait for completion */
861 	mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M3);
862 	write_unlock_irq(&mhi_cntrl->pm_lock);
863 	dev_dbg(dev, "Waiting for M3 completion\n");
864 
865 	ret = wait_event_timeout(mhi_cntrl->state_event,
866 				 mhi_cntrl->dev_state == MHI_STATE_M3 ||
867 				 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
868 				 msecs_to_jiffies(mhi_cntrl->timeout_ms));
869 
870 	if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
871 		dev_err(dev,
872 			"Did not enter M3 state, MHI state: %s, PM state: %s\n",
873 			TO_MHI_STATE_STR(mhi_cntrl->dev_state),
874 			to_mhi_pm_state_str(mhi_cntrl->pm_state));
875 		return -EIO;
876 	}
877 
878 	/* Notify clients about entering LPM */
879 	list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) {
880 		mutex_lock(&itr->mutex);
881 		if (itr->mhi_dev)
882 			mhi_notify(itr->mhi_dev, MHI_CB_LPM_ENTER);
883 		mutex_unlock(&itr->mutex);
884 	}
885 
886 	return 0;
887 }
888 EXPORT_SYMBOL_GPL(mhi_pm_suspend);
889 
__mhi_pm_resume(struct mhi_controller * mhi_cntrl,bool force)890 static int __mhi_pm_resume(struct mhi_controller *mhi_cntrl, bool force)
891 {
892 	struct mhi_chan *itr, *tmp;
893 	struct device *dev = &mhi_cntrl->mhi_dev->dev;
894 	enum mhi_pm_state cur_state;
895 	int ret;
896 
897 	dev_dbg(dev, "Entered with PM state: %s, MHI state: %s\n",
898 		to_mhi_pm_state_str(mhi_cntrl->pm_state),
899 		TO_MHI_STATE_STR(mhi_cntrl->dev_state));
900 
901 	if (mhi_cntrl->pm_state == MHI_PM_DISABLE)
902 		return 0;
903 
904 	if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))
905 		return -EIO;
906 
907 	if (mhi_get_mhi_state(mhi_cntrl) != MHI_STATE_M3) {
908 		dev_warn(dev, "Resuming from non M3 state (%s)\n",
909 			 TO_MHI_STATE_STR(mhi_get_mhi_state(mhi_cntrl)));
910 		if (!force)
911 			return -EINVAL;
912 	}
913 
914 	/* Notify clients about exiting LPM */
915 	list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) {
916 		mutex_lock(&itr->mutex);
917 		if (itr->mhi_dev)
918 			mhi_notify(itr->mhi_dev, MHI_CB_LPM_EXIT);
919 		mutex_unlock(&itr->mutex);
920 	}
921 
922 	write_lock_irq(&mhi_cntrl->pm_lock);
923 	cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_EXIT);
924 	if (cur_state != MHI_PM_M3_EXIT) {
925 		write_unlock_irq(&mhi_cntrl->pm_lock);
926 		dev_info(dev,
927 			 "Error setting to PM state: %s from: %s\n",
928 			 to_mhi_pm_state_str(MHI_PM_M3_EXIT),
929 			 to_mhi_pm_state_str(mhi_cntrl->pm_state));
930 		return -EIO;
931 	}
932 
933 	/* Set MHI to M0 and wait for completion */
934 	mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M0);
935 	write_unlock_irq(&mhi_cntrl->pm_lock);
936 
937 	ret = wait_event_timeout(mhi_cntrl->state_event,
938 				 mhi_cntrl->dev_state == MHI_STATE_M0 ||
939 				 mhi_cntrl->dev_state == MHI_STATE_M2 ||
940 				 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
941 				 msecs_to_jiffies(mhi_cntrl->timeout_ms));
942 
943 	if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
944 		dev_err(dev,
945 			"Did not enter M0 state, MHI state: %s, PM state: %s\n",
946 			TO_MHI_STATE_STR(mhi_cntrl->dev_state),
947 			to_mhi_pm_state_str(mhi_cntrl->pm_state));
948 		return -EIO;
949 	}
950 
951 	return 0;
952 }
953 
mhi_pm_resume(struct mhi_controller * mhi_cntrl)954 int mhi_pm_resume(struct mhi_controller *mhi_cntrl)
955 {
956 	return __mhi_pm_resume(mhi_cntrl, false);
957 }
958 EXPORT_SYMBOL_GPL(mhi_pm_resume);
959 
mhi_pm_resume_force(struct mhi_controller * mhi_cntrl)960 int mhi_pm_resume_force(struct mhi_controller *mhi_cntrl)
961 {
962 	return __mhi_pm_resume(mhi_cntrl, true);
963 }
964 EXPORT_SYMBOL_GPL(mhi_pm_resume_force);
965 
__mhi_device_get_sync(struct mhi_controller * mhi_cntrl)966 int __mhi_device_get_sync(struct mhi_controller *mhi_cntrl)
967 {
968 	int ret;
969 
970 	/* Wake up the device */
971 	read_lock_bh(&mhi_cntrl->pm_lock);
972 	if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
973 		read_unlock_bh(&mhi_cntrl->pm_lock);
974 		return -EIO;
975 	}
976 	mhi_cntrl->wake_get(mhi_cntrl, true);
977 	if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state))
978 		mhi_trigger_resume(mhi_cntrl);
979 	read_unlock_bh(&mhi_cntrl->pm_lock);
980 
981 	ret = wait_event_timeout(mhi_cntrl->state_event,
982 				 mhi_cntrl->pm_state == MHI_PM_M0 ||
983 				 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
984 				 msecs_to_jiffies(mhi_cntrl->timeout_ms));
985 
986 	if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
987 		read_lock_bh(&mhi_cntrl->pm_lock);
988 		mhi_cntrl->wake_put(mhi_cntrl, false);
989 		read_unlock_bh(&mhi_cntrl->pm_lock);
990 		return -EIO;
991 	}
992 
993 	return 0;
994 }
995 
996 /* Assert device wake db */
mhi_assert_dev_wake(struct mhi_controller * mhi_cntrl,bool force)997 static void mhi_assert_dev_wake(struct mhi_controller *mhi_cntrl, bool force)
998 {
999 	unsigned long flags;
1000 
1001 	/*
1002 	 * If force flag is set, then increment the wake count value and
1003 	 * ring wake db
1004 	 */
1005 	if (unlikely(force)) {
1006 		spin_lock_irqsave(&mhi_cntrl->wlock, flags);
1007 		atomic_inc(&mhi_cntrl->dev_wake);
1008 		if (MHI_WAKE_DB_FORCE_SET_VALID(mhi_cntrl->pm_state) &&
1009 		    !mhi_cntrl->wake_set) {
1010 			mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 1);
1011 			mhi_cntrl->wake_set = true;
1012 		}
1013 		spin_unlock_irqrestore(&mhi_cntrl->wlock, flags);
1014 	} else {
1015 		/*
1016 		 * If resources are already requested, then just increment
1017 		 * the wake count value and return
1018 		 */
1019 		if (likely(atomic_add_unless(&mhi_cntrl->dev_wake, 1, 0)))
1020 			return;
1021 
1022 		spin_lock_irqsave(&mhi_cntrl->wlock, flags);
1023 		if ((atomic_inc_return(&mhi_cntrl->dev_wake) == 1) &&
1024 		    MHI_WAKE_DB_SET_VALID(mhi_cntrl->pm_state) &&
1025 		    !mhi_cntrl->wake_set) {
1026 			mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 1);
1027 			mhi_cntrl->wake_set = true;
1028 		}
1029 		spin_unlock_irqrestore(&mhi_cntrl->wlock, flags);
1030 	}
1031 }
1032 
1033 /* De-assert device wake db */
mhi_deassert_dev_wake(struct mhi_controller * mhi_cntrl,bool override)1034 static void mhi_deassert_dev_wake(struct mhi_controller *mhi_cntrl,
1035 				  bool override)
1036 {
1037 	unsigned long flags;
1038 
1039 	/*
1040 	 * Only continue if there is a single resource, else just decrement
1041 	 * and return
1042 	 */
1043 	if (likely(atomic_add_unless(&mhi_cntrl->dev_wake, -1, 1)))
1044 		return;
1045 
1046 	spin_lock_irqsave(&mhi_cntrl->wlock, flags);
1047 	if ((atomic_dec_return(&mhi_cntrl->dev_wake) == 0) &&
1048 	    MHI_WAKE_DB_CLEAR_VALID(mhi_cntrl->pm_state) && !override &&
1049 	    mhi_cntrl->wake_set) {
1050 		mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 0);
1051 		mhi_cntrl->wake_set = false;
1052 	}
1053 	spin_unlock_irqrestore(&mhi_cntrl->wlock, flags);
1054 }
1055 
mhi_async_power_up(struct mhi_controller * mhi_cntrl)1056 int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
1057 {
1058 	enum mhi_state state;
1059 	enum mhi_ee_type current_ee;
1060 	enum dev_st_transition next_state;
1061 	struct device *dev = &mhi_cntrl->mhi_dev->dev;
1062 	u32 interval_us = 25000; /* poll register field every 25 milliseconds */
1063 	int ret;
1064 
1065 	dev_info(dev, "Requested to power ON\n");
1066 
1067 	/* Supply default wake routines if not provided by controller driver */
1068 	if (!mhi_cntrl->wake_get || !mhi_cntrl->wake_put ||
1069 	    !mhi_cntrl->wake_toggle) {
1070 		mhi_cntrl->wake_get = mhi_assert_dev_wake;
1071 		mhi_cntrl->wake_put = mhi_deassert_dev_wake;
1072 		mhi_cntrl->wake_toggle = (mhi_cntrl->db_access & MHI_PM_M2) ?
1073 			mhi_toggle_dev_wake_nop : mhi_toggle_dev_wake;
1074 	}
1075 
1076 	mutex_lock(&mhi_cntrl->pm_mutex);
1077 	mhi_cntrl->pm_state = MHI_PM_DISABLE;
1078 
1079 	/* Setup BHI INTVEC */
1080 	write_lock_irq(&mhi_cntrl->pm_lock);
1081 	mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
1082 	mhi_cntrl->pm_state = MHI_PM_POR;
1083 	mhi_cntrl->ee = MHI_EE_MAX;
1084 	current_ee = mhi_get_exec_env(mhi_cntrl);
1085 	write_unlock_irq(&mhi_cntrl->pm_lock);
1086 
1087 	/* Confirm that the device is in valid exec env */
1088 	if (!MHI_IN_PBL(current_ee) && current_ee != MHI_EE_AMSS) {
1089 		dev_err(dev, "%s is not a valid EE for power on\n",
1090 			TO_MHI_EXEC_STR(current_ee));
1091 		ret = -EIO;
1092 		goto error_exit;
1093 	}
1094 
1095 	state = mhi_get_mhi_state(mhi_cntrl);
1096 	dev_dbg(dev, "Attempting power on with EE: %s, state: %s\n",
1097 		TO_MHI_EXEC_STR(current_ee), TO_MHI_STATE_STR(state));
1098 
1099 	if (state == MHI_STATE_SYS_ERR) {
1100 		mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
1101 		ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
1102 				 MHICTRL_RESET_MASK, MHICTRL_RESET_SHIFT, 0,
1103 				 interval_us);
1104 		if (ret) {
1105 			dev_info(dev, "Failed to reset MHI due to syserr state\n");
1106 			goto error_exit;
1107 		}
1108 
1109 		/*
1110 		 * device cleares INTVEC as part of RESET processing,
1111 		 * re-program it
1112 		 */
1113 		mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);
1114 	}
1115 
1116 	ret = mhi_init_irq_setup(mhi_cntrl);
1117 	if (ret)
1118 		goto error_exit;
1119 
1120 	/* Transition to next state */
1121 	next_state = MHI_IN_PBL(current_ee) ?
1122 		DEV_ST_TRANSITION_PBL : DEV_ST_TRANSITION_READY;
1123 
1124 	mhi_queue_state_transition(mhi_cntrl, next_state);
1125 
1126 	mutex_unlock(&mhi_cntrl->pm_mutex);
1127 
1128 	dev_info(dev, "Power on setup success\n");
1129 
1130 	return 0;
1131 
1132 error_exit:
1133 	mhi_cntrl->pm_state = MHI_PM_DISABLE;
1134 	mutex_unlock(&mhi_cntrl->pm_mutex);
1135 
1136 	return ret;
1137 }
1138 EXPORT_SYMBOL_GPL(mhi_async_power_up);
1139 
mhi_power_down(struct mhi_controller * mhi_cntrl,bool graceful)1140 void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful)
1141 {
1142 	enum mhi_pm_state cur_state, transition_state;
1143 	struct device *dev = &mhi_cntrl->mhi_dev->dev;
1144 
1145 	mutex_lock(&mhi_cntrl->pm_mutex);
1146 	write_lock_irq(&mhi_cntrl->pm_lock);
1147 	cur_state = mhi_cntrl->pm_state;
1148 	if (cur_state == MHI_PM_DISABLE) {
1149 		write_unlock_irq(&mhi_cntrl->pm_lock);
1150 		mutex_unlock(&mhi_cntrl->pm_mutex);
1151 		return; /* Already powered down */
1152 	}
1153 
1154 	/* If it's not a graceful shutdown, force MHI to linkdown state */
1155 	transition_state = (graceful) ? MHI_PM_SHUTDOWN_PROCESS :
1156 			   MHI_PM_LD_ERR_FATAL_DETECT;
1157 
1158 	cur_state = mhi_tryset_pm_state(mhi_cntrl, transition_state);
1159 	if (cur_state != transition_state) {
1160 		dev_err(dev, "Failed to move to state: %s from: %s\n",
1161 			to_mhi_pm_state_str(transition_state),
1162 			to_mhi_pm_state_str(mhi_cntrl->pm_state));
1163 		/* Force link down or error fatal detected state */
1164 		mhi_cntrl->pm_state = MHI_PM_LD_ERR_FATAL_DETECT;
1165 	}
1166 
1167 	/* mark device inactive to avoid any further host processing */
1168 	mhi_cntrl->ee = MHI_EE_DISABLE_TRANSITION;
1169 	mhi_cntrl->dev_state = MHI_STATE_RESET;
1170 
1171 	wake_up_all(&mhi_cntrl->state_event);
1172 
1173 	write_unlock_irq(&mhi_cntrl->pm_lock);
1174 	mutex_unlock(&mhi_cntrl->pm_mutex);
1175 
1176 	mhi_queue_state_transition(mhi_cntrl, DEV_ST_TRANSITION_DISABLE);
1177 
1178 	/* Wait for shutdown to complete */
1179 	flush_work(&mhi_cntrl->st_worker);
1180 
1181 	free_irq(mhi_cntrl->irq[0], mhi_cntrl);
1182 }
1183 EXPORT_SYMBOL_GPL(mhi_power_down);
1184 
mhi_sync_power_up(struct mhi_controller * mhi_cntrl)1185 int mhi_sync_power_up(struct mhi_controller *mhi_cntrl)
1186 {
1187 	int ret = mhi_async_power_up(mhi_cntrl);
1188 
1189 	if (ret)
1190 		return ret;
1191 
1192 	wait_event_timeout(mhi_cntrl->state_event,
1193 			   MHI_IN_MISSION_MODE(mhi_cntrl->ee) ||
1194 			   MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
1195 			   msecs_to_jiffies(mhi_cntrl->timeout_ms));
1196 
1197 	ret = (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) ? 0 : -ETIMEDOUT;
1198 	if (ret)
1199 		mhi_power_down(mhi_cntrl, false);
1200 
1201 	return ret;
1202 }
1203 EXPORT_SYMBOL(mhi_sync_power_up);
1204 
mhi_force_rddm_mode(struct mhi_controller * mhi_cntrl)1205 int mhi_force_rddm_mode(struct mhi_controller *mhi_cntrl)
1206 {
1207 	struct device *dev = &mhi_cntrl->mhi_dev->dev;
1208 	int ret;
1209 
1210 	/* Check if device is already in RDDM */
1211 	if (mhi_cntrl->ee == MHI_EE_RDDM)
1212 		return 0;
1213 
1214 	dev_dbg(dev, "Triggering SYS_ERR to force RDDM state\n");
1215 	mhi_set_mhi_state(mhi_cntrl, MHI_STATE_SYS_ERR);
1216 
1217 	/* Wait for RDDM event */
1218 	ret = wait_event_timeout(mhi_cntrl->state_event,
1219 				 mhi_cntrl->ee == MHI_EE_RDDM,
1220 				 msecs_to_jiffies(mhi_cntrl->timeout_ms));
1221 	ret = ret ? 0 : -EIO;
1222 
1223 	return ret;
1224 }
1225 EXPORT_SYMBOL_GPL(mhi_force_rddm_mode);
1226 
mhi_device_get(struct mhi_device * mhi_dev)1227 void mhi_device_get(struct mhi_device *mhi_dev)
1228 {
1229 	struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1230 
1231 	mhi_dev->dev_wake++;
1232 	read_lock_bh(&mhi_cntrl->pm_lock);
1233 	if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state))
1234 		mhi_trigger_resume(mhi_cntrl);
1235 
1236 	mhi_cntrl->wake_get(mhi_cntrl, true);
1237 	read_unlock_bh(&mhi_cntrl->pm_lock);
1238 }
1239 EXPORT_SYMBOL_GPL(mhi_device_get);
1240 
mhi_device_get_sync(struct mhi_device * mhi_dev)1241 int mhi_device_get_sync(struct mhi_device *mhi_dev)
1242 {
1243 	struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1244 	int ret;
1245 
1246 	ret = __mhi_device_get_sync(mhi_cntrl);
1247 	if (!ret)
1248 		mhi_dev->dev_wake++;
1249 
1250 	return ret;
1251 }
1252 EXPORT_SYMBOL_GPL(mhi_device_get_sync);
1253 
mhi_device_put(struct mhi_device * mhi_dev)1254 void mhi_device_put(struct mhi_device *mhi_dev)
1255 {
1256 	struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
1257 
1258 	mhi_dev->dev_wake--;
1259 	read_lock_bh(&mhi_cntrl->pm_lock);
1260 	if (MHI_PM_IN_SUSPEND_STATE(mhi_cntrl->pm_state))
1261 		mhi_trigger_resume(mhi_cntrl);
1262 
1263 	mhi_cntrl->wake_put(mhi_cntrl, false);
1264 	read_unlock_bh(&mhi_cntrl->pm_lock);
1265 }
1266 EXPORT_SYMBOL_GPL(mhi_device_put);
1267