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1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #include <linux/mlx5/port.h>
34 #include "mlx5_core.h"
35 
mlx5_core_access_reg(struct mlx5_core_dev * dev,void * data_in,int size_in,void * data_out,int size_out,u16 reg_id,int arg,int write)36 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
37 			 int size_in, void *data_out, int size_out,
38 			 u16 reg_id, int arg, int write)
39 {
40 	int outlen = MLX5_ST_SZ_BYTES(access_register_out) + size_out;
41 	int inlen = MLX5_ST_SZ_BYTES(access_register_in) + size_in;
42 	int err = -ENOMEM;
43 	u32 *out = NULL;
44 	u32 *in = NULL;
45 	void *data;
46 
47 	in = kvzalloc(inlen, GFP_KERNEL);
48 	out = kvzalloc(outlen, GFP_KERNEL);
49 	if (!in || !out)
50 		goto out;
51 
52 	data = MLX5_ADDR_OF(access_register_in, in, register_data);
53 	memcpy(data, data_in, size_in);
54 
55 	MLX5_SET(access_register_in, in, opcode, MLX5_CMD_OP_ACCESS_REG);
56 	MLX5_SET(access_register_in, in, op_mod, !write);
57 	MLX5_SET(access_register_in, in, argument, arg);
58 	MLX5_SET(access_register_in, in, register_id, reg_id);
59 
60 	err = mlx5_cmd_exec(dev, in, inlen, out, outlen);
61 	if (err)
62 		goto out;
63 
64 	data = MLX5_ADDR_OF(access_register_out, out, register_data);
65 	memcpy(data_out, data, size_out);
66 
67 out:
68 	kvfree(out);
69 	kvfree(in);
70 	return err;
71 }
72 EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
73 
mlx5_query_pcam_reg(struct mlx5_core_dev * dev,u32 * pcam,u8 feature_group,u8 access_reg_group)74 int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
75 			u8 access_reg_group)
76 {
77 	u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {0};
78 	int sz = MLX5_ST_SZ_BYTES(pcam_reg);
79 
80 	MLX5_SET(pcam_reg, in, feature_group, feature_group);
81 	MLX5_SET(pcam_reg, in, access_reg_group, access_reg_group);
82 
83 	return mlx5_core_access_reg(dev, in, sz, pcam, sz, MLX5_REG_PCAM, 0, 0);
84 }
85 
mlx5_query_mcam_reg(struct mlx5_core_dev * dev,u32 * mcam,u8 feature_group,u8 access_reg_group)86 int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcam, u8 feature_group,
87 			u8 access_reg_group)
88 {
89 	u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {0};
90 	int sz = MLX5_ST_SZ_BYTES(mcam_reg);
91 
92 	MLX5_SET(mcam_reg, in, feature_group, feature_group);
93 	MLX5_SET(mcam_reg, in, access_reg_group, access_reg_group);
94 
95 	return mlx5_core_access_reg(dev, in, sz, mcam, sz, MLX5_REG_MCAM, 0, 0);
96 }
97 
mlx5_query_qcam_reg(struct mlx5_core_dev * mdev,u32 * qcam,u8 feature_group,u8 access_reg_group)98 int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
99 			u8 feature_group, u8 access_reg_group)
100 {
101 	u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {};
102 	int sz = MLX5_ST_SZ_BYTES(qcam_reg);
103 
104 	MLX5_SET(qcam_reg, in, feature_group, feature_group);
105 	MLX5_SET(qcam_reg, in, access_reg_group, access_reg_group);
106 
107 	return mlx5_core_access_reg(mdev, in, sz, qcam, sz, MLX5_REG_QCAM, 0, 0);
108 }
109 
110 struct mlx5_reg_pcap {
111 	u8			rsvd0;
112 	u8			port_num;
113 	u8			rsvd1[2];
114 	__be32			caps_127_96;
115 	__be32			caps_95_64;
116 	__be32			caps_63_32;
117 	__be32			caps_31_0;
118 };
119 
mlx5_set_port_caps(struct mlx5_core_dev * dev,u8 port_num,u32 caps)120 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
121 {
122 	struct mlx5_reg_pcap in;
123 	struct mlx5_reg_pcap out;
124 
125 	memset(&in, 0, sizeof(in));
126 	in.caps_127_96 = cpu_to_be32(caps);
127 	in.port_num = port_num;
128 
129 	return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
130 				    sizeof(out), MLX5_REG_PCAP, 0, 1);
131 }
132 EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
133 
mlx5_query_port_ptys(struct mlx5_core_dev * dev,u32 * ptys,int ptys_size,int proto_mask,u8 local_port)134 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
135 			 int ptys_size, int proto_mask, u8 local_port)
136 {
137 	u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0};
138 
139 	MLX5_SET(ptys_reg, in, local_port, local_port);
140 	MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
141 	return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
142 				    ptys_size, MLX5_REG_PTYS, 0, 0);
143 }
144 EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);
145 
mlx5_set_port_beacon(struct mlx5_core_dev * dev,u16 beacon_duration)146 int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration)
147 {
148 	u32 in[MLX5_ST_SZ_DW(mlcr_reg)]  = {0};
149 	u32 out[MLX5_ST_SZ_DW(mlcr_reg)];
150 
151 	MLX5_SET(mlcr_reg, in, local_port, 1);
152 	MLX5_SET(mlcr_reg, in, beacon_duration, beacon_duration);
153 	return mlx5_core_access_reg(dev, in, sizeof(in), out,
154 				    sizeof(out), MLX5_REG_MLCR, 0, 1);
155 }
156 
mlx5_query_ib_port_oper(struct mlx5_core_dev * dev,u16 * link_width_oper,u16 * proto_oper,u8 local_port)157 int mlx5_query_ib_port_oper(struct mlx5_core_dev *dev, u16 *link_width_oper,
158 			    u16 *proto_oper, u8 local_port)
159 {
160 	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
161 	int err;
162 
163 	err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB,
164 				   local_port);
165 	if (err)
166 		return err;
167 
168 	*link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);
169 	*proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);
170 
171 	return 0;
172 }
173 EXPORT_SYMBOL(mlx5_query_ib_port_oper);
174 
175 /* This function should be used after setting a port register only */
mlx5_toggle_port_link(struct mlx5_core_dev * dev)176 void mlx5_toggle_port_link(struct mlx5_core_dev *dev)
177 {
178 	enum mlx5_port_status ps;
179 
180 	mlx5_query_port_admin_status(dev, &ps);
181 	mlx5_set_port_admin_status(dev, MLX5_PORT_DOWN);
182 	if (ps == MLX5_PORT_UP)
183 		mlx5_set_port_admin_status(dev, MLX5_PORT_UP);
184 }
185 EXPORT_SYMBOL_GPL(mlx5_toggle_port_link);
186 
mlx5_set_port_admin_status(struct mlx5_core_dev * dev,enum mlx5_port_status status)187 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
188 			       enum mlx5_port_status status)
189 {
190 	u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
191 	u32 out[MLX5_ST_SZ_DW(paos_reg)];
192 
193 	MLX5_SET(paos_reg, in, local_port, 1);
194 	MLX5_SET(paos_reg, in, admin_status, status);
195 	MLX5_SET(paos_reg, in, ase, 1);
196 	return mlx5_core_access_reg(dev, in, sizeof(in), out,
197 				    sizeof(out), MLX5_REG_PAOS, 0, 1);
198 }
199 EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status);
200 
mlx5_query_port_admin_status(struct mlx5_core_dev * dev,enum mlx5_port_status * status)201 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
202 				 enum mlx5_port_status *status)
203 {
204 	u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
205 	u32 out[MLX5_ST_SZ_DW(paos_reg)];
206 	int err;
207 
208 	MLX5_SET(paos_reg, in, local_port, 1);
209 	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
210 				   sizeof(out), MLX5_REG_PAOS, 0, 0);
211 	if (err)
212 		return err;
213 	*status = MLX5_GET(paos_reg, out, admin_status);
214 	return 0;
215 }
216 EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);
217 
mlx5_query_port_mtu(struct mlx5_core_dev * dev,u16 * admin_mtu,u16 * max_mtu,u16 * oper_mtu,u8 port)218 static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, u16 *admin_mtu,
219 				u16 *max_mtu, u16 *oper_mtu, u8 port)
220 {
221 	u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
222 	u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
223 
224 	MLX5_SET(pmtu_reg, in, local_port, port);
225 	mlx5_core_access_reg(dev, in, sizeof(in), out,
226 			     sizeof(out), MLX5_REG_PMTU, 0, 0);
227 
228 	if (max_mtu)
229 		*max_mtu  = MLX5_GET(pmtu_reg, out, max_mtu);
230 	if (oper_mtu)
231 		*oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
232 	if (admin_mtu)
233 		*admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
234 }
235 
mlx5_set_port_mtu(struct mlx5_core_dev * dev,u16 mtu,u8 port)236 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port)
237 {
238 	u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
239 	u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
240 
241 	MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
242 	MLX5_SET(pmtu_reg, in, local_port, port);
243 	return mlx5_core_access_reg(dev, in, sizeof(in), out,
244 				   sizeof(out), MLX5_REG_PMTU, 0, 1);
245 }
246 EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
247 
mlx5_query_port_max_mtu(struct mlx5_core_dev * dev,u16 * max_mtu,u8 port)248 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu,
249 			     u8 port)
250 {
251 	mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
252 }
253 EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
254 
mlx5_query_port_oper_mtu(struct mlx5_core_dev * dev,u16 * oper_mtu,u8 port)255 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu,
256 			      u8 port)
257 {
258 	mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);
259 }
260 EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);
261 
mlx5_query_module_num(struct mlx5_core_dev * dev,int * module_num)262 static int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num)
263 {
264 	u32 in[MLX5_ST_SZ_DW(pmlp_reg)] = {0};
265 	u32 out[MLX5_ST_SZ_DW(pmlp_reg)];
266 	int module_mapping;
267 	int err;
268 
269 	MLX5_SET(pmlp_reg, in, local_port, 1);
270 	err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
271 				   MLX5_REG_PMLP, 0, 0);
272 	if (err)
273 		return err;
274 
275 	module_mapping = MLX5_GET(pmlp_reg, out, lane0_module_mapping);
276 	*module_num = module_mapping & MLX5_EEPROM_IDENTIFIER_BYTE_MASK;
277 
278 	return 0;
279 }
280 
mlx5_query_module_id(struct mlx5_core_dev * dev,int module_num,u8 * module_id)281 static int mlx5_query_module_id(struct mlx5_core_dev *dev, int module_num,
282 				u8 *module_id)
283 {
284 	u32 in[MLX5_ST_SZ_DW(mcia_reg)] = {};
285 	u32 out[MLX5_ST_SZ_DW(mcia_reg)];
286 	int err, status;
287 	u8 *ptr;
288 
289 	MLX5_SET(mcia_reg, in, i2c_device_address, MLX5_I2C_ADDR_LOW);
290 	MLX5_SET(mcia_reg, in, module, module_num);
291 	MLX5_SET(mcia_reg, in, device_address, 0);
292 	MLX5_SET(mcia_reg, in, page_number, 0);
293 	MLX5_SET(mcia_reg, in, size, 1);
294 	MLX5_SET(mcia_reg, in, l, 0);
295 
296 	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
297 				   sizeof(out), MLX5_REG_MCIA, 0, 0);
298 	if (err)
299 		return err;
300 
301 	status = MLX5_GET(mcia_reg, out, status);
302 	if (status) {
303 		mlx5_core_err(dev, "query_mcia_reg failed: status: 0x%x\n",
304 			      status);
305 		return -EIO;
306 	}
307 	ptr = MLX5_ADDR_OF(mcia_reg, out, dword_0);
308 
309 	*module_id = ptr[0];
310 
311 	return 0;
312 }
313 
mlx5_qsfp_eeprom_page(u16 offset)314 static int mlx5_qsfp_eeprom_page(u16 offset)
315 {
316 	if (offset < MLX5_EEPROM_PAGE_LENGTH)
317 		/* Addresses between 0-255 - page 00 */
318 		return 0;
319 
320 	/* Addresses between 256 - 639 belongs to pages 01, 02 and 03
321 	 * For example, offset = 400 belongs to page 02:
322 	 * 1 + ((400 - 256)/128) = 2
323 	 */
324 	return 1 + ((offset - MLX5_EEPROM_PAGE_LENGTH) /
325 		    MLX5_EEPROM_HIGH_PAGE_LENGTH);
326 }
327 
mlx5_qsfp_eeprom_high_page_offset(int page_num)328 static int mlx5_qsfp_eeprom_high_page_offset(int page_num)
329 {
330 	if (!page_num) /* Page 0 always start from low page */
331 		return 0;
332 
333 	/* High page */
334 	return page_num * MLX5_EEPROM_HIGH_PAGE_LENGTH;
335 }
336 
mlx5_qsfp_eeprom_params_set(u16 * i2c_addr,int * page_num,u16 * offset)337 static void mlx5_qsfp_eeprom_params_set(u16 *i2c_addr, int *page_num, u16 *offset)
338 {
339 	*i2c_addr = MLX5_I2C_ADDR_LOW;
340 	*page_num = mlx5_qsfp_eeprom_page(*offset);
341 	*offset -=  mlx5_qsfp_eeprom_high_page_offset(*page_num);
342 }
343 
mlx5_sfp_eeprom_params_set(u16 * i2c_addr,int * page_num,u16 * offset)344 static void mlx5_sfp_eeprom_params_set(u16 *i2c_addr, int *page_num, u16 *offset)
345 {
346 	*i2c_addr = MLX5_I2C_ADDR_LOW;
347 	*page_num = 0;
348 
349 	if (*offset < MLX5_EEPROM_PAGE_LENGTH)
350 		return;
351 
352 	*i2c_addr = MLX5_I2C_ADDR_HIGH;
353 	*offset -= MLX5_EEPROM_PAGE_LENGTH;
354 }
355 
mlx5_query_mcia(struct mlx5_core_dev * dev,struct mlx5_module_eeprom_query_params * params,u8 * data)356 static int mlx5_query_mcia(struct mlx5_core_dev *dev,
357 			   struct mlx5_module_eeprom_query_params *params, u8 *data)
358 {
359 	u32 in[MLX5_ST_SZ_DW(mcia_reg)] = {};
360 	u32 out[MLX5_ST_SZ_DW(mcia_reg)];
361 	int status, err;
362 	void *ptr;
363 	u16 size;
364 
365 	size = min_t(int, params->size, MLX5_EEPROM_MAX_BYTES);
366 
367 	MLX5_SET(mcia_reg, in, l, 0);
368 	MLX5_SET(mcia_reg, in, size, size);
369 	MLX5_SET(mcia_reg, in, module, params->module_number);
370 	MLX5_SET(mcia_reg, in, device_address, params->offset);
371 	MLX5_SET(mcia_reg, in, page_number, params->page);
372 	MLX5_SET(mcia_reg, in, i2c_device_address, params->i2c_address);
373 
374 	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
375 				   sizeof(out), MLX5_REG_MCIA, 0, 0);
376 	if (err)
377 		return err;
378 
379 	status = MLX5_GET(mcia_reg, out, status);
380 	if (status) {
381 		mlx5_core_err(dev, "query_mcia_reg failed: status: 0x%x\n",
382 			      status);
383 		return -EIO;
384 	}
385 
386 	ptr = MLX5_ADDR_OF(mcia_reg, out, dword_0);
387 	memcpy(data, ptr, size);
388 
389 	return size;
390 }
391 
mlx5_query_module_eeprom(struct mlx5_core_dev * dev,u16 offset,u16 size,u8 * data)392 int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
393 			     u16 offset, u16 size, u8 *data)
394 {
395 	struct mlx5_module_eeprom_query_params query = {0};
396 	u8 module_id;
397 	int err;
398 
399 	err = mlx5_query_module_num(dev, &query.module_number);
400 	if (err)
401 		return err;
402 
403 	err = mlx5_query_module_id(dev, query.module_number, &module_id);
404 	if (err)
405 		return err;
406 
407 	switch (module_id) {
408 	case MLX5_MODULE_ID_SFP:
409 		mlx5_sfp_eeprom_params_set(&query.i2c_address, &query.page, &offset);
410 		break;
411 	case MLX5_MODULE_ID_QSFP:
412 	case MLX5_MODULE_ID_QSFP_PLUS:
413 	case MLX5_MODULE_ID_QSFP28:
414 		mlx5_qsfp_eeprom_params_set(&query.i2c_address, &query.page, &offset);
415 		break;
416 	default:
417 		mlx5_core_err(dev, "Module ID not recognized: 0x%x\n", module_id);
418 		return -EINVAL;
419 	}
420 
421 	if (offset + size > MLX5_EEPROM_PAGE_LENGTH)
422 		/* Cross pages read, read until offset 256 in low page */
423 		size = MLX5_EEPROM_PAGE_LENGTH - offset;
424 
425 	query.size = size;
426 	query.offset = offset;
427 
428 	return mlx5_query_mcia(dev, &query, data);
429 }
430 EXPORT_SYMBOL_GPL(mlx5_query_module_eeprom);
431 
mlx5_query_module_eeprom_by_page(struct mlx5_core_dev * dev,struct mlx5_module_eeprom_query_params * params,u8 * data)432 int mlx5_query_module_eeprom_by_page(struct mlx5_core_dev *dev,
433 				     struct mlx5_module_eeprom_query_params *params,
434 				     u8 *data)
435 {
436 	int err;
437 
438 	err = mlx5_query_module_num(dev, &params->module_number);
439 	if (err)
440 		return err;
441 
442 	if (params->i2c_address != MLX5_I2C_ADDR_HIGH &&
443 	    params->i2c_address != MLX5_I2C_ADDR_LOW) {
444 		mlx5_core_err(dev, "I2C address not recognized: 0x%x\n", params->i2c_address);
445 		return -EINVAL;
446 	}
447 
448 	return mlx5_query_mcia(dev, params, data);
449 }
450 EXPORT_SYMBOL_GPL(mlx5_query_module_eeprom_by_page);
451 
mlx5_query_port_pvlc(struct mlx5_core_dev * dev,u32 * pvlc,int pvlc_size,u8 local_port)452 static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc,
453 				int pvlc_size,  u8 local_port)
454 {
455 	u32 in[MLX5_ST_SZ_DW(pvlc_reg)] = {0};
456 
457 	MLX5_SET(pvlc_reg, in, local_port, local_port);
458 	return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
459 				    pvlc_size, MLX5_REG_PVLC, 0, 0);
460 }
461 
mlx5_query_port_vl_hw_cap(struct mlx5_core_dev * dev,u8 * vl_hw_cap,u8 local_port)462 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
463 			      u8 *vl_hw_cap, u8 local_port)
464 {
465 	u32 out[MLX5_ST_SZ_DW(pvlc_reg)];
466 	int err;
467 
468 	err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port);
469 	if (err)
470 		return err;
471 
472 	*vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);
473 
474 	return 0;
475 }
476 EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap);
477 
mlx5_core_query_ib_ppcnt(struct mlx5_core_dev * dev,u8 port_num,void * out,size_t sz)478 int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
479 			     u8 port_num, void *out, size_t sz)
480 {
481 	u32 *in;
482 	int err;
483 
484 	in  = kvzalloc(sz, GFP_KERNEL);
485 	if (!in) {
486 		err = -ENOMEM;
487 		return err;
488 	}
489 
490 	MLX5_SET(ppcnt_reg, in, local_port, port_num);
491 
492 	MLX5_SET(ppcnt_reg, in, grp, MLX5_INFINIBAND_PORT_COUNTERS_GROUP);
493 	err = mlx5_core_access_reg(dev, in, sz, out,
494 				   sz, MLX5_REG_PPCNT, 0, 0);
495 
496 	kvfree(in);
497 	return err;
498 }
499 EXPORT_SYMBOL_GPL(mlx5_core_query_ib_ppcnt);
500 
mlx5_query_pfcc_reg(struct mlx5_core_dev * dev,u32 * out,u32 out_size)501 static int mlx5_query_pfcc_reg(struct mlx5_core_dev *dev, u32 *out,
502 			       u32 out_size)
503 {
504 	u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
505 
506 	MLX5_SET(pfcc_reg, in, local_port, 1);
507 
508 	return mlx5_core_access_reg(dev, in, sizeof(in), out,
509 				    out_size, MLX5_REG_PFCC, 0, 0);
510 }
511 
mlx5_set_port_pause(struct mlx5_core_dev * dev,u32 rx_pause,u32 tx_pause)512 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause)
513 {
514 	u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
515 	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
516 
517 	MLX5_SET(pfcc_reg, in, local_port, 1);
518 	MLX5_SET(pfcc_reg, in, pptx, tx_pause);
519 	MLX5_SET(pfcc_reg, in, pprx, rx_pause);
520 
521 	return mlx5_core_access_reg(dev, in, sizeof(in), out,
522 				    sizeof(out), MLX5_REG_PFCC, 0, 1);
523 }
524 EXPORT_SYMBOL_GPL(mlx5_set_port_pause);
525 
mlx5_query_port_pause(struct mlx5_core_dev * dev,u32 * rx_pause,u32 * tx_pause)526 int mlx5_query_port_pause(struct mlx5_core_dev *dev,
527 			  u32 *rx_pause, u32 *tx_pause)
528 {
529 	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
530 	int err;
531 
532 	err = mlx5_query_pfcc_reg(dev, out, sizeof(out));
533 	if (err)
534 		return err;
535 
536 	if (rx_pause)
537 		*rx_pause = MLX5_GET(pfcc_reg, out, pprx);
538 
539 	if (tx_pause)
540 		*tx_pause = MLX5_GET(pfcc_reg, out, pptx);
541 
542 	return 0;
543 }
544 EXPORT_SYMBOL_GPL(mlx5_query_port_pause);
545 
mlx5_set_port_stall_watermark(struct mlx5_core_dev * dev,u16 stall_critical_watermark,u16 stall_minor_watermark)546 int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev,
547 				  u16 stall_critical_watermark,
548 				  u16 stall_minor_watermark)
549 {
550 	u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
551 	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
552 
553 	MLX5_SET(pfcc_reg, in, local_port, 1);
554 	MLX5_SET(pfcc_reg, in, pptx_mask_n, 1);
555 	MLX5_SET(pfcc_reg, in, pprx_mask_n, 1);
556 	MLX5_SET(pfcc_reg, in, ppan_mask_n, 1);
557 	MLX5_SET(pfcc_reg, in, critical_stall_mask, 1);
558 	MLX5_SET(pfcc_reg, in, minor_stall_mask, 1);
559 	MLX5_SET(pfcc_reg, in, device_stall_critical_watermark,
560 		 stall_critical_watermark);
561 	MLX5_SET(pfcc_reg, in, device_stall_minor_watermark, stall_minor_watermark);
562 
563 	return mlx5_core_access_reg(dev, in, sizeof(in), out,
564 				    sizeof(out), MLX5_REG_PFCC, 0, 1);
565 }
566 
mlx5_query_port_stall_watermark(struct mlx5_core_dev * dev,u16 * stall_critical_watermark,u16 * stall_minor_watermark)567 int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev,
568 				    u16 *stall_critical_watermark,
569 				    u16 *stall_minor_watermark)
570 {
571 	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
572 	int err;
573 
574 	err = mlx5_query_pfcc_reg(dev, out, sizeof(out));
575 	if (err)
576 		return err;
577 
578 	if (stall_critical_watermark)
579 		*stall_critical_watermark = MLX5_GET(pfcc_reg, out,
580 						     device_stall_critical_watermark);
581 
582 	if (stall_minor_watermark)
583 		*stall_minor_watermark = MLX5_GET(pfcc_reg, out,
584 						  device_stall_minor_watermark);
585 
586 	return 0;
587 }
588 
mlx5_set_port_pfc(struct mlx5_core_dev * dev,u8 pfc_en_tx,u8 pfc_en_rx)589 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx)
590 {
591 	u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
592 	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
593 
594 	MLX5_SET(pfcc_reg, in, local_port, 1);
595 	MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
596 	MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx);
597 	MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx);
598 	MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx);
599 
600 	return mlx5_core_access_reg(dev, in, sizeof(in), out,
601 				    sizeof(out), MLX5_REG_PFCC, 0, 1);
602 }
603 EXPORT_SYMBOL_GPL(mlx5_set_port_pfc);
604 
mlx5_query_port_pfc(struct mlx5_core_dev * dev,u8 * pfc_en_tx,u8 * pfc_en_rx)605 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx)
606 {
607 	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
608 	int err;
609 
610 	err = mlx5_query_pfcc_reg(dev, out, sizeof(out));
611 	if (err)
612 		return err;
613 
614 	if (pfc_en_tx)
615 		*pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx);
616 
617 	if (pfc_en_rx)
618 		*pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx);
619 
620 	return 0;
621 }
622 EXPORT_SYMBOL_GPL(mlx5_query_port_pfc);
623 
mlx5_max_tc(struct mlx5_core_dev * mdev)624 int mlx5_max_tc(struct mlx5_core_dev *mdev)
625 {
626 	u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8;
627 
628 	return num_tc - 1;
629 }
630 
mlx5_query_port_dcbx_param(struct mlx5_core_dev * mdev,u32 * out)631 int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out)
632 {
633 	u32 in[MLX5_ST_SZ_DW(dcbx_param)] = {0};
634 
635 	MLX5_SET(dcbx_param, in, port_number, 1);
636 
637 	return  mlx5_core_access_reg(mdev, in, sizeof(in), out,
638 				    sizeof(in), MLX5_REG_DCBX_PARAM, 0, 0);
639 }
640 
mlx5_set_port_dcbx_param(struct mlx5_core_dev * mdev,u32 * in)641 int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in)
642 {
643 	u32 out[MLX5_ST_SZ_DW(dcbx_param)];
644 
645 	MLX5_SET(dcbx_param, in, port_number, 1);
646 
647 	return mlx5_core_access_reg(mdev, in, sizeof(out), out,
648 				    sizeof(out), MLX5_REG_DCBX_PARAM, 0, 1);
649 }
650 
mlx5_set_port_prio_tc(struct mlx5_core_dev * mdev,u8 * prio_tc)651 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc)
652 {
653 	u32 in[MLX5_ST_SZ_DW(qtct_reg)] = {0};
654 	u32 out[MLX5_ST_SZ_DW(qtct_reg)];
655 	int err;
656 	int i;
657 
658 	for (i = 0; i < 8; i++) {
659 		if (prio_tc[i] > mlx5_max_tc(mdev))
660 			return -EINVAL;
661 
662 		MLX5_SET(qtct_reg, in, prio, i);
663 		MLX5_SET(qtct_reg, in, tclass, prio_tc[i]);
664 
665 		err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
666 					   sizeof(out), MLX5_REG_QTCT, 0, 1);
667 		if (err)
668 			return err;
669 	}
670 
671 	return 0;
672 }
673 EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc);
674 
mlx5_query_port_prio_tc(struct mlx5_core_dev * mdev,u8 prio,u8 * tc)675 int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
676 			    u8 prio, u8 *tc)
677 {
678 	u32 in[MLX5_ST_SZ_DW(qtct_reg)];
679 	u32 out[MLX5_ST_SZ_DW(qtct_reg)];
680 	int err;
681 
682 	memset(in, 0, sizeof(in));
683 	memset(out, 0, sizeof(out));
684 
685 	MLX5_SET(qtct_reg, in, port_number, 1);
686 	MLX5_SET(qtct_reg, in, prio, prio);
687 
688 	err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
689 				   sizeof(out), MLX5_REG_QTCT, 0, 0);
690 	if (!err)
691 		*tc = MLX5_GET(qtct_reg, out, tclass);
692 
693 	return err;
694 }
695 EXPORT_SYMBOL_GPL(mlx5_query_port_prio_tc);
696 
mlx5_set_port_qetcr_reg(struct mlx5_core_dev * mdev,u32 * in,int inlen)697 static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in,
698 				   int inlen)
699 {
700 	u32 out[MLX5_ST_SZ_DW(qetc_reg)];
701 
702 	if (!MLX5_CAP_GEN(mdev, ets))
703 		return -EOPNOTSUPP;
704 
705 	return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out),
706 				    MLX5_REG_QETCR, 0, 1);
707 }
708 
mlx5_query_port_qetcr_reg(struct mlx5_core_dev * mdev,u32 * out,int outlen)709 static int mlx5_query_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *out,
710 				     int outlen)
711 {
712 	u32 in[MLX5_ST_SZ_DW(qetc_reg)];
713 
714 	if (!MLX5_CAP_GEN(mdev, ets))
715 		return -EOPNOTSUPP;
716 
717 	memset(in, 0, sizeof(in));
718 	return mlx5_core_access_reg(mdev, in, sizeof(in), out, outlen,
719 				    MLX5_REG_QETCR, 0, 0);
720 }
721 
mlx5_set_port_tc_group(struct mlx5_core_dev * mdev,u8 * tc_group)722 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group)
723 {
724 	u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
725 	int i;
726 
727 	for (i = 0; i <= mlx5_max_tc(mdev); i++) {
728 		MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1);
729 		MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]);
730 	}
731 
732 	return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
733 }
734 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group);
735 
mlx5_query_port_tc_group(struct mlx5_core_dev * mdev,u8 tc,u8 * tc_group)736 int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
737 			     u8 tc, u8 *tc_group)
738 {
739 	u32 out[MLX5_ST_SZ_DW(qetc_reg)];
740 	void *ets_tcn_conf;
741 	int err;
742 
743 	err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
744 	if (err)
745 		return err;
746 
747 	ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out,
748 				    tc_configuration[tc]);
749 
750 	*tc_group = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
751 			     group);
752 
753 	return 0;
754 }
755 EXPORT_SYMBOL_GPL(mlx5_query_port_tc_group);
756 
mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev * mdev,u8 * tc_bw)757 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw)
758 {
759 	u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
760 	int i;
761 
762 	for (i = 0; i <= mlx5_max_tc(mdev); i++) {
763 		MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1);
764 		MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]);
765 	}
766 
767 	return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
768 }
769 EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc);
770 
mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev * mdev,u8 tc,u8 * bw_pct)771 int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev,
772 				u8 tc, u8 *bw_pct)
773 {
774 	u32 out[MLX5_ST_SZ_DW(qetc_reg)];
775 	void *ets_tcn_conf;
776 	int err;
777 
778 	err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
779 	if (err)
780 		return err;
781 
782 	ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out,
783 				    tc_configuration[tc]);
784 
785 	*bw_pct = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
786 			   bw_allocation);
787 
788 	return 0;
789 }
790 EXPORT_SYMBOL_GPL(mlx5_query_port_tc_bw_alloc);
791 
mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev * mdev,u8 * max_bw_value,u8 * max_bw_units)792 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
793 				    u8 *max_bw_value,
794 				    u8 *max_bw_units)
795 {
796 	u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {0};
797 	void *ets_tcn_conf;
798 	int i;
799 
800 	MLX5_SET(qetc_reg, in, port_number, 1);
801 
802 	for (i = 0; i <= mlx5_max_tc(mdev); i++) {
803 		ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, in, tc_configuration[i]);
804 
805 		MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, r, 1);
806 		MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_units,
807 			 max_bw_units[i]);
808 		MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_value,
809 			 max_bw_value[i]);
810 	}
811 
812 	return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
813 }
814 EXPORT_SYMBOL_GPL(mlx5_modify_port_ets_rate_limit);
815 
mlx5_query_port_ets_rate_limit(struct mlx5_core_dev * mdev,u8 * max_bw_value,u8 * max_bw_units)816 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
817 				   u8 *max_bw_value,
818 				   u8 *max_bw_units)
819 {
820 	u32 out[MLX5_ST_SZ_DW(qetc_reg)];
821 	void *ets_tcn_conf;
822 	int err;
823 	int i;
824 
825 	err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
826 	if (err)
827 		return err;
828 
829 	for (i = 0; i <= mlx5_max_tc(mdev); i++) {
830 		ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, tc_configuration[i]);
831 
832 		max_bw_value[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
833 					   max_bw_value);
834 		max_bw_units[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
835 					   max_bw_units);
836 	}
837 
838 	return 0;
839 }
840 EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit);
841 
mlx5_set_port_wol(struct mlx5_core_dev * mdev,u8 wol_mode)842 int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode)
843 {
844 	u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)] = {};
845 
846 	MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL);
847 	MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1);
848 	MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode);
849 	return mlx5_cmd_exec_in(mdev, set_wol_rol, in);
850 }
851 EXPORT_SYMBOL_GPL(mlx5_set_port_wol);
852 
mlx5_query_port_wol(struct mlx5_core_dev * mdev,u8 * wol_mode)853 int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode)
854 {
855 	u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)] = {};
856 	u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)] = {};
857 	int err;
858 
859 	MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL);
860 	err = mlx5_cmd_exec_inout(mdev, query_wol_rol, in, out);
861 	if (!err)
862 		*wol_mode = MLX5_GET(query_wol_rol_out, out, wol_mode);
863 
864 	return err;
865 }
866 EXPORT_SYMBOL_GPL(mlx5_query_port_wol);
867 
mlx5_query_ports_check(struct mlx5_core_dev * mdev,u32 * out,int outlen)868 int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen)
869 {
870 	u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
871 
872 	MLX5_SET(pcmr_reg, in, local_port, 1);
873 	return mlx5_core_access_reg(mdev, in, sizeof(in), out,
874 				    outlen, MLX5_REG_PCMR, 0, 0);
875 }
876 
mlx5_set_ports_check(struct mlx5_core_dev * mdev,u32 * in,int inlen)877 int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen)
878 {
879 	u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
880 
881 	return mlx5_core_access_reg(mdev, in, inlen, out,
882 				    sizeof(out), MLX5_REG_PCMR, 0, 1);
883 }
884 
mlx5_set_port_fcs(struct mlx5_core_dev * mdev,u8 enable)885 int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable)
886 {
887 	u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0};
888 	int err;
889 
890 	err = mlx5_query_ports_check(mdev, in, sizeof(in));
891 	if (err)
892 		return err;
893 	MLX5_SET(pcmr_reg, in, local_port, 1);
894 	MLX5_SET(pcmr_reg, in, fcs_chk, enable);
895 	return mlx5_set_ports_check(mdev, in, sizeof(in));
896 }
897 
mlx5_query_port_fcs(struct mlx5_core_dev * mdev,bool * supported,bool * enabled)898 void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
899 			 bool *enabled)
900 {
901 	u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
902 	/* Default values for FW which do not support MLX5_REG_PCMR */
903 	*supported = false;
904 	*enabled = true;
905 
906 	if (!MLX5_CAP_GEN(mdev, ports_check))
907 		return;
908 
909 	if (mlx5_query_ports_check(mdev, out, sizeof(out)))
910 		return;
911 
912 	*supported = !!(MLX5_GET(pcmr_reg, out, fcs_cap));
913 	*enabled = !!(MLX5_GET(pcmr_reg, out, fcs_chk));
914 }
915 
mlx5_query_mtpps(struct mlx5_core_dev * mdev,u32 * mtpps,u32 mtpps_size)916 int mlx5_query_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)
917 {
918 	u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
919 
920 	return mlx5_core_access_reg(mdev, in, sizeof(in), mtpps,
921 				    mtpps_size, MLX5_REG_MTPPS, 0, 0);
922 }
923 
mlx5_set_mtpps(struct mlx5_core_dev * mdev,u32 * mtpps,u32 mtpps_size)924 int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size)
925 {
926 	u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {0};
927 
928 	return mlx5_core_access_reg(mdev, mtpps, mtpps_size, out,
929 				    sizeof(out), MLX5_REG_MTPPS, 0, 1);
930 }
931 
mlx5_query_mtppse(struct mlx5_core_dev * mdev,u8 pin,u8 * arm,u8 * mode)932 int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode)
933 {
934 	u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
935 	u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
936 	int err = 0;
937 
938 	MLX5_SET(mtppse_reg, in, pin, pin);
939 
940 	err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
941 				   sizeof(out), MLX5_REG_MTPPSE, 0, 0);
942 	if (err)
943 		return err;
944 
945 	*arm = MLX5_GET(mtppse_reg, in, event_arm);
946 	*mode = MLX5_GET(mtppse_reg, in, event_generation_mode);
947 
948 	return err;
949 }
950 
mlx5_set_mtppse(struct mlx5_core_dev * mdev,u8 pin,u8 arm,u8 mode)951 int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode)
952 {
953 	u32 out[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
954 	u32 in[MLX5_ST_SZ_DW(mtppse_reg)] = {0};
955 
956 	MLX5_SET(mtppse_reg, in, pin, pin);
957 	MLX5_SET(mtppse_reg, in, event_arm, arm);
958 	MLX5_SET(mtppse_reg, in, event_generation_mode, mode);
959 
960 	return mlx5_core_access_reg(mdev, in, sizeof(in), out,
961 				    sizeof(out), MLX5_REG_MTPPSE, 0, 1);
962 }
963 
mlx5_set_trust_state(struct mlx5_core_dev * mdev,u8 trust_state)964 int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state)
965 {
966 	u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
967 	u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
968 	int err;
969 
970 	MLX5_SET(qpts_reg, in, local_port, 1);
971 	MLX5_SET(qpts_reg, in, trust_state, trust_state);
972 
973 	err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
974 				   sizeof(out), MLX5_REG_QPTS, 0, 1);
975 	return err;
976 }
977 
mlx5_query_trust_state(struct mlx5_core_dev * mdev,u8 * trust_state)978 int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state)
979 {
980 	u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
981 	u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
982 	int err;
983 
984 	MLX5_SET(qpts_reg, in, local_port, 1);
985 
986 	err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
987 				   sizeof(out), MLX5_REG_QPTS, 0, 0);
988 	if (!err)
989 		*trust_state = MLX5_GET(qpts_reg, out, trust_state);
990 
991 	return err;
992 }
993 
mlx5_set_dscp2prio(struct mlx5_core_dev * mdev,u8 dscp,u8 prio)994 int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio)
995 {
996 	int sz = MLX5_ST_SZ_BYTES(qpdpm_reg);
997 	void *qpdpm_dscp;
998 	void *out;
999 	void *in;
1000 	int err;
1001 
1002 	in = kzalloc(sz, GFP_KERNEL);
1003 	out = kzalloc(sz, GFP_KERNEL);
1004 	if (!in || !out) {
1005 		err = -ENOMEM;
1006 		goto out;
1007 	}
1008 
1009 	MLX5_SET(qpdpm_reg, in, local_port, 1);
1010 	err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
1011 	if (err)
1012 		goto out;
1013 
1014 	memcpy(in, out, sz);
1015 	MLX5_SET(qpdpm_reg, in, local_port, 1);
1016 
1017 	/* Update the corresponding dscp entry */
1018 	qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, in, dscp[dscp]);
1019 	MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, prio, prio);
1020 	MLX5_SET16(qpdpm_dscp_reg, qpdpm_dscp, e, 1);
1021 	err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 1);
1022 
1023 out:
1024 	kfree(in);
1025 	kfree(out);
1026 	return err;
1027 }
1028 
1029 /* dscp2prio[i]: priority that dscp i mapped to */
1030 #define MLX5E_SUPPORTED_DSCP 64
mlx5_query_dscp2prio(struct mlx5_core_dev * mdev,u8 * dscp2prio)1031 int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio)
1032 {
1033 	int sz = MLX5_ST_SZ_BYTES(qpdpm_reg);
1034 	void *qpdpm_dscp;
1035 	void *out;
1036 	void *in;
1037 	int err;
1038 	int i;
1039 
1040 	in = kzalloc(sz, GFP_KERNEL);
1041 	out = kzalloc(sz, GFP_KERNEL);
1042 	if (!in || !out) {
1043 		err = -ENOMEM;
1044 		goto out;
1045 	}
1046 
1047 	MLX5_SET(qpdpm_reg, in, local_port, 1);
1048 	err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_QPDPM, 0, 0);
1049 	if (err)
1050 		goto out;
1051 
1052 	for (i = 0; i < (MLX5E_SUPPORTED_DSCP); i++) {
1053 		qpdpm_dscp = MLX5_ADDR_OF(qpdpm_reg, out, dscp[i]);
1054 		dscp2prio[i] = MLX5_GET16(qpdpm_dscp_reg, qpdpm_dscp, prio);
1055 	}
1056 
1057 out:
1058 	kfree(in);
1059 	kfree(out);
1060 	return err;
1061 }
1062