1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4 * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/irq.h>
9
10 #include "mt76x02.h"
11 #include "mt76x02_mcu.h"
12 #include "trace.h"
13
mt76x02_pre_tbtt_tasklet(struct tasklet_struct * t)14 static void mt76x02_pre_tbtt_tasklet(struct tasklet_struct *t)
15 {
16 struct mt76x02_dev *dev = from_tasklet(dev, t, mt76.pre_tbtt_tasklet);
17 struct mt76_dev *mdev = &dev->mt76;
18 struct mt76_queue *q = dev->mphy.q_tx[MT_TXQ_PSD];
19 struct beacon_bc_data data = {};
20 struct sk_buff *skb;
21 int i;
22
23 if (mt76_hw(dev)->conf.flags & IEEE80211_CONF_OFFCHANNEL)
24 return;
25
26 mt76x02_resync_beacon_timer(dev);
27
28 /* Prevent corrupt transmissions during update */
29 mt76_set(dev, MT_BCN_BYPASS_MASK, 0xffff);
30 dev->beacon_data_count = 0;
31
32 ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev),
33 IEEE80211_IFACE_ITER_RESUME_ALL,
34 mt76x02_update_beacon_iter, dev);
35
36 mt76_wr(dev, MT_BCN_BYPASS_MASK,
37 0xff00 | ~(0xff00 >> dev->beacon_data_count));
38
39 mt76_csa_check(mdev);
40
41 if (mdev->csa_complete)
42 return;
43
44 mt76x02_enqueue_buffered_bc(dev, &data, 8);
45
46 if (!skb_queue_len(&data.q))
47 return;
48
49 for (i = 0; i < ARRAY_SIZE(data.tail); i++) {
50 if (!data.tail[i])
51 continue;
52
53 mt76_skb_set_moredata(data.tail[i], false);
54 }
55
56 spin_lock_bh(&q->lock);
57 while ((skb = __skb_dequeue(&data.q)) != NULL) {
58 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
59 struct ieee80211_vif *vif = info->control.vif;
60 struct mt76x02_vif *mvif = (struct mt76x02_vif *)vif->drv_priv;
61
62 mt76_tx_queue_skb(dev, q, MT_TXQ_PSD, skb, &mvif->group_wcid,
63 NULL);
64 }
65 spin_unlock_bh(&q->lock);
66 }
67
mt76x02e_pre_tbtt_enable(struct mt76x02_dev * dev,bool en)68 static void mt76x02e_pre_tbtt_enable(struct mt76x02_dev *dev, bool en)
69 {
70 if (en)
71 tasklet_enable(&dev->mt76.pre_tbtt_tasklet);
72 else
73 tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
74 }
75
mt76x02e_beacon_enable(struct mt76x02_dev * dev,bool en)76 static void mt76x02e_beacon_enable(struct mt76x02_dev *dev, bool en)
77 {
78 mt76_rmw_field(dev, MT_INT_TIMER_EN, MT_INT_TIMER_EN_PRE_TBTT_EN, en);
79 if (en)
80 mt76x02_irq_enable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
81 else
82 mt76x02_irq_disable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
83 }
84
mt76x02e_init_beacon_config(struct mt76x02_dev * dev)85 void mt76x02e_init_beacon_config(struct mt76x02_dev *dev)
86 {
87 static const struct mt76x02_beacon_ops beacon_ops = {
88 .nslots = 8,
89 .slot_size = 1024,
90 .pre_tbtt_enable = mt76x02e_pre_tbtt_enable,
91 .beacon_enable = mt76x02e_beacon_enable,
92 };
93
94 dev->beacon_ops = &beacon_ops;
95
96 /* Fire a pre-TBTT interrupt 8 ms before TBTT */
97 mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_PRE_TBTT,
98 8 << 4);
99 mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_GP_TIMER,
100 MT_DFS_GP_INTERVAL);
101 mt76_wr(dev, MT_INT_TIMER_EN, 0);
102
103 mt76x02_init_beacon_config(dev);
104 }
105 EXPORT_SYMBOL_GPL(mt76x02e_init_beacon_config);
106
107 static int
mt76x02_init_rx_queue(struct mt76x02_dev * dev,struct mt76_queue * q,int idx,int n_desc,int bufsize)108 mt76x02_init_rx_queue(struct mt76x02_dev *dev, struct mt76_queue *q,
109 int idx, int n_desc, int bufsize)
110 {
111 int err;
112
113 err = mt76_queue_alloc(dev, q, idx, n_desc, bufsize,
114 MT_RX_RING_BASE);
115 if (err < 0)
116 return err;
117
118 mt76x02_irq_enable(dev, MT_INT_RX_DONE(idx));
119
120 return 0;
121 }
122
mt76x02_process_tx_status_fifo(struct mt76x02_dev * dev)123 static void mt76x02_process_tx_status_fifo(struct mt76x02_dev *dev)
124 {
125 struct mt76x02_tx_status stat;
126 u8 update = 1;
127
128 while (kfifo_get(&dev->txstatus_fifo, &stat))
129 mt76x02_send_tx_status(dev, &stat, &update);
130 }
131
mt76x02_tx_worker(struct mt76_worker * w)132 static void mt76x02_tx_worker(struct mt76_worker *w)
133 {
134 struct mt76x02_dev *dev;
135
136 dev = container_of(w, struct mt76x02_dev, mt76.tx_worker);
137
138 mt76x02_mac_poll_tx_status(dev, false);
139 mt76x02_process_tx_status_fifo(dev);
140
141 mt76_txq_schedule_all(&dev->mphy);
142 }
143
mt76x02_poll_tx(struct napi_struct * napi,int budget)144 static int mt76x02_poll_tx(struct napi_struct *napi, int budget)
145 {
146 struct mt76x02_dev *dev = container_of(napi, struct mt76x02_dev,
147 mt76.tx_napi);
148 int i;
149
150 mt76x02_mac_poll_tx_status(dev, false);
151
152 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);
153 for (i = MT_TXQ_PSD; i >= 0; i--)
154 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false);
155
156 if (napi_complete_done(napi, 0))
157 mt76x02_irq_enable(dev, MT_INT_TX_DONE_ALL);
158
159 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);
160 for (i = MT_TXQ_PSD; i >= 0; i--)
161 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], false);
162
163 mt76_worker_schedule(&dev->mt76.tx_worker);
164
165 return 0;
166 }
167
mt76x02_dma_init(struct mt76x02_dev * dev)168 int mt76x02_dma_init(struct mt76x02_dev *dev)
169 {
170 struct mt76_txwi_cache __maybe_unused *t;
171 int i, ret, fifo_size;
172 struct mt76_queue *q;
173 void *status_fifo;
174
175 BUILD_BUG_ON(sizeof(struct mt76x02_rxwi) > MT_RX_HEADROOM);
176
177 fifo_size = roundup_pow_of_two(32 * sizeof(struct mt76x02_tx_status));
178 status_fifo = devm_kzalloc(dev->mt76.dev, fifo_size, GFP_KERNEL);
179 if (!status_fifo)
180 return -ENOMEM;
181
182 dev->mt76.tx_worker.fn = mt76x02_tx_worker;
183 tasklet_setup(&dev->mt76.pre_tbtt_tasklet, mt76x02_pre_tbtt_tasklet);
184
185 spin_lock_init(&dev->txstatus_fifo_lock);
186 kfifo_init(&dev->txstatus_fifo, status_fifo, fifo_size);
187
188 mt76_dma_attach(&dev->mt76);
189
190 mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
191
192 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
193 ret = mt76_init_tx_queue(&dev->mphy, i, mt76_ac_to_hwq(i),
194 MT76x02_TX_RING_SIZE,
195 MT_TX_RING_BASE);
196 if (ret)
197 return ret;
198 }
199
200 ret = mt76_init_tx_queue(&dev->mphy, MT_TXQ_PSD, MT_TX_HW_QUEUE_MGMT,
201 MT76x02_PSD_RING_SIZE, MT_TX_RING_BASE);
202 if (ret)
203 return ret;
204
205 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT_TX_HW_QUEUE_MCU,
206 MT_MCU_RING_SIZE, MT_TX_RING_BASE);
207 if (ret)
208 return ret;
209
210 mt76x02_irq_enable(dev,
211 MT_INT_TX_DONE(IEEE80211_AC_VO) |
212 MT_INT_TX_DONE(IEEE80211_AC_VI) |
213 MT_INT_TX_DONE(IEEE80211_AC_BE) |
214 MT_INT_TX_DONE(IEEE80211_AC_BK) |
215 MT_INT_TX_DONE(MT_TX_HW_QUEUE_MGMT) |
216 MT_INT_TX_DONE(MT_TX_HW_QUEUE_MCU));
217
218 ret = mt76x02_init_rx_queue(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1,
219 MT_MCU_RING_SIZE, MT_RX_BUF_SIZE);
220 if (ret)
221 return ret;
222
223 q = &dev->mt76.q_rx[MT_RXQ_MAIN];
224 q->buf_offset = MT_RX_HEADROOM - sizeof(struct mt76x02_rxwi);
225 ret = mt76x02_init_rx_queue(dev, q, 0, MT76X02_RX_RING_SIZE,
226 MT_RX_BUF_SIZE);
227 if (ret)
228 return ret;
229
230 ret = mt76_init_queues(dev, mt76_dma_rx_poll);
231 if (ret)
232 return ret;
233
234 netif_tx_napi_add(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
235 mt76x02_poll_tx, NAPI_POLL_WEIGHT);
236 napi_enable(&dev->mt76.tx_napi);
237
238 return 0;
239 }
240 EXPORT_SYMBOL_GPL(mt76x02_dma_init);
241
mt76x02_rx_poll_complete(struct mt76_dev * mdev,enum mt76_rxq_id q)242 void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
243 {
244 struct mt76x02_dev *dev;
245
246 dev = container_of(mdev, struct mt76x02_dev, mt76);
247 mt76x02_irq_enable(dev, MT_INT_RX_DONE(q));
248 }
249 EXPORT_SYMBOL_GPL(mt76x02_rx_poll_complete);
250
mt76x02_irq_handler(int irq,void * dev_instance)251 irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance)
252 {
253 struct mt76x02_dev *dev = dev_instance;
254 u32 intr, mask;
255
256 intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
257 intr &= dev->mt76.mmio.irqmask;
258 mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
259
260 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
261 return IRQ_NONE;
262
263 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
264
265 mask = intr & (MT_INT_RX_DONE_ALL | MT_INT_GPTIMER);
266 if (intr & (MT_INT_TX_DONE_ALL | MT_INT_TX_STAT))
267 mask |= MT_INT_TX_DONE_ALL;
268
269 mt76x02_irq_disable(dev, mask);
270
271 if (intr & MT_INT_RX_DONE(0))
272 napi_schedule(&dev->mt76.napi[0]);
273
274 if (intr & MT_INT_RX_DONE(1))
275 napi_schedule(&dev->mt76.napi[1]);
276
277 if (intr & MT_INT_PRE_TBTT)
278 tasklet_schedule(&dev->mt76.pre_tbtt_tasklet);
279
280 /* send buffered multicast frames now */
281 if (intr & MT_INT_TBTT) {
282 if (dev->mt76.csa_complete)
283 mt76_csa_finish(&dev->mt76);
284 else
285 mt76_queue_kick(dev, dev->mphy.q_tx[MT_TXQ_PSD]);
286 }
287
288 if (intr & MT_INT_TX_STAT)
289 mt76x02_mac_poll_tx_status(dev, true);
290
291 if (intr & (MT_INT_TX_STAT | MT_INT_TX_DONE_ALL))
292 napi_schedule(&dev->mt76.tx_napi);
293
294 if (intr & MT_INT_GPTIMER)
295 tasklet_schedule(&dev->dfs_pd.dfs_tasklet);
296
297 return IRQ_HANDLED;
298 }
299 EXPORT_SYMBOL_GPL(mt76x02_irq_handler);
300
mt76x02_dma_enable(struct mt76x02_dev * dev)301 static void mt76x02_dma_enable(struct mt76x02_dev *dev)
302 {
303 u32 val;
304
305 mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
306 mt76x02_wait_for_wpdma(&dev->mt76, 1000);
307 usleep_range(50, 100);
308
309 val = FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3) |
310 MT_WPDMA_GLO_CFG_TX_DMA_EN |
311 MT_WPDMA_GLO_CFG_RX_DMA_EN;
312 mt76_set(dev, MT_WPDMA_GLO_CFG, val);
313 mt76_clear(dev, MT_WPDMA_GLO_CFG,
314 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
315 }
316
mt76x02_dma_disable(struct mt76x02_dev * dev)317 void mt76x02_dma_disable(struct mt76x02_dev *dev)
318 {
319 u32 val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
320
321 val &= MT_WPDMA_GLO_CFG_DMA_BURST_SIZE |
322 MT_WPDMA_GLO_CFG_BIG_ENDIAN |
323 MT_WPDMA_GLO_CFG_HDR_SEG_LEN;
324 val |= MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE;
325 mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
326 }
327 EXPORT_SYMBOL_GPL(mt76x02_dma_disable);
328
mt76x02_mac_start(struct mt76x02_dev * dev)329 void mt76x02_mac_start(struct mt76x02_dev *dev)
330 {
331 mt76x02_mac_reset_counters(dev);
332 mt76x02_dma_enable(dev);
333 mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter);
334 mt76_wr(dev, MT_MAC_SYS_CTRL,
335 MT_MAC_SYS_CTRL_ENABLE_TX |
336 MT_MAC_SYS_CTRL_ENABLE_RX);
337 mt76x02_irq_enable(dev,
338 MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
339 MT_INT_TX_STAT);
340 }
341 EXPORT_SYMBOL_GPL(mt76x02_mac_start);
342
mt76x02_tx_hang(struct mt76x02_dev * dev)343 static bool mt76x02_tx_hang(struct mt76x02_dev *dev)
344 {
345 u32 dma_idx, prev_dma_idx;
346 struct mt76_queue *q;
347 int i;
348
349 for (i = 0; i < 4; i++) {
350 q = dev->mphy.q_tx[i];
351
352 if (!q->queued)
353 continue;
354
355 prev_dma_idx = dev->mt76.tx_dma_idx[i];
356 dma_idx = readl(&q->regs->dma_idx);
357 dev->mt76.tx_dma_idx[i] = dma_idx;
358
359 if (prev_dma_idx == dma_idx)
360 break;
361 }
362
363 return i < 4;
364 }
365
mt76x02_key_sync(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key,void * data)366 static void mt76x02_key_sync(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
367 struct ieee80211_sta *sta,
368 struct ieee80211_key_conf *key, void *data)
369 {
370 struct mt76x02_dev *dev = hw->priv;
371 struct mt76_wcid *wcid;
372
373 if (!sta)
374 return;
375
376 wcid = (struct mt76_wcid *)sta->drv_priv;
377
378 if (wcid->hw_key_idx != key->keyidx || wcid->sw_iv)
379 return;
380
381 mt76x02_mac_wcid_sync_pn(dev, wcid->idx, key);
382 }
383
mt76x02_reset_state(struct mt76x02_dev * dev)384 static void mt76x02_reset_state(struct mt76x02_dev *dev)
385 {
386 int i;
387
388 lockdep_assert_held(&dev->mt76.mutex);
389
390 clear_bit(MT76_STATE_RUNNING, &dev->mphy.state);
391
392 rcu_read_lock();
393 ieee80211_iter_keys_rcu(dev->mt76.hw, NULL, mt76x02_key_sync, NULL);
394 rcu_read_unlock();
395
396 for (i = 0; i < MT76x02_N_WCIDS; i++) {
397 struct ieee80211_sta *sta;
398 struct ieee80211_vif *vif;
399 struct mt76x02_sta *msta;
400 struct mt76_wcid *wcid;
401 void *priv;
402
403 wcid = rcu_dereference_protected(dev->mt76.wcid[i],
404 lockdep_is_held(&dev->mt76.mutex));
405 if (!wcid)
406 continue;
407
408 rcu_assign_pointer(dev->mt76.wcid[i], NULL);
409
410 priv = msta = container_of(wcid, struct mt76x02_sta, wcid);
411 sta = container_of(priv, struct ieee80211_sta, drv_priv);
412
413 priv = msta->vif;
414 vif = container_of(priv, struct ieee80211_vif, drv_priv);
415
416 __mt76_sta_remove(&dev->mt76, vif, sta);
417 memset(msta, 0, sizeof(*msta));
418 }
419
420 dev->mt76.vif_mask = 0;
421 dev->mt76.beacon_mask = 0;
422 }
423
mt76x02_watchdog_reset(struct mt76x02_dev * dev)424 static void mt76x02_watchdog_reset(struct mt76x02_dev *dev)
425 {
426 u32 mask = dev->mt76.mmio.irqmask;
427 bool restart = dev->mt76.mcu_ops->mcu_restart;
428 int i;
429
430 ieee80211_stop_queues(dev->mt76.hw);
431 set_bit(MT76_RESET, &dev->mphy.state);
432
433 tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
434 mt76_worker_disable(&dev->mt76.tx_worker);
435 napi_disable(&dev->mt76.tx_napi);
436
437 mt76_for_each_q_rx(&dev->mt76, i) {
438 napi_disable(&dev->mt76.napi[i]);
439 }
440
441 mutex_lock(&dev->mt76.mutex);
442
443 dev->mcu_timeout = 0;
444 if (restart)
445 mt76x02_reset_state(dev);
446
447 if (dev->mt76.beacon_mask)
448 mt76_clear(dev, MT_BEACON_TIME_CFG,
449 MT_BEACON_TIME_CFG_BEACON_TX |
450 MT_BEACON_TIME_CFG_TBTT_EN);
451
452 mt76x02_irq_disable(dev, mask);
453
454 /* perform device reset */
455 mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
456 mt76_wr(dev, MT_MAC_SYS_CTRL, 0);
457 mt76_clear(dev, MT_WPDMA_GLO_CFG,
458 MT_WPDMA_GLO_CFG_TX_DMA_EN | MT_WPDMA_GLO_CFG_RX_DMA_EN);
459 usleep_range(5000, 10000);
460 mt76_wr(dev, MT_INT_SOURCE_CSR, 0xffffffff);
461
462 /* let fw reset DMA */
463 mt76_set(dev, 0x734, 0x3);
464
465 if (restart)
466 mt76_mcu_restart(dev);
467
468 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], true);
469 for (i = 0; i < __MT_TXQ_MAX; i++)
470 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);
471
472 mt76_for_each_q_rx(&dev->mt76, i) {
473 mt76_queue_rx_reset(dev, i);
474 }
475
476 mt76_tx_status_check(&dev->mt76, NULL, true);
477
478 mt76x02_mac_start(dev);
479
480 if (dev->ed_monitor)
481 mt76_set(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
482
483 if (dev->mt76.beacon_mask && !restart)
484 mt76_set(dev, MT_BEACON_TIME_CFG,
485 MT_BEACON_TIME_CFG_BEACON_TX |
486 MT_BEACON_TIME_CFG_TBTT_EN);
487
488 mt76x02_irq_enable(dev, mask);
489
490 mutex_unlock(&dev->mt76.mutex);
491
492 clear_bit(MT76_RESET, &dev->mphy.state);
493
494 mt76_worker_enable(&dev->mt76.tx_worker);
495 napi_enable(&dev->mt76.tx_napi);
496 napi_schedule(&dev->mt76.tx_napi);
497
498 tasklet_enable(&dev->mt76.pre_tbtt_tasklet);
499
500 mt76_for_each_q_rx(&dev->mt76, i) {
501 napi_enable(&dev->mt76.napi[i]);
502 napi_schedule(&dev->mt76.napi[i]);
503 }
504
505 if (restart) {
506 set_bit(MT76_RESTART, &dev->mphy.state);
507 mt76x02_mcu_function_select(dev, Q_SELECT, 1);
508 ieee80211_restart_hw(dev->mt76.hw);
509 } else {
510 ieee80211_wake_queues(dev->mt76.hw);
511 mt76_txq_schedule_all(&dev->mphy);
512 }
513 }
514
mt76x02_reconfig_complete(struct ieee80211_hw * hw,enum ieee80211_reconfig_type reconfig_type)515 void mt76x02_reconfig_complete(struct ieee80211_hw *hw,
516 enum ieee80211_reconfig_type reconfig_type)
517 {
518 struct mt76x02_dev *dev = hw->priv;
519
520 if (reconfig_type != IEEE80211_RECONFIG_TYPE_RESTART)
521 return;
522
523 clear_bit(MT76_RESTART, &dev->mphy.state);
524 }
525 EXPORT_SYMBOL_GPL(mt76x02_reconfig_complete);
526
mt76x02_check_tx_hang(struct mt76x02_dev * dev)527 static void mt76x02_check_tx_hang(struct mt76x02_dev *dev)
528 {
529 if (test_bit(MT76_RESTART, &dev->mphy.state))
530 return;
531
532 if (mt76x02_tx_hang(dev)) {
533 if (++dev->tx_hang_check >= MT_TX_HANG_TH)
534 goto restart;
535 } else {
536 dev->tx_hang_check = 0;
537 }
538
539 if (dev->mcu_timeout)
540 goto restart;
541
542 return;
543
544 restart:
545 mt76x02_watchdog_reset(dev);
546
547 dev->tx_hang_reset++;
548 dev->tx_hang_check = 0;
549 memset(dev->mt76.tx_dma_idx, 0xff,
550 sizeof(dev->mt76.tx_dma_idx));
551 }
552
mt76x02_wdt_work(struct work_struct * work)553 void mt76x02_wdt_work(struct work_struct *work)
554 {
555 struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev,
556 wdt_work.work);
557
558 mt76x02_check_tx_hang(dev);
559
560 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->wdt_work,
561 MT_WATCHDOG_TIME);
562 }
563