1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #ifndef __AMDGPU_SMU_H__ 23 #define __AMDGPU_SMU_H__ 24 25 #include "amdgpu.h" 26 #include "kgd_pp_interface.h" 27 #include "dm_pp_interface.h" 28 #include "dm_pp_smu.h" 29 #include "smu_types.h" 30 31 #define SMU_THERMAL_MINIMUM_ALERT_TEMP 0 32 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255 33 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000 34 #define SMU_FW_NAME_LEN 0x24 35 36 #define SMU_DPM_USER_PROFILE_RESTORE (1 << 0) 37 #define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1) 38 #define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2) 39 40 // Power Throttlers 41 #define SMU_THROTTLER_PPT0_BIT 0 42 #define SMU_THROTTLER_PPT1_BIT 1 43 #define SMU_THROTTLER_PPT2_BIT 2 44 #define SMU_THROTTLER_PPT3_BIT 3 45 #define SMU_THROTTLER_SPL_BIT 4 46 #define SMU_THROTTLER_FPPT_BIT 5 47 #define SMU_THROTTLER_SPPT_BIT 6 48 #define SMU_THROTTLER_SPPT_APU_BIT 7 49 50 // Current Throttlers 51 #define SMU_THROTTLER_TDC_GFX_BIT 16 52 #define SMU_THROTTLER_TDC_SOC_BIT 17 53 #define SMU_THROTTLER_TDC_MEM_BIT 18 54 #define SMU_THROTTLER_TDC_VDD_BIT 19 55 #define SMU_THROTTLER_TDC_CVIP_BIT 20 56 #define SMU_THROTTLER_EDC_CPU_BIT 21 57 #define SMU_THROTTLER_EDC_GFX_BIT 22 58 #define SMU_THROTTLER_APCC_BIT 23 59 60 // Temperature 61 #define SMU_THROTTLER_TEMP_GPU_BIT 32 62 #define SMU_THROTTLER_TEMP_CORE_BIT 33 63 #define SMU_THROTTLER_TEMP_MEM_BIT 34 64 #define SMU_THROTTLER_TEMP_EDGE_BIT 35 65 #define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36 66 #define SMU_THROTTLER_TEMP_SOC_BIT 37 67 #define SMU_THROTTLER_TEMP_VR_GFX_BIT 38 68 #define SMU_THROTTLER_TEMP_VR_SOC_BIT 39 69 #define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40 70 #define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41 71 #define SMU_THROTTLER_TEMP_LIQUID0_BIT 42 72 #define SMU_THROTTLER_TEMP_LIQUID1_BIT 43 73 #define SMU_THROTTLER_VRHOT0_BIT 44 74 #define SMU_THROTTLER_VRHOT1_BIT 45 75 #define SMU_THROTTLER_PROCHOT_CPU_BIT 46 76 #define SMU_THROTTLER_PROCHOT_GFX_BIT 47 77 78 // Other 79 #define SMU_THROTTLER_PPM_BIT 56 80 #define SMU_THROTTLER_FIT_BIT 57 81 82 struct smu_hw_power_state { 83 unsigned int magic; 84 }; 85 86 struct smu_power_state; 87 88 enum smu_state_ui_label { 89 SMU_STATE_UI_LABEL_NONE, 90 SMU_STATE_UI_LABEL_BATTERY, 91 SMU_STATE_UI_TABEL_MIDDLE_LOW, 92 SMU_STATE_UI_LABEL_BALLANCED, 93 SMU_STATE_UI_LABEL_MIDDLE_HIGHT, 94 SMU_STATE_UI_LABEL_PERFORMANCE, 95 SMU_STATE_UI_LABEL_BACO, 96 }; 97 98 enum smu_state_classification_flag { 99 SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001, 100 SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002, 101 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004, 102 SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008, 103 SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010, 104 SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020, 105 SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040, 106 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080, 107 SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100, 108 SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200, 109 SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400, 110 SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800, 111 SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000, 112 SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000, 113 SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000, 114 SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000, 115 SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000, 116 SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000, 117 SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000, 118 SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000, 119 SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000, 120 }; 121 122 struct smu_state_classification_block { 123 enum smu_state_ui_label ui_label; 124 enum smu_state_classification_flag flags; 125 int bios_index; 126 bool temporary_state; 127 bool to_be_deleted; 128 }; 129 130 struct smu_state_pcie_block { 131 unsigned int lanes; 132 }; 133 134 enum smu_refreshrate_source { 135 SMU_REFRESHRATE_SOURCE_EDID, 136 SMU_REFRESHRATE_SOURCE_EXPLICIT 137 }; 138 139 struct smu_state_display_block { 140 bool disable_frame_modulation; 141 bool limit_refreshrate; 142 enum smu_refreshrate_source refreshrate_source; 143 int explicit_refreshrate; 144 int edid_refreshrate_index; 145 bool enable_vari_bright; 146 }; 147 148 struct smu_state_memory_block { 149 bool dll_off; 150 uint8_t m3arb; 151 uint8_t unused[3]; 152 }; 153 154 struct smu_state_software_algorithm_block { 155 bool disable_load_balancing; 156 bool enable_sleep_for_timestamps; 157 }; 158 159 struct smu_temperature_range { 160 int min; 161 int max; 162 int edge_emergency_max; 163 int hotspot_min; 164 int hotspot_crit_max; 165 int hotspot_emergency_max; 166 int mem_min; 167 int mem_crit_max; 168 int mem_emergency_max; 169 int software_shutdown_temp; 170 }; 171 172 struct smu_state_validation_block { 173 bool single_display_only; 174 bool disallow_on_dc; 175 uint8_t supported_power_levels; 176 }; 177 178 struct smu_uvd_clocks { 179 uint32_t vclk; 180 uint32_t dclk; 181 }; 182 183 /** 184 * Structure to hold a SMU Power State. 185 */ 186 struct smu_power_state { 187 uint32_t id; 188 struct list_head ordered_list; 189 struct list_head all_states_list; 190 191 struct smu_state_classification_block classification; 192 struct smu_state_validation_block validation; 193 struct smu_state_pcie_block pcie; 194 struct smu_state_display_block display; 195 struct smu_state_memory_block memory; 196 struct smu_state_software_algorithm_block software; 197 struct smu_uvd_clocks uvd_clocks; 198 struct smu_hw_power_state hardware; 199 }; 200 201 enum smu_power_src_type 202 { 203 SMU_POWER_SOURCE_AC, 204 SMU_POWER_SOURCE_DC, 205 SMU_POWER_SOURCE_COUNT, 206 }; 207 208 enum smu_ppt_limit_type 209 { 210 SMU_DEFAULT_PPT_LIMIT = 0, 211 SMU_FAST_PPT_LIMIT, 212 }; 213 214 enum smu_ppt_limit_level 215 { 216 SMU_PPT_LIMIT_MIN = -1, 217 SMU_PPT_LIMIT_CURRENT, 218 SMU_PPT_LIMIT_DEFAULT, 219 SMU_PPT_LIMIT_MAX, 220 }; 221 222 enum smu_memory_pool_size 223 { 224 SMU_MEMORY_POOL_SIZE_ZERO = 0, 225 SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000, 226 SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000, 227 SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000, 228 SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000, 229 }; 230 231 struct smu_user_dpm_profile { 232 uint32_t fan_mode; 233 uint32_t power_limit; 234 uint32_t fan_speed_pwm; 235 uint32_t fan_speed_rpm; 236 uint32_t flags; 237 uint32_t user_od; 238 239 /* user clock state information */ 240 uint32_t clk_mask[SMU_CLK_COUNT]; 241 uint32_t clk_dependency; 242 }; 243 244 enum smu_event_type { 245 246 SMU_EVENT_RESET_COMPLETE = 0, 247 }; 248 249 #define SMU_TABLE_INIT(tables, table_id, s, a, d) \ 250 do { \ 251 tables[table_id].size = s; \ 252 tables[table_id].align = a; \ 253 tables[table_id].domain = d; \ 254 } while (0) 255 256 struct smu_table { 257 uint64_t size; 258 uint32_t align; 259 uint8_t domain; 260 uint64_t mc_address; 261 void *cpu_addr; 262 struct amdgpu_bo *bo; 263 }; 264 265 enum smu_perf_level_designation { 266 PERF_LEVEL_ACTIVITY, 267 PERF_LEVEL_POWER_CONTAINMENT, 268 }; 269 270 struct smu_performance_level { 271 uint32_t core_clock; 272 uint32_t memory_clock; 273 uint32_t vddc; 274 uint32_t vddci; 275 uint32_t non_local_mem_freq; 276 uint32_t non_local_mem_width; 277 }; 278 279 struct smu_clock_info { 280 uint32_t min_mem_clk; 281 uint32_t max_mem_clk; 282 uint32_t min_eng_clk; 283 uint32_t max_eng_clk; 284 uint32_t min_bus_bandwidth; 285 uint32_t max_bus_bandwidth; 286 }; 287 288 struct smu_bios_boot_up_values 289 { 290 uint32_t revision; 291 uint32_t gfxclk; 292 uint32_t uclk; 293 uint32_t socclk; 294 uint32_t dcefclk; 295 uint32_t eclk; 296 uint32_t vclk; 297 uint32_t dclk; 298 uint16_t vddc; 299 uint16_t vddci; 300 uint16_t mvddc; 301 uint16_t vdd_gfx; 302 uint8_t cooling_id; 303 uint32_t pp_table_id; 304 uint32_t format_revision; 305 uint32_t content_revision; 306 uint32_t fclk; 307 uint32_t lclk; 308 uint32_t firmware_caps; 309 }; 310 311 enum smu_table_id 312 { 313 SMU_TABLE_PPTABLE = 0, 314 SMU_TABLE_WATERMARKS, 315 SMU_TABLE_CUSTOM_DPM, 316 SMU_TABLE_DPMCLOCKS, 317 SMU_TABLE_AVFS, 318 SMU_TABLE_AVFS_PSM_DEBUG, 319 SMU_TABLE_AVFS_FUSE_OVERRIDE, 320 SMU_TABLE_PMSTATUSLOG, 321 SMU_TABLE_SMU_METRICS, 322 SMU_TABLE_DRIVER_SMU_CONFIG, 323 SMU_TABLE_ACTIVITY_MONITOR_COEFF, 324 SMU_TABLE_OVERDRIVE, 325 SMU_TABLE_I2C_COMMANDS, 326 SMU_TABLE_PACE, 327 SMU_TABLE_COUNT, 328 }; 329 330 struct smu_table_context 331 { 332 void *power_play_table; 333 uint32_t power_play_table_size; 334 void *hardcode_pptable; 335 unsigned long metrics_time; 336 void *metrics_table; 337 void *clocks_table; 338 void *watermarks_table; 339 340 void *max_sustainable_clocks; 341 struct smu_bios_boot_up_values boot_values; 342 void *driver_pptable; 343 struct smu_table tables[SMU_TABLE_COUNT]; 344 /* 345 * The driver table is just a staging buffer for 346 * uploading/downloading content from the SMU. 347 * 348 * And the table_id for SMU_MSG_TransferTableSmu2Dram/ 349 * SMU_MSG_TransferTableDram2Smu instructs SMU 350 * which content driver is interested. 351 */ 352 struct smu_table driver_table; 353 struct smu_table memory_pool; 354 struct smu_table dummy_read_1_table; 355 uint8_t thermal_controller_type; 356 357 void *overdrive_table; 358 void *boot_overdrive_table; 359 void *user_overdrive_table; 360 361 uint32_t gpu_metrics_table_size; 362 void *gpu_metrics_table; 363 }; 364 365 struct smu_dpm_context { 366 uint32_t dpm_context_size; 367 void *dpm_context; 368 void *golden_dpm_context; 369 bool enable_umd_pstate; 370 enum amd_dpm_forced_level dpm_level; 371 enum amd_dpm_forced_level saved_dpm_level; 372 enum amd_dpm_forced_level requested_dpm_level; 373 struct smu_power_state *dpm_request_power_state; 374 struct smu_power_state *dpm_current_power_state; 375 struct mclock_latency_table *mclk_latency_table; 376 }; 377 378 struct smu_power_gate { 379 bool uvd_gated; 380 bool vce_gated; 381 atomic_t vcn_gated; 382 atomic_t jpeg_gated; 383 struct mutex vcn_gate_lock; 384 struct mutex jpeg_gate_lock; 385 }; 386 387 struct smu_power_context { 388 void *power_context; 389 uint32_t power_context_size; 390 struct smu_power_gate power_gate; 391 }; 392 393 #define SMU_FEATURE_MAX (64) 394 struct smu_feature 395 { 396 uint32_t feature_num; 397 DECLARE_BITMAP(supported, SMU_FEATURE_MAX); 398 DECLARE_BITMAP(allowed, SMU_FEATURE_MAX); 399 DECLARE_BITMAP(enabled, SMU_FEATURE_MAX); 400 struct mutex mutex; 401 }; 402 403 struct smu_clocks { 404 uint32_t engine_clock; 405 uint32_t memory_clock; 406 uint32_t bus_bandwidth; 407 uint32_t engine_clock_in_sr; 408 uint32_t dcef_clock; 409 uint32_t dcef_clock_in_sr; 410 }; 411 412 #define MAX_REGULAR_DPM_NUM 16 413 struct mclk_latency_entries { 414 uint32_t frequency; 415 uint32_t latency; 416 }; 417 struct mclock_latency_table { 418 uint32_t count; 419 struct mclk_latency_entries entries[MAX_REGULAR_DPM_NUM]; 420 }; 421 422 enum smu_reset_mode 423 { 424 SMU_RESET_MODE_0, 425 SMU_RESET_MODE_1, 426 SMU_RESET_MODE_2, 427 }; 428 429 enum smu_baco_state 430 { 431 SMU_BACO_STATE_ENTER = 0, 432 SMU_BACO_STATE_EXIT, 433 }; 434 435 struct smu_baco_context 436 { 437 struct mutex mutex; 438 uint32_t state; 439 bool platform_support; 440 }; 441 442 struct smu_freq_info { 443 uint32_t min; 444 uint32_t max; 445 uint32_t freq_level; 446 }; 447 448 struct pstates_clk_freq { 449 uint32_t min; 450 uint32_t standard; 451 uint32_t peak; 452 struct smu_freq_info custom; 453 struct smu_freq_info curr; 454 }; 455 456 struct smu_umd_pstate_table { 457 struct pstates_clk_freq gfxclk_pstate; 458 struct pstates_clk_freq socclk_pstate; 459 struct pstates_clk_freq uclk_pstate; 460 struct pstates_clk_freq vclk_pstate; 461 struct pstates_clk_freq dclk_pstate; 462 }; 463 464 struct cmn2asic_msg_mapping { 465 int valid_mapping; 466 int map_to; 467 int valid_in_vf; 468 }; 469 470 struct cmn2asic_mapping { 471 int valid_mapping; 472 int map_to; 473 }; 474 475 #define WORKLOAD_POLICY_MAX 7 476 struct smu_context 477 { 478 struct amdgpu_device *adev; 479 struct amdgpu_irq_src irq_source; 480 481 const struct pptable_funcs *ppt_funcs; 482 const struct cmn2asic_msg_mapping *message_map; 483 const struct cmn2asic_mapping *clock_map; 484 const struct cmn2asic_mapping *feature_map; 485 const struct cmn2asic_mapping *table_map; 486 const struct cmn2asic_mapping *pwr_src_map; 487 const struct cmn2asic_mapping *workload_map; 488 struct mutex mutex; 489 struct mutex sensor_lock; 490 struct mutex metrics_lock; 491 struct mutex message_lock; 492 uint64_t pool_size; 493 494 struct smu_table_context smu_table; 495 struct smu_dpm_context smu_dpm; 496 struct smu_power_context smu_power; 497 struct smu_feature smu_feature; 498 struct amd_pp_display_configuration *display_config; 499 struct smu_baco_context smu_baco; 500 struct smu_temperature_range thermal_range; 501 void *od_settings; 502 503 struct smu_umd_pstate_table pstate_table; 504 uint32_t pstate_sclk; 505 uint32_t pstate_mclk; 506 507 bool od_enabled; 508 uint32_t current_power_limit; 509 uint32_t default_power_limit; 510 uint32_t max_power_limit; 511 512 /* soft pptable */ 513 uint32_t ppt_offset_bytes; 514 uint32_t ppt_size_bytes; 515 uint8_t *ppt_start_addr; 516 517 bool support_power_containment; 518 bool disable_watermark; 519 520 #define WATERMARKS_EXIST (1 << 0) 521 #define WATERMARKS_LOADED (1 << 1) 522 uint32_t watermarks_bitmap; 523 uint32_t hard_min_uclk_req_from_dal; 524 bool disable_uclk_switch; 525 526 uint32_t workload_mask; 527 uint32_t workload_prority[WORKLOAD_POLICY_MAX]; 528 uint32_t workload_setting[WORKLOAD_POLICY_MAX]; 529 uint32_t power_profile_mode; 530 uint32_t default_power_profile_mode; 531 bool pm_enabled; 532 bool is_apu; 533 534 uint32_t smc_driver_if_version; 535 uint32_t smc_fw_if_version; 536 uint32_t smc_fw_version; 537 538 bool uploading_custom_pp_table; 539 bool dc_controlled_by_gpio; 540 541 struct work_struct throttling_logging_work; 542 atomic64_t throttle_int_counter; 543 struct work_struct interrupt_work; 544 545 unsigned fan_max_rpm; 546 unsigned manual_fan_speed_pwm; 547 548 uint32_t gfx_default_hard_min_freq; 549 uint32_t gfx_default_soft_max_freq; 550 uint32_t gfx_actual_hard_min_freq; 551 uint32_t gfx_actual_soft_max_freq; 552 553 /* APU only */ 554 uint32_t cpu_default_soft_min_freq; 555 uint32_t cpu_default_soft_max_freq; 556 uint32_t cpu_actual_soft_min_freq; 557 uint32_t cpu_actual_soft_max_freq; 558 uint32_t cpu_core_id_select; 559 uint16_t cpu_core_num; 560 561 struct smu_user_dpm_profile user_dpm_profile; 562 }; 563 564 struct i2c_adapter; 565 566 /** 567 * struct pptable_funcs - Callbacks used to interact with the SMU. 568 */ 569 struct pptable_funcs { 570 /** 571 * @run_btc: Calibrate voltage/frequency curve to fit the system's 572 * power delivery and voltage margins. Required for adaptive 573 * voltage frequency scaling (AVFS). 574 */ 575 int (*run_btc)(struct smu_context *smu); 576 577 /** 578 * @get_allowed_feature_mask: Get allowed feature mask. 579 * &feature_mask: Array to store feature mask. 580 * &num: Elements in &feature_mask. 581 */ 582 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 583 584 /** 585 * @get_current_power_state: Get the current power state. 586 * 587 * Return: Current power state on success, negative errno on failure. 588 */ 589 enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu); 590 591 /** 592 * @set_default_dpm_table: Retrieve the default overdrive settings from 593 * the SMU. 594 */ 595 int (*set_default_dpm_table)(struct smu_context *smu); 596 597 int (*set_power_state)(struct smu_context *smu); 598 599 /** 600 * @populate_umd_state_clk: Populate the UMD power state table with 601 * defaults. 602 */ 603 int (*populate_umd_state_clk)(struct smu_context *smu); 604 605 /** 606 * @print_clk_levels: Print DPM clock levels for a clock domain 607 * to buffer. Star current level. 608 * 609 * Used for sysfs interfaces. 610 */ 611 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); 612 613 /** 614 * @force_clk_levels: Set a range of allowed DPM levels for a clock 615 * domain. 616 * &clk_type: Clock domain. 617 * &mask: Range of allowed DPM levels. 618 */ 619 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); 620 621 /** 622 * @od_edit_dpm_table: Edit the custom overdrive DPM table. 623 * &type: Type of edit. 624 * &input: Edit parameters. 625 * &size: Size of &input. 626 */ 627 int (*od_edit_dpm_table)(struct smu_context *smu, 628 enum PP_OD_DPM_TABLE_COMMAND type, 629 long *input, uint32_t size); 630 631 /** 632 * @restore_user_od_settings: Restore the user customized 633 * OD settings on S3/S4/Runpm resume. 634 */ 635 int (*restore_user_od_settings)(struct smu_context *smu); 636 637 /** 638 * @get_clock_by_type_with_latency: Get the speed and latency of a clock 639 * domain. 640 */ 641 int (*get_clock_by_type_with_latency)(struct smu_context *smu, 642 enum smu_clk_type clk_type, 643 struct 644 pp_clock_levels_with_latency 645 *clocks); 646 /** 647 * @get_clock_by_type_with_voltage: Get the speed and voltage of a clock 648 * domain. 649 */ 650 int (*get_clock_by_type_with_voltage)(struct smu_context *smu, 651 enum amd_pp_clock_type type, 652 struct 653 pp_clock_levels_with_voltage 654 *clocks); 655 656 /** 657 * @get_power_profile_mode: Print all power profile modes to 658 * buffer. Star current mode. 659 */ 660 int (*get_power_profile_mode)(struct smu_context *smu, char *buf); 661 662 /** 663 * @set_power_profile_mode: Set a power profile mode. Also used to 664 * create/set custom power profile modes. 665 * &input: Power profile mode parameters. 666 * &size: Size of &input. 667 */ 668 int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size); 669 670 /** 671 * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power 672 * management. 673 */ 674 int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable); 675 676 /** 677 * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power 678 * management. 679 */ 680 int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable); 681 682 /** 683 * @read_sensor: Read data from a sensor. 684 * &sensor: Sensor to read data from. 685 * &data: Sensor reading. 686 * &size: Size of &data. 687 */ 688 int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor, 689 void *data, uint32_t *size); 690 691 /** 692 * @pre_display_config_changed: Prepare GPU for a display configuration 693 * change. 694 * 695 * Disable display tracking and pin memory clock speed to maximum. Used 696 * in display component synchronization. 697 */ 698 int (*pre_display_config_changed)(struct smu_context *smu); 699 700 /** 701 * @display_config_changed: Notify the SMU of the current display 702 * configuration. 703 * 704 * Allows SMU to properly track blanking periods for memory clock 705 * adjustment. Used in display component synchronization. 706 */ 707 int (*display_config_changed)(struct smu_context *smu); 708 709 int (*apply_clocks_adjust_rules)(struct smu_context *smu); 710 711 /** 712 * @notify_smc_display_config: Applies display requirements to the 713 * current power state. 714 * 715 * Optimize deep sleep DCEFclk and mclk for the current display 716 * configuration. Used in display component synchronization. 717 */ 718 int (*notify_smc_display_config)(struct smu_context *smu); 719 720 /** 721 * @is_dpm_running: Check if DPM is running. 722 * 723 * Return: True if DPM is running, false otherwise. 724 */ 725 bool (*is_dpm_running)(struct smu_context *smu); 726 727 /** 728 * @get_fan_speed_pwm: Get the current fan speed in PWM. 729 */ 730 int (*get_fan_speed_pwm)(struct smu_context *smu, uint32_t *speed); 731 732 /** 733 * @get_fan_speed_rpm: Get the current fan speed in rpm. 734 */ 735 int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed); 736 737 /** 738 * @set_watermarks_table: Configure and upload the watermarks tables to 739 * the SMU. 740 */ 741 int (*set_watermarks_table)(struct smu_context *smu, 742 struct pp_smu_wm_range_sets *clock_ranges); 743 744 /** 745 * @get_thermal_temperature_range: Get safe thermal limits in Celcius. 746 */ 747 int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range); 748 749 /** 750 * @get_uclk_dpm_states: Get memory clock DPM levels in kHz. 751 * &clocks_in_khz: Array of DPM levels. 752 * &num_states: Elements in &clocks_in_khz. 753 */ 754 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states); 755 756 /** 757 * @set_default_od_settings: Set the overdrive tables to defaults. 758 */ 759 int (*set_default_od_settings)(struct smu_context *smu); 760 761 /** 762 * @set_performance_level: Set a performance level. 763 */ 764 int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level); 765 766 /** 767 * @display_disable_memory_clock_switch: Enable/disable dynamic memory 768 * clock switching. 769 * 770 * Disabling this feature forces memory clock speed to maximum. 771 * Enabling sets the minimum memory clock capable of driving the 772 * current display configuration. 773 */ 774 int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch); 775 776 /** 777 * @dump_pptable: Print the power play table to the system log. 778 */ 779 void (*dump_pptable)(struct smu_context *smu); 780 781 /** 782 * @get_power_limit: Get the device's power limits. 783 */ 784 int (*get_power_limit)(struct smu_context *smu, 785 uint32_t *current_power_limit, 786 uint32_t *default_power_limit, 787 uint32_t *max_power_limit); 788 789 /** 790 * @get_ppt_limit: Get the device's ppt limits. 791 */ 792 int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit, 793 enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level); 794 795 /** 796 * @set_df_cstate: Set data fabric cstate. 797 */ 798 int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state); 799 800 /** 801 * @allow_xgmi_power_down: Enable/disable external global memory 802 * interconnect power down. 803 */ 804 int (*allow_xgmi_power_down)(struct smu_context *smu, bool en); 805 806 /** 807 * @update_pcie_parameters: Update and upload the system's PCIe 808 * capabilites to the SMU. 809 * &pcie_gen_cap: Maximum allowed PCIe generation. 810 * &pcie_width_cap: Maximum allowed PCIe width. 811 */ 812 int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap); 813 814 /** 815 * @i2c_init: Initialize i2c. 816 * 817 * The i2c bus is used internally by the SMU voltage regulators and 818 * other devices. The i2c's EEPROM also stores bad page tables on boards 819 * with ECC. 820 */ 821 int (*i2c_init)(struct smu_context *smu, struct i2c_adapter *control); 822 823 /** 824 * @i2c_fini: Tear down i2c. 825 */ 826 void (*i2c_fini)(struct smu_context *smu, struct i2c_adapter *control); 827 828 /** 829 * @get_unique_id: Get the GPU's unique id. Used for asset tracking. 830 */ 831 void (*get_unique_id)(struct smu_context *smu); 832 833 /** 834 * @get_dpm_clock_table: Get a copy of the DPM clock table. 835 * 836 * Used by display component in bandwidth and watermark calculations. 837 */ 838 int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table); 839 840 /** 841 * @init_microcode: Request the SMU's firmware from the kernel. 842 */ 843 int (*init_microcode)(struct smu_context *smu); 844 845 /** 846 * @load_microcode: Load firmware onto the SMU. 847 */ 848 int (*load_microcode)(struct smu_context *smu); 849 850 /** 851 * @fini_microcode: Release the SMU's firmware. 852 */ 853 void (*fini_microcode)(struct smu_context *smu); 854 855 /** 856 * @init_smc_tables: Initialize the SMU tables. 857 */ 858 int (*init_smc_tables)(struct smu_context *smu); 859 860 /** 861 * @fini_smc_tables: Release the SMU tables. 862 */ 863 int (*fini_smc_tables)(struct smu_context *smu); 864 865 /** 866 * @init_power: Initialize the power gate table context. 867 */ 868 int (*init_power)(struct smu_context *smu); 869 870 /** 871 * @fini_power: Release the power gate table context. 872 */ 873 int (*fini_power)(struct smu_context *smu); 874 875 /** 876 * @check_fw_status: Check the SMU's firmware status. 877 * 878 * Return: Zero if check passes, negative errno on failure. 879 */ 880 int (*check_fw_status)(struct smu_context *smu); 881 882 /** 883 * @set_mp1_state: put SMU into a correct state for comming 884 * resume from runpm or gpu reset. 885 */ 886 int (*set_mp1_state)(struct smu_context *smu, 887 enum pp_mp1_state mp1_state); 888 889 /** 890 * @setup_pptable: Initialize the power play table and populate it with 891 * default values. 892 */ 893 int (*setup_pptable)(struct smu_context *smu); 894 895 /** 896 * @get_vbios_bootup_values: Get default boot values from the VBIOS. 897 */ 898 int (*get_vbios_bootup_values)(struct smu_context *smu); 899 900 /** 901 * @check_fw_version: Print driver and SMU interface versions to the 902 * system log. 903 * 904 * Interface mismatch is not a critical failure. 905 */ 906 int (*check_fw_version)(struct smu_context *smu); 907 908 /** 909 * @powergate_sdma: Power up/down system direct memory access. 910 */ 911 int (*powergate_sdma)(struct smu_context *smu, bool gate); 912 913 /** 914 * @set_gfx_cgpg: Enable/disable graphics engine course grain power 915 * gating. 916 */ 917 int (*set_gfx_cgpg)(struct smu_context *smu, bool enable); 918 919 /** 920 * @write_pptable: Write the power play table to the SMU. 921 */ 922 int (*write_pptable)(struct smu_context *smu); 923 924 /** 925 * @set_driver_table_location: Send the location of the driver table to 926 * the SMU. 927 */ 928 int (*set_driver_table_location)(struct smu_context *smu); 929 930 /** 931 * @set_tool_table_location: Send the location of the tool table to the 932 * SMU. 933 */ 934 int (*set_tool_table_location)(struct smu_context *smu); 935 936 /** 937 * @notify_memory_pool_location: Send the location of the memory pool to 938 * the SMU. 939 */ 940 int (*notify_memory_pool_location)(struct smu_context *smu); 941 942 /** 943 * @system_features_control: Enable/disable all SMU features. 944 */ 945 int (*system_features_control)(struct smu_context *smu, bool en); 946 947 /** 948 * @send_smc_msg_with_param: Send a message with a parameter to the SMU. 949 * &msg: Type of message. 950 * ¶m: Message parameter. 951 * &read_arg: SMU response (optional). 952 */ 953 int (*send_smc_msg_with_param)(struct smu_context *smu, 954 enum smu_message_type msg, uint32_t param, uint32_t *read_arg); 955 956 /** 957 * @send_smc_msg: Send a message to the SMU. 958 * &msg: Type of message. 959 * &read_arg: SMU response (optional). 960 */ 961 int (*send_smc_msg)(struct smu_context *smu, 962 enum smu_message_type msg, 963 uint32_t *read_arg); 964 965 /** 966 * @init_display_count: Notify the SMU of the number of display 967 * components in current display configuration. 968 */ 969 int (*init_display_count)(struct smu_context *smu, uint32_t count); 970 971 /** 972 * @set_allowed_mask: Notify the SMU of the features currently allowed 973 * by the driver. 974 */ 975 int (*set_allowed_mask)(struct smu_context *smu); 976 977 /** 978 * @get_enabled_mask: Get a mask of features that are currently enabled 979 * on the SMU. 980 * &feature_mask: Array representing enabled feature mask. 981 * &num: Elements in &feature_mask. 982 */ 983 int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 984 985 /** 986 * @feature_is_enabled: Test if a feature is enabled. 987 * 988 * Return: One if enabled, zero if disabled. 989 */ 990 int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask); 991 992 /** 993 * @disable_all_features_with_exception: Disable all features with 994 * exception to those in &mask. 995 */ 996 int (*disable_all_features_with_exception)(struct smu_context *smu, 997 bool no_hw_disablement, 998 enum smu_feature_mask mask); 999 1000 /** 1001 * @notify_display_change: Enable fast memory clock switching. 1002 * 1003 * Allows for fine grained memory clock switching but has more stringent 1004 * timing requirements. 1005 */ 1006 int (*notify_display_change)(struct smu_context *smu); 1007 1008 /** 1009 * @set_power_limit: Set power limit in watts. 1010 */ 1011 int (*set_power_limit)(struct smu_context *smu, uint32_t n); 1012 1013 /** 1014 * @init_max_sustainable_clocks: Populate max sustainable clock speed 1015 * table with values from the SMU. 1016 */ 1017 int (*init_max_sustainable_clocks)(struct smu_context *smu); 1018 1019 /** 1020 * @enable_thermal_alert: Enable thermal alert interrupts. 1021 */ 1022 int (*enable_thermal_alert)(struct smu_context *smu); 1023 1024 /** 1025 * @disable_thermal_alert: Disable thermal alert interrupts. 1026 */ 1027 int (*disable_thermal_alert)(struct smu_context *smu); 1028 1029 /** 1030 * @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep 1031 * clock speed in MHz. 1032 */ 1033 int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk); 1034 1035 /** 1036 * @display_clock_voltage_request: Set a hard minimum frequency 1037 * for a clock domain. 1038 */ 1039 int (*display_clock_voltage_request)(struct smu_context *smu, struct 1040 pp_display_clock_request 1041 *clock_req); 1042 1043 /** 1044 * @get_fan_control_mode: Get the current fan control mode. 1045 */ 1046 uint32_t (*get_fan_control_mode)(struct smu_context *smu); 1047 1048 /** 1049 * @set_fan_control_mode: Set the fan control mode. 1050 */ 1051 int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode); 1052 1053 /** 1054 * @set_fan_speed_pwm: Set a static fan speed in PWM. 1055 */ 1056 int (*set_fan_speed_pwm)(struct smu_context *smu, uint32_t speed); 1057 1058 /** 1059 * @set_fan_speed_rpm: Set a static fan speed in rpm. 1060 */ 1061 int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed); 1062 1063 /** 1064 * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate. 1065 * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise. 1066 */ 1067 int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate); 1068 1069 /** 1070 * @gfx_off_control: Enable/disable graphics engine poweroff. 1071 */ 1072 int (*gfx_off_control)(struct smu_context *smu, bool enable); 1073 1074 1075 /** 1076 * @get_gfx_off_status: Get graphics engine poweroff status. 1077 * 1078 * Return: 1079 * 0 - GFXOFF(default). 1080 * 1 - Transition out of GFX State. 1081 * 2 - Not in GFXOFF. 1082 * 3 - Transition into GFXOFF. 1083 */ 1084 uint32_t (*get_gfx_off_status)(struct smu_context *smu); 1085 1086 /** 1087 * @register_irq_handler: Register interupt request handlers. 1088 */ 1089 int (*register_irq_handler)(struct smu_context *smu); 1090 1091 /** 1092 * @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep. 1093 */ 1094 int (*set_azalia_d3_pme)(struct smu_context *smu); 1095 1096 /** 1097 * @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable 1098 * clock speeds table. 1099 * 1100 * Provides a way for the display component (DC) to get the max 1101 * sustainable clocks from the SMU. 1102 */ 1103 int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks); 1104 1105 /** 1106 * @baco_is_support: Check if GPU supports BACO (Bus Active, Chip Off). 1107 */ 1108 bool (*baco_is_support)(struct smu_context *smu); 1109 1110 /** 1111 * @baco_get_state: Get the current BACO state. 1112 * 1113 * Return: Current BACO state. 1114 */ 1115 enum smu_baco_state (*baco_get_state)(struct smu_context *smu); 1116 1117 /** 1118 * @baco_set_state: Enter/exit BACO. 1119 */ 1120 int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state); 1121 1122 /** 1123 * @baco_enter: Enter BACO. 1124 */ 1125 int (*baco_enter)(struct smu_context *smu); 1126 1127 /** 1128 * @baco_exit: Exit Baco. 1129 */ 1130 int (*baco_exit)(struct smu_context *smu); 1131 1132 /** 1133 * @mode1_reset_is_support: Check if GPU supports mode1 reset. 1134 */ 1135 bool (*mode1_reset_is_support)(struct smu_context *smu); 1136 /** 1137 * @mode2_reset_is_support: Check if GPU supports mode2 reset. 1138 */ 1139 bool (*mode2_reset_is_support)(struct smu_context *smu); 1140 1141 /** 1142 * @mode1_reset: Perform mode1 reset. 1143 * 1144 * Complete GPU reset. 1145 */ 1146 int (*mode1_reset)(struct smu_context *smu); 1147 1148 /** 1149 * @mode2_reset: Perform mode2 reset. 1150 * 1151 * Mode2 reset generally does not reset as many IPs as mode1 reset. The 1152 * IPs reset varies by asic. 1153 */ 1154 int (*mode2_reset)(struct smu_context *smu); 1155 1156 /** 1157 * @get_dpm_ultimate_freq: Get the hard frequency range of a clock 1158 * domain in MHz. 1159 */ 1160 int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max); 1161 1162 /** 1163 * @set_soft_freq_limited_range: Set the soft frequency range of a clock 1164 * domain in MHz. 1165 */ 1166 int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max); 1167 1168 /** 1169 * @set_power_source: Notify the SMU of the current power source. 1170 */ 1171 int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src); 1172 1173 /** 1174 * @log_thermal_throttling_event: Print a thermal throttling warning to 1175 * the system's log. 1176 */ 1177 void (*log_thermal_throttling_event)(struct smu_context *smu); 1178 1179 /** 1180 * @get_pp_feature_mask: Print a human readable table of enabled 1181 * features to buffer. 1182 */ 1183 size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf); 1184 1185 /** 1186 * @set_pp_feature_mask: Request the SMU enable/disable features to 1187 * match those enabled in &new_mask. 1188 */ 1189 int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask); 1190 1191 /** 1192 * @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU. 1193 * 1194 * Return: Size of &table 1195 */ 1196 ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table); 1197 1198 /** 1199 * @enable_mgpu_fan_boost: Enable multi-GPU fan boost. 1200 */ 1201 int (*enable_mgpu_fan_boost)(struct smu_context *smu); 1202 1203 /** 1204 * @gfx_ulv_control: Enable/disable ultra low voltage. 1205 */ 1206 int (*gfx_ulv_control)(struct smu_context *smu, bool enablement); 1207 1208 /** 1209 * @deep_sleep_control: Enable/disable deep sleep. 1210 */ 1211 int (*deep_sleep_control)(struct smu_context *smu, bool enablement); 1212 1213 /** 1214 * @get_fan_parameters: Get fan parameters. 1215 * 1216 * Get maximum fan speed from the power play table. 1217 */ 1218 int (*get_fan_parameters)(struct smu_context *smu); 1219 1220 /** 1221 * @post_init: Helper function for asic specific workarounds. 1222 */ 1223 int (*post_init)(struct smu_context *smu); 1224 1225 /** 1226 * @interrupt_work: Work task scheduled from SMU interrupt handler. 1227 */ 1228 void (*interrupt_work)(struct smu_context *smu); 1229 1230 /** 1231 * @gpo_control: Enable/disable graphics power optimization if supported. 1232 */ 1233 int (*gpo_control)(struct smu_context *smu, bool enablement); 1234 1235 /** 1236 * @gfx_state_change_set: Send the current graphics state to the SMU. 1237 */ 1238 int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state); 1239 1240 /** 1241 * @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock 1242 * parameters to defaults. 1243 */ 1244 int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu); 1245 1246 /** 1247 * @set_light_sbr: Set light sbr mode for the SMU. 1248 */ 1249 int (*set_light_sbr)(struct smu_context *smu, bool enable); 1250 1251 /** 1252 * @wait_for_event: Wait for events from SMU. 1253 */ 1254 int (*wait_for_event)(struct smu_context *smu, 1255 enum smu_event_type event, uint64_t event_arg); 1256 1257 /** 1258 * @sned_hbm_bad_pages_num: message SMU to update bad page number 1259 * of SMUBUS table. 1260 */ 1261 int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size); 1262 }; 1263 1264 typedef enum { 1265 METRICS_CURR_GFXCLK, 1266 METRICS_CURR_SOCCLK, 1267 METRICS_CURR_UCLK, 1268 METRICS_CURR_VCLK, 1269 METRICS_CURR_VCLK1, 1270 METRICS_CURR_DCLK, 1271 METRICS_CURR_DCLK1, 1272 METRICS_CURR_FCLK, 1273 METRICS_CURR_DCEFCLK, 1274 METRICS_AVERAGE_CPUCLK, 1275 METRICS_AVERAGE_GFXCLK, 1276 METRICS_AVERAGE_SOCCLK, 1277 METRICS_AVERAGE_FCLK, 1278 METRICS_AVERAGE_UCLK, 1279 METRICS_AVERAGE_VCLK, 1280 METRICS_AVERAGE_DCLK, 1281 METRICS_AVERAGE_GFXACTIVITY, 1282 METRICS_AVERAGE_MEMACTIVITY, 1283 METRICS_AVERAGE_VCNACTIVITY, 1284 METRICS_AVERAGE_SOCKETPOWER, 1285 METRICS_TEMPERATURE_EDGE, 1286 METRICS_TEMPERATURE_HOTSPOT, 1287 METRICS_TEMPERATURE_MEM, 1288 METRICS_TEMPERATURE_VRGFX, 1289 METRICS_TEMPERATURE_VRSOC, 1290 METRICS_TEMPERATURE_VRMEM, 1291 METRICS_THROTTLER_STATUS, 1292 METRICS_CURR_FANSPEED, 1293 METRICS_VOLTAGE_VDDSOC, 1294 METRICS_VOLTAGE_VDDGFX, 1295 METRICS_SS_APU_SHARE, 1296 METRICS_SS_DGPU_SHARE, 1297 } MetricsMember_t; 1298 1299 enum smu_cmn2asic_mapping_type { 1300 CMN2ASIC_MAPPING_MSG, 1301 CMN2ASIC_MAPPING_CLK, 1302 CMN2ASIC_MAPPING_FEATURE, 1303 CMN2ASIC_MAPPING_TABLE, 1304 CMN2ASIC_MAPPING_PWR, 1305 CMN2ASIC_MAPPING_WORKLOAD, 1306 }; 1307 1308 #define MSG_MAP(msg, index, valid_in_vf) \ 1309 [SMU_MSG_##msg] = {1, (index), (valid_in_vf)} 1310 1311 #define CLK_MAP(clk, index) \ 1312 [SMU_##clk] = {1, (index)} 1313 1314 #define FEA_MAP(fea) \ 1315 [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT} 1316 1317 #define FEA_MAP_REVERSE(fea) \ 1318 [SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1319 1320 #define FEA_MAP_HALF_REVERSE(fea) \ 1321 [SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT} 1322 1323 #define TAB_MAP(tab) \ 1324 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1325 1326 #define TAB_MAP_VALID(tab) \ 1327 [SMU_TABLE_##tab] = {1, TABLE_##tab} 1328 1329 #define TAB_MAP_INVALID(tab) \ 1330 [SMU_TABLE_##tab] = {0, TABLE_##tab} 1331 1332 #define PWR_MAP(tab) \ 1333 [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab} 1334 1335 #define WORKLOAD_MAP(profile, workload) \ 1336 [profile] = {1, (workload)} 1337 1338 /** 1339 * smu_memcpy_trailing - Copy the end of one structure into the middle of another 1340 * 1341 * @dst: Pointer to destination struct 1342 * @first_dst_member: The member name in @dst where the overwrite begins 1343 * @last_dst_member: The member name in @dst where the overwrite ends after 1344 * @src: Pointer to the source struct 1345 * @first_src_member: The member name in @src where the copy begins 1346 * 1347 */ 1348 #define smu_memcpy_trailing(dst, first_dst_member, last_dst_member, \ 1349 src, first_src_member) \ 1350 ({ \ 1351 size_t __src_offset = offsetof(typeof(*(src)), first_src_member); \ 1352 size_t __src_size = sizeof(*(src)) - __src_offset; \ 1353 size_t __dst_offset = offsetof(typeof(*(dst)), first_dst_member); \ 1354 size_t __dst_size = offsetofend(typeof(*(dst)), last_dst_member) - \ 1355 __dst_offset; \ 1356 BUILD_BUG_ON(__src_size != __dst_size); \ 1357 __builtin_memcpy((u8 *)(dst) + __dst_offset, \ 1358 (u8 *)(src) + __src_offset, \ 1359 __dst_size); \ 1360 }) 1361 1362 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4) 1363 int smu_get_power_limit(void *handle, 1364 uint32_t *limit, 1365 enum pp_power_limit_level pp_limit_level, 1366 enum pp_power_type pp_power_type); 1367 1368 bool smu_mode1_reset_is_support(struct smu_context *smu); 1369 bool smu_mode2_reset_is_support(struct smu_context *smu); 1370 int smu_mode1_reset(struct smu_context *smu); 1371 1372 extern const struct amd_ip_funcs smu_ip_funcs; 1373 1374 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 1375 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 1376 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 1377 1378 bool is_support_sw_smu(struct amdgpu_device *adev); 1379 bool is_support_cclk_dpm(struct amdgpu_device *adev); 1380 int smu_write_watermarks_table(struct smu_context *smu); 1381 1382 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1383 uint32_t *min, uint32_t *max); 1384 1385 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1386 uint32_t min, uint32_t max); 1387 1388 int smu_set_ac_dc(struct smu_context *smu); 1389 1390 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en); 1391 1392 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value); 1393 1394 int smu_set_light_sbr(struct smu_context *smu, bool enable); 1395 1396 int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event, 1397 uint64_t event_arg); 1398 1399 #endif 1400 #endif 1401