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1 // SPDX-License-Identifier: GPL-2.0
2 /* pci.c: UltraSparc PCI controller support.
3  *
4  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
5  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
6  * Copyright (C) 1999 Jakub Jelinek   (jj@ultra.linux.cz)
7  *
8  * OF tree based PCI bus probing taken from the PowerPC port
9  * with minor modifications, see there for credits.
10  */
11 
12 #include <linux/export.h>
13 #include <linux/kernel.h>
14 #include <linux/string.h>
15 #include <linux/sched.h>
16 #include <linux/capability.h>
17 #include <linux/errno.h>
18 #include <linux/pci.h>
19 #include <linux/msi.h>
20 #include <linux/irq.h>
21 #include <linux/init.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/pgtable.h>
25 
26 #include <linux/uaccess.h>
27 #include <asm/irq.h>
28 #include <asm/prom.h>
29 #include <asm/apb.h>
30 
31 #include "pci_impl.h"
32 #include "kernel.h"
33 
34 /* List of all PCI controllers found in the system. */
35 struct pci_pbm_info *pci_pbm_root = NULL;
36 
37 /* Each PBM found gets a unique index. */
38 int pci_num_pbms = 0;
39 
40 volatile int pci_poke_in_progress;
41 volatile int pci_poke_cpu = -1;
42 volatile int pci_poke_faulted;
43 
44 static DEFINE_SPINLOCK(pci_poke_lock);
45 
pci_config_read8(u8 * addr,u8 * ret)46 void pci_config_read8(u8 *addr, u8 *ret)
47 {
48 	unsigned long flags;
49 	u8 byte;
50 
51 	spin_lock_irqsave(&pci_poke_lock, flags);
52 	pci_poke_cpu = smp_processor_id();
53 	pci_poke_in_progress = 1;
54 	pci_poke_faulted = 0;
55 	__asm__ __volatile__("membar #Sync\n\t"
56 			     "lduba [%1] %2, %0\n\t"
57 			     "membar #Sync"
58 			     : "=r" (byte)
59 			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
60 			     : "memory");
61 	pci_poke_in_progress = 0;
62 	pci_poke_cpu = -1;
63 	if (!pci_poke_faulted)
64 		*ret = byte;
65 	spin_unlock_irqrestore(&pci_poke_lock, flags);
66 }
67 
pci_config_read16(u16 * addr,u16 * ret)68 void pci_config_read16(u16 *addr, u16 *ret)
69 {
70 	unsigned long flags;
71 	u16 word;
72 
73 	spin_lock_irqsave(&pci_poke_lock, flags);
74 	pci_poke_cpu = smp_processor_id();
75 	pci_poke_in_progress = 1;
76 	pci_poke_faulted = 0;
77 	__asm__ __volatile__("membar #Sync\n\t"
78 			     "lduha [%1] %2, %0\n\t"
79 			     "membar #Sync"
80 			     : "=r" (word)
81 			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
82 			     : "memory");
83 	pci_poke_in_progress = 0;
84 	pci_poke_cpu = -1;
85 	if (!pci_poke_faulted)
86 		*ret = word;
87 	spin_unlock_irqrestore(&pci_poke_lock, flags);
88 }
89 
pci_config_read32(u32 * addr,u32 * ret)90 void pci_config_read32(u32 *addr, u32 *ret)
91 {
92 	unsigned long flags;
93 	u32 dword;
94 
95 	spin_lock_irqsave(&pci_poke_lock, flags);
96 	pci_poke_cpu = smp_processor_id();
97 	pci_poke_in_progress = 1;
98 	pci_poke_faulted = 0;
99 	__asm__ __volatile__("membar #Sync\n\t"
100 			     "lduwa [%1] %2, %0\n\t"
101 			     "membar #Sync"
102 			     : "=r" (dword)
103 			     : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
104 			     : "memory");
105 	pci_poke_in_progress = 0;
106 	pci_poke_cpu = -1;
107 	if (!pci_poke_faulted)
108 		*ret = dword;
109 	spin_unlock_irqrestore(&pci_poke_lock, flags);
110 }
111 
pci_config_write8(u8 * addr,u8 val)112 void pci_config_write8(u8 *addr, u8 val)
113 {
114 	unsigned long flags;
115 
116 	spin_lock_irqsave(&pci_poke_lock, flags);
117 	pci_poke_cpu = smp_processor_id();
118 	pci_poke_in_progress = 1;
119 	pci_poke_faulted = 0;
120 	__asm__ __volatile__("membar #Sync\n\t"
121 			     "stba %0, [%1] %2\n\t"
122 			     "membar #Sync"
123 			     : /* no outputs */
124 			     : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
125 			     : "memory");
126 	pci_poke_in_progress = 0;
127 	pci_poke_cpu = -1;
128 	spin_unlock_irqrestore(&pci_poke_lock, flags);
129 }
130 
pci_config_write16(u16 * addr,u16 val)131 void pci_config_write16(u16 *addr, u16 val)
132 {
133 	unsigned long flags;
134 
135 	spin_lock_irqsave(&pci_poke_lock, flags);
136 	pci_poke_cpu = smp_processor_id();
137 	pci_poke_in_progress = 1;
138 	pci_poke_faulted = 0;
139 	__asm__ __volatile__("membar #Sync\n\t"
140 			     "stha %0, [%1] %2\n\t"
141 			     "membar #Sync"
142 			     : /* no outputs */
143 			     : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
144 			     : "memory");
145 	pci_poke_in_progress = 0;
146 	pci_poke_cpu = -1;
147 	spin_unlock_irqrestore(&pci_poke_lock, flags);
148 }
149 
pci_config_write32(u32 * addr,u32 val)150 void pci_config_write32(u32 *addr, u32 val)
151 {
152 	unsigned long flags;
153 
154 	spin_lock_irqsave(&pci_poke_lock, flags);
155 	pci_poke_cpu = smp_processor_id();
156 	pci_poke_in_progress = 1;
157 	pci_poke_faulted = 0;
158 	__asm__ __volatile__("membar #Sync\n\t"
159 			     "stwa %0, [%1] %2\n\t"
160 			     "membar #Sync"
161 			     : /* no outputs */
162 			     : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
163 			     : "memory");
164 	pci_poke_in_progress = 0;
165 	pci_poke_cpu = -1;
166 	spin_unlock_irqrestore(&pci_poke_lock, flags);
167 }
168 
169 static int ofpci_verbose;
170 
ofpci_debug(char * str)171 static int __init ofpci_debug(char *str)
172 {
173 	int val = 0;
174 
175 	get_option(&str, &val);
176 	if (val)
177 		ofpci_verbose = 1;
178 	return 1;
179 }
180 
181 __setup("ofpci_debug=", ofpci_debug);
182 
pci_parse_of_flags(u32 addr0)183 static unsigned long pci_parse_of_flags(u32 addr0)
184 {
185 	unsigned long flags = 0;
186 
187 	if (addr0 & 0x02000000) {
188 		flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
189 		flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
190 		if (addr0 & 0x01000000)
191 			flags |= IORESOURCE_MEM_64
192 				 | PCI_BASE_ADDRESS_MEM_TYPE_64;
193 		if (addr0 & 0x40000000)
194 			flags |= IORESOURCE_PREFETCH
195 				 | PCI_BASE_ADDRESS_MEM_PREFETCH;
196 	} else if (addr0 & 0x01000000)
197 		flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
198 	return flags;
199 }
200 
201 /* The of_device layer has translated all of the assigned-address properties
202  * into physical address resources, we only have to figure out the register
203  * mapping.
204  */
pci_parse_of_addrs(struct platform_device * op,struct device_node * node,struct pci_dev * dev)205 static void pci_parse_of_addrs(struct platform_device *op,
206 			       struct device_node *node,
207 			       struct pci_dev *dev)
208 {
209 	struct resource *op_res;
210 	const u32 *addrs;
211 	int proplen;
212 
213 	addrs = of_get_property(node, "assigned-addresses", &proplen);
214 	if (!addrs)
215 		return;
216 	if (ofpci_verbose)
217 		pci_info(dev, "    parse addresses (%d bytes) @ %p\n",
218 			 proplen, addrs);
219 	op_res = &op->resource[0];
220 	for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
221 		struct resource *res;
222 		unsigned long flags;
223 		int i;
224 
225 		flags = pci_parse_of_flags(addrs[0]);
226 		if (!flags)
227 			continue;
228 		i = addrs[0] & 0xff;
229 		if (ofpci_verbose)
230 			pci_info(dev, "  start: %llx, end: %llx, i: %x\n",
231 				 op_res->start, op_res->end, i);
232 
233 		if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
234 			res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
235 		} else if (i == dev->rom_base_reg) {
236 			res = &dev->resource[PCI_ROM_RESOURCE];
237 			flags |= IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
238 		} else {
239 			pci_err(dev, "bad cfg reg num 0x%x\n", i);
240 			continue;
241 		}
242 		res->start = op_res->start;
243 		res->end = op_res->end;
244 		res->flags = flags;
245 		res->name = pci_name(dev);
246 
247 		pci_info(dev, "reg 0x%x: %pR\n", i, res);
248 	}
249 }
250 
pci_init_dev_archdata(struct dev_archdata * sd,void * iommu,void * stc,void * host_controller,struct platform_device * op,int numa_node)251 static void pci_init_dev_archdata(struct dev_archdata *sd, void *iommu,
252 				  void *stc, void *host_controller,
253 				  struct platform_device  *op,
254 				  int numa_node)
255 {
256 	sd->iommu = iommu;
257 	sd->stc = stc;
258 	sd->host_controller = host_controller;
259 	sd->op = op;
260 	sd->numa_node = numa_node;
261 }
262 
of_create_pci_dev(struct pci_pbm_info * pbm,struct device_node * node,struct pci_bus * bus,int devfn)263 static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
264 					 struct device_node *node,
265 					 struct pci_bus *bus, int devfn)
266 {
267 	struct dev_archdata *sd;
268 	struct platform_device *op;
269 	struct pci_dev *dev;
270 	u32 class;
271 
272 	dev = pci_alloc_dev(bus);
273 	if (!dev)
274 		return NULL;
275 
276 	op = of_find_device_by_node(node);
277 	sd = &dev->dev.archdata;
278 	pci_init_dev_archdata(sd, pbm->iommu, &pbm->stc, pbm, op,
279 			      pbm->numa_node);
280 	sd = &op->dev.archdata;
281 	sd->iommu = pbm->iommu;
282 	sd->stc = &pbm->stc;
283 	sd->numa_node = pbm->numa_node;
284 
285 	if (of_node_name_eq(node, "ebus"))
286 		of_propagate_archdata(op);
287 
288 	if (ofpci_verbose)
289 		pci_info(bus,"    create device, devfn: %x, type: %s\n",
290 			 devfn, of_node_get_device_type(node));
291 
292 	dev->sysdata = node;
293 	dev->dev.parent = bus->bridge;
294 	dev->dev.bus = &pci_bus_type;
295 	dev->dev.of_node = of_node_get(node);
296 	dev->devfn = devfn;
297 	dev->multifunction = 0;		/* maybe a lie? */
298 	set_pcie_port_type(dev);
299 
300 	pci_dev_assign_slot(dev);
301 	dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
302 	dev->device = of_getintprop_default(node, "device-id", 0xffff);
303 	dev->subsystem_vendor =
304 		of_getintprop_default(node, "subsystem-vendor-id", 0);
305 	dev->subsystem_device =
306 		of_getintprop_default(node, "subsystem-id", 0);
307 
308 	dev->cfg_size = pci_cfg_space_size(dev);
309 
310 	/* We can't actually use the firmware value, we have
311 	 * to read what is in the register right now.  One
312 	 * reason is that in the case of IDE interfaces the
313 	 * firmware can sample the value before the the IDE
314 	 * interface is programmed into native mode.
315 	 */
316 	pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
317 	dev->class = class >> 8;
318 	dev->revision = class & 0xff;
319 
320 	dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
321 		dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
322 
323 	/* I have seen IDE devices which will not respond to
324 	 * the bmdma simplex check reads if bus mastering is
325 	 * disabled.
326 	 */
327 	if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
328 		pci_set_master(dev);
329 
330 	dev->current_state = PCI_UNKNOWN;	/* unknown power state */
331 	dev->error_state = pci_channel_io_normal;
332 	dev->dma_mask = 0xffffffff;
333 
334 	if (of_node_name_eq(node, "pci")) {
335 		/* a PCI-PCI bridge */
336 		dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
337 		dev->rom_base_reg = PCI_ROM_ADDRESS1;
338 	} else if (of_node_is_type(node, "cardbus")) {
339 		dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
340 	} else {
341 		dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
342 		dev->rom_base_reg = PCI_ROM_ADDRESS;
343 
344 		dev->irq = sd->op->archdata.irqs[0];
345 		if (dev->irq == 0xffffffff)
346 			dev->irq = PCI_IRQ_NONE;
347 	}
348 
349 	pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
350 		 dev->vendor, dev->device, dev->hdr_type, dev->class);
351 
352 	pci_parse_of_addrs(sd->op, node, dev);
353 
354 	if (ofpci_verbose)
355 		pci_info(dev, "    adding to system ...\n");
356 
357 	pci_device_add(dev, bus);
358 
359 	return dev;
360 }
361 
apb_calc_first_last(u8 map,u32 * first_p,u32 * last_p)362 static void apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
363 {
364 	u32 idx, first, last;
365 
366 	first = 8;
367 	last = 0;
368 	for (idx = 0; idx < 8; idx++) {
369 		if ((map & (1 << idx)) != 0) {
370 			if (first > idx)
371 				first = idx;
372 			if (last < idx)
373 				last = idx;
374 		}
375 	}
376 
377 	*first_p = first;
378 	*last_p = last;
379 }
380 
381 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
382  * a proper 'ranges' property.
383  */
apb_fake_ranges(struct pci_dev * dev,struct pci_bus * bus,struct pci_pbm_info * pbm)384 static void apb_fake_ranges(struct pci_dev *dev,
385 			    struct pci_bus *bus,
386 			    struct pci_pbm_info *pbm)
387 {
388 	struct pci_bus_region region;
389 	struct resource *res;
390 	u32 first, last;
391 	u8 map;
392 
393 	pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
394 	apb_calc_first_last(map, &first, &last);
395 	res = bus->resource[0];
396 	res->flags = IORESOURCE_IO;
397 	region.start = (first << 21);
398 	region.end = (last << 21) + ((1 << 21) - 1);
399 	pcibios_bus_to_resource(dev->bus, res, &region);
400 
401 	pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
402 	apb_calc_first_last(map, &first, &last);
403 	res = bus->resource[1];
404 	res->flags = IORESOURCE_MEM;
405 	region.start = (first << 29);
406 	region.end = (last << 29) + ((1 << 29) - 1);
407 	pcibios_bus_to_resource(dev->bus, res, &region);
408 }
409 
410 static void pci_of_scan_bus(struct pci_pbm_info *pbm,
411 			    struct device_node *node,
412 			    struct pci_bus *bus);
413 
414 #define GET_64BIT(prop, i)	((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
415 
of_scan_pci_bridge(struct pci_pbm_info * pbm,struct device_node * node,struct pci_dev * dev)416 static void of_scan_pci_bridge(struct pci_pbm_info *pbm,
417 			       struct device_node *node,
418 			       struct pci_dev *dev)
419 {
420 	struct pci_bus *bus;
421 	const u32 *busrange, *ranges;
422 	int len, i, simba;
423 	struct pci_bus_region region;
424 	struct resource *res;
425 	unsigned int flags;
426 	u64 size;
427 
428 	if (ofpci_verbose)
429 		pci_info(dev, "of_scan_pci_bridge(%pOF)\n", node);
430 
431 	/* parse bus-range property */
432 	busrange = of_get_property(node, "bus-range", &len);
433 	if (busrange == NULL || len != 8) {
434 		pci_info(dev, "Can't get bus-range for PCI-PCI bridge %pOF\n",
435 		       node);
436 		return;
437 	}
438 
439 	if (ofpci_verbose)
440 		pci_info(dev, "    Bridge bus range [%u --> %u]\n",
441 			 busrange[0], busrange[1]);
442 
443 	ranges = of_get_property(node, "ranges", &len);
444 	simba = 0;
445 	if (ranges == NULL) {
446 		const char *model = of_get_property(node, "model", NULL);
447 		if (model && !strcmp(model, "SUNW,simba"))
448 			simba = 1;
449 	}
450 
451 	bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
452 	if (!bus) {
453 		pci_err(dev, "Failed to create pci bus for %pOF\n",
454 			node);
455 		return;
456 	}
457 
458 	bus->primary = dev->bus->number;
459 	pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
460 	bus->bridge_ctl = 0;
461 
462 	if (ofpci_verbose)
463 		pci_info(dev, "    Bridge ranges[%p] simba[%d]\n",
464 			 ranges, simba);
465 
466 	/* parse ranges property, or cook one up by hand for Simba */
467 	/* PCI #address-cells == 3 and #size-cells == 2 always */
468 	res = &dev->resource[PCI_BRIDGE_RESOURCES];
469 	for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
470 		res->flags = 0;
471 		bus->resource[i] = res;
472 		++res;
473 	}
474 	if (simba) {
475 		apb_fake_ranges(dev, bus, pbm);
476 		goto after_ranges;
477 	} else if (ranges == NULL) {
478 		pci_read_bridge_bases(bus);
479 		goto after_ranges;
480 	}
481 	i = 1;
482 	for (; len >= 32; len -= 32, ranges += 8) {
483 		u64 start;
484 
485 		if (ofpci_verbose)
486 			pci_info(dev, "    RAW Range[%08x:%08x:%08x:%08x:%08x:%08x:"
487 				 "%08x:%08x]\n",
488 				 ranges[0], ranges[1], ranges[2], ranges[3],
489 				 ranges[4], ranges[5], ranges[6], ranges[7]);
490 
491 		flags = pci_parse_of_flags(ranges[0]);
492 		size = GET_64BIT(ranges, 6);
493 		if (flags == 0 || size == 0)
494 			continue;
495 
496 		/* On PCI-Express systems, PCI bridges that have no devices downstream
497 		 * have a bogus size value where the first 32-bit cell is 0xffffffff.
498 		 * This results in a bogus range where start + size overflows.
499 		 *
500 		 * Just skip these otherwise the kernel will complain when the resource
501 		 * tries to be claimed.
502 		 */
503 		if (size >> 32 == 0xffffffff)
504 			continue;
505 
506 		if (flags & IORESOURCE_IO) {
507 			res = bus->resource[0];
508 			if (res->flags) {
509 				pci_err(dev, "ignoring extra I/O range"
510 					" for bridge %pOF\n", node);
511 				continue;
512 			}
513 		} else {
514 			if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
515 				pci_err(dev, "too many memory ranges"
516 					" for bridge %pOF\n", node);
517 				continue;
518 			}
519 			res = bus->resource[i];
520 			++i;
521 		}
522 
523 		res->flags = flags;
524 		region.start = start = GET_64BIT(ranges, 1);
525 		region.end = region.start + size - 1;
526 
527 		if (ofpci_verbose)
528 			pci_info(dev, "      Using flags[%08x] start[%016llx] size[%016llx]\n",
529 				 flags, start, size);
530 
531 		pcibios_bus_to_resource(dev->bus, res, &region);
532 	}
533 after_ranges:
534 	sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
535 		bus->number);
536 	if (ofpci_verbose)
537 		pci_info(dev, "    bus name: %s\n", bus->name);
538 
539 	pci_of_scan_bus(pbm, node, bus);
540 }
541 
pci_of_scan_bus(struct pci_pbm_info * pbm,struct device_node * node,struct pci_bus * bus)542 static void pci_of_scan_bus(struct pci_pbm_info *pbm,
543 			    struct device_node *node,
544 			    struct pci_bus *bus)
545 {
546 	struct device_node *child;
547 	const u32 *reg;
548 	int reglen, devfn, prev_devfn;
549 	struct pci_dev *dev;
550 
551 	if (ofpci_verbose)
552 		pci_info(bus, "scan_bus[%pOF] bus no %d\n",
553 			 node, bus->number);
554 
555 	prev_devfn = -1;
556 	for_each_child_of_node(node, child) {
557 		if (ofpci_verbose)
558 			pci_info(bus, "  * %pOF\n", child);
559 		reg = of_get_property(child, "reg", &reglen);
560 		if (reg == NULL || reglen < 20)
561 			continue;
562 
563 		devfn = (reg[0] >> 8) & 0xff;
564 
565 		/* This is a workaround for some device trees
566 		 * which list PCI devices twice.  On the V100
567 		 * for example, device number 3 is listed twice.
568 		 * Once as "pm" and once again as "lomp".
569 		 */
570 		if (devfn == prev_devfn)
571 			continue;
572 		prev_devfn = devfn;
573 
574 		/* create a new pci_dev for this device */
575 		dev = of_create_pci_dev(pbm, child, bus, devfn);
576 		if (!dev)
577 			continue;
578 		if (ofpci_verbose)
579 			pci_info(dev, "dev header type: %x\n", dev->hdr_type);
580 
581 		if (pci_is_bridge(dev))
582 			of_scan_pci_bridge(pbm, child, dev);
583 	}
584 }
585 
586 static ssize_t
show_pciobppath_attr(struct device * dev,struct device_attribute * attr,char * buf)587 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
588 {
589 	struct pci_dev *pdev;
590 	struct device_node *dp;
591 
592 	pdev = to_pci_dev(dev);
593 	dp = pdev->dev.of_node;
594 
595 	return scnprintf(buf, PAGE_SIZE, "%pOF\n", dp);
596 }
597 
598 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
599 
pci_bus_register_of_sysfs(struct pci_bus * bus)600 static void pci_bus_register_of_sysfs(struct pci_bus *bus)
601 {
602 	struct pci_dev *dev;
603 	struct pci_bus *child_bus;
604 	int err;
605 
606 	list_for_each_entry(dev, &bus->devices, bus_list) {
607 		/* we don't really care if we can create this file or
608 		 * not, but we need to assign the result of the call
609 		 * or the world will fall under alien invasion and
610 		 * everybody will be frozen on a spaceship ready to be
611 		 * eaten on alpha centauri by some green and jelly
612 		 * humanoid.
613 		 */
614 		err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
615 		(void) err;
616 	}
617 	list_for_each_entry(child_bus, &bus->children, node)
618 		pci_bus_register_of_sysfs(child_bus);
619 }
620 
pci_claim_legacy_resources(struct pci_dev * dev)621 static void pci_claim_legacy_resources(struct pci_dev *dev)
622 {
623 	struct pci_bus_region region;
624 	struct resource *p, *root, *conflict;
625 
626 	if ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
627 		return;
628 
629 	p = kzalloc(sizeof(*p), GFP_KERNEL);
630 	if (!p)
631 		return;
632 
633 	p->name = "Video RAM area";
634 	p->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
635 
636 	region.start = 0xa0000UL;
637 	region.end = region.start + 0x1ffffUL;
638 	pcibios_bus_to_resource(dev->bus, p, &region);
639 
640 	root = pci_find_parent_resource(dev, p);
641 	if (!root) {
642 		pci_info(dev, "can't claim VGA legacy %pR: no compatible bridge window\n", p);
643 		goto err;
644 	}
645 
646 	conflict = request_resource_conflict(root, p);
647 	if (conflict) {
648 		pci_info(dev, "can't claim VGA legacy %pR: address conflict with %s %pR\n",
649 			 p, conflict->name, conflict);
650 		goto err;
651 	}
652 
653 	pci_info(dev, "VGA legacy framebuffer %pR\n", p);
654 	return;
655 
656 err:
657 	kfree(p);
658 }
659 
pci_claim_bus_resources(struct pci_bus * bus)660 static void pci_claim_bus_resources(struct pci_bus *bus)
661 {
662 	struct pci_bus *child_bus;
663 	struct pci_dev *dev;
664 
665 	list_for_each_entry(dev, &bus->devices, bus_list) {
666 		int i;
667 
668 		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
669 			struct resource *r = &dev->resource[i];
670 
671 			if (r->parent || !r->start || !r->flags)
672 				continue;
673 
674 			if (ofpci_verbose)
675 				pci_info(dev, "Claiming Resource %d: %pR\n",
676 					 i, r);
677 
678 			pci_claim_resource(dev, i);
679 		}
680 
681 		pci_claim_legacy_resources(dev);
682 	}
683 
684 	list_for_each_entry(child_bus, &bus->children, node)
685 		pci_claim_bus_resources(child_bus);
686 }
687 
pci_scan_one_pbm(struct pci_pbm_info * pbm,struct device * parent)688 struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
689 				 struct device *parent)
690 {
691 	LIST_HEAD(resources);
692 	struct device_node *node = pbm->op->dev.of_node;
693 	struct pci_bus *bus;
694 
695 	printk("PCI: Scanning PBM %pOF\n", node);
696 
697 	pci_add_resource_offset(&resources, &pbm->io_space,
698 				pbm->io_offset);
699 	pci_add_resource_offset(&resources, &pbm->mem_space,
700 				pbm->mem_offset);
701 	if (pbm->mem64_space.flags)
702 		pci_add_resource_offset(&resources, &pbm->mem64_space,
703 					pbm->mem64_offset);
704 	pbm->busn.start = pbm->pci_first_busno;
705 	pbm->busn.end	= pbm->pci_last_busno;
706 	pbm->busn.flags	= IORESOURCE_BUS;
707 	pci_add_resource(&resources, &pbm->busn);
708 	bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
709 				  pbm, &resources);
710 	if (!bus) {
711 		printk(KERN_ERR "Failed to create bus for %pOF\n", node);
712 		pci_free_resource_list(&resources);
713 		return NULL;
714 	}
715 
716 	pci_of_scan_bus(pbm, node, bus);
717 	pci_bus_register_of_sysfs(bus);
718 
719 	pci_claim_bus_resources(bus);
720 
721 	pci_bus_add_devices(bus);
722 	return bus;
723 }
724 
pcibios_enable_device(struct pci_dev * dev,int mask)725 int pcibios_enable_device(struct pci_dev *dev, int mask)
726 {
727 	u16 cmd, oldcmd;
728 	int i;
729 
730 	pci_read_config_word(dev, PCI_COMMAND, &cmd);
731 	oldcmd = cmd;
732 
733 	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
734 		struct resource *res = &dev->resource[i];
735 
736 		/* Only set up the requested stuff */
737 		if (!(mask & (1<<i)))
738 			continue;
739 
740 		if (res->flags & IORESOURCE_IO)
741 			cmd |= PCI_COMMAND_IO;
742 		if (res->flags & IORESOURCE_MEM)
743 			cmd |= PCI_COMMAND_MEMORY;
744 	}
745 
746 	if (cmd != oldcmd) {
747 		pci_info(dev, "enabling device (%04x -> %04x)\n", oldcmd, cmd);
748 		pci_write_config_word(dev, PCI_COMMAND, cmd);
749 	}
750 	return 0;
751 }
752 
753 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
754 
755 /* If the user uses a host-bridge as the PCI device, he may use
756  * this to perform a raw mmap() of the I/O or MEM space behind
757  * that controller.
758  *
759  * This can be useful for execution of x86 PCI bios initialization code
760  * on a PCI card, like the xfree86 int10 stuff does.
761  */
__pci_mmap_make_offset_bus(struct pci_dev * pdev,struct vm_area_struct * vma,enum pci_mmap_state mmap_state)762 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
763 				      enum pci_mmap_state mmap_state)
764 {
765 	struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
766 	unsigned long space_size, user_offset, user_size;
767 
768 	if (mmap_state == pci_mmap_io) {
769 		space_size = resource_size(&pbm->io_space);
770 	} else {
771 		space_size = resource_size(&pbm->mem_space);
772 	}
773 
774 	/* Make sure the request is in range. */
775 	user_offset = vma->vm_pgoff << PAGE_SHIFT;
776 	user_size = vma->vm_end - vma->vm_start;
777 
778 	if (user_offset >= space_size ||
779 	    (user_offset + user_size) > space_size)
780 		return -EINVAL;
781 
782 	if (mmap_state == pci_mmap_io) {
783 		vma->vm_pgoff = (pbm->io_space.start +
784 				 user_offset) >> PAGE_SHIFT;
785 	} else {
786 		vma->vm_pgoff = (pbm->mem_space.start +
787 				 user_offset) >> PAGE_SHIFT;
788 	}
789 
790 	return 0;
791 }
792 
793 /* Adjust vm_pgoff of VMA such that it is the physical page offset
794  * corresponding to the 32-bit pci bus offset for DEV requested by the user.
795  *
796  * Basically, the user finds the base address for his device which he wishes
797  * to mmap.  They read the 32-bit value from the config space base register,
798  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
799  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
800  *
801  * Returns negative error code on failure, zero on success.
802  */
__pci_mmap_make_offset(struct pci_dev * pdev,struct vm_area_struct * vma,enum pci_mmap_state mmap_state)803 static int __pci_mmap_make_offset(struct pci_dev *pdev,
804 				  struct vm_area_struct *vma,
805 				  enum pci_mmap_state mmap_state)
806 {
807 	unsigned long user_paddr, user_size;
808 	int i, err;
809 
810 	/* First compute the physical address in vma->vm_pgoff,
811 	 * making sure the user offset is within range in the
812 	 * appropriate PCI space.
813 	 */
814 	err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state);
815 	if (err)
816 		return err;
817 
818 	/* If this is a mapping on a host bridge, any address
819 	 * is OK.
820 	 */
821 	if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
822 		return err;
823 
824 	/* Otherwise make sure it's in the range for one of the
825 	 * device's resources.
826 	 */
827 	user_paddr = vma->vm_pgoff << PAGE_SHIFT;
828 	user_size = vma->vm_end - vma->vm_start;
829 
830 	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
831 		struct resource *rp = &pdev->resource[i];
832 		resource_size_t aligned_end;
833 
834 		/* Active? */
835 		if (!rp->flags)
836 			continue;
837 
838 		/* Same type? */
839 		if (i == PCI_ROM_RESOURCE) {
840 			if (mmap_state != pci_mmap_mem)
841 				continue;
842 		} else {
843 			if ((mmap_state == pci_mmap_io &&
844 			     (rp->flags & IORESOURCE_IO) == 0) ||
845 			    (mmap_state == pci_mmap_mem &&
846 			     (rp->flags & IORESOURCE_MEM) == 0))
847 				continue;
848 		}
849 
850 		/* Align the resource end to the next page address.
851 		 * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1),
852 		 * because actually we need the address of the next byte
853 		 * after rp->end.
854 		 */
855 		aligned_end = (rp->end + PAGE_SIZE) & PAGE_MASK;
856 
857 		if ((rp->start <= user_paddr) &&
858 		    (user_paddr + user_size) <= aligned_end)
859 			break;
860 	}
861 
862 	if (i > PCI_ROM_RESOURCE)
863 		return -EINVAL;
864 
865 	return 0;
866 }
867 
868 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
869  * device mapping.
870  */
__pci_mmap_set_pgprot(struct pci_dev * dev,struct vm_area_struct * vma,enum pci_mmap_state mmap_state)871 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
872 					     enum pci_mmap_state mmap_state)
873 {
874 	/* Our io_remap_pfn_range takes care of this, do nothing.  */
875 }
876 
877 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
878  * for this architecture.  The region in the process to map is described by vm_start
879  * and vm_end members of VMA, the base physical address is found in vm_pgoff.
880  * The pci device structure is provided so that architectures may make mapping
881  * decisions on a per-device or per-bus basis.
882  *
883  * Returns a negative error code on failure, zero on success.
884  */
pci_mmap_page_range(struct pci_dev * dev,int bar,struct vm_area_struct * vma,enum pci_mmap_state mmap_state,int write_combine)885 int pci_mmap_page_range(struct pci_dev *dev, int bar,
886 			struct vm_area_struct *vma,
887 			enum pci_mmap_state mmap_state, int write_combine)
888 {
889 	int ret;
890 
891 	ret = __pci_mmap_make_offset(dev, vma, mmap_state);
892 	if (ret < 0)
893 		return ret;
894 
895 	__pci_mmap_set_pgprot(dev, vma, mmap_state);
896 
897 	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
898 	ret = io_remap_pfn_range(vma, vma->vm_start,
899 				 vma->vm_pgoff,
900 				 vma->vm_end - vma->vm_start,
901 				 vma->vm_page_prot);
902 	if (ret)
903 		return ret;
904 
905 	return 0;
906 }
907 
908 #ifdef CONFIG_NUMA
pcibus_to_node(struct pci_bus * pbus)909 int pcibus_to_node(struct pci_bus *pbus)
910 {
911 	struct pci_pbm_info *pbm = pbus->sysdata;
912 
913 	return pbm->numa_node;
914 }
915 EXPORT_SYMBOL(pcibus_to_node);
916 #endif
917 
918 /* Return the domain number for this pci bus */
919 
pci_domain_nr(struct pci_bus * pbus)920 int pci_domain_nr(struct pci_bus *pbus)
921 {
922 	struct pci_pbm_info *pbm = pbus->sysdata;
923 	int ret;
924 
925 	if (!pbm) {
926 		ret = -ENXIO;
927 	} else {
928 		ret = pbm->index;
929 	}
930 
931 	return ret;
932 }
933 EXPORT_SYMBOL(pci_domain_nr);
934 
935 #ifdef CONFIG_PCI_MSI
arch_setup_msi_irq(struct pci_dev * pdev,struct msi_desc * desc)936 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
937 {
938 	struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
939 	unsigned int irq;
940 
941 	if (!pbm->setup_msi_irq)
942 		return -EINVAL;
943 
944 	return pbm->setup_msi_irq(&irq, pdev, desc);
945 }
946 
arch_teardown_msi_irq(unsigned int irq)947 void arch_teardown_msi_irq(unsigned int irq)
948 {
949 	struct msi_desc *entry = irq_get_msi_desc(irq);
950 	struct pci_dev *pdev = msi_desc_to_pci_dev(entry);
951 	struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
952 
953 	if (pbm->teardown_msi_irq)
954 		pbm->teardown_msi_irq(irq, pdev);
955 }
956 #endif /* !(CONFIG_PCI_MSI) */
957 
958 /* ALI sound chips generate 31-bits of DMA, a special register
959  * determines what bit 31 is emitted as.
960  */
ali_sound_dma_hack(struct device * dev,u64 device_mask)961 int ali_sound_dma_hack(struct device *dev, u64 device_mask)
962 {
963 	struct iommu *iommu = dev->archdata.iommu;
964 	struct pci_dev *ali_isa_bridge;
965 	u8 val;
966 
967 	if (!dev_is_pci(dev))
968 		return 0;
969 
970 	if (to_pci_dev(dev)->vendor != PCI_VENDOR_ID_AL ||
971 	    to_pci_dev(dev)->device != PCI_DEVICE_ID_AL_M5451 ||
972 	    device_mask != 0x7fffffff)
973 		return 0;
974 
975 	ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
976 					 PCI_DEVICE_ID_AL_M1533,
977 					 NULL);
978 
979 	pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
980 	if (iommu->dma_addr_mask & 0x80000000)
981 		val |= 0x01;
982 	else
983 		val &= ~0x01;
984 	pci_write_config_byte(ali_isa_bridge, 0x7e, val);
985 	pci_dev_put(ali_isa_bridge);
986 	return 1;
987 }
988 
pci_resource_to_user(const struct pci_dev * pdev,int bar,const struct resource * rp,resource_size_t * start,resource_size_t * end)989 void pci_resource_to_user(const struct pci_dev *pdev, int bar,
990 			  const struct resource *rp, resource_size_t *start,
991 			  resource_size_t *end)
992 {
993 	struct pci_bus_region region;
994 
995 	/*
996 	 * "User" addresses are shown in /sys/devices/pci.../.../resource
997 	 * and /proc/bus/pci/devices and used as mmap offsets for
998 	 * /proc/bus/pci/BB/DD.F files (see proc_bus_pci_mmap()).
999 	 *
1000 	 * On sparc, these are PCI bus addresses, i.e., raw BAR values.
1001 	 */
1002 	pcibios_resource_to_bus(pdev->bus, &region, (struct resource *) rp);
1003 	*start = region.start;
1004 	*end = region.end;
1005 }
1006 
pcibios_set_master(struct pci_dev * dev)1007 void pcibios_set_master(struct pci_dev *dev)
1008 {
1009 	/* No special bus mastering setup handling */
1010 }
1011 
1012 #ifdef CONFIG_PCI_IOV
pcibios_add_device(struct pci_dev * dev)1013 int pcibios_add_device(struct pci_dev *dev)
1014 {
1015 	struct pci_dev *pdev;
1016 
1017 	/* Add sriov arch specific initialization here.
1018 	 * Copy dev_archdata from PF to VF
1019 	 */
1020 	if (dev->is_virtfn) {
1021 		struct dev_archdata *psd;
1022 
1023 		pdev = dev->physfn;
1024 		psd = &pdev->dev.archdata;
1025 		pci_init_dev_archdata(&dev->dev.archdata, psd->iommu,
1026 				      psd->stc, psd->host_controller, NULL,
1027 				      psd->numa_node);
1028 	}
1029 	return 0;
1030 }
1031 #endif /* CONFIG_PCI_IOV */
1032 
pcibios_init(void)1033 static int __init pcibios_init(void)
1034 {
1035 	pci_dfl_cache_line_size = 64 >> 2;
1036 	return 0;
1037 }
1038 subsys_initcall(pcibios_init);
1039 
1040 #ifdef CONFIG_SYSFS
1041 
1042 #define SLOT_NAME_SIZE  11  /* Max decimal digits + null in u32 */
1043 
pcie_bus_slot_names(struct pci_bus * pbus)1044 static void pcie_bus_slot_names(struct pci_bus *pbus)
1045 {
1046 	struct pci_dev *pdev;
1047 	struct pci_bus *bus;
1048 
1049 	list_for_each_entry(pdev, &pbus->devices, bus_list) {
1050 		char name[SLOT_NAME_SIZE];
1051 		struct pci_slot *pci_slot;
1052 		const u32 *slot_num;
1053 		int len;
1054 
1055 		slot_num = of_get_property(pdev->dev.of_node,
1056 					   "physical-slot#", &len);
1057 
1058 		if (slot_num == NULL || len != 4)
1059 			continue;
1060 
1061 		snprintf(name, sizeof(name), "%u", slot_num[0]);
1062 		pci_slot = pci_create_slot(pbus, slot_num[0], name, NULL);
1063 
1064 		if (IS_ERR(pci_slot))
1065 			pr_err("PCI: pci_create_slot returned %ld.\n",
1066 			       PTR_ERR(pci_slot));
1067 	}
1068 
1069 	list_for_each_entry(bus, &pbus->children, node)
1070 		pcie_bus_slot_names(bus);
1071 }
1072 
pci_bus_slot_names(struct device_node * node,struct pci_bus * bus)1073 static void pci_bus_slot_names(struct device_node *node, struct pci_bus *bus)
1074 {
1075 	const struct pci_slot_names {
1076 		u32	slot_mask;
1077 		char	names[0];
1078 	} *prop;
1079 	const char *sp;
1080 	int len, i;
1081 	u32 mask;
1082 
1083 	prop = of_get_property(node, "slot-names", &len);
1084 	if (!prop)
1085 		return;
1086 
1087 	mask = prop->slot_mask;
1088 	sp = prop->names;
1089 
1090 	if (ofpci_verbose)
1091 		pci_info(bus, "Making slots for [%pOF] mask[0x%02x]\n",
1092 			 node, mask);
1093 
1094 	i = 0;
1095 	while (mask) {
1096 		struct pci_slot *pci_slot;
1097 		u32 this_bit = 1 << i;
1098 
1099 		if (!(mask & this_bit)) {
1100 			i++;
1101 			continue;
1102 		}
1103 
1104 		if (ofpci_verbose)
1105 			pci_info(bus, "Making slot [%s]\n", sp);
1106 
1107 		pci_slot = pci_create_slot(bus, i, sp, NULL);
1108 		if (IS_ERR(pci_slot))
1109 			pci_err(bus, "pci_create_slot returned %ld\n",
1110 				PTR_ERR(pci_slot));
1111 
1112 		sp += strlen(sp) + 1;
1113 		mask &= ~this_bit;
1114 		i++;
1115 	}
1116 }
1117 
of_pci_slot_init(void)1118 static int __init of_pci_slot_init(void)
1119 {
1120 	struct pci_bus *pbus = NULL;
1121 
1122 	while ((pbus = pci_find_next_bus(pbus)) != NULL) {
1123 		struct device_node *node;
1124 		struct pci_dev *pdev;
1125 
1126 		pdev = list_first_entry(&pbus->devices, struct pci_dev,
1127 					bus_list);
1128 
1129 		if (pdev && pci_is_pcie(pdev)) {
1130 			pcie_bus_slot_names(pbus);
1131 		} else {
1132 
1133 			if (pbus->self) {
1134 
1135 				/* PCI->PCI bridge */
1136 				node = pbus->self->dev.of_node;
1137 
1138 			} else {
1139 				struct pci_pbm_info *pbm = pbus->sysdata;
1140 
1141 				/* Host PCI controller */
1142 				node = pbm->op->dev.of_node;
1143 			}
1144 
1145 			pci_bus_slot_names(node, pbus);
1146 		}
1147 	}
1148 
1149 	return 0;
1150 }
1151 device_initcall(of_pci_slot_init);
1152 #endif
1153