1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * pci.h
4 *
5 * PCI defines and function prototypes
6 * Copyright 1994, Drew Eckhardt
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 *
9 * PCI Express ASPM defines and function prototypes
10 * Copyright (c) 2007 Intel Corp.
11 * Zhang Yanmin (yanmin.zhang@intel.com)
12 * Shaohua Li (shaohua.li@intel.com)
13 *
14 * For more information, please consult the following manuals (look at
15 * http://www.pcisig.com/ for how to get them):
16 *
17 * PCI BIOS Specification
18 * PCI Local Bus Specification
19 * PCI to PCI Bridge Specification
20 * PCI Express Specification
21 * PCI System Design Guide
22 */
23 #ifndef LINUX_PCI_H
24 #define LINUX_PCI_H
25
26
27 #include <linux/mod_devicetable.h>
28
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/compiler.h>
34 #include <linux/errno.h>
35 #include <linux/kobject.h>
36 #include <linux/atomic.h>
37 #include <linux/device.h>
38 #include <linux/interrupt.h>
39 #include <linux/io.h>
40 #include <linux/resource_ext.h>
41 #include <uapi/linux/pci.h>
42
43 #include <linux/pci_ids.h>
44 #include <linux/android_kabi.h>
45
46 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
47 PCI_STATUS_SIG_SYSTEM_ERROR | \
48 PCI_STATUS_REC_MASTER_ABORT | \
49 PCI_STATUS_REC_TARGET_ABORT | \
50 PCI_STATUS_SIG_TARGET_ABORT | \
51 PCI_STATUS_PARITY)
52
53 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */
54 #define PCI_NUM_RESET_METHODS 7
55
56 #define PCI_RESET_PROBE true
57 #define PCI_RESET_DO_RESET false
58
59 /*
60 * The PCI interface treats multi-function devices as independent
61 * devices. The slot/function address of each device is encoded
62 * in a single byte as follows:
63 *
64 * 7:3 = slot
65 * 2:0 = function
66 *
67 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
68 * In the interest of not exposing interfaces to user-space unnecessarily,
69 * the following kernel-only defines are being added here.
70 */
71 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
72 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
73 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
74
75 /* pci_slot represents a physical slot */
76 struct pci_slot {
77 struct pci_bus *bus; /* Bus this slot is on */
78 struct list_head list; /* Node in list of slots */
79 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
80 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
81 struct kobject kobj;
82 };
83
pci_slot_name(const struct pci_slot * slot)84 static inline const char *pci_slot_name(const struct pci_slot *slot)
85 {
86 return kobject_name(&slot->kobj);
87 }
88
89 /* File state for mmap()s on /proc/bus/pci/X/Y */
90 enum pci_mmap_state {
91 pci_mmap_io,
92 pci_mmap_mem
93 };
94
95 /* For PCI devices, the region numbers are assigned this way: */
96 enum {
97 /* #0-5: standard PCI resources */
98 PCI_STD_RESOURCES,
99 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
100
101 /* #6: expansion ROM resource */
102 PCI_ROM_RESOURCE,
103
104 /* Device-specific resources */
105 #ifdef CONFIG_PCI_IOV
106 PCI_IOV_RESOURCES,
107 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
108 #endif
109
110 /* PCI-to-PCI (P2P) bridge windows */
111 #define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
112 #define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
113 #define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
114
115 /* CardBus bridge windows */
116 #define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
117 #define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
118 #define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
119 #define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
120
121 /* Total number of bridge resources for P2P and CardBus */
122 #define PCI_BRIDGE_RESOURCE_NUM 4
123
124 /* Resources assigned to buses behind the bridge */
125 PCI_BRIDGE_RESOURCES,
126 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
127 PCI_BRIDGE_RESOURCE_NUM - 1,
128
129 /* Total resources associated with a PCI device */
130 PCI_NUM_RESOURCES,
131
132 /* Preserve this for compatibility */
133 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
134 };
135
136 /**
137 * enum pci_interrupt_pin - PCI INTx interrupt values
138 * @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
139 * @PCI_INTERRUPT_INTA: PCI INTA pin
140 * @PCI_INTERRUPT_INTB: PCI INTB pin
141 * @PCI_INTERRUPT_INTC: PCI INTC pin
142 * @PCI_INTERRUPT_INTD: PCI INTD pin
143 *
144 * Corresponds to values for legacy PCI INTx interrupts, as can be found in the
145 * PCI_INTERRUPT_PIN register.
146 */
147 enum pci_interrupt_pin {
148 PCI_INTERRUPT_UNKNOWN,
149 PCI_INTERRUPT_INTA,
150 PCI_INTERRUPT_INTB,
151 PCI_INTERRUPT_INTC,
152 PCI_INTERRUPT_INTD,
153 };
154
155 /* The number of legacy PCI INTx interrupts */
156 #define PCI_NUM_INTX 4
157
158 /*
159 * pci_power_t values must match the bits in the Capabilities PME_Support
160 * and Control/Status PowerState fields in the Power Management capability.
161 */
162 typedef int __bitwise pci_power_t;
163
164 #define PCI_D0 ((pci_power_t __force) 0)
165 #define PCI_D1 ((pci_power_t __force) 1)
166 #define PCI_D2 ((pci_power_t __force) 2)
167 #define PCI_D3hot ((pci_power_t __force) 3)
168 #define PCI_D3cold ((pci_power_t __force) 4)
169 #define PCI_UNKNOWN ((pci_power_t __force) 5)
170 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
171
172 /* Remember to update this when the list above changes! */
173 extern const char *pci_power_names[];
174
pci_power_name(pci_power_t state)175 static inline const char *pci_power_name(pci_power_t state)
176 {
177 return pci_power_names[1 + (__force int) state];
178 }
179
180 /**
181 * typedef pci_channel_state_t
182 *
183 * The pci_channel state describes connectivity between the CPU and
184 * the PCI device. If some PCI bus between here and the PCI device
185 * has crashed or locked up, this info is reflected here.
186 */
187 typedef unsigned int __bitwise pci_channel_state_t;
188
189 enum {
190 /* I/O channel is in normal state */
191 pci_channel_io_normal = (__force pci_channel_state_t) 1,
192
193 /* I/O to channel is blocked */
194 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
195
196 /* PCI card is dead */
197 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
198 };
199
200 typedef unsigned int __bitwise pcie_reset_state_t;
201
202 enum pcie_reset_state {
203 /* Reset is NOT asserted (Use to deassert reset) */
204 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
205
206 /* Use #PERST to reset PCIe device */
207 pcie_warm_reset = (__force pcie_reset_state_t) 2,
208
209 /* Use PCIe Hot Reset to reset device */
210 pcie_hot_reset = (__force pcie_reset_state_t) 3
211 };
212
213 typedef unsigned short __bitwise pci_dev_flags_t;
214 enum pci_dev_flags {
215 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
216 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
217 /* Device configuration is irrevocably lost if disabled into D3 */
218 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
219 /* Provide indication device is assigned by a Virtual Machine Manager */
220 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
221 /* Flag for quirk use to store if quirk-specific ACS is enabled */
222 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
223 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
224 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
225 /* Do not use bus resets for device */
226 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
227 /* Do not use PM reset even if device advertises NoSoftRst- */
228 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
229 /* Get VPD from function 0 VPD */
230 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
231 /* A non-root bridge where translation occurs, stop alias search here */
232 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
233 /* Do not use FLR even if device advertises PCI_AF_CAP */
234 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
235 /* Don't use Relaxed Ordering for TLPs directed at this device */
236 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
237 /* Device does honor MSI masking despite saying otherwise */
238 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
239 };
240
241 enum pci_irq_reroute_variant {
242 INTEL_IRQ_REROUTE_VARIANT = 1,
243 MAX_IRQ_REROUTE_VARIANTS = 3
244 };
245
246 typedef unsigned short __bitwise pci_bus_flags_t;
247 enum pci_bus_flags {
248 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
249 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
250 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
251 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
252 };
253
254 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
255 enum pcie_link_width {
256 PCIE_LNK_WIDTH_RESRV = 0x00,
257 PCIE_LNK_X1 = 0x01,
258 PCIE_LNK_X2 = 0x02,
259 PCIE_LNK_X4 = 0x04,
260 PCIE_LNK_X8 = 0x08,
261 PCIE_LNK_X12 = 0x0c,
262 PCIE_LNK_X16 = 0x10,
263 PCIE_LNK_X32 = 0x20,
264 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
265 };
266
267 /* See matching string table in pci_speed_string() */
268 enum pci_bus_speed {
269 PCI_SPEED_33MHz = 0x00,
270 PCI_SPEED_66MHz = 0x01,
271 PCI_SPEED_66MHz_PCIX = 0x02,
272 PCI_SPEED_100MHz_PCIX = 0x03,
273 PCI_SPEED_133MHz_PCIX = 0x04,
274 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
275 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
276 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
277 PCI_SPEED_66MHz_PCIX_266 = 0x09,
278 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
279 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
280 AGP_UNKNOWN = 0x0c,
281 AGP_1X = 0x0d,
282 AGP_2X = 0x0e,
283 AGP_4X = 0x0f,
284 AGP_8X = 0x10,
285 PCI_SPEED_66MHz_PCIX_533 = 0x11,
286 PCI_SPEED_100MHz_PCIX_533 = 0x12,
287 PCI_SPEED_133MHz_PCIX_533 = 0x13,
288 PCIE_SPEED_2_5GT = 0x14,
289 PCIE_SPEED_5_0GT = 0x15,
290 PCIE_SPEED_8_0GT = 0x16,
291 PCIE_SPEED_16_0GT = 0x17,
292 PCIE_SPEED_32_0GT = 0x18,
293 PCIE_SPEED_64_0GT = 0x19,
294 PCI_SPEED_UNKNOWN = 0xff,
295 };
296
297 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
298 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
299
300 struct pci_vpd {
301 struct mutex lock;
302 unsigned int len;
303 u8 cap;
304 };
305
306 struct irq_affinity;
307 struct pcie_link_state;
308 struct pci_sriov;
309 struct pci_p2pdma;
310 struct rcec_ea;
311
312 /* The pci_dev structure describes PCI devices */
313 struct pci_dev {
314 struct list_head bus_list; /* Node in per-bus list */
315 struct pci_bus *bus; /* Bus this device is on */
316 struct pci_bus *subordinate; /* Bus this device bridges to */
317
318 void *sysdata; /* Hook for sys-specific extension */
319 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
320 struct pci_slot *slot; /* Physical slot this device is in */
321
322 unsigned int devfn; /* Encoded device & function index */
323 unsigned short vendor;
324 unsigned short device;
325 unsigned short subsystem_vendor;
326 unsigned short subsystem_device;
327 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
328 u8 revision; /* PCI revision, low byte of class word */
329 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
330 #ifdef CONFIG_PCIEAER
331 u16 aer_cap; /* AER capability offset */
332 struct aer_stats *aer_stats; /* AER stats for this device */
333 #endif
334 #ifdef CONFIG_PCIEPORTBUS
335 struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
336 struct pci_dev *rcec; /* Associated RCEC device */
337 #endif
338 u32 devcap; /* PCIe Device Capabilities */
339 u8 pcie_cap; /* PCIe capability offset */
340 u8 msi_cap; /* MSI capability offset */
341 u8 msix_cap; /* MSI-X capability offset */
342 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
343 u8 rom_base_reg; /* Config register controlling ROM */
344 u8 pin; /* Interrupt pin this device uses */
345 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
346 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
347
348 struct pci_driver *driver; /* Driver bound to this device */
349 u64 dma_mask; /* Mask of the bits of bus address this
350 device implements. Normally this is
351 0xffffffff. You only need to change
352 this if your device has broken DMA
353 or supports 64-bit transfers. */
354
355 struct device_dma_parameters dma_parms;
356
357 pci_power_t current_state; /* Current operating state. In ACPI,
358 this is D0-D3, D0 being fully
359 functional, and D3 being off. */
360 unsigned int imm_ready:1; /* Supports Immediate Readiness */
361 u8 pm_cap; /* PM capability offset */
362 unsigned int pme_support:5; /* Bitmask of states from which PME#
363 can be generated */
364 unsigned int pme_poll:1; /* Poll device's PME status bit */
365 unsigned int d1_support:1; /* Low power state D1 is supported */
366 unsigned int d2_support:1; /* Low power state D2 is supported */
367 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
368 unsigned int no_d3cold:1; /* D3cold is forbidden */
369 unsigned int bridge_d3:1; /* Allow D3 for bridge */
370 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
371 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
372 decoding during BAR sizing */
373 unsigned int wakeup_prepared:1;
374 unsigned int runtime_d3cold:1; /* Whether go through runtime
375 D3cold, not set for devices
376 powered on/off by the
377 corresponding bridge */
378 unsigned int skip_bus_pm:1; /* Internal: Skip bus-level PM */
379 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
380 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
381 controlled exclusively by
382 user sysfs */
383 unsigned int clear_retrain_link:1; /* Need to clear Retrain Link
384 bit manually */
385 unsigned int d3hot_delay; /* D3hot->D0 transition time in ms */
386 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
387
388 #ifdef CONFIG_PCIEASPM
389 struct pcie_link_state *link_state; /* ASPM link state */
390 unsigned int ltr_path:1; /* Latency Tolerance Reporting
391 supported from root to here */
392 u16 l1ss; /* L1SS Capability pointer */
393 #endif
394 unsigned int pasid_no_tlp:1; /* PASID works without TLP Prefix */
395 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
396
397 pci_channel_state_t error_state; /* Current connectivity state */
398 struct device dev; /* Generic device interface */
399
400 int cfg_size; /* Size of config space */
401
402 /*
403 * Instead of touching interrupt line and base address registers
404 * directly, use the values stored here. They might be different!
405 */
406 unsigned int irq;
407 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
408
409 bool match_driver; /* Skip attaching driver */
410
411 unsigned int transparent:1; /* Subtractive decode bridge */
412 unsigned int io_window:1; /* Bridge has I/O window */
413 unsigned int pref_window:1; /* Bridge has pref mem window */
414 unsigned int pref_64_window:1; /* Pref mem window is 64-bit */
415 unsigned int multifunction:1; /* Multi-function device */
416
417 unsigned int is_busmaster:1; /* Is busmaster */
418 unsigned int no_msi:1; /* May not use MSI */
419 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
420 unsigned int block_cfg_access:1; /* Config space access blocked */
421 unsigned int broken_parity_status:1; /* Generates false positive parity */
422 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
423 unsigned int msi_enabled:1;
424 unsigned int msix_enabled:1;
425 unsigned int ari_enabled:1; /* ARI forwarding */
426 unsigned int ats_enabled:1; /* Address Translation Svc */
427 unsigned int pasid_enabled:1; /* Process Address Space ID */
428 unsigned int pri_enabled:1; /* Page Request Interface */
429 unsigned int is_managed:1;
430 unsigned int needs_freset:1; /* Requires fundamental reset */
431 unsigned int state_saved:1;
432 unsigned int is_physfn:1;
433 unsigned int is_virtfn:1;
434 unsigned int is_hotplug_bridge:1;
435 unsigned int shpc_managed:1; /* SHPC owned by shpchp */
436 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
437 /*
438 * Devices marked being untrusted are the ones that can potentially
439 * execute DMA attacks and similar. They are typically connected
440 * through external ports such as Thunderbolt but not limited to
441 * that. When an IOMMU is enabled they should be getting full
442 * mappings to make sure they cannot access arbitrary memory.
443 */
444 unsigned int untrusted:1;
445 /*
446 * Info from the platform, e.g., ACPI or device tree, may mark a
447 * device as "external-facing". An external-facing device is
448 * itself internal but devices downstream from it are external.
449 */
450 unsigned int external_facing:1;
451 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
452 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
453 unsigned int irq_managed:1;
454 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
455 unsigned int is_probed:1; /* Device probing in progress */
456 unsigned int link_active_reporting:1;/* Device capable of reporting link active */
457 unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */
458 unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */
459 pci_dev_flags_t dev_flags;
460 atomic_t enable_cnt; /* pci_enable_device has been called */
461
462 u32 saved_config_space[16]; /* Config space saved at suspend time */
463 struct hlist_head saved_cap_space;
464 int rom_attr_enabled; /* Display of ROM attribute enabled? */
465 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
466 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
467
468 #ifdef CONFIG_HOTPLUG_PCI_PCIE
469 unsigned int broken_cmd_compl:1; /* No compl for some cmds */
470 #endif
471 #ifdef CONFIG_PCIE_PTM
472 unsigned int ptm_root:1;
473 unsigned int ptm_enabled:1;
474 u8 ptm_granularity;
475 #endif
476 #ifdef CONFIG_PCI_MSI
477 const struct attribute_group **msi_irq_groups;
478 #endif
479 struct pci_vpd vpd;
480 #ifdef CONFIG_PCIE_DPC
481 u16 dpc_cap;
482 unsigned int dpc_rp_extensions:1;
483 u8 dpc_rp_log_size;
484 #endif
485 #ifdef CONFIG_PCI_ATS
486 union {
487 struct pci_sriov *sriov; /* PF: SR-IOV info */
488 struct pci_dev *physfn; /* VF: related PF */
489 };
490 u16 ats_cap; /* ATS Capability offset */
491 u8 ats_stu; /* ATS Smallest Translation Unit */
492 #endif
493 #ifdef CONFIG_PCI_PRI
494 u16 pri_cap; /* PRI Capability offset */
495 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
496 unsigned int pasid_required:1; /* PRG Response PASID Required */
497 #endif
498 #ifdef CONFIG_PCI_PASID
499 u16 pasid_cap; /* PASID Capability offset */
500 u16 pasid_features;
501 #endif
502 #ifdef CONFIG_PCI_P2PDMA
503 struct pci_p2pdma __rcu *p2pdma;
504 #endif
505 u16 acs_cap; /* ACS Capability offset */
506 phys_addr_t rom; /* Physical address if not from BAR */
507 size_t romlen; /* Length if not from BAR */
508 char *driver_override; /* Driver name to force a match */
509
510 unsigned long priv_flags; /* Private flags for the PCI driver */
511
512 /* These methods index pci_reset_fn_methods[] */
513 u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */
514
515 ANDROID_KABI_RESERVE(1);
516 ANDROID_KABI_RESERVE(2);
517 ANDROID_KABI_RESERVE(3);
518 ANDROID_KABI_RESERVE(4);
519 };
520
pci_physfn(struct pci_dev * dev)521 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
522 {
523 #ifdef CONFIG_PCI_IOV
524 if (dev->is_virtfn)
525 dev = dev->physfn;
526 #endif
527 return dev;
528 }
529
530 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
531
532 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
533 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
534
pci_channel_offline(struct pci_dev * pdev)535 static inline int pci_channel_offline(struct pci_dev *pdev)
536 {
537 return (pdev->error_state != pci_channel_io_normal);
538 }
539
540 /*
541 * Currently in ACPI spec, for each PCI host bridge, PCI Segment
542 * Group number is limited to a 16-bit value, therefore (int)-1 is
543 * not a valid PCI domain number, and can be used as a sentinel
544 * value indicating ->domain_nr is not set by the driver (and
545 * CONFIG_PCI_DOMAINS_GENERIC=y archs will set it with
546 * pci_bus_find_domain_nr()).
547 */
548 #define PCI_DOMAIN_NR_NOT_SET (-1)
549
550 struct pci_host_bridge {
551 struct device dev;
552 struct pci_bus *bus; /* Root bus */
553 struct pci_ops *ops;
554 struct pci_ops *child_ops;
555 void *sysdata;
556 int busnr;
557 int domain_nr;
558 struct list_head windows; /* resource_entry */
559 struct list_head dma_ranges; /* dma ranges resource list */
560 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
561 int (*map_irq)(const struct pci_dev *, u8, u8);
562 void (*release_fn)(struct pci_host_bridge *);
563 void *release_data;
564 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
565 unsigned int no_ext_tags:1; /* No Extended Tags */
566 unsigned int native_aer:1; /* OS may use PCIe AER */
567 unsigned int native_pcie_hotplug:1; /* OS may use PCIe hotplug */
568 unsigned int native_shpc_hotplug:1; /* OS may use SHPC hotplug */
569 unsigned int native_pme:1; /* OS may use PCIe PME */
570 unsigned int native_ltr:1; /* OS may use PCIe LTR */
571 unsigned int native_dpc:1; /* OS may use PCIe DPC */
572 unsigned int preserve_config:1; /* Preserve FW resource setup */
573 unsigned int size_windows:1; /* Enable root bus sizing */
574 unsigned int msi_domain:1; /* Bridge wants MSI domain */
575
576 /* Resource alignment requirements */
577 resource_size_t (*align_resource)(struct pci_dev *dev,
578 const struct resource *res,
579 resource_size_t start,
580 resource_size_t size,
581 resource_size_t align);
582
583 ANDROID_KABI_RESERVE(1);
584 ANDROID_KABI_RESERVE(2);
585
586 unsigned long private[] ____cacheline_aligned;
587 };
588
589 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
590
pci_host_bridge_priv(struct pci_host_bridge * bridge)591 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
592 {
593 return (void *)bridge->private;
594 }
595
pci_host_bridge_from_priv(void * priv)596 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
597 {
598 return container_of(priv, struct pci_host_bridge, private);
599 }
600
601 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
602 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
603 size_t priv);
604 void pci_free_host_bridge(struct pci_host_bridge *bridge);
605 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
606
607 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
608 void (*release_fn)(struct pci_host_bridge *),
609 void *release_data);
610
611 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
612
613 /*
614 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
615 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
616 * buses below host bridges or subtractive decode bridges) go in the list.
617 * Use pci_bus_for_each_resource() to iterate through all the resources.
618 */
619
620 /*
621 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
622 * and there's no way to program the bridge with the details of the window.
623 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
624 * decode bit set, because they are explicit and can be programmed with _SRS.
625 */
626 #define PCI_SUBTRACTIVE_DECODE 0x1
627
628 struct pci_bus_resource {
629 struct list_head list;
630 struct resource *res;
631 unsigned int flags;
632 };
633
634 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
635
636 struct pci_bus {
637 struct list_head node; /* Node in list of buses */
638 struct pci_bus *parent; /* Parent bus this bridge is on */
639 struct list_head children; /* List of child buses */
640 struct list_head devices; /* List of devices on this bus */
641 struct pci_dev *self; /* Bridge device as seen by parent */
642 struct list_head slots; /* List of slots on this bus;
643 protected by pci_slot_mutex */
644 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
645 struct list_head resources; /* Address space routed to this bus */
646 struct resource busn_res; /* Bus numbers routed to this bus */
647
648 struct pci_ops *ops; /* Configuration access functions */
649 void *sysdata; /* Hook for sys-specific extension */
650 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
651
652 unsigned char number; /* Bus number */
653 unsigned char primary; /* Number of primary bridge */
654 unsigned char max_bus_speed; /* enum pci_bus_speed */
655 unsigned char cur_bus_speed; /* enum pci_bus_speed */
656 #ifdef CONFIG_PCI_DOMAINS_GENERIC
657 int domain_nr;
658 #endif
659
660 char name[48];
661
662 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
663 pci_bus_flags_t bus_flags; /* Inherited by child buses */
664 struct device *bridge;
665 struct device dev;
666 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
667 struct bin_attribute *legacy_mem; /* Legacy mem */
668 unsigned int is_added:1;
669 unsigned int unsafe_warn:1; /* warned about RW1C config write */
670
671 ANDROID_KABI_RESERVE(1);
672 ANDROID_KABI_RESERVE(2);
673 ANDROID_KABI_RESERVE(3);
674 ANDROID_KABI_RESERVE(4);
675 };
676
677 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
678
pci_dev_id(struct pci_dev * dev)679 static inline u16 pci_dev_id(struct pci_dev *dev)
680 {
681 return PCI_DEVID(dev->bus->number, dev->devfn);
682 }
683
684 /*
685 * Returns true if the PCI bus is root (behind host-PCI bridge),
686 * false otherwise
687 *
688 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
689 * This is incorrect because "virtual" buses added for SR-IOV (via
690 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
691 */
pci_is_root_bus(struct pci_bus * pbus)692 static inline bool pci_is_root_bus(struct pci_bus *pbus)
693 {
694 return !(pbus->parent);
695 }
696
697 /**
698 * pci_is_bridge - check if the PCI device is a bridge
699 * @dev: PCI device
700 *
701 * Return true if the PCI device is bridge whether it has subordinate
702 * or not.
703 */
pci_is_bridge(struct pci_dev * dev)704 static inline bool pci_is_bridge(struct pci_dev *dev)
705 {
706 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
707 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
708 }
709
710 #define for_each_pci_bridge(dev, bus) \
711 list_for_each_entry(dev, &bus->devices, bus_list) \
712 if (!pci_is_bridge(dev)) {} else
713
pci_upstream_bridge(struct pci_dev * dev)714 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
715 {
716 dev = pci_physfn(dev);
717 if (pci_is_root_bus(dev->bus))
718 return NULL;
719
720 return dev->bus->self;
721 }
722
723 #ifdef CONFIG_PCI_MSI
pci_dev_msi_enabled(struct pci_dev * pci_dev)724 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
725 {
726 return pci_dev->msi_enabled || pci_dev->msix_enabled;
727 }
728 #else
pci_dev_msi_enabled(struct pci_dev * pci_dev)729 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
730 #endif
731
732 /* Error values that may be returned by PCI functions */
733 #define PCIBIOS_SUCCESSFUL 0x00
734 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
735 #define PCIBIOS_BAD_VENDOR_ID 0x83
736 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
737 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
738 #define PCIBIOS_SET_FAILED 0x88
739 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
740
741 /* Translate above to generic errno for passing back through non-PCI code */
pcibios_err_to_errno(int err)742 static inline int pcibios_err_to_errno(int err)
743 {
744 if (err <= PCIBIOS_SUCCESSFUL)
745 return err; /* Assume already errno */
746
747 switch (err) {
748 case PCIBIOS_FUNC_NOT_SUPPORTED:
749 return -ENOENT;
750 case PCIBIOS_BAD_VENDOR_ID:
751 return -ENOTTY;
752 case PCIBIOS_DEVICE_NOT_FOUND:
753 return -ENODEV;
754 case PCIBIOS_BAD_REGISTER_NUMBER:
755 return -EFAULT;
756 case PCIBIOS_SET_FAILED:
757 return -EIO;
758 case PCIBIOS_BUFFER_TOO_SMALL:
759 return -ENOSPC;
760 }
761
762 return -ERANGE;
763 }
764
765 /* Low-level architecture-dependent routines */
766
767 struct pci_ops {
768 int (*add_bus)(struct pci_bus *bus);
769 void (*remove_bus)(struct pci_bus *bus);
770 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
771 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
772 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
773
774 ANDROID_KABI_RESERVE(1);
775 };
776
777 /*
778 * ACPI needs to be able to access PCI config space before we've done a
779 * PCI bus scan and created pci_bus structures.
780 */
781 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
782 int reg, int len, u32 *val);
783 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
784 int reg, int len, u32 val);
785
786 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
787 typedef u64 pci_bus_addr_t;
788 #else
789 typedef u32 pci_bus_addr_t;
790 #endif
791
792 struct pci_bus_region {
793 pci_bus_addr_t start;
794 pci_bus_addr_t end;
795 };
796
797 struct pci_dynids {
798 spinlock_t lock; /* Protects list, index */
799 struct list_head list; /* For IDs added at runtime */
800 };
801
802
803 /*
804 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
805 * a set of callbacks in struct pci_error_handlers, that device driver
806 * will be notified of PCI bus errors, and will be driven to recovery
807 * when an error occurs.
808 */
809
810 typedef unsigned int __bitwise pci_ers_result_t;
811
812 enum pci_ers_result {
813 /* No result/none/not supported in device driver */
814 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
815
816 /* Device driver can recover without slot reset */
817 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
818
819 /* Device driver wants slot to be reset */
820 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
821
822 /* Device has completely failed, is unrecoverable */
823 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
824
825 /* Device driver is fully recovered and operational */
826 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
827
828 /* No AER capabilities registered for the driver */
829 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
830 };
831
832 /* PCI bus error event callbacks */
833 struct pci_error_handlers {
834 /* PCI bus error detected on this device */
835 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
836 pci_channel_state_t error);
837
838 /* MMIO has been re-enabled, but not DMA */
839 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
840
841 /* PCI slot has been reset */
842 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
843
844 /* PCI function reset prepare or completed */
845 void (*reset_prepare)(struct pci_dev *dev);
846 void (*reset_done)(struct pci_dev *dev);
847
848 /* Device driver may resume normal operations */
849 void (*resume)(struct pci_dev *dev);
850
851 ANDROID_KABI_RESERVE(1);
852 };
853
854
855 struct module;
856
857 /**
858 * struct pci_driver - PCI driver structure
859 * @node: List of driver structures.
860 * @name: Driver name.
861 * @id_table: Pointer to table of device IDs the driver is
862 * interested in. Most drivers should export this
863 * table using MODULE_DEVICE_TABLE(pci,...).
864 * @probe: This probing function gets called (during execution
865 * of pci_register_driver() for already existing
866 * devices or later if a new device gets inserted) for
867 * all PCI devices which match the ID table and are not
868 * "owned" by the other drivers yet. This function gets
869 * passed a "struct pci_dev \*" for each device whose
870 * entry in the ID table matches the device. The probe
871 * function returns zero when the driver chooses to
872 * take "ownership" of the device or an error code
873 * (negative number) otherwise.
874 * The probe function always gets called from process
875 * context, so it can sleep.
876 * @remove: The remove() function gets called whenever a device
877 * being handled by this driver is removed (either during
878 * deregistration of the driver or when it's manually
879 * pulled out of a hot-pluggable slot).
880 * The remove function always gets called from process
881 * context, so it can sleep.
882 * @suspend: Put device into low power state.
883 * @resume: Wake device from low power state.
884 * (Please see Documentation/power/pci.rst for descriptions
885 * of PCI Power Management and the related functions.)
886 * @shutdown: Hook into reboot_notifier_list (kernel/sys.c).
887 * Intended to stop any idling DMA operations.
888 * Useful for enabling wake-on-lan (NIC) or changing
889 * the power state of a device before reboot.
890 * e.g. drivers/net/e100.c.
891 * @sriov_configure: Optional driver callback to allow configuration of
892 * number of VFs to enable via sysfs "sriov_numvfs" file.
893 * @sriov_set_msix_vec_count: PF Driver callback to change number of MSI-X
894 * vectors on a VF. Triggered via sysfs "sriov_vf_msix_count".
895 * This will change MSI-X Table Size in the VF Message Control
896 * registers.
897 * @sriov_get_vf_total_msix: PF driver callback to get the total number of
898 * MSI-X vectors available for distribution to the VFs.
899 * @err_handler: See Documentation/PCI/pci-error-recovery.rst
900 * @groups: Sysfs attribute groups.
901 * @dev_groups: Attributes attached to the device that will be
902 * created once it is bound to the driver.
903 * @driver: Driver model structure.
904 * @dynids: List of dynamically added device IDs.
905 */
906 struct pci_driver {
907 struct list_head node;
908 const char *name;
909 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
910 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
911 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
912 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
913 int (*resume)(struct pci_dev *dev); /* Device woken up */
914 void (*shutdown)(struct pci_dev *dev);
915 int (*sriov_configure)(struct pci_dev *dev, int num_vfs); /* On PF */
916 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count); /* On PF */
917 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
918 const struct pci_error_handlers *err_handler;
919 const struct attribute_group **groups;
920 const struct attribute_group **dev_groups;
921 struct device_driver driver;
922 struct pci_dynids dynids;
923
924 ANDROID_KABI_RESERVE(1);
925 ANDROID_KABI_RESERVE(2);
926 ANDROID_KABI_RESERVE(3);
927 ANDROID_KABI_RESERVE(4);
928 };
929
930 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
931
932 /**
933 * PCI_DEVICE - macro used to describe a specific PCI device
934 * @vend: the 16 bit PCI Vendor ID
935 * @dev: the 16 bit PCI Device ID
936 *
937 * This macro is used to create a struct pci_device_id that matches a
938 * specific device. The subvendor and subdevice fields will be set to
939 * PCI_ANY_ID.
940 */
941 #define PCI_DEVICE(vend,dev) \
942 .vendor = (vend), .device = (dev), \
943 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
944
945 /**
946 * PCI_DEVICE_DRIVER_OVERRIDE - macro used to describe a PCI device with
947 * override_only flags.
948 * @vend: the 16 bit PCI Vendor ID
949 * @dev: the 16 bit PCI Device ID
950 * @driver_override: the 32 bit PCI Device override_only
951 *
952 * This macro is used to create a struct pci_device_id that matches only a
953 * driver_override device. The subvendor and subdevice fields will be set to
954 * PCI_ANY_ID.
955 */
956 #define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
957 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
958 .subdevice = PCI_ANY_ID, .override_only = (driver_override)
959
960 /**
961 * PCI_DRIVER_OVERRIDE_DEVICE_VFIO - macro used to describe a VFIO
962 * "driver_override" PCI device.
963 * @vend: the 16 bit PCI Vendor ID
964 * @dev: the 16 bit PCI Device ID
965 *
966 * This macro is used to create a struct pci_device_id that matches a
967 * specific device. The subvendor and subdevice fields will be set to
968 * PCI_ANY_ID and the driver_override will be set to
969 * PCI_ID_F_VFIO_DRIVER_OVERRIDE.
970 */
971 #define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
972 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
973
974 /**
975 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
976 * @vend: the 16 bit PCI Vendor ID
977 * @dev: the 16 bit PCI Device ID
978 * @subvend: the 16 bit PCI Subvendor ID
979 * @subdev: the 16 bit PCI Subdevice ID
980 *
981 * This macro is used to create a struct pci_device_id that matches a
982 * specific device with subsystem information.
983 */
984 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
985 .vendor = (vend), .device = (dev), \
986 .subvendor = (subvend), .subdevice = (subdev)
987
988 /**
989 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
990 * @dev_class: the class, subclass, prog-if triple for this device
991 * @dev_class_mask: the class mask for this device
992 *
993 * This macro is used to create a struct pci_device_id that matches a
994 * specific PCI class. The vendor, device, subvendor, and subdevice
995 * fields will be set to PCI_ANY_ID.
996 */
997 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
998 .class = (dev_class), .class_mask = (dev_class_mask), \
999 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1000 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1001
1002 /**
1003 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
1004 * @vend: the vendor name
1005 * @dev: the 16 bit PCI Device ID
1006 *
1007 * This macro is used to create a struct pci_device_id that matches a
1008 * specific PCI device. The subvendor, and subdevice fields will be set
1009 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1010 * private data.
1011 */
1012 #define PCI_VDEVICE(vend, dev) \
1013 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1014 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1015
1016 /**
1017 * PCI_DEVICE_DATA - macro used to describe a specific PCI device in very short form
1018 * @vend: the vendor name (without PCI_VENDOR_ID_ prefix)
1019 * @dev: the device name (without PCI_DEVICE_ID_<vend>_ prefix)
1020 * @data: the driver data to be filled
1021 *
1022 * This macro is used to create a struct pci_device_id that matches a
1023 * specific PCI device. The subvendor, and subdevice fields will be set
1024 * to PCI_ANY_ID.
1025 */
1026 #define PCI_DEVICE_DATA(vend, dev, data) \
1027 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1028 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1029 .driver_data = (kernel_ulong_t)(data)
1030
1031 enum {
1032 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
1033 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
1034 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
1035 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
1036 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
1037 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
1038 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
1039 };
1040
1041 #define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1042 #define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1043 #define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1044 #define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1045
1046 /* These external functions are only available when PCI support is enabled */
1047 #ifdef CONFIG_PCI
1048
1049 extern unsigned int pci_flags;
1050
pci_set_flags(int flags)1051 static inline void pci_set_flags(int flags) { pci_flags = flags; }
pci_add_flags(int flags)1052 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
pci_clear_flags(int flags)1053 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
pci_has_flag(int flag)1054 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1055
1056 void pcie_bus_configure_settings(struct pci_bus *bus);
1057
1058 enum pcie_bus_config_types {
1059 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
1060 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
1061 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
1062 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
1063 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
1064 };
1065
1066 extern enum pcie_bus_config_types pcie_bus_config;
1067
1068 extern struct bus_type pci_bus_type;
1069
1070 /* Do NOT directly access these two variables, unless you are arch-specific PCI
1071 * code, or PCI core code. */
1072 extern struct list_head pci_root_buses; /* List of all known PCI buses */
1073 /* Some device drivers need know if PCI is initiated */
1074 int no_pci_devices(void);
1075
1076 void pcibios_resource_survey_bus(struct pci_bus *bus);
1077 void pcibios_bus_add_device(struct pci_dev *pdev);
1078 void pcibios_add_bus(struct pci_bus *bus);
1079 void pcibios_remove_bus(struct pci_bus *bus);
1080 void pcibios_fixup_bus(struct pci_bus *);
1081 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1082 /* Architecture-specific versions may override this (weak) */
1083 char *pcibios_setup(char *str);
1084
1085 /* Used only when drivers/pci/setup.c is used */
1086 resource_size_t pcibios_align_resource(void *, const struct resource *,
1087 resource_size_t,
1088 resource_size_t);
1089
1090 /* Weak but can be overridden by arch */
1091 void pci_fixup_cardbus(struct pci_bus *);
1092
1093 /* Generic PCI functions used internally */
1094
1095 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1096 struct resource *res);
1097 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1098 struct pci_bus_region *region);
1099 void pcibios_scan_specific_bus(int busn);
1100 struct pci_bus *pci_find_bus(int domain, int busnr);
1101 void pci_bus_add_devices(const struct pci_bus *bus);
1102 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1103 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1104 struct pci_ops *ops, void *sysdata,
1105 struct list_head *resources);
1106 int pci_host_probe(struct pci_host_bridge *bridge);
1107 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1108 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1109 void pci_bus_release_busn_res(struct pci_bus *b);
1110 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1111 struct pci_ops *ops, void *sysdata,
1112 struct list_head *resources);
1113 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1114 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1115 int busnr);
1116 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1117 const char *name,
1118 struct hotplug_slot *hotplug);
1119 void pci_destroy_slot(struct pci_slot *slot);
1120 #ifdef CONFIG_SYSFS
1121 void pci_dev_assign_slot(struct pci_dev *dev);
1122 #else
pci_dev_assign_slot(struct pci_dev * dev)1123 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1124 #endif
1125 int pci_scan_slot(struct pci_bus *bus, int devfn);
1126 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1127 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1128 unsigned int pci_scan_child_bus(struct pci_bus *bus);
1129 void pci_bus_add_device(struct pci_dev *dev);
1130 void pci_read_bridge_bases(struct pci_bus *child);
1131 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1132 struct resource *res);
1133 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1134 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1135 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1136 struct pci_dev *pci_dev_get(struct pci_dev *dev);
1137 void pci_dev_put(struct pci_dev *dev);
1138 void pci_remove_bus(struct pci_bus *b);
1139 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1140 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1141 void pci_stop_root_bus(struct pci_bus *bus);
1142 void pci_remove_root_bus(struct pci_bus *bus);
1143 void pci_setup_cardbus(struct pci_bus *bus);
1144 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1145 void pci_sort_breadthfirst(void);
1146 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1147 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1148
1149 /* Generic PCI functions exported to card drivers */
1150
1151 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1152 u8 pci_find_capability(struct pci_dev *dev, int cap);
1153 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1154 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1155 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1156 u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1157 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1158 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1159 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1160
1161 u64 pci_get_dsn(struct pci_dev *dev);
1162
1163 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1164 struct pci_dev *from);
1165 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1166 unsigned int ss_vendor, unsigned int ss_device,
1167 struct pci_dev *from);
1168 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1169 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1170 unsigned int devfn);
1171 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1172 int pci_dev_present(const struct pci_device_id *ids);
1173
1174 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1175 int where, u8 *val);
1176 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1177 int where, u16 *val);
1178 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1179 int where, u32 *val);
1180 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1181 int where, u8 val);
1182 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1183 int where, u16 val);
1184 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1185 int where, u32 val);
1186
1187 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1188 int where, int size, u32 *val);
1189 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1190 int where, int size, u32 val);
1191 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1192 int where, int size, u32 *val);
1193 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1194 int where, int size, u32 val);
1195
1196 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1197
1198 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1199 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1200 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1201 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1202 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1203 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1204
1205 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1206 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1207 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1208 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1209 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1210 u16 clear, u16 set);
1211 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1212 u32 clear, u32 set);
1213
pcie_capability_set_word(struct pci_dev * dev,int pos,u16 set)1214 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1215 u16 set)
1216 {
1217 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1218 }
1219
pcie_capability_set_dword(struct pci_dev * dev,int pos,u32 set)1220 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1221 u32 set)
1222 {
1223 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1224 }
1225
pcie_capability_clear_word(struct pci_dev * dev,int pos,u16 clear)1226 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1227 u16 clear)
1228 {
1229 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1230 }
1231
pcie_capability_clear_dword(struct pci_dev * dev,int pos,u32 clear)1232 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1233 u32 clear)
1234 {
1235 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1236 }
1237
1238 /* User-space driven config access */
1239 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1240 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1241 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1242 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1243 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1244 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1245
1246 int __must_check pci_enable_device(struct pci_dev *dev);
1247 int __must_check pci_enable_device_io(struct pci_dev *dev);
1248 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1249 int __must_check pci_reenable_device(struct pci_dev *);
1250 int __must_check pcim_enable_device(struct pci_dev *pdev);
1251 void pcim_pin_device(struct pci_dev *pdev);
1252
pci_intx_mask_supported(struct pci_dev * pdev)1253 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1254 {
1255 /*
1256 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1257 * writable and no quirk has marked the feature broken.
1258 */
1259 return !pdev->broken_intx_masking;
1260 }
1261
pci_is_enabled(struct pci_dev * pdev)1262 static inline int pci_is_enabled(struct pci_dev *pdev)
1263 {
1264 return (atomic_read(&pdev->enable_cnt) > 0);
1265 }
1266
pci_is_managed(struct pci_dev * pdev)1267 static inline int pci_is_managed(struct pci_dev *pdev)
1268 {
1269 return pdev->is_managed;
1270 }
1271
1272 void pci_disable_device(struct pci_dev *dev);
1273
1274 extern unsigned int pcibios_max_latency;
1275 void pci_set_master(struct pci_dev *dev);
1276 void pci_clear_master(struct pci_dev *dev);
1277
1278 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1279 int pci_set_cacheline_size(struct pci_dev *dev);
1280 int __must_check pci_set_mwi(struct pci_dev *dev);
1281 int __must_check pcim_set_mwi(struct pci_dev *dev);
1282 int pci_try_set_mwi(struct pci_dev *dev);
1283 void pci_clear_mwi(struct pci_dev *dev);
1284 void pci_disable_parity(struct pci_dev *dev);
1285 void pci_intx(struct pci_dev *dev, int enable);
1286 bool pci_check_and_mask_intx(struct pci_dev *dev);
1287 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1288 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1289 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1290 int pcix_get_max_mmrbc(struct pci_dev *dev);
1291 int pcix_get_mmrbc(struct pci_dev *dev);
1292 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1293 int pcie_get_readrq(struct pci_dev *dev);
1294 int pcie_set_readrq(struct pci_dev *dev, int rq);
1295 int pcie_get_mps(struct pci_dev *dev);
1296 int pcie_set_mps(struct pci_dev *dev, int mps);
1297 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1298 enum pci_bus_speed *speed,
1299 enum pcie_link_width *width);
1300 void pcie_print_link_status(struct pci_dev *dev);
1301 int pcie_reset_flr(struct pci_dev *dev, bool probe);
1302 int pcie_flr(struct pci_dev *dev);
1303 int __pci_reset_function_locked(struct pci_dev *dev);
1304 int pci_reset_function(struct pci_dev *dev);
1305 int pci_reset_function_locked(struct pci_dev *dev);
1306 int pci_try_reset_function(struct pci_dev *dev);
1307 int pci_probe_reset_slot(struct pci_slot *slot);
1308 int pci_probe_reset_bus(struct pci_bus *bus);
1309 int pci_reset_bus(struct pci_dev *dev);
1310 void pci_reset_secondary_bus(struct pci_dev *dev);
1311 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1312 void pci_update_resource(struct pci_dev *dev, int resno);
1313 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1314 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1315 void pci_release_resource(struct pci_dev *dev, int resno);
pci_rebar_bytes_to_size(u64 bytes)1316 static inline int pci_rebar_bytes_to_size(u64 bytes)
1317 {
1318 bytes = roundup_pow_of_two(bytes);
1319
1320 /* Return BAR size as defined in the resizable BAR specification */
1321 return max(ilog2(bytes), 20) - 20;
1322 }
1323
1324 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1325 int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1326 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1327 bool pci_device_is_present(struct pci_dev *pdev);
1328 void pci_ignore_hotplug(struct pci_dev *dev);
1329 struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1330 int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1331
1332 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1333 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1334 const char *fmt, ...);
1335 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1336
1337 /* ROM control related routines */
1338 int pci_enable_rom(struct pci_dev *pdev);
1339 void pci_disable_rom(struct pci_dev *pdev);
1340 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1341 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1342
1343 /* Power management related routines */
1344 int pci_save_state(struct pci_dev *dev);
1345 void pci_restore_state(struct pci_dev *dev);
1346 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1347 int pci_load_saved_state(struct pci_dev *dev,
1348 struct pci_saved_state *state);
1349 int pci_load_and_free_saved_state(struct pci_dev *dev,
1350 struct pci_saved_state **state);
1351 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1352 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1353 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1354 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1355 void pci_pme_active(struct pci_dev *dev, bool enable);
1356 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1357 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1358 int pci_prepare_to_sleep(struct pci_dev *dev);
1359 int pci_back_from_sleep(struct pci_dev *dev);
1360 bool pci_dev_run_wake(struct pci_dev *dev);
1361 void pci_d3cold_enable(struct pci_dev *dev);
1362 void pci_d3cold_disable(struct pci_dev *dev);
1363 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1364 void pci_resume_bus(struct pci_bus *bus);
1365 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1366
1367 /* For use by arch with custom probe code */
1368 void set_pcie_port_type(struct pci_dev *pdev);
1369 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1370
1371 /* Functions for PCI Hotplug drivers to use */
1372 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1373 unsigned int pci_rescan_bus(struct pci_bus *bus);
1374 void pci_lock_rescan_remove(void);
1375 void pci_unlock_rescan_remove(void);
1376
1377 /* Vital Product Data routines */
1378 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1379 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1380
1381 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1382 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1383 void pci_bus_assign_resources(const struct pci_bus *bus);
1384 void pci_bus_claim_resources(struct pci_bus *bus);
1385 void pci_bus_size_bridges(struct pci_bus *bus);
1386 int pci_claim_resource(struct pci_dev *, int);
1387 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1388 void pci_assign_unassigned_resources(void);
1389 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1390 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1391 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1392 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1393 void pdev_enable_device(struct pci_dev *);
1394 int pci_enable_resources(struct pci_dev *, int mask);
1395 void pci_assign_irq(struct pci_dev *dev);
1396 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1397 #define HAVE_PCI_REQ_REGIONS 2
1398 int __must_check pci_request_regions(struct pci_dev *, const char *);
1399 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1400 void pci_release_regions(struct pci_dev *);
1401 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1402 void pci_release_region(struct pci_dev *, int);
1403 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1404 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1405 void pci_release_selected_regions(struct pci_dev *, int);
1406
1407 /* drivers/pci/bus.c */
1408 void pci_add_resource(struct list_head *resources, struct resource *res);
1409 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1410 resource_size_t offset);
1411 void pci_free_resource_list(struct list_head *resources);
1412 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1413 unsigned int flags);
1414 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1415 void pci_bus_remove_resources(struct pci_bus *bus);
1416 void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res);
1417 int devm_request_pci_bus_resources(struct device *dev,
1418 struct list_head *resources);
1419
1420 /* Temporary until new and working PCI SBR API in place */
1421 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1422
1423 #define pci_bus_for_each_resource(bus, res, i) \
1424 for (i = 0; \
1425 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1426 i++)
1427
1428 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1429 struct resource *res, resource_size_t size,
1430 resource_size_t align, resource_size_t min,
1431 unsigned long type_mask,
1432 resource_size_t (*alignf)(void *,
1433 const struct resource *,
1434 resource_size_t,
1435 resource_size_t),
1436 void *alignf_data);
1437
1438
1439 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1440 resource_size_t size);
1441 unsigned long pci_address_to_pio(phys_addr_t addr);
1442 phys_addr_t pci_pio_to_address(unsigned long pio);
1443 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1444 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1445 phys_addr_t phys_addr);
1446 void pci_unmap_iospace(struct resource *res);
1447 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1448 resource_size_t offset,
1449 resource_size_t size);
1450 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1451 struct resource *res);
1452
pci_bus_address(struct pci_dev * pdev,int bar)1453 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1454 {
1455 struct pci_bus_region region;
1456
1457 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1458 return region.start;
1459 }
1460
1461 /* Proper probing supporting hot-pluggable devices */
1462 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1463 const char *mod_name);
1464
1465 /* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1466 #define pci_register_driver(driver) \
1467 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1468
1469 void pci_unregister_driver(struct pci_driver *dev);
1470
1471 /**
1472 * module_pci_driver() - Helper macro for registering a PCI driver
1473 * @__pci_driver: pci_driver struct
1474 *
1475 * Helper macro for PCI drivers which do not do anything special in module
1476 * init/exit. This eliminates a lot of boilerplate. Each module may only
1477 * use this macro once, and calling it replaces module_init() and module_exit()
1478 */
1479 #define module_pci_driver(__pci_driver) \
1480 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1481
1482 /**
1483 * builtin_pci_driver() - Helper macro for registering a PCI driver
1484 * @__pci_driver: pci_driver struct
1485 *
1486 * Helper macro for PCI drivers which do not do anything special in their
1487 * init code. This eliminates a lot of boilerplate. Each driver may only
1488 * use this macro once, and calling it replaces device_initcall(...)
1489 */
1490 #define builtin_pci_driver(__pci_driver) \
1491 builtin_driver(__pci_driver, pci_register_driver)
1492
1493 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1494 int pci_add_dynid(struct pci_driver *drv,
1495 unsigned int vendor, unsigned int device,
1496 unsigned int subvendor, unsigned int subdevice,
1497 unsigned int class, unsigned int class_mask,
1498 unsigned long driver_data);
1499 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1500 struct pci_dev *dev);
1501 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1502 int pass);
1503
1504 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1505 void *userdata);
1506 int pci_cfg_space_size(struct pci_dev *dev);
1507 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1508 void pci_setup_bridge(struct pci_bus *bus);
1509 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1510 unsigned long type);
1511
1512 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1513 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1514
1515 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1516 unsigned int command_bits, u32 flags);
1517
1518 /*
1519 * Virtual interrupts allow for more interrupts to be allocated
1520 * than the device has interrupts for. These are not programmed
1521 * into the device's MSI-X table and must be handled by some
1522 * other driver means.
1523 */
1524 #define PCI_IRQ_VIRTUAL (1 << 4)
1525
1526 #define PCI_IRQ_ALL_TYPES \
1527 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1528
1529 /* kmem_cache style wrapper around pci_alloc_consistent() */
1530
1531 #include <linux/dmapool.h>
1532
1533 #define pci_pool dma_pool
1534 #define pci_pool_create(name, pdev, size, align, allocation) \
1535 dma_pool_create(name, &pdev->dev, size, align, allocation)
1536 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1537 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1538 #define pci_pool_zalloc(pool, flags, handle) \
1539 dma_pool_zalloc(pool, flags, handle)
1540 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1541
1542 struct msix_entry {
1543 u32 vector; /* Kernel uses to write allocated vector */
1544 u16 entry; /* Driver uses to specify entry, OS writes */
1545 };
1546
1547 #ifdef CONFIG_PCI_MSI
1548 int pci_msi_vec_count(struct pci_dev *dev);
1549 void pci_disable_msi(struct pci_dev *dev);
1550 int pci_msix_vec_count(struct pci_dev *dev);
1551 void pci_disable_msix(struct pci_dev *dev);
1552 void pci_restore_msi_state(struct pci_dev *dev);
1553 int pci_msi_enabled(void);
1554 int pci_enable_msi(struct pci_dev *dev);
1555 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1556 int minvec, int maxvec);
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1557 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1558 struct msix_entry *entries, int nvec)
1559 {
1560 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1561 if (rc < 0)
1562 return rc;
1563 return 0;
1564 }
1565 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1566 unsigned int max_vecs, unsigned int flags,
1567 struct irq_affinity *affd);
1568
1569 void pci_free_irq_vectors(struct pci_dev *dev);
1570 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1571 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1572
1573 #else
pci_msi_vec_count(struct pci_dev * dev)1574 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msi(struct pci_dev * dev)1575 static inline void pci_disable_msi(struct pci_dev *dev) { }
pci_msix_vec_count(struct pci_dev * dev)1576 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
pci_disable_msix(struct pci_dev * dev)1577 static inline void pci_disable_msix(struct pci_dev *dev) { }
pci_restore_msi_state(struct pci_dev * dev)1578 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
pci_msi_enabled(void)1579 static inline int pci_msi_enabled(void) { return 0; }
pci_enable_msi(struct pci_dev * dev)1580 static inline int pci_enable_msi(struct pci_dev *dev)
1581 { return -ENOSYS; }
pci_enable_msix_range(struct pci_dev * dev,struct msix_entry * entries,int minvec,int maxvec)1582 static inline int pci_enable_msix_range(struct pci_dev *dev,
1583 struct msix_entry *entries, int minvec, int maxvec)
1584 { return -ENOSYS; }
pci_enable_msix_exact(struct pci_dev * dev,struct msix_entry * entries,int nvec)1585 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1586 struct msix_entry *entries, int nvec)
1587 { return -ENOSYS; }
1588
1589 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1590 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1591 unsigned int max_vecs, unsigned int flags,
1592 struct irq_affinity *aff_desc)
1593 {
1594 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1595 return 1;
1596 return -ENOSPC;
1597 }
1598
pci_free_irq_vectors(struct pci_dev * dev)1599 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1600 {
1601 }
1602
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1603 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1604 {
1605 if (WARN_ON_ONCE(nr > 0))
1606 return -EINVAL;
1607 return dev->irq;
1608 }
pci_irq_get_affinity(struct pci_dev * pdev,int vec)1609 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1610 int vec)
1611 {
1612 return cpu_possible_mask;
1613 }
1614 #endif
1615
1616 /**
1617 * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
1618 * @d: the INTx IRQ domain
1619 * @node: the DT node for the device whose interrupt we're translating
1620 * @intspec: the interrupt specifier data from the DT
1621 * @intsize: the number of entries in @intspec
1622 * @out_hwirq: pointer at which to write the hwirq number
1623 * @out_type: pointer at which to write the interrupt type
1624 *
1625 * Translate a PCI INTx interrupt number from device tree in the range 1-4, as
1626 * stored in the standard PCI_INTERRUPT_PIN register, to a value in the range
1627 * 0-3 suitable for use in a 4 entry IRQ domain. That is, subtract one from the
1628 * INTx value to obtain the hwirq number.
1629 *
1630 * Returns 0 on success, or -EINVAL if the interrupt specifier is out of range.
1631 */
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1632 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1633 struct device_node *node,
1634 const u32 *intspec,
1635 unsigned int intsize,
1636 unsigned long *out_hwirq,
1637 unsigned int *out_type)
1638 {
1639 const u32 intx = intspec[0];
1640
1641 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1642 return -EINVAL;
1643
1644 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1645 return 0;
1646 }
1647
1648 #ifdef CONFIG_PCIEPORTBUS
1649 extern bool pcie_ports_disabled;
1650 extern bool pcie_ports_native;
1651 #else
1652 #define pcie_ports_disabled true
1653 #define pcie_ports_native false
1654 #endif
1655
1656 #define PCIE_LINK_STATE_L0S BIT(0)
1657 #define PCIE_LINK_STATE_L1 BIT(1)
1658 #define PCIE_LINK_STATE_CLKPM BIT(2)
1659 #define PCIE_LINK_STATE_L1_1 BIT(3)
1660 #define PCIE_LINK_STATE_L1_2 BIT(4)
1661 #define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1662 #define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1663
1664 #ifdef CONFIG_PCIEASPM
1665 int pci_disable_link_state(struct pci_dev *pdev, int state);
1666 int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1667 void pcie_no_aspm(void);
1668 bool pcie_aspm_support_enabled(void);
1669 bool pcie_aspm_enabled(struct pci_dev *pdev);
1670 #else
pci_disable_link_state(struct pci_dev * pdev,int state)1671 static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1672 { return 0; }
pci_disable_link_state_locked(struct pci_dev * pdev,int state)1673 static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1674 { return 0; }
pcie_no_aspm(void)1675 static inline void pcie_no_aspm(void) { }
pcie_aspm_support_enabled(void)1676 static inline bool pcie_aspm_support_enabled(void) { return false; }
pcie_aspm_enabled(struct pci_dev * pdev)1677 static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1678 #endif
1679
1680 #ifdef CONFIG_PCIEAER
1681 bool pci_aer_available(void);
1682 #else
pci_aer_available(void)1683 static inline bool pci_aer_available(void) { return false; }
1684 #endif
1685
1686 bool pci_ats_disabled(void);
1687
1688 #ifdef CONFIG_PCIE_PTM
1689 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1690 bool pcie_ptm_enabled(struct pci_dev *dev);
1691 #else
pci_enable_ptm(struct pci_dev * dev,u8 * granularity)1692 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1693 { return -EINVAL; }
pcie_ptm_enabled(struct pci_dev * dev)1694 static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1695 { return false; }
1696 #endif
1697
1698 void pci_cfg_access_lock(struct pci_dev *dev);
1699 bool pci_cfg_access_trylock(struct pci_dev *dev);
1700 void pci_cfg_access_unlock(struct pci_dev *dev);
1701
1702 int pci_dev_trylock(struct pci_dev *dev);
1703 void pci_dev_unlock(struct pci_dev *dev);
1704
1705 /*
1706 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1707 * a PCI domain is defined to be a set of PCI buses which share
1708 * configuration space.
1709 */
1710 #ifdef CONFIG_PCI_DOMAINS
1711 extern int pci_domains_supported;
1712 #else
1713 enum { pci_domains_supported = 0 };
pci_domain_nr(struct pci_bus * bus)1714 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_proc_domain(struct pci_bus * bus)1715 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1716 #endif /* CONFIG_PCI_DOMAINS */
1717
1718 /*
1719 * Generic implementation for PCI domain support. If your
1720 * architecture does not need custom management of PCI
1721 * domains then this implementation will be used
1722 */
1723 #ifdef CONFIG_PCI_DOMAINS_GENERIC
pci_domain_nr(struct pci_bus * bus)1724 static inline int pci_domain_nr(struct pci_bus *bus)
1725 {
1726 return bus->domain_nr;
1727 }
1728 #ifdef CONFIG_ACPI
1729 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1730 #else
acpi_pci_bus_find_domain_nr(struct pci_bus * bus)1731 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1732 { return 0; }
1733 #endif
1734 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1735 #endif
1736
1737 /* Some architectures require additional setup to direct VGA traffic */
1738 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1739 unsigned int command_bits, u32 flags);
1740 void pci_register_set_vga_state(arch_set_vga_state_t func);
1741
1742 static inline int
pci_request_io_regions(struct pci_dev * pdev,const char * name)1743 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1744 {
1745 return pci_request_selected_regions(pdev,
1746 pci_select_bars(pdev, IORESOURCE_IO), name);
1747 }
1748
1749 static inline void
pci_release_io_regions(struct pci_dev * pdev)1750 pci_release_io_regions(struct pci_dev *pdev)
1751 {
1752 return pci_release_selected_regions(pdev,
1753 pci_select_bars(pdev, IORESOURCE_IO));
1754 }
1755
1756 static inline int
pci_request_mem_regions(struct pci_dev * pdev,const char * name)1757 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1758 {
1759 return pci_request_selected_regions(pdev,
1760 pci_select_bars(pdev, IORESOURCE_MEM), name);
1761 }
1762
1763 static inline void
pci_release_mem_regions(struct pci_dev * pdev)1764 pci_release_mem_regions(struct pci_dev *pdev)
1765 {
1766 return pci_release_selected_regions(pdev,
1767 pci_select_bars(pdev, IORESOURCE_MEM));
1768 }
1769
1770 #else /* CONFIG_PCI is not enabled */
1771
pci_set_flags(int flags)1772 static inline void pci_set_flags(int flags) { }
pci_add_flags(int flags)1773 static inline void pci_add_flags(int flags) { }
pci_clear_flags(int flags)1774 static inline void pci_clear_flags(int flags) { }
pci_has_flag(int flag)1775 static inline int pci_has_flag(int flag) { return 0; }
1776
1777 /*
1778 * If the system does not have PCI, clearly these return errors. Define
1779 * these as simple inline functions to avoid hair in drivers.
1780 */
1781 #define _PCI_NOP(o, s, t) \
1782 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1783 int where, t val) \
1784 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1785
1786 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1787 _PCI_NOP(o, word, u16 x) \
1788 _PCI_NOP(o, dword, u32 x)
1789 _PCI_NOP_ALL(read, *)
1790 _PCI_NOP_ALL(write,)
1791
pci_get_device(unsigned int vendor,unsigned int device,struct pci_dev * from)1792 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1793 unsigned int device,
1794 struct pci_dev *from)
1795 { return NULL; }
1796
pci_get_subsys(unsigned int vendor,unsigned int device,unsigned int ss_vendor,unsigned int ss_device,struct pci_dev * from)1797 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1798 unsigned int device,
1799 unsigned int ss_vendor,
1800 unsigned int ss_device,
1801 struct pci_dev *from)
1802 { return NULL; }
1803
pci_get_class(unsigned int class,struct pci_dev * from)1804 static inline struct pci_dev *pci_get_class(unsigned int class,
1805 struct pci_dev *from)
1806 { return NULL; }
1807
1808 #define pci_dev_present(ids) (0)
1809 #define no_pci_devices() (1)
1810 #define pci_dev_put(dev) do { } while (0)
1811
pci_set_master(struct pci_dev * dev)1812 static inline void pci_set_master(struct pci_dev *dev) { }
pci_clear_master(struct pci_dev * dev)1813 static inline void pci_clear_master(struct pci_dev *dev) { }
pci_enable_device(struct pci_dev * dev)1814 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
pci_disable_device(struct pci_dev * dev)1815 static inline void pci_disable_device(struct pci_dev *dev) { }
pcim_enable_device(struct pci_dev * pdev)1816 static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
pci_assign_resource(struct pci_dev * dev,int i)1817 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1818 { return -EBUSY; }
__pci_register_driver(struct pci_driver * drv,struct module * owner,const char * mod_name)1819 static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1820 struct module *owner,
1821 const char *mod_name)
1822 { return 0; }
pci_register_driver(struct pci_driver * drv)1823 static inline int pci_register_driver(struct pci_driver *drv)
1824 { return 0; }
pci_unregister_driver(struct pci_driver * drv)1825 static inline void pci_unregister_driver(struct pci_driver *drv) { }
pci_find_capability(struct pci_dev * dev,int cap)1826 static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
1827 { return 0; }
pci_find_next_capability(struct pci_dev * dev,u8 post,int cap)1828 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1829 int cap)
1830 { return 0; }
pci_find_ext_capability(struct pci_dev * dev,int cap)1831 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1832 { return 0; }
1833
pci_get_dsn(struct pci_dev * dev)1834 static inline u64 pci_get_dsn(struct pci_dev *dev)
1835 { return 0; }
1836
1837 /* Power management related routines */
pci_save_state(struct pci_dev * dev)1838 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
pci_restore_state(struct pci_dev * dev)1839 static inline void pci_restore_state(struct pci_dev *dev) { }
pci_set_power_state(struct pci_dev * dev,pci_power_t state)1840 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1841 { return 0; }
pci_wake_from_d3(struct pci_dev * dev,bool enable)1842 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1843 { return 0; }
pci_choose_state(struct pci_dev * dev,pm_message_t state)1844 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1845 pm_message_t state)
1846 { return PCI_D0; }
pci_enable_wake(struct pci_dev * dev,pci_power_t state,int enable)1847 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1848 int enable)
1849 { return 0; }
1850
pci_find_resource(struct pci_dev * dev,struct resource * res)1851 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1852 struct resource *res)
1853 { return NULL; }
pci_request_regions(struct pci_dev * dev,const char * res_name)1854 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1855 { return -EIO; }
pci_release_regions(struct pci_dev * dev)1856 static inline void pci_release_regions(struct pci_dev *dev) { }
1857
pci_register_io_range(struct fwnode_handle * fwnode,phys_addr_t addr,resource_size_t size)1858 static inline int pci_register_io_range(struct fwnode_handle *fwnode,
1859 phys_addr_t addr, resource_size_t size)
1860 { return -EINVAL; }
1861
pci_address_to_pio(phys_addr_t addr)1862 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1863
pci_find_next_bus(const struct pci_bus * from)1864 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1865 { return NULL; }
pci_get_slot(struct pci_bus * bus,unsigned int devfn)1866 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1867 unsigned int devfn)
1868 { return NULL; }
pci_get_domain_bus_and_slot(int domain,unsigned int bus,unsigned int devfn)1869 static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1870 unsigned int bus, unsigned int devfn)
1871 { return NULL; }
1872
pci_domain_nr(struct pci_bus * bus)1873 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
pci_dev_get(struct pci_dev * dev)1874 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1875
1876 #define dev_is_pci(d) (false)
1877 #define dev_is_pf(d) (false)
pci_acs_enabled(struct pci_dev * pdev,u16 acs_flags)1878 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1879 { return false; }
pci_irqd_intx_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1880 static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1881 struct device_node *node,
1882 const u32 *intspec,
1883 unsigned int intsize,
1884 unsigned long *out_hwirq,
1885 unsigned int *out_type)
1886 { return -EINVAL; }
1887
pci_match_id(const struct pci_device_id * ids,struct pci_dev * dev)1888 static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1889 struct pci_dev *dev)
1890 { return NULL; }
pci_ats_disabled(void)1891 static inline bool pci_ats_disabled(void) { return true; }
1892
pci_irq_vector(struct pci_dev * dev,unsigned int nr)1893 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1894 {
1895 return -EINVAL;
1896 }
1897
1898 static inline int
pci_alloc_irq_vectors_affinity(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags,struct irq_affinity * aff_desc)1899 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1900 unsigned int max_vecs, unsigned int flags,
1901 struct irq_affinity *aff_desc)
1902 {
1903 return -ENOSPC;
1904 }
1905 #endif /* CONFIG_PCI */
1906
1907 static inline int
pci_alloc_irq_vectors(struct pci_dev * dev,unsigned int min_vecs,unsigned int max_vecs,unsigned int flags)1908 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1909 unsigned int max_vecs, unsigned int flags)
1910 {
1911 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1912 NULL);
1913 }
1914
1915 /* Include architecture-dependent settings and functions */
1916
1917 #include <asm/pci.h>
1918
1919 /* These two functions provide almost identical functionality. Depending
1920 * on the architecture, one will be implemented as a wrapper around the
1921 * other (in drivers/pci/mmap.c).
1922 *
1923 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1924 * is expected to be an offset within that region.
1925 *
1926 * pci_mmap_page_range() is the legacy architecture-specific interface,
1927 * which accepts a "user visible" resource address converted by
1928 * pci_resource_to_user(), as used in the legacy mmap() interface in
1929 * /proc/bus/pci/.
1930 */
1931 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1932 struct vm_area_struct *vma,
1933 enum pci_mmap_state mmap_state, int write_combine);
1934 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1935 struct vm_area_struct *vma,
1936 enum pci_mmap_state mmap_state, int write_combine);
1937
1938 #ifndef arch_can_pci_mmap_wc
1939 #define arch_can_pci_mmap_wc() 0
1940 #endif
1941
1942 #ifndef arch_can_pci_mmap_io
1943 #define arch_can_pci_mmap_io() 0
1944 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1945 #else
1946 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1947 #endif
1948
1949 #ifndef pci_root_bus_fwnode
1950 #define pci_root_bus_fwnode(bus) NULL
1951 #endif
1952
1953 /*
1954 * These helpers provide future and backwards compatibility
1955 * for accessing popular PCI BAR info
1956 */
1957 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1958 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1959 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1960 #define pci_resource_len(dev,bar) \
1961 ((pci_resource_end((dev), (bar)) == 0) ? 0 : \
1962 \
1963 (pci_resource_end((dev), (bar)) - \
1964 pci_resource_start((dev), (bar)) + 1))
1965
1966 /*
1967 * Similar to the helpers above, these manipulate per-pci_dev
1968 * driver-specific data. They are really just a wrapper around
1969 * the generic device structure functions of these calls.
1970 */
pci_get_drvdata(struct pci_dev * pdev)1971 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1972 {
1973 return dev_get_drvdata(&pdev->dev);
1974 }
1975
pci_set_drvdata(struct pci_dev * pdev,void * data)1976 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1977 {
1978 dev_set_drvdata(&pdev->dev, data);
1979 }
1980
pci_name(const struct pci_dev * pdev)1981 static inline const char *pci_name(const struct pci_dev *pdev)
1982 {
1983 return dev_name(&pdev->dev);
1984 }
1985
1986 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1987 const struct resource *rsrc,
1988 resource_size_t *start, resource_size_t *end);
1989
1990 /*
1991 * The world is not perfect and supplies us with broken PCI devices.
1992 * For at least a part of these bugs we need a work-around, so both
1993 * generic (drivers/pci/quirks.c) and per-architecture code can define
1994 * fixup hooks to be called for particular buggy devices.
1995 */
1996
1997 struct pci_fixup {
1998 u16 vendor; /* Or PCI_ANY_ID */
1999 u16 device; /* Or PCI_ANY_ID */
2000 u32 class; /* Or PCI_ANY_ID */
2001 unsigned int class_shift; /* should be 0, 8, 16 */
2002 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2003 int hook_offset;
2004 #else
2005 void (*hook)(struct pci_dev *dev);
2006 #endif
2007 };
2008
2009 enum pci_fixup_pass {
2010 pci_fixup_early, /* Before probing BARs */
2011 pci_fixup_header, /* After reading configuration header */
2012 pci_fixup_final, /* Final phase of device fixups */
2013 pci_fixup_enable, /* pci_enable_device() time */
2014 pci_fixup_resume, /* pci_device_resume() */
2015 pci_fixup_suspend, /* pci_device_suspend() */
2016 pci_fixup_resume_early, /* pci_device_resume_early() */
2017 pci_fixup_suspend_late, /* pci_device_suspend_late() */
2018 };
2019
2020 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
2021 #define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2022 class_shift, hook) \
2023 __ADDRESSABLE(hook) \
2024 asm(".section " #sec ", \"a\" \n" \
2025 ".balign 16 \n" \
2026 ".short " #vendor ", " #device " \n" \
2027 ".long " #class ", " #class_shift " \n" \
2028 ".long " #hook " - . \n" \
2029 ".previous \n");
2030
2031 /*
2032 * Clang's LTO may rename static functions in C, but has no way to
2033 * handle such renamings when referenced from inline asm. To work
2034 * around this, create global C stubs for these cases.
2035 */
2036 #ifdef CONFIG_LTO_CLANG
2037 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2038 class_shift, hook, stub) \
2039 void __cficanonical stub(struct pci_dev *dev); \
2040 void __cficanonical stub(struct pci_dev *dev) \
2041 { \
2042 hook(dev); \
2043 } \
2044 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2045 class_shift, stub)
2046 #else
2047 #define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2048 class_shift, hook, stub) \
2049 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2050 class_shift, hook)
2051 #endif
2052
2053 #define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2054 class_shift, hook) \
2055 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2056 class_shift, hook, __UNIQUE_ID(hook))
2057 #else
2058 /* Anonymous variables would be nice... */
2059 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
2060 class_shift, hook) \
2061 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
2062 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
2063 = { vendor, device, class, class_shift, hook };
2064 #endif
2065
2066 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
2067 class_shift, hook) \
2068 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2069 hook, vendor, device, class, class_shift, hook)
2070 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2071 class_shift, hook) \
2072 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2073 hook, vendor, device, class, class_shift, hook)
2074 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2075 class_shift, hook) \
2076 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2077 hook, vendor, device, class, class_shift, hook)
2078 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2079 class_shift, hook) \
2080 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2081 hook, vendor, device, class, class_shift, hook)
2082 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2083 class_shift, hook) \
2084 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2085 resume##hook, vendor, device, class, class_shift, hook)
2086 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2087 class_shift, hook) \
2088 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2089 resume_early##hook, vendor, device, class, class_shift, hook)
2090 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2091 class_shift, hook) \
2092 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2093 suspend##hook, vendor, device, class, class_shift, hook)
2094 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2095 class_shift, hook) \
2096 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2097 suspend_late##hook, vendor, device, class, class_shift, hook)
2098
2099 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2100 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2101 hook, vendor, device, PCI_ANY_ID, 0, hook)
2102 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2103 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2104 hook, vendor, device, PCI_ANY_ID, 0, hook)
2105 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2106 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2107 hook, vendor, device, PCI_ANY_ID, 0, hook)
2108 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2109 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2110 hook, vendor, device, PCI_ANY_ID, 0, hook)
2111 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2112 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2113 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2114 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2115 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2116 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2117 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2118 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2119 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2120 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2121 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2122 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2123
2124 #ifdef CONFIG_PCI_QUIRKS
2125 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2126 #else
pci_fixup_device(enum pci_fixup_pass pass,struct pci_dev * dev)2127 static inline void pci_fixup_device(enum pci_fixup_pass pass,
2128 struct pci_dev *dev) { }
2129 #endif
2130
2131 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2132 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2133 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2134 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2135 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2136 const char *name);
2137 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2138
2139 extern int pci_pci_problems;
2140 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
2141 #define PCIPCI_TRITON 2
2142 #define PCIPCI_NATOMA 4
2143 #define PCIPCI_VIAETBF 8
2144 #define PCIPCI_VSFX 16
2145 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
2146 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
2147
2148 extern unsigned long pci_cardbus_io_size;
2149 extern unsigned long pci_cardbus_mem_size;
2150 extern u8 pci_dfl_cache_line_size;
2151 extern u8 pci_cache_line_size;
2152
2153 /* Architecture-specific versions may override these (weak) */
2154 void pcibios_disable_device(struct pci_dev *dev);
2155 void pcibios_set_master(struct pci_dev *dev);
2156 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2157 enum pcie_reset_state state);
2158 int pcibios_add_device(struct pci_dev *dev);
2159 void pcibios_release_device(struct pci_dev *dev);
2160 #ifdef CONFIG_PCI
2161 void pcibios_penalize_isa_irq(int irq, int active);
2162 #else
pcibios_penalize_isa_irq(int irq,int active)2163 static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2164 #endif
2165 int pcibios_alloc_irq(struct pci_dev *dev);
2166 void pcibios_free_irq(struct pci_dev *dev);
2167 resource_size_t pcibios_default_alignment(void);
2168
2169 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2170 void __init pci_mmcfg_early_init(void);
2171 void __init pci_mmcfg_late_init(void);
2172 #else
pci_mmcfg_early_init(void)2173 static inline void pci_mmcfg_early_init(void) { }
pci_mmcfg_late_init(void)2174 static inline void pci_mmcfg_late_init(void) { }
2175 #endif
2176
2177 int pci_ext_cfg_avail(void);
2178
2179 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2180 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2181
2182 #ifdef CONFIG_PCI_IOV
2183 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2184 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2185
2186 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2187 void pci_disable_sriov(struct pci_dev *dev);
2188
2189 int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2190 int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2191 void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2192 int pci_num_vf(struct pci_dev *dev);
2193 int pci_vfs_assigned(struct pci_dev *dev);
2194 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2195 int pci_sriov_get_totalvfs(struct pci_dev *dev);
2196 int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2197 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2198 void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2199
2200 /* Arch may override these (weak) */
2201 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2202 int pcibios_sriov_disable(struct pci_dev *pdev);
2203 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2204 #else
pci_iov_virtfn_bus(struct pci_dev * dev,int id)2205 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2206 {
2207 return -ENOSYS;
2208 }
pci_iov_virtfn_devfn(struct pci_dev * dev,int id)2209 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2210 {
2211 return -ENOSYS;
2212 }
pci_enable_sriov(struct pci_dev * dev,int nr_virtfn)2213 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2214 { return -ENODEV; }
2215
pci_iov_sysfs_link(struct pci_dev * dev,struct pci_dev * virtfn,int id)2216 static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2217 struct pci_dev *virtfn, int id)
2218 {
2219 return -ENODEV;
2220 }
pci_iov_add_virtfn(struct pci_dev * dev,int id)2221 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2222 {
2223 return -ENOSYS;
2224 }
pci_iov_remove_virtfn(struct pci_dev * dev,int id)2225 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2226 int id) { }
pci_disable_sriov(struct pci_dev * dev)2227 static inline void pci_disable_sriov(struct pci_dev *dev) { }
pci_num_vf(struct pci_dev * dev)2228 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
pci_vfs_assigned(struct pci_dev * dev)2229 static inline int pci_vfs_assigned(struct pci_dev *dev)
2230 { return 0; }
pci_sriov_set_totalvfs(struct pci_dev * dev,u16 numvfs)2231 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2232 { return 0; }
pci_sriov_get_totalvfs(struct pci_dev * dev)2233 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2234 { return 0; }
2235 #define pci_sriov_configure_simple NULL
pci_iov_resource_size(struct pci_dev * dev,int resno)2236 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2237 { return 0; }
pci_vf_drivers_autoprobe(struct pci_dev * dev,bool probe)2238 static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2239 #endif
2240
2241 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2242 void pci_hp_create_module_link(struct pci_slot *pci_slot);
2243 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2244 #endif
2245
2246 /**
2247 * pci_pcie_cap - get the saved PCIe capability offset
2248 * @dev: PCI device
2249 *
2250 * PCIe capability offset is calculated at PCI device initialization
2251 * time and saved in the data structure. This function returns saved
2252 * PCIe capability offset. Using this instead of pci_find_capability()
2253 * reduces unnecessary search in the PCI configuration space. If you
2254 * need to calculate PCIe capability offset from raw device for some
2255 * reasons, please use pci_find_capability() instead.
2256 */
pci_pcie_cap(struct pci_dev * dev)2257 static inline int pci_pcie_cap(struct pci_dev *dev)
2258 {
2259 return dev->pcie_cap;
2260 }
2261
2262 /**
2263 * pci_is_pcie - check if the PCI device is PCI Express capable
2264 * @dev: PCI device
2265 *
2266 * Returns: true if the PCI device is PCI Express capable, false otherwise.
2267 */
pci_is_pcie(struct pci_dev * dev)2268 static inline bool pci_is_pcie(struct pci_dev *dev)
2269 {
2270 return pci_pcie_cap(dev);
2271 }
2272
2273 /**
2274 * pcie_caps_reg - get the PCIe Capabilities Register
2275 * @dev: PCI device
2276 */
pcie_caps_reg(const struct pci_dev * dev)2277 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2278 {
2279 return dev->pcie_flags_reg;
2280 }
2281
2282 /**
2283 * pci_pcie_type - get the PCIe device/port type
2284 * @dev: PCI device
2285 */
pci_pcie_type(const struct pci_dev * dev)2286 static inline int pci_pcie_type(const struct pci_dev *dev)
2287 {
2288 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2289 }
2290
2291 /**
2292 * pcie_find_root_port - Get the PCIe root port device
2293 * @dev: PCI device
2294 *
2295 * Traverse up the parent chain and return the PCIe Root Port PCI Device
2296 * for a given PCI/PCIe Device.
2297 */
pcie_find_root_port(struct pci_dev * dev)2298 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2299 {
2300 while (dev) {
2301 if (pci_is_pcie(dev) &&
2302 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2303 return dev;
2304 dev = pci_upstream_bridge(dev);
2305 }
2306
2307 return NULL;
2308 }
2309
2310 void pci_request_acs(void);
2311 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2312 bool pci_acs_path_enabled(struct pci_dev *start,
2313 struct pci_dev *end, u16 acs_flags);
2314 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2315
2316 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2317 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2318
2319 /* Large Resource Data Type Tag Item Names */
2320 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2321 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2322 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2323
2324 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2325 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2326 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2327
2328 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2329 #define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2330 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2331 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2332 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2333
2334 /**
2335 * pci_vpd_alloc - Allocate buffer and read VPD into it
2336 * @dev: PCI device
2337 * @size: pointer to field where VPD length is returned
2338 *
2339 * Returns pointer to allocated buffer or an ERR_PTR in case of failure
2340 */
2341 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
2342
2343 /**
2344 * pci_vpd_find_id_string - Locate id string in VPD
2345 * @buf: Pointer to buffered VPD data
2346 * @len: The length of the buffer area in which to search
2347 * @size: Pointer to field where length of id string is returned
2348 *
2349 * Returns the index of the id string or -ENOENT if not found.
2350 */
2351 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
2352
2353 /**
2354 * pci_vpd_find_ro_info_keyword - Locate info field keyword in VPD RO section
2355 * @buf: Pointer to buffered VPD data
2356 * @len: The length of the buffer area in which to search
2357 * @kw: The keyword to search for
2358 * @size: Pointer to field where length of found keyword data is returned
2359 *
2360 * Returns the index of the information field keyword data or -ENOENT if
2361 * not found.
2362 */
2363 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2364 const char *kw, unsigned int *size);
2365
2366 /**
2367 * pci_vpd_check_csum - Check VPD checksum
2368 * @buf: Pointer to buffered VPD data
2369 * @len: VPD size
2370 *
2371 * Returns 1 if VPD has no checksum, otherwise 0 or an errno
2372 */
2373 int pci_vpd_check_csum(const void *buf, unsigned int len);
2374
2375 /* PCI <-> OF binding helpers */
2376 #ifdef CONFIG_OF
2377 struct device_node;
2378 struct irq_domain;
2379 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2380 bool pci_host_of_has_msi_map(struct device *dev);
2381
2382 /* Arch may override this (weak) */
2383 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2384
2385 #else /* CONFIG_OF */
2386 static inline struct irq_domain *
pci_host_bridge_of_msi_domain(struct pci_bus * bus)2387 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
pci_host_of_has_msi_map(struct device * dev)2388 static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2389 #endif /* CONFIG_OF */
2390
2391 static inline struct device_node *
pci_device_to_OF_node(const struct pci_dev * pdev)2392 pci_device_to_OF_node(const struct pci_dev *pdev)
2393 {
2394 return pdev ? pdev->dev.of_node : NULL;
2395 }
2396
pci_bus_to_OF_node(struct pci_bus * bus)2397 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2398 {
2399 return bus ? bus->dev.of_node : NULL;
2400 }
2401
2402 #ifdef CONFIG_ACPI
2403 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2404
2405 void
2406 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2407 bool pci_pr3_present(struct pci_dev *pdev);
2408 #else
2409 static inline struct irq_domain *
pci_host_bridge_acpi_msi_domain(struct pci_bus * bus)2410 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
pci_pr3_present(struct pci_dev * pdev)2411 static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2412 #endif
2413
2414 #ifdef CONFIG_EEH
pci_dev_to_eeh_dev(struct pci_dev * pdev)2415 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2416 {
2417 return pdev->dev.archdata.edev;
2418 }
2419 #endif
2420
2421 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2422 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2423 int pci_for_each_dma_alias(struct pci_dev *pdev,
2424 int (*fn)(struct pci_dev *pdev,
2425 u16 alias, void *data), void *data);
2426
2427 /* Helper functions for operation of device flag */
pci_set_dev_assigned(struct pci_dev * pdev)2428 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2429 {
2430 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2431 }
pci_clear_dev_assigned(struct pci_dev * pdev)2432 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2433 {
2434 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2435 }
pci_is_dev_assigned(struct pci_dev * pdev)2436 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2437 {
2438 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2439 }
2440
2441 /**
2442 * pci_ari_enabled - query ARI forwarding status
2443 * @bus: the PCI bus
2444 *
2445 * Returns true if ARI forwarding is enabled.
2446 */
pci_ari_enabled(struct pci_bus * bus)2447 static inline bool pci_ari_enabled(struct pci_bus *bus)
2448 {
2449 return bus->self && bus->self->ari_enabled;
2450 }
2451
2452 /**
2453 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2454 * @pdev: PCI device to check
2455 *
2456 * Walk upwards from @pdev and check for each encountered bridge if it's part
2457 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2458 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2459 */
pci_is_thunderbolt_attached(struct pci_dev * pdev)2460 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2461 {
2462 struct pci_dev *parent = pdev;
2463
2464 if (pdev->is_thunderbolt)
2465 return true;
2466
2467 while ((parent = pci_upstream_bridge(parent)))
2468 if (parent->is_thunderbolt)
2469 return true;
2470
2471 return false;
2472 }
2473
2474 #if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2475 void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2476 #endif
2477
2478 /* Provide the legacy pci_dma_* API */
2479 #include <linux/pci-dma-compat.h>
2480
2481 #define pci_printk(level, pdev, fmt, arg...) \
2482 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2483
2484 #define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2485 #define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2486 #define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2487 #define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2488 #define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2489 #define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2490 #define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2491 #define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2492
2493 #define pci_notice_ratelimited(pdev, fmt, arg...) \
2494 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2495
2496 #define pci_info_ratelimited(pdev, fmt, arg...) \
2497 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2498
2499 #define pci_WARN(pdev, condition, fmt, arg...) \
2500 WARN(condition, "%s %s: " fmt, \
2501 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2502
2503 #define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2504 WARN_ONCE(condition, "%s %s: " fmt, \
2505 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2506
2507 #endif /* LINUX_PCI_H */
2508