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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * PCI Express PCI Hot Plug Driver
4  *
5  * Copyright (C) 1995,2001 Compaq Computer Corporation
6  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
7  * Copyright (C) 2001 IBM Corp.
8  * Copyright (C) 2003-2004 Intel Corporation
9  *
10  * All rights reserved.
11  *
12  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
13  */
14 
15 #define dev_fmt(fmt) "pciehp: " fmt
16 
17 #include <linux/dmi.h>
18 #include <linux/kernel.h>
19 #include <linux/types.h>
20 #include <linux/jiffies.h>
21 #include <linux/kthread.h>
22 #include <linux/pci.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 
27 #include "../pci.h"
28 #include "pciehp.h"
29 
30 static const struct dmi_system_id inband_presence_disabled_dmi_table[] = {
31 	/*
32 	 * Match all Dell systems, as some Dell systems have inband
33 	 * presence disabled on NVMe slots (but don't support the bit to
34 	 * report it). Setting inband presence disabled should have no
35 	 * negative effect, except on broken hotplug slots that never
36 	 * assert presence detect--and those will still work, they will
37 	 * just have a bit of extra delay before being probed.
38 	 */
39 	{
40 		.ident = "Dell System",
41 		.matches = {
42 			DMI_MATCH(DMI_OEM_STRING, "Dell System"),
43 		},
44 	},
45 	{}
46 };
47 
ctrl_dev(struct controller * ctrl)48 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
49 {
50 	return ctrl->pcie->port;
51 }
52 
53 static irqreturn_t pciehp_isr(int irq, void *dev_id);
54 static irqreturn_t pciehp_ist(int irq, void *dev_id);
55 static int pciehp_poll(void *data);
56 
pciehp_request_irq(struct controller * ctrl)57 static inline int pciehp_request_irq(struct controller *ctrl)
58 {
59 	int retval, irq = ctrl->pcie->irq;
60 
61 	if (pciehp_poll_mode) {
62 		ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl,
63 						"pciehp_poll-%s",
64 						slot_name(ctrl));
65 		return PTR_ERR_OR_ZERO(ctrl->poll_thread);
66 	}
67 
68 	/* Installs the interrupt handler */
69 	retval = request_threaded_irq(irq, pciehp_isr, pciehp_ist,
70 				      IRQF_SHARED, "pciehp", ctrl);
71 	if (retval)
72 		ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
73 			 irq);
74 	return retval;
75 }
76 
pciehp_free_irq(struct controller * ctrl)77 static inline void pciehp_free_irq(struct controller *ctrl)
78 {
79 	if (pciehp_poll_mode)
80 		kthread_stop(ctrl->poll_thread);
81 	else
82 		free_irq(ctrl->pcie->irq, ctrl);
83 }
84 
pcie_poll_cmd(struct controller * ctrl,int timeout)85 static int pcie_poll_cmd(struct controller *ctrl, int timeout)
86 {
87 	struct pci_dev *pdev = ctrl_dev(ctrl);
88 	u16 slot_status;
89 
90 	do {
91 		pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
92 		if (slot_status == (u16) ~0) {
93 			ctrl_info(ctrl, "%s: no response from device\n",
94 				  __func__);
95 			return 0;
96 		}
97 
98 		if (slot_status & PCI_EXP_SLTSTA_CC) {
99 			pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
100 						   PCI_EXP_SLTSTA_CC);
101 			ctrl->cmd_busy = 0;
102 			smp_mb();
103 			return 1;
104 		}
105 		msleep(10);
106 		timeout -= 10;
107 	} while (timeout >= 0);
108 	return 0;	/* timeout */
109 }
110 
pcie_wait_cmd(struct controller * ctrl)111 static void pcie_wait_cmd(struct controller *ctrl)
112 {
113 	unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
114 	unsigned long duration = msecs_to_jiffies(msecs);
115 	unsigned long cmd_timeout = ctrl->cmd_started + duration;
116 	unsigned long now, timeout;
117 	int rc;
118 
119 	/*
120 	 * If the controller does not generate notifications for command
121 	 * completions, we never need to wait between writes.
122 	 */
123 	if (NO_CMD_CMPL(ctrl))
124 		return;
125 
126 	if (!ctrl->cmd_busy)
127 		return;
128 
129 	/*
130 	 * Even if the command has already timed out, we want to call
131 	 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
132 	 */
133 	now = jiffies;
134 	if (time_before_eq(cmd_timeout, now))
135 		timeout = 1;
136 	else
137 		timeout = cmd_timeout - now;
138 
139 	if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
140 	    ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
141 		rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
142 	else
143 		rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
144 
145 	if (!rc)
146 		ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
147 			  ctrl->slot_ctrl,
148 			  jiffies_to_msecs(jiffies - ctrl->cmd_started));
149 }
150 
151 #define CC_ERRATUM_MASK		(PCI_EXP_SLTCTL_PCC |	\
152 				 PCI_EXP_SLTCTL_PIC |	\
153 				 PCI_EXP_SLTCTL_AIC |	\
154 				 PCI_EXP_SLTCTL_EIC)
155 
pcie_do_write_cmd(struct controller * ctrl,u16 cmd,u16 mask,bool wait)156 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
157 			      u16 mask, bool wait)
158 {
159 	struct pci_dev *pdev = ctrl_dev(ctrl);
160 	u16 slot_ctrl_orig, slot_ctrl;
161 
162 	mutex_lock(&ctrl->ctrl_lock);
163 
164 	/*
165 	 * Always wait for any previous command that might still be in progress
166 	 */
167 	pcie_wait_cmd(ctrl);
168 
169 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
170 	if (slot_ctrl == (u16) ~0) {
171 		ctrl_info(ctrl, "%s: no response from device\n", __func__);
172 		goto out;
173 	}
174 
175 	slot_ctrl_orig = slot_ctrl;
176 	slot_ctrl &= ~mask;
177 	slot_ctrl |= (cmd & mask);
178 	ctrl->cmd_busy = 1;
179 	smp_mb();
180 	ctrl->slot_ctrl = slot_ctrl;
181 	pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
182 	ctrl->cmd_started = jiffies;
183 
184 	/*
185 	 * Controllers with the Intel CF118 and similar errata advertise
186 	 * Command Completed support, but they only set Command Completed
187 	 * if we change the "Control" bits for power, power indicator,
188 	 * attention indicator, or interlock.  If we only change the
189 	 * "Enable" bits, they never set the Command Completed bit.
190 	 */
191 	if (pdev->broken_cmd_compl &&
192 	    (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK))
193 		ctrl->cmd_busy = 0;
194 
195 	/*
196 	 * Optionally wait for the hardware to be ready for a new command,
197 	 * indicating completion of the above issued command.
198 	 */
199 	if (wait)
200 		pcie_wait_cmd(ctrl);
201 
202 out:
203 	mutex_unlock(&ctrl->ctrl_lock);
204 }
205 
206 /**
207  * pcie_write_cmd - Issue controller command
208  * @ctrl: controller to which the command is issued
209  * @cmd:  command value written to slot control register
210  * @mask: bitmask of slot control register to be modified
211  */
pcie_write_cmd(struct controller * ctrl,u16 cmd,u16 mask)212 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
213 {
214 	pcie_do_write_cmd(ctrl, cmd, mask, true);
215 }
216 
217 /* Same as above without waiting for the hardware to latch */
pcie_write_cmd_nowait(struct controller * ctrl,u16 cmd,u16 mask)218 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
219 {
220 	pcie_do_write_cmd(ctrl, cmd, mask, false);
221 }
222 
223 /**
224  * pciehp_check_link_active() - Is the link active
225  * @ctrl: PCIe hotplug controller
226  *
227  * Check whether the downstream link is currently active. Note it is
228  * possible that the card is removed immediately after this so the
229  * caller may need to take it into account.
230  *
231  * If the hotplug controller itself is not available anymore returns
232  * %-ENODEV.
233  */
pciehp_check_link_active(struct controller * ctrl)234 int pciehp_check_link_active(struct controller *ctrl)
235 {
236 	struct pci_dev *pdev = ctrl_dev(ctrl);
237 	u16 lnk_status;
238 	int ret;
239 
240 	ret = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
241 	if (ret == PCIBIOS_DEVICE_NOT_FOUND || lnk_status == (u16)~0)
242 		return -ENODEV;
243 
244 	ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
245 	ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
246 
247 	return ret;
248 }
249 
pci_bus_check_dev(struct pci_bus * bus,int devfn)250 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
251 {
252 	u32 l;
253 	int count = 0;
254 	int delay = 1000, step = 20;
255 	bool found = false;
256 
257 	do {
258 		found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
259 		count++;
260 
261 		if (found)
262 			break;
263 
264 		msleep(step);
265 		delay -= step;
266 	} while (delay > 0);
267 
268 	if (count > 1)
269 		pr_debug("pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
270 			pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
271 			PCI_FUNC(devfn), count, step, l);
272 
273 	return found;
274 }
275 
pcie_wait_for_presence(struct pci_dev * pdev)276 static void pcie_wait_for_presence(struct pci_dev *pdev)
277 {
278 	int timeout = 1250;
279 	u16 slot_status;
280 
281 	do {
282 		pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
283 		if (slot_status & PCI_EXP_SLTSTA_PDS)
284 			return;
285 		msleep(10);
286 		timeout -= 10;
287 	} while (timeout > 0);
288 }
289 
pciehp_check_link_status(struct controller * ctrl)290 int pciehp_check_link_status(struct controller *ctrl)
291 {
292 	struct pci_dev *pdev = ctrl_dev(ctrl);
293 	bool found;
294 	u16 lnk_status;
295 
296 	if (!pcie_wait_for_link(pdev, true)) {
297 		ctrl_info(ctrl, "Slot(%s): No link\n", slot_name(ctrl));
298 		return -1;
299 	}
300 
301 	if (ctrl->inband_presence_disabled)
302 		pcie_wait_for_presence(pdev);
303 
304 	found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
305 					PCI_DEVFN(0, 0));
306 
307 	/* ignore link or presence changes up to this point */
308 	if (found)
309 		atomic_and(~(PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC),
310 			   &ctrl->pending_events);
311 
312 	pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
313 	ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
314 	if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
315 	    !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
316 		ctrl_info(ctrl, "Slot(%s): Cannot train link: status %#06x\n",
317 			  slot_name(ctrl), lnk_status);
318 		return -1;
319 	}
320 
321 	pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
322 
323 	if (!found) {
324 		ctrl_info(ctrl, "Slot(%s): No device found\n",
325 			  slot_name(ctrl));
326 		return -1;
327 	}
328 
329 	return 0;
330 }
331 
__pciehp_link_set(struct controller * ctrl,bool enable)332 static int __pciehp_link_set(struct controller *ctrl, bool enable)
333 {
334 	struct pci_dev *pdev = ctrl_dev(ctrl);
335 
336 	pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
337 					   PCI_EXP_LNKCTL_LD,
338 					   enable ? 0 : PCI_EXP_LNKCTL_LD);
339 
340 	return 0;
341 }
342 
pciehp_link_enable(struct controller * ctrl)343 static int pciehp_link_enable(struct controller *ctrl)
344 {
345 	return __pciehp_link_set(ctrl, true);
346 }
347 
pciehp_get_raw_indicator_status(struct hotplug_slot * hotplug_slot,u8 * status)348 int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot,
349 				    u8 *status)
350 {
351 	struct controller *ctrl = to_ctrl(hotplug_slot);
352 	struct pci_dev *pdev = ctrl_dev(ctrl);
353 	u16 slot_ctrl;
354 
355 	pci_config_pm_runtime_get(pdev);
356 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
357 	pci_config_pm_runtime_put(pdev);
358 	*status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;
359 	return 0;
360 }
361 
pciehp_get_attention_status(struct hotplug_slot * hotplug_slot,u8 * status)362 int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status)
363 {
364 	struct controller *ctrl = to_ctrl(hotplug_slot);
365 	struct pci_dev *pdev = ctrl_dev(ctrl);
366 	u16 slot_ctrl;
367 
368 	pci_config_pm_runtime_get(pdev);
369 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
370 	pci_config_pm_runtime_put(pdev);
371 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
372 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
373 
374 	switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
375 	case PCI_EXP_SLTCTL_ATTN_IND_ON:
376 		*status = 1;	/* On */
377 		break;
378 	case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
379 		*status = 2;	/* Blink */
380 		break;
381 	case PCI_EXP_SLTCTL_ATTN_IND_OFF:
382 		*status = 0;	/* Off */
383 		break;
384 	default:
385 		*status = 0xFF;
386 		break;
387 	}
388 
389 	return 0;
390 }
391 
pciehp_get_power_status(struct controller * ctrl,u8 * status)392 void pciehp_get_power_status(struct controller *ctrl, u8 *status)
393 {
394 	struct pci_dev *pdev = ctrl_dev(ctrl);
395 	u16 slot_ctrl;
396 
397 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
398 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
399 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
400 
401 	switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
402 	case PCI_EXP_SLTCTL_PWR_ON:
403 		*status = 1;	/* On */
404 		break;
405 	case PCI_EXP_SLTCTL_PWR_OFF:
406 		*status = 0;	/* Off */
407 		break;
408 	default:
409 		*status = 0xFF;
410 		break;
411 	}
412 }
413 
pciehp_get_latch_status(struct controller * ctrl,u8 * status)414 void pciehp_get_latch_status(struct controller *ctrl, u8 *status)
415 {
416 	struct pci_dev *pdev = ctrl_dev(ctrl);
417 	u16 slot_status;
418 
419 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
420 	*status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
421 }
422 
423 /**
424  * pciehp_card_present() - Is the card present
425  * @ctrl: PCIe hotplug controller
426  *
427  * Function checks whether the card is currently present in the slot and
428  * in that case returns true. Note it is possible that the card is
429  * removed immediately after the check so the caller may need to take
430  * this into account.
431  *
432  * It the hotplug controller itself is not available anymore returns
433  * %-ENODEV.
434  */
pciehp_card_present(struct controller * ctrl)435 int pciehp_card_present(struct controller *ctrl)
436 {
437 	struct pci_dev *pdev = ctrl_dev(ctrl);
438 	u16 slot_status;
439 	int ret;
440 
441 	ret = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
442 	if (ret == PCIBIOS_DEVICE_NOT_FOUND || slot_status == (u16)~0)
443 		return -ENODEV;
444 
445 	return !!(slot_status & PCI_EXP_SLTSTA_PDS);
446 }
447 
448 /**
449  * pciehp_card_present_or_link_active() - whether given slot is occupied
450  * @ctrl: PCIe hotplug controller
451  *
452  * Unlike pciehp_card_present(), which determines presence solely from the
453  * Presence Detect State bit, this helper also returns true if the Link Active
454  * bit is set.  This is a concession to broken hotplug ports which hardwire
455  * Presence Detect State to zero, such as Wilocity's [1ae9:0200].
456  *
457  * Returns: %1 if the slot is occupied and %0 if it is not. If the hotplug
458  *	    port is not present anymore returns %-ENODEV.
459  */
pciehp_card_present_or_link_active(struct controller * ctrl)460 int pciehp_card_present_or_link_active(struct controller *ctrl)
461 {
462 	int ret;
463 
464 	ret = pciehp_card_present(ctrl);
465 	if (ret)
466 		return ret;
467 
468 	return pciehp_check_link_active(ctrl);
469 }
470 
pciehp_query_power_fault(struct controller * ctrl)471 int pciehp_query_power_fault(struct controller *ctrl)
472 {
473 	struct pci_dev *pdev = ctrl_dev(ctrl);
474 	u16 slot_status;
475 
476 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
477 	return !!(slot_status & PCI_EXP_SLTSTA_PFD);
478 }
479 
pciehp_set_raw_indicator_status(struct hotplug_slot * hotplug_slot,u8 status)480 int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot,
481 				    u8 status)
482 {
483 	struct controller *ctrl = to_ctrl(hotplug_slot);
484 	struct pci_dev *pdev = ctrl_dev(ctrl);
485 
486 	pci_config_pm_runtime_get(pdev);
487 	pcie_write_cmd_nowait(ctrl, status << 6,
488 			      PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC);
489 	pci_config_pm_runtime_put(pdev);
490 	return 0;
491 }
492 
493 /**
494  * pciehp_set_indicators() - set attention indicator, power indicator, or both
495  * @ctrl: PCIe hotplug controller
496  * @pwr: one of:
497  *	PCI_EXP_SLTCTL_PWR_IND_ON
498  *	PCI_EXP_SLTCTL_PWR_IND_BLINK
499  *	PCI_EXP_SLTCTL_PWR_IND_OFF
500  * @attn: one of:
501  *	PCI_EXP_SLTCTL_ATTN_IND_ON
502  *	PCI_EXP_SLTCTL_ATTN_IND_BLINK
503  *	PCI_EXP_SLTCTL_ATTN_IND_OFF
504  *
505  * Either @pwr or @attn can also be INDICATOR_NOOP to leave that indicator
506  * unchanged.
507  */
pciehp_set_indicators(struct controller * ctrl,int pwr,int attn)508 void pciehp_set_indicators(struct controller *ctrl, int pwr, int attn)
509 {
510 	u16 cmd = 0, mask = 0;
511 
512 	if (PWR_LED(ctrl) && pwr != INDICATOR_NOOP) {
513 		cmd |= (pwr & PCI_EXP_SLTCTL_PIC);
514 		mask |= PCI_EXP_SLTCTL_PIC;
515 	}
516 
517 	if (ATTN_LED(ctrl) && attn != INDICATOR_NOOP) {
518 		cmd |= (attn & PCI_EXP_SLTCTL_AIC);
519 		mask |= PCI_EXP_SLTCTL_AIC;
520 	}
521 
522 	if (cmd) {
523 		pcie_write_cmd_nowait(ctrl, cmd, mask);
524 		ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
525 			 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
526 	}
527 }
528 
pciehp_power_on_slot(struct controller * ctrl)529 int pciehp_power_on_slot(struct controller *ctrl)
530 {
531 	struct pci_dev *pdev = ctrl_dev(ctrl);
532 	u16 slot_status;
533 	int retval;
534 
535 	/* Clear power-fault bit from previous power failures */
536 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
537 	if (slot_status & PCI_EXP_SLTSTA_PFD)
538 		pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
539 					   PCI_EXP_SLTSTA_PFD);
540 	ctrl->power_fault_detected = 0;
541 
542 	pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
543 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
544 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
545 		 PCI_EXP_SLTCTL_PWR_ON);
546 
547 	retval = pciehp_link_enable(ctrl);
548 	if (retval)
549 		ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
550 
551 	return retval;
552 }
553 
pciehp_power_off_slot(struct controller * ctrl)554 void pciehp_power_off_slot(struct controller *ctrl)
555 {
556 	pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
557 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
558 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
559 		 PCI_EXP_SLTCTL_PWR_OFF);
560 }
561 
pciehp_ignore_dpc_link_change(struct controller * ctrl,struct pci_dev * pdev,int irq)562 static void pciehp_ignore_dpc_link_change(struct controller *ctrl,
563 					  struct pci_dev *pdev, int irq)
564 {
565 	/*
566 	 * Ignore link changes which occurred while waiting for DPC recovery.
567 	 * Could be several if DPC triggered multiple times consecutively.
568 	 */
569 	synchronize_hardirq(irq);
570 	atomic_and(~PCI_EXP_SLTSTA_DLLSC, &ctrl->pending_events);
571 	if (pciehp_poll_mode)
572 		pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
573 					   PCI_EXP_SLTSTA_DLLSC);
574 	ctrl_info(ctrl, "Slot(%s): Link Down/Up ignored (recovered by DPC)\n",
575 		  slot_name(ctrl));
576 
577 	/*
578 	 * If the link is unexpectedly down after successful recovery,
579 	 * the corresponding link change may have been ignored above.
580 	 * Synthesize it to ensure that it is acted on.
581 	 */
582 	down_read_nested(&ctrl->reset_lock, ctrl->depth);
583 	if (!pciehp_check_link_active(ctrl))
584 		pciehp_request(ctrl, PCI_EXP_SLTSTA_DLLSC);
585 	up_read(&ctrl->reset_lock);
586 }
587 
pciehp_isr(int irq,void * dev_id)588 static irqreturn_t pciehp_isr(int irq, void *dev_id)
589 {
590 	struct controller *ctrl = (struct controller *)dev_id;
591 	struct pci_dev *pdev = ctrl_dev(ctrl);
592 	struct device *parent = pdev->dev.parent;
593 	u16 status, events = 0;
594 
595 	/*
596 	 * Interrupts only occur in D3hot or shallower and only if enabled
597 	 * in the Slot Control register (PCIe r4.0, sec 6.7.3.4).
598 	 */
599 	if (pdev->current_state == PCI_D3cold ||
600 	    (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode))
601 		return IRQ_NONE;
602 
603 	/*
604 	 * Keep the port accessible by holding a runtime PM ref on its parent.
605 	 * Defer resume of the parent to the IRQ thread if it's suspended.
606 	 * Mask the interrupt until then.
607 	 */
608 	if (parent) {
609 		pm_runtime_get_noresume(parent);
610 		if (!pm_runtime_active(parent)) {
611 			pm_runtime_put(parent);
612 			disable_irq_nosync(irq);
613 			atomic_or(RERUN_ISR, &ctrl->pending_events);
614 			return IRQ_WAKE_THREAD;
615 		}
616 	}
617 
618 read_status:
619 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status);
620 	if (status == (u16) ~0) {
621 		ctrl_info(ctrl, "%s: no response from device\n", __func__);
622 		if (parent)
623 			pm_runtime_put(parent);
624 		return IRQ_NONE;
625 	}
626 
627 	/*
628 	 * Slot Status contains plain status bits as well as event
629 	 * notification bits; right now we only want the event bits.
630 	 */
631 	status &= PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
632 		  PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
633 		  PCI_EXP_SLTSTA_DLLSC;
634 
635 	/*
636 	 * If we've already reported a power fault, don't report it again
637 	 * until we've done something to handle it.
638 	 */
639 	if (ctrl->power_fault_detected)
640 		status &= ~PCI_EXP_SLTSTA_PFD;
641 	else if (status & PCI_EXP_SLTSTA_PFD)
642 		ctrl->power_fault_detected = true;
643 
644 	events |= status;
645 	if (!events) {
646 		if (parent)
647 			pm_runtime_put(parent);
648 		return IRQ_NONE;
649 	}
650 
651 	if (status) {
652 		pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, status);
653 
654 		/*
655 		 * In MSI mode, all event bits must be zero before the port
656 		 * will send a new interrupt (PCIe Base Spec r5.0 sec 6.7.3.4).
657 		 * So re-read the Slot Status register in case a bit was set
658 		 * between read and write.
659 		 */
660 		if (pci_dev_msi_enabled(pdev) && !pciehp_poll_mode)
661 			goto read_status;
662 	}
663 
664 	ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events);
665 	if (parent)
666 		pm_runtime_put(parent);
667 
668 	/*
669 	 * Command Completed notifications are not deferred to the
670 	 * IRQ thread because it may be waiting for their arrival.
671 	 */
672 	if (events & PCI_EXP_SLTSTA_CC) {
673 		ctrl->cmd_busy = 0;
674 		smp_mb();
675 		wake_up(&ctrl->queue);
676 
677 		if (events == PCI_EXP_SLTSTA_CC)
678 			return IRQ_HANDLED;
679 
680 		events &= ~PCI_EXP_SLTSTA_CC;
681 	}
682 
683 	if (pdev->ignore_hotplug) {
684 		ctrl_dbg(ctrl, "ignoring hotplug event %#06x\n", events);
685 		return IRQ_HANDLED;
686 	}
687 
688 	/* Save pending events for consumption by IRQ thread. */
689 	atomic_or(events, &ctrl->pending_events);
690 	return IRQ_WAKE_THREAD;
691 }
692 
pciehp_ist(int irq,void * dev_id)693 static irqreturn_t pciehp_ist(int irq, void *dev_id)
694 {
695 	struct controller *ctrl = (struct controller *)dev_id;
696 	struct pci_dev *pdev = ctrl_dev(ctrl);
697 	irqreturn_t ret;
698 	u32 events;
699 
700 	ctrl->ist_running = true;
701 	pci_config_pm_runtime_get(pdev);
702 
703 	/* rerun pciehp_isr() if the port was inaccessible on interrupt */
704 	if (atomic_fetch_and(~RERUN_ISR, &ctrl->pending_events) & RERUN_ISR) {
705 		ret = pciehp_isr(irq, dev_id);
706 		enable_irq(irq);
707 		if (ret != IRQ_WAKE_THREAD)
708 			goto out;
709 	}
710 
711 	synchronize_hardirq(irq);
712 	events = atomic_xchg(&ctrl->pending_events, 0);
713 	if (!events) {
714 		ret = IRQ_NONE;
715 		goto out;
716 	}
717 
718 	/* Check Attention Button Pressed */
719 	if (events & PCI_EXP_SLTSTA_ABP) {
720 		ctrl_info(ctrl, "Slot(%s): Attention button pressed\n",
721 			  slot_name(ctrl));
722 		pciehp_handle_button_press(ctrl);
723 	}
724 
725 	/* Check Power Fault Detected */
726 	if (events & PCI_EXP_SLTSTA_PFD) {
727 		ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(ctrl));
728 		pciehp_set_indicators(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
729 				      PCI_EXP_SLTCTL_ATTN_IND_ON);
730 	}
731 
732 	/*
733 	 * Ignore Link Down/Up events caused by Downstream Port Containment
734 	 * if recovery from the error succeeded.
735 	 */
736 	if ((events & PCI_EXP_SLTSTA_DLLSC) && pci_dpc_recovered(pdev) &&
737 	    ctrl->state == ON_STATE) {
738 		events &= ~PCI_EXP_SLTSTA_DLLSC;
739 		pciehp_ignore_dpc_link_change(ctrl, pdev, irq);
740 	}
741 
742 	/*
743 	 * Disable requests have higher priority than Presence Detect Changed
744 	 * or Data Link Layer State Changed events.
745 	 */
746 	down_read_nested(&ctrl->reset_lock, ctrl->depth);
747 	if (events & DISABLE_SLOT)
748 		pciehp_handle_disable_request(ctrl);
749 	else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC))
750 		pciehp_handle_presence_or_link_change(ctrl, events);
751 	up_read(&ctrl->reset_lock);
752 
753 	ret = IRQ_HANDLED;
754 out:
755 	pci_config_pm_runtime_put(pdev);
756 	ctrl->ist_running = false;
757 	wake_up(&ctrl->requester);
758 	return ret;
759 }
760 
pciehp_poll(void * data)761 static int pciehp_poll(void *data)
762 {
763 	struct controller *ctrl = data;
764 
765 	schedule_timeout_idle(10 * HZ); /* start with 10 sec delay */
766 
767 	while (!kthread_should_stop()) {
768 		/* poll for interrupt events or user requests */
769 		while (pciehp_isr(IRQ_NOTCONNECTED, ctrl) == IRQ_WAKE_THREAD ||
770 		       atomic_read(&ctrl->pending_events))
771 			pciehp_ist(IRQ_NOTCONNECTED, ctrl);
772 
773 		if (pciehp_poll_time <= 0 || pciehp_poll_time > 60)
774 			pciehp_poll_time = 2; /* clamp to sane value */
775 
776 		schedule_timeout_idle(pciehp_poll_time * HZ);
777 	}
778 
779 	return 0;
780 }
781 
pcie_enable_notification(struct controller * ctrl)782 static void pcie_enable_notification(struct controller *ctrl)
783 {
784 	u16 cmd, mask;
785 
786 	/*
787 	 * TBD: Power fault detected software notification support.
788 	 *
789 	 * Power fault detected software notification is not enabled
790 	 * now, because it caused power fault detected interrupt storm
791 	 * on some machines. On those machines, power fault detected
792 	 * bit in the slot status register was set again immediately
793 	 * when it is cleared in the interrupt service routine, and
794 	 * next power fault detected interrupt was notified again.
795 	 */
796 
797 	/*
798 	 * Always enable link events: thus link-up and link-down shall
799 	 * always be treated as hotplug and unplug respectively. Enable
800 	 * presence detect only if Attention Button is not present.
801 	 */
802 	cmd = PCI_EXP_SLTCTL_DLLSCE;
803 	if (ATTN_BUTTN(ctrl))
804 		cmd |= PCI_EXP_SLTCTL_ABPE;
805 	else
806 		cmd |= PCI_EXP_SLTCTL_PDCE;
807 	if (!pciehp_poll_mode)
808 		cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
809 
810 	mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
811 		PCI_EXP_SLTCTL_PFDE |
812 		PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
813 		PCI_EXP_SLTCTL_DLLSCE);
814 
815 	pcie_write_cmd_nowait(ctrl, cmd, mask);
816 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
817 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
818 }
819 
pcie_disable_notification(struct controller * ctrl)820 static void pcie_disable_notification(struct controller *ctrl)
821 {
822 	u16 mask;
823 
824 	mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
825 		PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
826 		PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
827 		PCI_EXP_SLTCTL_DLLSCE);
828 	pcie_write_cmd(ctrl, 0, mask);
829 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
830 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
831 }
832 
pcie_clear_hotplug_events(struct controller * ctrl)833 void pcie_clear_hotplug_events(struct controller *ctrl)
834 {
835 	pcie_capability_write_word(ctrl_dev(ctrl), PCI_EXP_SLTSTA,
836 				   PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC);
837 }
838 
pcie_enable_interrupt(struct controller * ctrl)839 void pcie_enable_interrupt(struct controller *ctrl)
840 {
841 	u16 mask;
842 
843 	mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
844 	pcie_write_cmd(ctrl, mask, mask);
845 }
846 
pcie_disable_interrupt(struct controller * ctrl)847 void pcie_disable_interrupt(struct controller *ctrl)
848 {
849 	u16 mask;
850 
851 	/*
852 	 * Mask hot-plug interrupt to prevent it triggering immediately
853 	 * when the link goes inactive (we still get PME when any of the
854 	 * enabled events is detected). Same goes with Link Layer State
855 	 * changed event which generates PME immediately when the link goes
856 	 * inactive so mask it as well.
857 	 */
858 	mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
859 	pcie_write_cmd(ctrl, 0, mask);
860 }
861 
862 /**
863  * pciehp_slot_reset() - ignore link event caused by error-induced hot reset
864  * @dev: PCI Express port service device
865  *
866  * Called from pcie_portdrv_slot_reset() after AER or DPC initiated a reset
867  * further up in the hierarchy to recover from an error.  The reset was
868  * propagated down to this hotplug port.  Ignore the resulting link flap.
869  * If the link failed to retrain successfully, synthesize the ignored event.
870  * Surprise removal during reset is detected through Presence Detect Changed.
871  */
pciehp_slot_reset(struct pcie_device * dev)872 int pciehp_slot_reset(struct pcie_device *dev)
873 {
874 	struct controller *ctrl = get_service_data(dev);
875 
876 	if (ctrl->state != ON_STATE)
877 		return 0;
878 
879 	pcie_capability_write_word(dev->port, PCI_EXP_SLTSTA,
880 				   PCI_EXP_SLTSTA_DLLSC);
881 
882 	if (!pciehp_check_link_active(ctrl))
883 		pciehp_request(ctrl, PCI_EXP_SLTSTA_DLLSC);
884 
885 	return 0;
886 }
887 
888 /*
889  * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
890  * bus reset of the bridge, but at the same time we want to ensure that it is
891  * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
892  * disable link state notification and presence detection change notification
893  * momentarily, if we see that they could interfere. Also, clear any spurious
894  * events after.
895  */
pciehp_reset_slot(struct hotplug_slot * hotplug_slot,bool probe)896 int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, bool probe)
897 {
898 	struct controller *ctrl = to_ctrl(hotplug_slot);
899 	struct pci_dev *pdev = ctrl_dev(ctrl);
900 	u16 stat_mask = 0, ctrl_mask = 0;
901 	int rc;
902 
903 	if (probe)
904 		return 0;
905 
906 	down_write_nested(&ctrl->reset_lock, ctrl->depth);
907 
908 	if (!ATTN_BUTTN(ctrl)) {
909 		ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
910 		stat_mask |= PCI_EXP_SLTSTA_PDC;
911 	}
912 	ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
913 	stat_mask |= PCI_EXP_SLTSTA_DLLSC;
914 
915 	pcie_write_cmd(ctrl, 0, ctrl_mask);
916 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
917 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
918 
919 	rc = pci_bridge_secondary_bus_reset(ctrl->pcie->port);
920 
921 	pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
922 	pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
923 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
924 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
925 
926 	up_write(&ctrl->reset_lock);
927 	return rc;
928 }
929 
pcie_init_notification(struct controller * ctrl)930 int pcie_init_notification(struct controller *ctrl)
931 {
932 	if (pciehp_request_irq(ctrl))
933 		return -1;
934 	pcie_enable_notification(ctrl);
935 	ctrl->notification_enabled = 1;
936 	return 0;
937 }
938 
pcie_shutdown_notification(struct controller * ctrl)939 void pcie_shutdown_notification(struct controller *ctrl)
940 {
941 	if (ctrl->notification_enabled) {
942 		pcie_disable_notification(ctrl);
943 		pciehp_free_irq(ctrl);
944 		ctrl->notification_enabled = 0;
945 	}
946 }
947 
dbg_ctrl(struct controller * ctrl)948 static inline void dbg_ctrl(struct controller *ctrl)
949 {
950 	struct pci_dev *pdev = ctrl->pcie->port;
951 	u16 reg16;
952 
953 	ctrl_dbg(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
954 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &reg16);
955 	ctrl_dbg(ctrl, "Slot Status            : 0x%04x\n", reg16);
956 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &reg16);
957 	ctrl_dbg(ctrl, "Slot Control           : 0x%04x\n", reg16);
958 }
959 
960 #define FLAG(x, y)	(((x) & (y)) ? '+' : '-')
961 
pcie_hotplug_depth(struct pci_dev * dev)962 static inline int pcie_hotplug_depth(struct pci_dev *dev)
963 {
964 	struct pci_bus *bus = dev->bus;
965 	int depth = 0;
966 
967 	while (bus->parent) {
968 		bus = bus->parent;
969 		if (bus->self && bus->self->is_hotplug_bridge)
970 			depth++;
971 	}
972 
973 	return depth;
974 }
975 
pcie_init(struct pcie_device * dev)976 struct controller *pcie_init(struct pcie_device *dev)
977 {
978 	struct controller *ctrl;
979 	u32 slot_cap, slot_cap2, link_cap;
980 	u8 poweron;
981 	struct pci_dev *pdev = dev->port;
982 	struct pci_bus *subordinate = pdev->subordinate;
983 
984 	ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
985 	if (!ctrl)
986 		return NULL;
987 
988 	ctrl->pcie = dev;
989 	ctrl->depth = pcie_hotplug_depth(dev->port);
990 	pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
991 
992 	if (pdev->hotplug_user_indicators)
993 		slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP);
994 
995 	/*
996 	 * We assume no Thunderbolt controllers support Command Complete events,
997 	 * but some controllers falsely claim they do.
998 	 */
999 	if (pdev->is_thunderbolt)
1000 		slot_cap |= PCI_EXP_SLTCAP_NCCS;
1001 
1002 	ctrl->slot_cap = slot_cap;
1003 	mutex_init(&ctrl->ctrl_lock);
1004 	mutex_init(&ctrl->state_lock);
1005 	init_rwsem(&ctrl->reset_lock);
1006 	init_waitqueue_head(&ctrl->requester);
1007 	init_waitqueue_head(&ctrl->queue);
1008 	INIT_DELAYED_WORK(&ctrl->button_work, pciehp_queue_pushbutton_work);
1009 	dbg_ctrl(ctrl);
1010 
1011 	down_read(&pci_bus_sem);
1012 	ctrl->state = list_empty(&subordinate->devices) ? OFF_STATE : ON_STATE;
1013 	up_read(&pci_bus_sem);
1014 
1015 	pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP2, &slot_cap2);
1016 	if (slot_cap2 & PCI_EXP_SLTCAP2_IBPD) {
1017 		pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_IBPD_DISABLE,
1018 				      PCI_EXP_SLTCTL_IBPD_DISABLE);
1019 		ctrl->inband_presence_disabled = 1;
1020 	}
1021 
1022 	if (dmi_first_match(inband_presence_disabled_dmi_table))
1023 		ctrl->inband_presence_disabled = 1;
1024 
1025 	/* Check if Data Link Layer Link Active Reporting is implemented */
1026 	pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
1027 
1028 	/* Clear all remaining event bits in Slot Status register. */
1029 	pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
1030 		PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
1031 		PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC |
1032 		PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC);
1033 
1034 	ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c IbPresDis%c LLActRep%c%s\n",
1035 		(slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
1036 		FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
1037 		FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
1038 		FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
1039 		FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
1040 		FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
1041 		FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
1042 		FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
1043 		FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
1044 		FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
1045 		FLAG(slot_cap2, PCI_EXP_SLTCAP2_IBPD),
1046 		FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC),
1047 		pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : "");
1048 
1049 	/*
1050 	 * If empty slot's power status is on, turn power off.  The IRQ isn't
1051 	 * requested yet, so avoid triggering a notification with this command.
1052 	 */
1053 	if (POWER_CTRL(ctrl)) {
1054 		pciehp_get_power_status(ctrl, &poweron);
1055 		if (!pciehp_card_present_or_link_active(ctrl) && poweron) {
1056 			pcie_disable_notification(ctrl);
1057 			pciehp_power_off_slot(ctrl);
1058 		}
1059 	}
1060 
1061 	return ctrl;
1062 }
1063 
pciehp_release_ctrl(struct controller * ctrl)1064 void pciehp_release_ctrl(struct controller *ctrl)
1065 {
1066 	cancel_delayed_work_sync(&ctrl->button_work);
1067 	kfree(ctrl);
1068 }
1069 
quirk_cmd_compl(struct pci_dev * pdev)1070 static void quirk_cmd_compl(struct pci_dev *pdev)
1071 {
1072 	u32 slot_cap;
1073 
1074 	if (pci_is_pcie(pdev)) {
1075 		pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
1076 		if (slot_cap & PCI_EXP_SLTCAP_HPC &&
1077 		    !(slot_cap & PCI_EXP_SLTCAP_NCCS))
1078 			pdev->broken_cmd_compl = 1;
1079 	}
1080 }
1081 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1082 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1083 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0110,
1084 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1085 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400,
1086 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1087 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401,
1088 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1089 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_HXT, 0x0401,
1090 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1091