1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2006, Intel Corporation.
4 *
5 * Copyright (C) 2006-2008 Intel Corporation
6 * Author: Ashok Raj <ashok.raj@intel.com>
7 * Author: Shaohua Li <shaohua.li@intel.com>
8 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
9 *
10 * This file implements early detection/parsing of Remapping Devices
11 * reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI
12 * tables.
13 *
14 * These routines are used by both DMA-remapping and Interrupt-remapping
15 */
16
17 #define pr_fmt(fmt) "DMAR: " fmt
18
19 #include <linux/pci.h>
20 #include <linux/dmar.h>
21 #include <linux/iova.h>
22 #include <linux/intel-iommu.h>
23 #include <linux/timer.h>
24 #include <linux/irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/tboot.h>
27 #include <linux/dmi.h>
28 #include <linux/slab.h>
29 #include <linux/iommu.h>
30 #include <linux/numa.h>
31 #include <linux/limits.h>
32 #include <asm/irq_remapping.h>
33 #include <asm/iommu_table.h>
34 #include <trace/events/intel_iommu.h>
35
36 #include "../irq_remapping.h"
37 #include "perf.h"
38
39 typedef int (*dmar_res_handler_t)(struct acpi_dmar_header *, void *);
40 struct dmar_res_callback {
41 dmar_res_handler_t cb[ACPI_DMAR_TYPE_RESERVED];
42 void *arg[ACPI_DMAR_TYPE_RESERVED];
43 bool ignore_unhandled;
44 bool print_entry;
45 };
46
47 /*
48 * Assumptions:
49 * 1) The hotplug framework guarentees that DMAR unit will be hot-added
50 * before IO devices managed by that unit.
51 * 2) The hotplug framework guarantees that DMAR unit will be hot-removed
52 * after IO devices managed by that unit.
53 * 3) Hotplug events are rare.
54 *
55 * Locking rules for DMA and interrupt remapping related global data structures:
56 * 1) Use dmar_global_lock in process context
57 * 2) Use RCU in interrupt context
58 */
59 DECLARE_RWSEM(dmar_global_lock);
60 LIST_HEAD(dmar_drhd_units);
61
62 struct acpi_table_header * __initdata dmar_tbl;
63 static int dmar_dev_scope_status = 1;
64 static unsigned long dmar_seq_ids[BITS_TO_LONGS(DMAR_UNITS_SUPPORTED)];
65
66 static int alloc_iommu(struct dmar_drhd_unit *drhd);
67 static void free_iommu(struct intel_iommu *iommu);
68
69 extern const struct iommu_ops intel_iommu_ops;
70
dmar_register_drhd_unit(struct dmar_drhd_unit * drhd)71 static void dmar_register_drhd_unit(struct dmar_drhd_unit *drhd)
72 {
73 /*
74 * add INCLUDE_ALL at the tail, so scan the list will find it at
75 * the very end.
76 */
77 if (drhd->include_all)
78 list_add_tail_rcu(&drhd->list, &dmar_drhd_units);
79 else
80 list_add_rcu(&drhd->list, &dmar_drhd_units);
81 }
82
dmar_alloc_dev_scope(void * start,void * end,int * cnt)83 void *dmar_alloc_dev_scope(void *start, void *end, int *cnt)
84 {
85 struct acpi_dmar_device_scope *scope;
86
87 *cnt = 0;
88 while (start < end) {
89 scope = start;
90 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_NAMESPACE ||
91 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT ||
92 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE)
93 (*cnt)++;
94 else if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_IOAPIC &&
95 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_HPET) {
96 pr_warn("Unsupported device scope\n");
97 }
98 start += scope->length;
99 }
100 if (*cnt == 0)
101 return NULL;
102
103 return kcalloc(*cnt, sizeof(struct dmar_dev_scope), GFP_KERNEL);
104 }
105
dmar_free_dev_scope(struct dmar_dev_scope ** devices,int * cnt)106 void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt)
107 {
108 int i;
109 struct device *tmp_dev;
110
111 if (*devices && *cnt) {
112 for_each_active_dev_scope(*devices, *cnt, i, tmp_dev)
113 put_device(tmp_dev);
114 kfree(*devices);
115 }
116
117 *devices = NULL;
118 *cnt = 0;
119 }
120
121 /* Optimize out kzalloc()/kfree() for normal cases */
122 static char dmar_pci_notify_info_buf[64];
123
124 static struct dmar_pci_notify_info *
dmar_alloc_pci_notify_info(struct pci_dev * dev,unsigned long event)125 dmar_alloc_pci_notify_info(struct pci_dev *dev, unsigned long event)
126 {
127 int level = 0;
128 size_t size;
129 struct pci_dev *tmp;
130 struct dmar_pci_notify_info *info;
131
132 BUG_ON(dev->is_virtfn);
133
134 /*
135 * Ignore devices that have a domain number higher than what can
136 * be looked up in DMAR, e.g. VMD subdevices with domain 0x10000
137 */
138 if (pci_domain_nr(dev->bus) > U16_MAX)
139 return NULL;
140
141 /* Only generate path[] for device addition event */
142 if (event == BUS_NOTIFY_ADD_DEVICE)
143 for (tmp = dev; tmp; tmp = tmp->bus->self)
144 level++;
145
146 size = struct_size(info, path, level);
147 if (size <= sizeof(dmar_pci_notify_info_buf)) {
148 info = (struct dmar_pci_notify_info *)dmar_pci_notify_info_buf;
149 } else {
150 info = kzalloc(size, GFP_KERNEL);
151 if (!info) {
152 if (dmar_dev_scope_status == 0)
153 dmar_dev_scope_status = -ENOMEM;
154 return NULL;
155 }
156 }
157
158 info->event = event;
159 info->dev = dev;
160 info->seg = pci_domain_nr(dev->bus);
161 info->level = level;
162 if (event == BUS_NOTIFY_ADD_DEVICE) {
163 for (tmp = dev; tmp; tmp = tmp->bus->self) {
164 level--;
165 info->path[level].bus = tmp->bus->number;
166 info->path[level].device = PCI_SLOT(tmp->devfn);
167 info->path[level].function = PCI_FUNC(tmp->devfn);
168 if (pci_is_root_bus(tmp->bus))
169 info->bus = tmp->bus->number;
170 }
171 }
172
173 return info;
174 }
175
dmar_free_pci_notify_info(struct dmar_pci_notify_info * info)176 static inline void dmar_free_pci_notify_info(struct dmar_pci_notify_info *info)
177 {
178 if ((void *)info != dmar_pci_notify_info_buf)
179 kfree(info);
180 }
181
dmar_match_pci_path(struct dmar_pci_notify_info * info,int bus,struct acpi_dmar_pci_path * path,int count)182 static bool dmar_match_pci_path(struct dmar_pci_notify_info *info, int bus,
183 struct acpi_dmar_pci_path *path, int count)
184 {
185 int i;
186
187 if (info->bus != bus)
188 goto fallback;
189 if (info->level != count)
190 goto fallback;
191
192 for (i = 0; i < count; i++) {
193 if (path[i].device != info->path[i].device ||
194 path[i].function != info->path[i].function)
195 goto fallback;
196 }
197
198 return true;
199
200 fallback:
201
202 if (count != 1)
203 return false;
204
205 i = info->level - 1;
206 if (bus == info->path[i].bus &&
207 path[0].device == info->path[i].device &&
208 path[0].function == info->path[i].function) {
209 pr_info(FW_BUG "RMRR entry for device %02x:%02x.%x is broken - applying workaround\n",
210 bus, path[0].device, path[0].function);
211 return true;
212 }
213
214 return false;
215 }
216
217 /* Return: > 0 if match found, 0 if no match found, < 0 if error happens */
dmar_insert_dev_scope(struct dmar_pci_notify_info * info,void * start,void * end,u16 segment,struct dmar_dev_scope * devices,int devices_cnt)218 int dmar_insert_dev_scope(struct dmar_pci_notify_info *info,
219 void *start, void*end, u16 segment,
220 struct dmar_dev_scope *devices,
221 int devices_cnt)
222 {
223 int i, level;
224 struct device *tmp, *dev = &info->dev->dev;
225 struct acpi_dmar_device_scope *scope;
226 struct acpi_dmar_pci_path *path;
227
228 if (segment != info->seg)
229 return 0;
230
231 for (; start < end; start += scope->length) {
232 scope = start;
233 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
234 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
235 continue;
236
237 path = (struct acpi_dmar_pci_path *)(scope + 1);
238 level = (scope->length - sizeof(*scope)) / sizeof(*path);
239 if (!dmar_match_pci_path(info, scope->bus, path, level))
240 continue;
241
242 /*
243 * We expect devices with endpoint scope to have normal PCI
244 * headers, and devices with bridge scope to have bridge PCI
245 * headers. However PCI NTB devices may be listed in the
246 * DMAR table with bridge scope, even though they have a
247 * normal PCI header. NTB devices are identified by class
248 * "BRIDGE_OTHER" (0680h) - we don't declare a socpe mismatch
249 * for this special case.
250 */
251 if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
252 info->dev->hdr_type != PCI_HEADER_TYPE_NORMAL) ||
253 (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE &&
254 (info->dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
255 info->dev->class >> 16 != PCI_BASE_CLASS_BRIDGE))) {
256 pr_warn("Device scope type does not match for %s\n",
257 pci_name(info->dev));
258 return -EINVAL;
259 }
260
261 for_each_dev_scope(devices, devices_cnt, i, tmp)
262 if (tmp == NULL) {
263 devices[i].bus = info->dev->bus->number;
264 devices[i].devfn = info->dev->devfn;
265 rcu_assign_pointer(devices[i].dev,
266 get_device(dev));
267 return 1;
268 }
269 BUG_ON(i >= devices_cnt);
270 }
271
272 return 0;
273 }
274
dmar_remove_dev_scope(struct dmar_pci_notify_info * info,u16 segment,struct dmar_dev_scope * devices,int count)275 int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, u16 segment,
276 struct dmar_dev_scope *devices, int count)
277 {
278 int index;
279 struct device *tmp;
280
281 if (info->seg != segment)
282 return 0;
283
284 for_each_active_dev_scope(devices, count, index, tmp)
285 if (tmp == &info->dev->dev) {
286 RCU_INIT_POINTER(devices[index].dev, NULL);
287 synchronize_rcu();
288 put_device(tmp);
289 return 1;
290 }
291
292 return 0;
293 }
294
dmar_pci_bus_add_dev(struct dmar_pci_notify_info * info)295 static int dmar_pci_bus_add_dev(struct dmar_pci_notify_info *info)
296 {
297 int ret = 0;
298 struct dmar_drhd_unit *dmaru;
299 struct acpi_dmar_hardware_unit *drhd;
300
301 for_each_drhd_unit(dmaru) {
302 if (dmaru->include_all)
303 continue;
304
305 drhd = container_of(dmaru->hdr,
306 struct acpi_dmar_hardware_unit, header);
307 ret = dmar_insert_dev_scope(info, (void *)(drhd + 1),
308 ((void *)drhd) + drhd->header.length,
309 dmaru->segment,
310 dmaru->devices, dmaru->devices_cnt);
311 if (ret)
312 break;
313 }
314 if (ret >= 0)
315 ret = dmar_iommu_notify_scope_dev(info);
316 if (ret < 0 && dmar_dev_scope_status == 0)
317 dmar_dev_scope_status = ret;
318
319 if (ret >= 0)
320 intel_irq_remap_add_device(info);
321
322 return ret;
323 }
324
dmar_pci_bus_del_dev(struct dmar_pci_notify_info * info)325 static void dmar_pci_bus_del_dev(struct dmar_pci_notify_info *info)
326 {
327 struct dmar_drhd_unit *dmaru;
328
329 for_each_drhd_unit(dmaru)
330 if (dmar_remove_dev_scope(info, dmaru->segment,
331 dmaru->devices, dmaru->devices_cnt))
332 break;
333 dmar_iommu_notify_scope_dev(info);
334 }
335
vf_inherit_msi_domain(struct pci_dev * pdev)336 static inline void vf_inherit_msi_domain(struct pci_dev *pdev)
337 {
338 struct pci_dev *physfn = pci_physfn(pdev);
339
340 dev_set_msi_domain(&pdev->dev, dev_get_msi_domain(&physfn->dev));
341 }
342
dmar_pci_bus_notifier(struct notifier_block * nb,unsigned long action,void * data)343 static int dmar_pci_bus_notifier(struct notifier_block *nb,
344 unsigned long action, void *data)
345 {
346 struct pci_dev *pdev = to_pci_dev(data);
347 struct dmar_pci_notify_info *info;
348
349 /* Only care about add/remove events for physical functions.
350 * For VFs we actually do the lookup based on the corresponding
351 * PF in device_to_iommu() anyway. */
352 if (pdev->is_virtfn) {
353 /*
354 * Ensure that the VF device inherits the irq domain of the
355 * PF device. Ideally the device would inherit the domain
356 * from the bus, but DMAR can have multiple units per bus
357 * which makes this impossible. The VF 'bus' could inherit
358 * from the PF device, but that's yet another x86'sism to
359 * inflict on everybody else.
360 */
361 if (action == BUS_NOTIFY_ADD_DEVICE)
362 vf_inherit_msi_domain(pdev);
363 return NOTIFY_DONE;
364 }
365
366 if (action != BUS_NOTIFY_ADD_DEVICE &&
367 action != BUS_NOTIFY_REMOVED_DEVICE)
368 return NOTIFY_DONE;
369
370 info = dmar_alloc_pci_notify_info(pdev, action);
371 if (!info)
372 return NOTIFY_DONE;
373
374 down_write(&dmar_global_lock);
375 if (action == BUS_NOTIFY_ADD_DEVICE)
376 dmar_pci_bus_add_dev(info);
377 else if (action == BUS_NOTIFY_REMOVED_DEVICE)
378 dmar_pci_bus_del_dev(info);
379 up_write(&dmar_global_lock);
380
381 dmar_free_pci_notify_info(info);
382
383 return NOTIFY_OK;
384 }
385
386 static struct notifier_block dmar_pci_bus_nb = {
387 .notifier_call = dmar_pci_bus_notifier,
388 .priority = 1,
389 };
390
391 static struct dmar_drhd_unit *
dmar_find_dmaru(struct acpi_dmar_hardware_unit * drhd)392 dmar_find_dmaru(struct acpi_dmar_hardware_unit *drhd)
393 {
394 struct dmar_drhd_unit *dmaru;
395
396 list_for_each_entry_rcu(dmaru, &dmar_drhd_units, list,
397 dmar_rcu_check())
398 if (dmaru->segment == drhd->segment &&
399 dmaru->reg_base_addr == drhd->address)
400 return dmaru;
401
402 return NULL;
403 }
404
405 /*
406 * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition
407 * structure which uniquely represent one DMA remapping hardware unit
408 * present in the platform
409 */
dmar_parse_one_drhd(struct acpi_dmar_header * header,void * arg)410 static int dmar_parse_one_drhd(struct acpi_dmar_header *header, void *arg)
411 {
412 struct acpi_dmar_hardware_unit *drhd;
413 struct dmar_drhd_unit *dmaru;
414 int ret;
415
416 drhd = (struct acpi_dmar_hardware_unit *)header;
417 dmaru = dmar_find_dmaru(drhd);
418 if (dmaru)
419 goto out;
420
421 dmaru = kzalloc(sizeof(*dmaru) + header->length, GFP_KERNEL);
422 if (!dmaru)
423 return -ENOMEM;
424
425 /*
426 * If header is allocated from slab by ACPI _DSM method, we need to
427 * copy the content because the memory buffer will be freed on return.
428 */
429 dmaru->hdr = (void *)(dmaru + 1);
430 memcpy(dmaru->hdr, header, header->length);
431 dmaru->reg_base_addr = drhd->address;
432 dmaru->segment = drhd->segment;
433 dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */
434 dmaru->devices = dmar_alloc_dev_scope((void *)(drhd + 1),
435 ((void *)drhd) + drhd->header.length,
436 &dmaru->devices_cnt);
437 if (dmaru->devices_cnt && dmaru->devices == NULL) {
438 kfree(dmaru);
439 return -ENOMEM;
440 }
441
442 ret = alloc_iommu(dmaru);
443 if (ret) {
444 dmar_free_dev_scope(&dmaru->devices,
445 &dmaru->devices_cnt);
446 kfree(dmaru);
447 return ret;
448 }
449 dmar_register_drhd_unit(dmaru);
450
451 out:
452 if (arg)
453 (*(int *)arg)++;
454
455 return 0;
456 }
457
dmar_free_drhd(struct dmar_drhd_unit * dmaru)458 static void dmar_free_drhd(struct dmar_drhd_unit *dmaru)
459 {
460 if (dmaru->devices && dmaru->devices_cnt)
461 dmar_free_dev_scope(&dmaru->devices, &dmaru->devices_cnt);
462 if (dmaru->iommu)
463 free_iommu(dmaru->iommu);
464 kfree(dmaru);
465 }
466
dmar_parse_one_andd(struct acpi_dmar_header * header,void * arg)467 static int __init dmar_parse_one_andd(struct acpi_dmar_header *header,
468 void *arg)
469 {
470 struct acpi_dmar_andd *andd = (void *)header;
471
472 /* Check for NUL termination within the designated length */
473 if (strnlen(andd->device_name, header->length - 8) == header->length - 8) {
474 pr_warn(FW_BUG
475 "Your BIOS is broken; ANDD object name is not NUL-terminated\n"
476 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
477 dmi_get_system_info(DMI_BIOS_VENDOR),
478 dmi_get_system_info(DMI_BIOS_VERSION),
479 dmi_get_system_info(DMI_PRODUCT_VERSION));
480 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
481 return -EINVAL;
482 }
483 pr_info("ANDD device: %x name: %s\n", andd->device_number,
484 andd->device_name);
485
486 return 0;
487 }
488
489 #ifdef CONFIG_ACPI_NUMA
dmar_parse_one_rhsa(struct acpi_dmar_header * header,void * arg)490 static int dmar_parse_one_rhsa(struct acpi_dmar_header *header, void *arg)
491 {
492 struct acpi_dmar_rhsa *rhsa;
493 struct dmar_drhd_unit *drhd;
494
495 rhsa = (struct acpi_dmar_rhsa *)header;
496 for_each_drhd_unit(drhd) {
497 if (drhd->reg_base_addr == rhsa->base_address) {
498 int node = pxm_to_node(rhsa->proximity_domain);
499
500 if (node != NUMA_NO_NODE && !node_online(node))
501 node = NUMA_NO_NODE;
502 drhd->iommu->node = node;
503 return 0;
504 }
505 }
506 pr_warn(FW_BUG
507 "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n"
508 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
509 rhsa->base_address,
510 dmi_get_system_info(DMI_BIOS_VENDOR),
511 dmi_get_system_info(DMI_BIOS_VERSION),
512 dmi_get_system_info(DMI_PRODUCT_VERSION));
513 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
514
515 return 0;
516 }
517 #else
518 #define dmar_parse_one_rhsa dmar_res_noop
519 #endif
520
521 static void
dmar_table_print_dmar_entry(struct acpi_dmar_header * header)522 dmar_table_print_dmar_entry(struct acpi_dmar_header *header)
523 {
524 struct acpi_dmar_hardware_unit *drhd;
525 struct acpi_dmar_reserved_memory *rmrr;
526 struct acpi_dmar_atsr *atsr;
527 struct acpi_dmar_rhsa *rhsa;
528 struct acpi_dmar_satc *satc;
529
530 switch (header->type) {
531 case ACPI_DMAR_TYPE_HARDWARE_UNIT:
532 drhd = container_of(header, struct acpi_dmar_hardware_unit,
533 header);
534 pr_info("DRHD base: %#016Lx flags: %#x\n",
535 (unsigned long long)drhd->address, drhd->flags);
536 break;
537 case ACPI_DMAR_TYPE_RESERVED_MEMORY:
538 rmrr = container_of(header, struct acpi_dmar_reserved_memory,
539 header);
540 pr_info("RMRR base: %#016Lx end: %#016Lx\n",
541 (unsigned long long)rmrr->base_address,
542 (unsigned long long)rmrr->end_address);
543 break;
544 case ACPI_DMAR_TYPE_ROOT_ATS:
545 atsr = container_of(header, struct acpi_dmar_atsr, header);
546 pr_info("ATSR flags: %#x\n", atsr->flags);
547 break;
548 case ACPI_DMAR_TYPE_HARDWARE_AFFINITY:
549 rhsa = container_of(header, struct acpi_dmar_rhsa, header);
550 pr_info("RHSA base: %#016Lx proximity domain: %#x\n",
551 (unsigned long long)rhsa->base_address,
552 rhsa->proximity_domain);
553 break;
554 case ACPI_DMAR_TYPE_NAMESPACE:
555 /* We don't print this here because we need to sanity-check
556 it first. So print it in dmar_parse_one_andd() instead. */
557 break;
558 case ACPI_DMAR_TYPE_SATC:
559 satc = container_of(header, struct acpi_dmar_satc, header);
560 pr_info("SATC flags: 0x%x\n", satc->flags);
561 break;
562 }
563 }
564
565 /**
566 * dmar_table_detect - checks to see if the platform supports DMAR devices
567 */
dmar_table_detect(void)568 static int __init dmar_table_detect(void)
569 {
570 acpi_status status = AE_OK;
571
572 /* if we could find DMAR table, then there are DMAR devices */
573 status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl);
574
575 if (ACPI_SUCCESS(status) && !dmar_tbl) {
576 pr_warn("Unable to map DMAR\n");
577 status = AE_NOT_FOUND;
578 }
579
580 return ACPI_SUCCESS(status) ? 0 : -ENOENT;
581 }
582
dmar_walk_remapping_entries(struct acpi_dmar_header * start,size_t len,struct dmar_res_callback * cb)583 static int dmar_walk_remapping_entries(struct acpi_dmar_header *start,
584 size_t len, struct dmar_res_callback *cb)
585 {
586 struct acpi_dmar_header *iter, *next;
587 struct acpi_dmar_header *end = ((void *)start) + len;
588
589 for (iter = start; iter < end; iter = next) {
590 next = (void *)iter + iter->length;
591 if (iter->length == 0) {
592 /* Avoid looping forever on bad ACPI tables */
593 pr_debug(FW_BUG "Invalid 0-length structure\n");
594 break;
595 } else if (next > end) {
596 /* Avoid passing table end */
597 pr_warn(FW_BUG "Record passes table end\n");
598 return -EINVAL;
599 }
600
601 if (cb->print_entry)
602 dmar_table_print_dmar_entry(iter);
603
604 if (iter->type >= ACPI_DMAR_TYPE_RESERVED) {
605 /* continue for forward compatibility */
606 pr_debug("Unknown DMAR structure type %d\n",
607 iter->type);
608 } else if (cb->cb[iter->type]) {
609 int ret;
610
611 ret = cb->cb[iter->type](iter, cb->arg[iter->type]);
612 if (ret)
613 return ret;
614 } else if (!cb->ignore_unhandled) {
615 pr_warn("No handler for DMAR structure type %d\n",
616 iter->type);
617 return -EINVAL;
618 }
619 }
620
621 return 0;
622 }
623
dmar_walk_dmar_table(struct acpi_table_dmar * dmar,struct dmar_res_callback * cb)624 static inline int dmar_walk_dmar_table(struct acpi_table_dmar *dmar,
625 struct dmar_res_callback *cb)
626 {
627 return dmar_walk_remapping_entries((void *)(dmar + 1),
628 dmar->header.length - sizeof(*dmar), cb);
629 }
630
631 /**
632 * parse_dmar_table - parses the DMA reporting table
633 */
634 static int __init
parse_dmar_table(void)635 parse_dmar_table(void)
636 {
637 struct acpi_table_dmar *dmar;
638 int drhd_count = 0;
639 int ret;
640 struct dmar_res_callback cb = {
641 .print_entry = true,
642 .ignore_unhandled = true,
643 .arg[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &drhd_count,
644 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_parse_one_drhd,
645 .cb[ACPI_DMAR_TYPE_RESERVED_MEMORY] = &dmar_parse_one_rmrr,
646 .cb[ACPI_DMAR_TYPE_ROOT_ATS] = &dmar_parse_one_atsr,
647 .cb[ACPI_DMAR_TYPE_HARDWARE_AFFINITY] = &dmar_parse_one_rhsa,
648 .cb[ACPI_DMAR_TYPE_NAMESPACE] = &dmar_parse_one_andd,
649 .cb[ACPI_DMAR_TYPE_SATC] = &dmar_parse_one_satc,
650 };
651
652 /*
653 * Do it again, earlier dmar_tbl mapping could be mapped with
654 * fixed map.
655 */
656 dmar_table_detect();
657
658 /*
659 * ACPI tables may not be DMA protected by tboot, so use DMAR copy
660 * SINIT saved in SinitMleData in TXT heap (which is DMA protected)
661 */
662 dmar_tbl = tboot_get_dmar_table(dmar_tbl);
663
664 dmar = (struct acpi_table_dmar *)dmar_tbl;
665 if (!dmar)
666 return -ENODEV;
667
668 if (dmar->width < PAGE_SHIFT - 1) {
669 pr_warn("Invalid DMAR haw\n");
670 return -EINVAL;
671 }
672
673 pr_info("Host address width %d\n", dmar->width + 1);
674 ret = dmar_walk_dmar_table(dmar, &cb);
675 if (ret == 0 && drhd_count == 0)
676 pr_warn(FW_BUG "No DRHD structure found in DMAR table\n");
677
678 return ret;
679 }
680
dmar_pci_device_match(struct dmar_dev_scope devices[],int cnt,struct pci_dev * dev)681 static int dmar_pci_device_match(struct dmar_dev_scope devices[],
682 int cnt, struct pci_dev *dev)
683 {
684 int index;
685 struct device *tmp;
686
687 while (dev) {
688 for_each_active_dev_scope(devices, cnt, index, tmp)
689 if (dev_is_pci(tmp) && dev == to_pci_dev(tmp))
690 return 1;
691
692 /* Check our parent */
693 dev = dev->bus->self;
694 }
695
696 return 0;
697 }
698
699 struct dmar_drhd_unit *
dmar_find_matched_drhd_unit(struct pci_dev * dev)700 dmar_find_matched_drhd_unit(struct pci_dev *dev)
701 {
702 struct dmar_drhd_unit *dmaru;
703 struct acpi_dmar_hardware_unit *drhd;
704
705 dev = pci_physfn(dev);
706
707 rcu_read_lock();
708 for_each_drhd_unit(dmaru) {
709 drhd = container_of(dmaru->hdr,
710 struct acpi_dmar_hardware_unit,
711 header);
712
713 if (dmaru->include_all &&
714 drhd->segment == pci_domain_nr(dev->bus))
715 goto out;
716
717 if (dmar_pci_device_match(dmaru->devices,
718 dmaru->devices_cnt, dev))
719 goto out;
720 }
721 dmaru = NULL;
722 out:
723 rcu_read_unlock();
724
725 return dmaru;
726 }
727
dmar_acpi_insert_dev_scope(u8 device_number,struct acpi_device * adev)728 static void __init dmar_acpi_insert_dev_scope(u8 device_number,
729 struct acpi_device *adev)
730 {
731 struct dmar_drhd_unit *dmaru;
732 struct acpi_dmar_hardware_unit *drhd;
733 struct acpi_dmar_device_scope *scope;
734 struct device *tmp;
735 int i;
736 struct acpi_dmar_pci_path *path;
737
738 for_each_drhd_unit(dmaru) {
739 drhd = container_of(dmaru->hdr,
740 struct acpi_dmar_hardware_unit,
741 header);
742
743 for (scope = (void *)(drhd + 1);
744 (unsigned long)scope < ((unsigned long)drhd) + drhd->header.length;
745 scope = ((void *)scope) + scope->length) {
746 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NAMESPACE)
747 continue;
748 if (scope->enumeration_id != device_number)
749 continue;
750
751 path = (void *)(scope + 1);
752 pr_info("ACPI device \"%s\" under DMAR at %llx as %02x:%02x.%d\n",
753 dev_name(&adev->dev), dmaru->reg_base_addr,
754 scope->bus, path->device, path->function);
755 for_each_dev_scope(dmaru->devices, dmaru->devices_cnt, i, tmp)
756 if (tmp == NULL) {
757 dmaru->devices[i].bus = scope->bus;
758 dmaru->devices[i].devfn = PCI_DEVFN(path->device,
759 path->function);
760 rcu_assign_pointer(dmaru->devices[i].dev,
761 get_device(&adev->dev));
762 return;
763 }
764 BUG_ON(i >= dmaru->devices_cnt);
765 }
766 }
767 pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n",
768 device_number, dev_name(&adev->dev));
769 }
770
dmar_acpi_dev_scope_init(void)771 static int __init dmar_acpi_dev_scope_init(void)
772 {
773 struct acpi_dmar_andd *andd;
774
775 if (dmar_tbl == NULL)
776 return -ENODEV;
777
778 for (andd = (void *)dmar_tbl + sizeof(struct acpi_table_dmar);
779 ((unsigned long)andd) < ((unsigned long)dmar_tbl) + dmar_tbl->length;
780 andd = ((void *)andd) + andd->header.length) {
781 if (andd->header.type == ACPI_DMAR_TYPE_NAMESPACE) {
782 acpi_handle h;
783 struct acpi_device *adev;
784
785 if (!ACPI_SUCCESS(acpi_get_handle(ACPI_ROOT_OBJECT,
786 andd->device_name,
787 &h))) {
788 pr_err("Failed to find handle for ACPI object %s\n",
789 andd->device_name);
790 continue;
791 }
792 if (acpi_bus_get_device(h, &adev)) {
793 pr_err("Failed to get device for ACPI object %s\n",
794 andd->device_name);
795 continue;
796 }
797 dmar_acpi_insert_dev_scope(andd->device_number, adev);
798 }
799 }
800 return 0;
801 }
802
dmar_dev_scope_init(void)803 int __init dmar_dev_scope_init(void)
804 {
805 struct pci_dev *dev = NULL;
806 struct dmar_pci_notify_info *info;
807
808 if (dmar_dev_scope_status != 1)
809 return dmar_dev_scope_status;
810
811 if (list_empty(&dmar_drhd_units)) {
812 dmar_dev_scope_status = -ENODEV;
813 } else {
814 dmar_dev_scope_status = 0;
815
816 dmar_acpi_dev_scope_init();
817
818 for_each_pci_dev(dev) {
819 if (dev->is_virtfn)
820 continue;
821
822 info = dmar_alloc_pci_notify_info(dev,
823 BUS_NOTIFY_ADD_DEVICE);
824 if (!info) {
825 pci_dev_put(dev);
826 return dmar_dev_scope_status;
827 } else {
828 dmar_pci_bus_add_dev(info);
829 dmar_free_pci_notify_info(info);
830 }
831 }
832 }
833
834 return dmar_dev_scope_status;
835 }
836
dmar_register_bus_notifier(void)837 void __init dmar_register_bus_notifier(void)
838 {
839 bus_register_notifier(&pci_bus_type, &dmar_pci_bus_nb);
840 }
841
842
dmar_table_init(void)843 int __init dmar_table_init(void)
844 {
845 static int dmar_table_initialized;
846 int ret;
847
848 if (dmar_table_initialized == 0) {
849 ret = parse_dmar_table();
850 if (ret < 0) {
851 if (ret != -ENODEV)
852 pr_info("Parse DMAR table failure.\n");
853 } else if (list_empty(&dmar_drhd_units)) {
854 pr_info("No DMAR devices found\n");
855 ret = -ENODEV;
856 }
857
858 if (ret < 0)
859 dmar_table_initialized = ret;
860 else
861 dmar_table_initialized = 1;
862 }
863
864 return dmar_table_initialized < 0 ? dmar_table_initialized : 0;
865 }
866
warn_invalid_dmar(u64 addr,const char * message)867 static void warn_invalid_dmar(u64 addr, const char *message)
868 {
869 pr_warn_once(FW_BUG
870 "Your BIOS is broken; DMAR reported at address %llx%s!\n"
871 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
872 addr, message,
873 dmi_get_system_info(DMI_BIOS_VENDOR),
874 dmi_get_system_info(DMI_BIOS_VERSION),
875 dmi_get_system_info(DMI_PRODUCT_VERSION));
876 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
877 }
878
879 static int __ref
dmar_validate_one_drhd(struct acpi_dmar_header * entry,void * arg)880 dmar_validate_one_drhd(struct acpi_dmar_header *entry, void *arg)
881 {
882 struct acpi_dmar_hardware_unit *drhd;
883 void __iomem *addr;
884 u64 cap, ecap;
885
886 drhd = (void *)entry;
887 if (!drhd->address) {
888 warn_invalid_dmar(0, "");
889 return -EINVAL;
890 }
891
892 if (arg)
893 addr = ioremap(drhd->address, VTD_PAGE_SIZE);
894 else
895 addr = early_ioremap(drhd->address, VTD_PAGE_SIZE);
896 if (!addr) {
897 pr_warn("Can't validate DRHD address: %llx\n", drhd->address);
898 return -EINVAL;
899 }
900
901 cap = dmar_readq(addr + DMAR_CAP_REG);
902 ecap = dmar_readq(addr + DMAR_ECAP_REG);
903
904 if (arg)
905 iounmap(addr);
906 else
907 early_iounmap(addr, VTD_PAGE_SIZE);
908
909 if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) {
910 warn_invalid_dmar(drhd->address, " returns all ones");
911 return -EINVAL;
912 }
913
914 return 0;
915 }
916
detect_intel_iommu(void)917 int __init detect_intel_iommu(void)
918 {
919 int ret;
920 struct dmar_res_callback validate_drhd_cb = {
921 .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_validate_one_drhd,
922 .ignore_unhandled = true,
923 };
924
925 down_write(&dmar_global_lock);
926 ret = dmar_table_detect();
927 if (!ret)
928 ret = dmar_walk_dmar_table((struct acpi_table_dmar *)dmar_tbl,
929 &validate_drhd_cb);
930 if (!ret && !no_iommu && !iommu_detected &&
931 (!dmar_disabled || dmar_platform_optin())) {
932 iommu_detected = 1;
933 /* Make sure ACS will be enabled */
934 pci_request_acs();
935 }
936
937 #ifdef CONFIG_X86
938 if (!ret) {
939 x86_init.iommu.iommu_init = intel_iommu_init;
940 x86_platform.iommu_shutdown = intel_iommu_shutdown;
941 }
942
943 #endif
944
945 if (dmar_tbl) {
946 acpi_put_table(dmar_tbl);
947 dmar_tbl = NULL;
948 }
949 up_write(&dmar_global_lock);
950
951 return ret ? ret : 1;
952 }
953
unmap_iommu(struct intel_iommu * iommu)954 static void unmap_iommu(struct intel_iommu *iommu)
955 {
956 iounmap(iommu->reg);
957 release_mem_region(iommu->reg_phys, iommu->reg_size);
958 }
959
960 /**
961 * map_iommu: map the iommu's registers
962 * @iommu: the iommu to map
963 * @phys_addr: the physical address of the base resgister
964 *
965 * Memory map the iommu's registers. Start w/ a single page, and
966 * possibly expand if that turns out to be insufficent.
967 */
map_iommu(struct intel_iommu * iommu,u64 phys_addr)968 static int map_iommu(struct intel_iommu *iommu, u64 phys_addr)
969 {
970 int map_size, err=0;
971
972 iommu->reg_phys = phys_addr;
973 iommu->reg_size = VTD_PAGE_SIZE;
974
975 if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) {
976 pr_err("Can't reserve memory\n");
977 err = -EBUSY;
978 goto out;
979 }
980
981 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
982 if (!iommu->reg) {
983 pr_err("Can't map the region\n");
984 err = -ENOMEM;
985 goto release;
986 }
987
988 iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);
989 iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);
990
991 if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) {
992 err = -EINVAL;
993 warn_invalid_dmar(phys_addr, " returns all ones");
994 goto unmap;
995 }
996 if (ecap_vcs(iommu->ecap))
997 iommu->vccap = dmar_readq(iommu->reg + DMAR_VCCAP_REG);
998
999 /* the registers might be more than one page */
1000 map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),
1001 cap_max_fault_reg_offset(iommu->cap));
1002 map_size = VTD_PAGE_ALIGN(map_size);
1003 if (map_size > iommu->reg_size) {
1004 iounmap(iommu->reg);
1005 release_mem_region(iommu->reg_phys, iommu->reg_size);
1006 iommu->reg_size = map_size;
1007 if (!request_mem_region(iommu->reg_phys, iommu->reg_size,
1008 iommu->name)) {
1009 pr_err("Can't reserve memory\n");
1010 err = -EBUSY;
1011 goto out;
1012 }
1013 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size);
1014 if (!iommu->reg) {
1015 pr_err("Can't map the region\n");
1016 err = -ENOMEM;
1017 goto release;
1018 }
1019 }
1020 err = 0;
1021 goto out;
1022
1023 unmap:
1024 iounmap(iommu->reg);
1025 release:
1026 release_mem_region(iommu->reg_phys, iommu->reg_size);
1027 out:
1028 return err;
1029 }
1030
dmar_alloc_seq_id(struct intel_iommu * iommu)1031 static int dmar_alloc_seq_id(struct intel_iommu *iommu)
1032 {
1033 iommu->seq_id = find_first_zero_bit(dmar_seq_ids,
1034 DMAR_UNITS_SUPPORTED);
1035 if (iommu->seq_id >= DMAR_UNITS_SUPPORTED) {
1036 iommu->seq_id = -1;
1037 } else {
1038 set_bit(iommu->seq_id, dmar_seq_ids);
1039 sprintf(iommu->name, "dmar%d", iommu->seq_id);
1040 }
1041
1042 return iommu->seq_id;
1043 }
1044
dmar_free_seq_id(struct intel_iommu * iommu)1045 static void dmar_free_seq_id(struct intel_iommu *iommu)
1046 {
1047 if (iommu->seq_id >= 0) {
1048 clear_bit(iommu->seq_id, dmar_seq_ids);
1049 iommu->seq_id = -1;
1050 }
1051 }
1052
alloc_iommu(struct dmar_drhd_unit * drhd)1053 static int alloc_iommu(struct dmar_drhd_unit *drhd)
1054 {
1055 struct intel_iommu *iommu;
1056 u32 ver, sts;
1057 int agaw = -1;
1058 int msagaw = -1;
1059 int err;
1060
1061 if (!drhd->reg_base_addr) {
1062 warn_invalid_dmar(0, "");
1063 return -EINVAL;
1064 }
1065
1066 iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
1067 if (!iommu)
1068 return -ENOMEM;
1069
1070 if (dmar_alloc_seq_id(iommu) < 0) {
1071 pr_err("Failed to allocate seq_id\n");
1072 err = -ENOSPC;
1073 goto error;
1074 }
1075
1076 err = map_iommu(iommu, drhd->reg_base_addr);
1077 if (err) {
1078 pr_err("Failed to map %s\n", iommu->name);
1079 goto error_free_seq_id;
1080 }
1081
1082 err = -EINVAL;
1083 if (!cap_sagaw(iommu->cap) &&
1084 (!ecap_smts(iommu->ecap) || ecap_slts(iommu->ecap))) {
1085 pr_info("%s: No supported address widths. Not attempting DMA translation.\n",
1086 iommu->name);
1087 drhd->ignored = 1;
1088 }
1089
1090 if (!drhd->ignored) {
1091 agaw = iommu_calculate_agaw(iommu);
1092 if (agaw < 0) {
1093 pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n",
1094 iommu->seq_id);
1095 drhd->ignored = 1;
1096 }
1097 }
1098 if (!drhd->ignored) {
1099 msagaw = iommu_calculate_max_sagaw(iommu);
1100 if (msagaw < 0) {
1101 pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n",
1102 iommu->seq_id);
1103 drhd->ignored = 1;
1104 agaw = -1;
1105 }
1106 }
1107 iommu->agaw = agaw;
1108 iommu->msagaw = msagaw;
1109 iommu->segment = drhd->segment;
1110
1111 iommu->node = NUMA_NO_NODE;
1112
1113 ver = readl(iommu->reg + DMAR_VER_REG);
1114 pr_info("%s: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n",
1115 iommu->name,
1116 (unsigned long long)drhd->reg_base_addr,
1117 DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver),
1118 (unsigned long long)iommu->cap,
1119 (unsigned long long)iommu->ecap);
1120
1121 /* Reflect status in gcmd */
1122 sts = readl(iommu->reg + DMAR_GSTS_REG);
1123 if (sts & DMA_GSTS_IRES)
1124 iommu->gcmd |= DMA_GCMD_IRE;
1125 if (sts & DMA_GSTS_TES)
1126 iommu->gcmd |= DMA_GCMD_TE;
1127 if (sts & DMA_GSTS_QIES)
1128 iommu->gcmd |= DMA_GCMD_QIE;
1129
1130 raw_spin_lock_init(&iommu->register_lock);
1131
1132 /*
1133 * This is only for hotplug; at boot time intel_iommu_enabled won't
1134 * be set yet. When intel_iommu_init() runs, it registers the units
1135 * present at boot time, then sets intel_iommu_enabled.
1136 */
1137 if (intel_iommu_enabled && !drhd->ignored) {
1138 err = iommu_device_sysfs_add(&iommu->iommu, NULL,
1139 intel_iommu_groups,
1140 "%s", iommu->name);
1141 if (err)
1142 goto err_unmap;
1143
1144 err = iommu_device_register(&iommu->iommu, &intel_iommu_ops, NULL);
1145 if (err)
1146 goto err_sysfs;
1147 }
1148
1149 drhd->iommu = iommu;
1150 iommu->drhd = drhd;
1151
1152 return 0;
1153
1154 err_sysfs:
1155 iommu_device_sysfs_remove(&iommu->iommu);
1156 err_unmap:
1157 unmap_iommu(iommu);
1158 error_free_seq_id:
1159 dmar_free_seq_id(iommu);
1160 error:
1161 kfree(iommu);
1162 return err;
1163 }
1164
free_iommu(struct intel_iommu * iommu)1165 static void free_iommu(struct intel_iommu *iommu)
1166 {
1167 if (intel_iommu_enabled && !iommu->drhd->ignored) {
1168 iommu_device_unregister(&iommu->iommu);
1169 iommu_device_sysfs_remove(&iommu->iommu);
1170 }
1171
1172 if (iommu->irq) {
1173 if (iommu->pr_irq) {
1174 free_irq(iommu->pr_irq, iommu);
1175 dmar_free_hwirq(iommu->pr_irq);
1176 iommu->pr_irq = 0;
1177 }
1178 free_irq(iommu->irq, iommu);
1179 dmar_free_hwirq(iommu->irq);
1180 iommu->irq = 0;
1181 }
1182
1183 if (iommu->qi) {
1184 free_page((unsigned long)iommu->qi->desc);
1185 kfree(iommu->qi->desc_status);
1186 kfree(iommu->qi);
1187 }
1188
1189 if (iommu->reg)
1190 unmap_iommu(iommu);
1191
1192 dmar_free_seq_id(iommu);
1193 kfree(iommu);
1194 }
1195
1196 /*
1197 * Reclaim all the submitted descriptors which have completed its work.
1198 */
reclaim_free_desc(struct q_inval * qi)1199 static inline void reclaim_free_desc(struct q_inval *qi)
1200 {
1201 while (qi->desc_status[qi->free_tail] == QI_DONE ||
1202 qi->desc_status[qi->free_tail] == QI_ABORT) {
1203 qi->desc_status[qi->free_tail] = QI_FREE;
1204 qi->free_tail = (qi->free_tail + 1) % QI_LENGTH;
1205 qi->free_cnt++;
1206 }
1207 }
1208
qi_type_string(u8 type)1209 static const char *qi_type_string(u8 type)
1210 {
1211 switch (type) {
1212 case QI_CC_TYPE:
1213 return "Context-cache Invalidation";
1214 case QI_IOTLB_TYPE:
1215 return "IOTLB Invalidation";
1216 case QI_DIOTLB_TYPE:
1217 return "Device-TLB Invalidation";
1218 case QI_IEC_TYPE:
1219 return "Interrupt Entry Cache Invalidation";
1220 case QI_IWD_TYPE:
1221 return "Invalidation Wait";
1222 case QI_EIOTLB_TYPE:
1223 return "PASID-based IOTLB Invalidation";
1224 case QI_PC_TYPE:
1225 return "PASID-cache Invalidation";
1226 case QI_DEIOTLB_TYPE:
1227 return "PASID-based Device-TLB Invalidation";
1228 case QI_PGRP_RESP_TYPE:
1229 return "Page Group Response";
1230 default:
1231 return "UNKNOWN";
1232 }
1233 }
1234
qi_dump_fault(struct intel_iommu * iommu,u32 fault)1235 static void qi_dump_fault(struct intel_iommu *iommu, u32 fault)
1236 {
1237 unsigned int head = dmar_readl(iommu->reg + DMAR_IQH_REG);
1238 u64 iqe_err = dmar_readq(iommu->reg + DMAR_IQER_REG);
1239 struct qi_desc *desc = iommu->qi->desc + head;
1240
1241 if (fault & DMA_FSTS_IQE)
1242 pr_err("VT-d detected Invalidation Queue Error: Reason %llx",
1243 DMAR_IQER_REG_IQEI(iqe_err));
1244 if (fault & DMA_FSTS_ITE)
1245 pr_err("VT-d detected Invalidation Time-out Error: SID %llx",
1246 DMAR_IQER_REG_ITESID(iqe_err));
1247 if (fault & DMA_FSTS_ICE)
1248 pr_err("VT-d detected Invalidation Completion Error: SID %llx",
1249 DMAR_IQER_REG_ICESID(iqe_err));
1250
1251 pr_err("QI HEAD: %s qw0 = 0x%llx, qw1 = 0x%llx\n",
1252 qi_type_string(desc->qw0 & 0xf),
1253 (unsigned long long)desc->qw0,
1254 (unsigned long long)desc->qw1);
1255
1256 head = ((head >> qi_shift(iommu)) + QI_LENGTH - 1) % QI_LENGTH;
1257 head <<= qi_shift(iommu);
1258 desc = iommu->qi->desc + head;
1259
1260 pr_err("QI PRIOR: %s qw0 = 0x%llx, qw1 = 0x%llx\n",
1261 qi_type_string(desc->qw0 & 0xf),
1262 (unsigned long long)desc->qw0,
1263 (unsigned long long)desc->qw1);
1264 }
1265
qi_check_fault(struct intel_iommu * iommu,int index,int wait_index)1266 static int qi_check_fault(struct intel_iommu *iommu, int index, int wait_index)
1267 {
1268 u32 fault;
1269 int head, tail;
1270 struct q_inval *qi = iommu->qi;
1271 int shift = qi_shift(iommu);
1272
1273 if (qi->desc_status[wait_index] == QI_ABORT)
1274 return -EAGAIN;
1275
1276 fault = readl(iommu->reg + DMAR_FSTS_REG);
1277 if (fault & (DMA_FSTS_IQE | DMA_FSTS_ITE | DMA_FSTS_ICE))
1278 qi_dump_fault(iommu, fault);
1279
1280 /*
1281 * If IQE happens, the head points to the descriptor associated
1282 * with the error. No new descriptors are fetched until the IQE
1283 * is cleared.
1284 */
1285 if (fault & DMA_FSTS_IQE) {
1286 head = readl(iommu->reg + DMAR_IQH_REG);
1287 if ((head >> shift) == index) {
1288 struct qi_desc *desc = qi->desc + head;
1289
1290 /*
1291 * desc->qw2 and desc->qw3 are either reserved or
1292 * used by software as private data. We won't print
1293 * out these two qw's for security consideration.
1294 */
1295 memcpy(desc, qi->desc + (wait_index << shift),
1296 1 << shift);
1297 writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG);
1298 pr_info("Invalidation Queue Error (IQE) cleared\n");
1299 return -EINVAL;
1300 }
1301 }
1302
1303 /*
1304 * If ITE happens, all pending wait_desc commands are aborted.
1305 * No new descriptors are fetched until the ITE is cleared.
1306 */
1307 if (fault & DMA_FSTS_ITE) {
1308 head = readl(iommu->reg + DMAR_IQH_REG);
1309 head = ((head >> shift) - 1 + QI_LENGTH) % QI_LENGTH;
1310 head |= 1;
1311 tail = readl(iommu->reg + DMAR_IQT_REG);
1312 tail = ((tail >> shift) - 1 + QI_LENGTH) % QI_LENGTH;
1313
1314 writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG);
1315 pr_info("Invalidation Time-out Error (ITE) cleared\n");
1316
1317 do {
1318 if (qi->desc_status[head] == QI_IN_USE)
1319 qi->desc_status[head] = QI_ABORT;
1320 head = (head - 2 + QI_LENGTH) % QI_LENGTH;
1321 } while (head != tail);
1322
1323 if (qi->desc_status[wait_index] == QI_ABORT)
1324 return -EAGAIN;
1325 }
1326
1327 if (fault & DMA_FSTS_ICE) {
1328 writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG);
1329 pr_info("Invalidation Completion Error (ICE) cleared\n");
1330 }
1331
1332 return 0;
1333 }
1334
1335 /*
1336 * Function to submit invalidation descriptors of all types to the queued
1337 * invalidation interface(QI). Multiple descriptors can be submitted at a
1338 * time, a wait descriptor will be appended to each submission to ensure
1339 * hardware has completed the invalidation before return. Wait descriptors
1340 * can be part of the submission but it will not be polled for completion.
1341 */
qi_submit_sync(struct intel_iommu * iommu,struct qi_desc * desc,unsigned int count,unsigned long options)1342 int qi_submit_sync(struct intel_iommu *iommu, struct qi_desc *desc,
1343 unsigned int count, unsigned long options)
1344 {
1345 struct q_inval *qi = iommu->qi;
1346 s64 devtlb_start_ktime = 0;
1347 s64 iotlb_start_ktime = 0;
1348 s64 iec_start_ktime = 0;
1349 struct qi_desc wait_desc;
1350 int wait_index, index;
1351 unsigned long flags;
1352 int offset, shift;
1353 int rc, i;
1354 u64 type;
1355
1356 if (!qi)
1357 return 0;
1358
1359 type = desc->qw0 & GENMASK_ULL(3, 0);
1360
1361 if ((type == QI_IOTLB_TYPE || type == QI_EIOTLB_TYPE) &&
1362 dmar_latency_enabled(iommu, DMAR_LATENCY_INV_IOTLB))
1363 iotlb_start_ktime = ktime_to_ns(ktime_get());
1364
1365 if ((type == QI_DIOTLB_TYPE || type == QI_DEIOTLB_TYPE) &&
1366 dmar_latency_enabled(iommu, DMAR_LATENCY_INV_DEVTLB))
1367 devtlb_start_ktime = ktime_to_ns(ktime_get());
1368
1369 if (type == QI_IEC_TYPE &&
1370 dmar_latency_enabled(iommu, DMAR_LATENCY_INV_IEC))
1371 iec_start_ktime = ktime_to_ns(ktime_get());
1372
1373 restart:
1374 rc = 0;
1375
1376 raw_spin_lock_irqsave(&qi->q_lock, flags);
1377 /*
1378 * Check if we have enough empty slots in the queue to submit,
1379 * the calculation is based on:
1380 * # of desc + 1 wait desc + 1 space between head and tail
1381 */
1382 while (qi->free_cnt < count + 2) {
1383 raw_spin_unlock_irqrestore(&qi->q_lock, flags);
1384 cpu_relax();
1385 raw_spin_lock_irqsave(&qi->q_lock, flags);
1386 }
1387
1388 index = qi->free_head;
1389 wait_index = (index + count) % QI_LENGTH;
1390 shift = qi_shift(iommu);
1391
1392 for (i = 0; i < count; i++) {
1393 offset = ((index + i) % QI_LENGTH) << shift;
1394 memcpy(qi->desc + offset, &desc[i], 1 << shift);
1395 qi->desc_status[(index + i) % QI_LENGTH] = QI_IN_USE;
1396 trace_qi_submit(iommu, desc[i].qw0, desc[i].qw1,
1397 desc[i].qw2, desc[i].qw3);
1398 }
1399 qi->desc_status[wait_index] = QI_IN_USE;
1400
1401 wait_desc.qw0 = QI_IWD_STATUS_DATA(QI_DONE) |
1402 QI_IWD_STATUS_WRITE | QI_IWD_TYPE;
1403 if (options & QI_OPT_WAIT_DRAIN)
1404 wait_desc.qw0 |= QI_IWD_PRQ_DRAIN;
1405 wait_desc.qw1 = virt_to_phys(&qi->desc_status[wait_index]);
1406 wait_desc.qw2 = 0;
1407 wait_desc.qw3 = 0;
1408
1409 offset = wait_index << shift;
1410 memcpy(qi->desc + offset, &wait_desc, 1 << shift);
1411
1412 qi->free_head = (qi->free_head + count + 1) % QI_LENGTH;
1413 qi->free_cnt -= count + 1;
1414
1415 /*
1416 * update the HW tail register indicating the presence of
1417 * new descriptors.
1418 */
1419 writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG);
1420
1421 while (qi->desc_status[wait_index] != QI_DONE) {
1422 /*
1423 * We will leave the interrupts disabled, to prevent interrupt
1424 * context to queue another cmd while a cmd is already submitted
1425 * and waiting for completion on this cpu. This is to avoid
1426 * a deadlock where the interrupt context can wait indefinitely
1427 * for free slots in the queue.
1428 */
1429 rc = qi_check_fault(iommu, index, wait_index);
1430 if (rc)
1431 break;
1432
1433 raw_spin_unlock(&qi->q_lock);
1434 cpu_relax();
1435 raw_spin_lock(&qi->q_lock);
1436 }
1437
1438 for (i = 0; i < count; i++)
1439 qi->desc_status[(index + i) % QI_LENGTH] = QI_DONE;
1440
1441 reclaim_free_desc(qi);
1442 raw_spin_unlock_irqrestore(&qi->q_lock, flags);
1443
1444 if (rc == -EAGAIN)
1445 goto restart;
1446
1447 if (iotlb_start_ktime)
1448 dmar_latency_update(iommu, DMAR_LATENCY_INV_IOTLB,
1449 ktime_to_ns(ktime_get()) - iotlb_start_ktime);
1450
1451 if (devtlb_start_ktime)
1452 dmar_latency_update(iommu, DMAR_LATENCY_INV_DEVTLB,
1453 ktime_to_ns(ktime_get()) - devtlb_start_ktime);
1454
1455 if (iec_start_ktime)
1456 dmar_latency_update(iommu, DMAR_LATENCY_INV_IEC,
1457 ktime_to_ns(ktime_get()) - iec_start_ktime);
1458
1459 return rc;
1460 }
1461
1462 /*
1463 * Flush the global interrupt entry cache.
1464 */
qi_global_iec(struct intel_iommu * iommu)1465 void qi_global_iec(struct intel_iommu *iommu)
1466 {
1467 struct qi_desc desc;
1468
1469 desc.qw0 = QI_IEC_TYPE;
1470 desc.qw1 = 0;
1471 desc.qw2 = 0;
1472 desc.qw3 = 0;
1473
1474 /* should never fail */
1475 qi_submit_sync(iommu, &desc, 1, 0);
1476 }
1477
qi_flush_context(struct intel_iommu * iommu,u16 did,u16 sid,u8 fm,u64 type)1478 void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
1479 u64 type)
1480 {
1481 struct qi_desc desc;
1482
1483 desc.qw0 = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did)
1484 | QI_CC_GRAN(type) | QI_CC_TYPE;
1485 desc.qw1 = 0;
1486 desc.qw2 = 0;
1487 desc.qw3 = 0;
1488
1489 qi_submit_sync(iommu, &desc, 1, 0);
1490 }
1491
qi_flush_iotlb(struct intel_iommu * iommu,u16 did,u64 addr,unsigned int size_order,u64 type)1492 void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
1493 unsigned int size_order, u64 type)
1494 {
1495 u8 dw = 0, dr = 0;
1496
1497 struct qi_desc desc;
1498 int ih = 0;
1499
1500 if (cap_write_drain(iommu->cap))
1501 dw = 1;
1502
1503 if (cap_read_drain(iommu->cap))
1504 dr = 1;
1505
1506 desc.qw0 = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw)
1507 | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE;
1508 desc.qw1 = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih)
1509 | QI_IOTLB_AM(size_order);
1510 desc.qw2 = 0;
1511 desc.qw3 = 0;
1512
1513 qi_submit_sync(iommu, &desc, 1, 0);
1514 }
1515
qi_flush_dev_iotlb(struct intel_iommu * iommu,u16 sid,u16 pfsid,u16 qdep,u64 addr,unsigned mask)1516 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
1517 u16 qdep, u64 addr, unsigned mask)
1518 {
1519 struct qi_desc desc;
1520
1521 /*
1522 * VT-d spec, section 4.3:
1523 *
1524 * Software is recommended to not submit any Device-TLB invalidation
1525 * requests while address remapping hardware is disabled.
1526 */
1527 if (!(iommu->gcmd & DMA_GCMD_TE))
1528 return;
1529
1530 if (mask) {
1531 addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1;
1532 desc.qw1 = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE;
1533 } else
1534 desc.qw1 = QI_DEV_IOTLB_ADDR(addr);
1535
1536 if (qdep >= QI_DEV_IOTLB_MAX_INVS)
1537 qdep = 0;
1538
1539 desc.qw0 = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) |
1540 QI_DIOTLB_TYPE | QI_DEV_IOTLB_PFSID(pfsid);
1541 desc.qw2 = 0;
1542 desc.qw3 = 0;
1543
1544 qi_submit_sync(iommu, &desc, 1, 0);
1545 }
1546
1547 /* PASID-based IOTLB invalidation */
qi_flush_piotlb(struct intel_iommu * iommu,u16 did,u32 pasid,u64 addr,unsigned long npages,bool ih)1548 void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
1549 unsigned long npages, bool ih)
1550 {
1551 struct qi_desc desc = {.qw2 = 0, .qw3 = 0};
1552
1553 /*
1554 * npages == -1 means a PASID-selective invalidation, otherwise,
1555 * a positive value for Page-selective-within-PASID invalidation.
1556 * 0 is not a valid input.
1557 */
1558 if (WARN_ON(!npages)) {
1559 pr_err("Invalid input npages = %ld\n", npages);
1560 return;
1561 }
1562
1563 if (npages == -1) {
1564 desc.qw0 = QI_EIOTLB_PASID(pasid) |
1565 QI_EIOTLB_DID(did) |
1566 QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
1567 QI_EIOTLB_TYPE;
1568 desc.qw1 = 0;
1569 } else {
1570 int mask = ilog2(__roundup_pow_of_two(npages));
1571 unsigned long align = (1ULL << (VTD_PAGE_SHIFT + mask));
1572
1573 if (WARN_ON_ONCE(!IS_ALIGNED(addr, align)))
1574 addr = ALIGN_DOWN(addr, align);
1575
1576 desc.qw0 = QI_EIOTLB_PASID(pasid) |
1577 QI_EIOTLB_DID(did) |
1578 QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) |
1579 QI_EIOTLB_TYPE;
1580 desc.qw1 = QI_EIOTLB_ADDR(addr) |
1581 QI_EIOTLB_IH(ih) |
1582 QI_EIOTLB_AM(mask);
1583 }
1584
1585 qi_submit_sync(iommu, &desc, 1, 0);
1586 }
1587
1588 /* PASID-based device IOTLB Invalidate */
qi_flush_dev_iotlb_pasid(struct intel_iommu * iommu,u16 sid,u16 pfsid,u32 pasid,u16 qdep,u64 addr,unsigned int size_order)1589 void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
1590 u32 pasid, u16 qdep, u64 addr, unsigned int size_order)
1591 {
1592 unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1);
1593 struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0};
1594
1595 /*
1596 * VT-d spec, section 4.3:
1597 *
1598 * Software is recommended to not submit any Device-TLB invalidation
1599 * requests while address remapping hardware is disabled.
1600 */
1601 if (!(iommu->gcmd & DMA_GCMD_TE))
1602 return;
1603
1604 desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) |
1605 QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE |
1606 QI_DEV_IOTLB_PFSID(pfsid);
1607
1608 /*
1609 * If S bit is 0, we only flush a single page. If S bit is set,
1610 * The least significant zero bit indicates the invalidation address
1611 * range. VT-d spec 6.5.2.6.
1612 * e.g. address bit 12[0] indicates 8KB, 13[0] indicates 16KB.
1613 * size order = 0 is PAGE_SIZE 4KB
1614 * Max Invs Pending (MIP) is set to 0 for now until we have DIT in
1615 * ECAP.
1616 */
1617 if (!IS_ALIGNED(addr, VTD_PAGE_SIZE << size_order))
1618 pr_warn_ratelimited("Invalidate non-aligned address %llx, order %d\n",
1619 addr, size_order);
1620
1621 /* Take page address */
1622 desc.qw1 = QI_DEV_EIOTLB_ADDR(addr);
1623
1624 if (size_order) {
1625 /*
1626 * Existing 0s in address below size_order may be the least
1627 * significant bit, we must set them to 1s to avoid having
1628 * smaller size than desired.
1629 */
1630 desc.qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT - 1,
1631 VTD_PAGE_SHIFT);
1632 /* Clear size_order bit to indicate size */
1633 desc.qw1 &= ~mask;
1634 /* Set the S bit to indicate flushing more than 1 page */
1635 desc.qw1 |= QI_DEV_EIOTLB_SIZE;
1636 }
1637
1638 qi_submit_sync(iommu, &desc, 1, 0);
1639 }
1640
qi_flush_pasid_cache(struct intel_iommu * iommu,u16 did,u64 granu,u32 pasid)1641 void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did,
1642 u64 granu, u32 pasid)
1643 {
1644 struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0};
1645
1646 desc.qw0 = QI_PC_PASID(pasid) | QI_PC_DID(did) |
1647 QI_PC_GRAN(granu) | QI_PC_TYPE;
1648 qi_submit_sync(iommu, &desc, 1, 0);
1649 }
1650
1651 /*
1652 * Disable Queued Invalidation interface.
1653 */
dmar_disable_qi(struct intel_iommu * iommu)1654 void dmar_disable_qi(struct intel_iommu *iommu)
1655 {
1656 unsigned long flags;
1657 u32 sts;
1658 cycles_t start_time = get_cycles();
1659
1660 if (!ecap_qis(iommu->ecap))
1661 return;
1662
1663 raw_spin_lock_irqsave(&iommu->register_lock, flags);
1664
1665 sts = readl(iommu->reg + DMAR_GSTS_REG);
1666 if (!(sts & DMA_GSTS_QIES))
1667 goto end;
1668
1669 /*
1670 * Give a chance to HW to complete the pending invalidation requests.
1671 */
1672 while ((readl(iommu->reg + DMAR_IQT_REG) !=
1673 readl(iommu->reg + DMAR_IQH_REG)) &&
1674 (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time)))
1675 cpu_relax();
1676
1677 iommu->gcmd &= ~DMA_GCMD_QIE;
1678 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1679
1680 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl,
1681 !(sts & DMA_GSTS_QIES), sts);
1682 end:
1683 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1684 }
1685
1686 /*
1687 * Enable queued invalidation.
1688 */
__dmar_enable_qi(struct intel_iommu * iommu)1689 static void __dmar_enable_qi(struct intel_iommu *iommu)
1690 {
1691 u32 sts;
1692 unsigned long flags;
1693 struct q_inval *qi = iommu->qi;
1694 u64 val = virt_to_phys(qi->desc);
1695
1696 qi->free_head = qi->free_tail = 0;
1697 qi->free_cnt = QI_LENGTH;
1698
1699 /*
1700 * Set DW=1 and QS=1 in IQA_REG when Scalable Mode capability
1701 * is present.
1702 */
1703 if (ecap_smts(iommu->ecap))
1704 val |= (1 << 11) | 1;
1705
1706 raw_spin_lock_irqsave(&iommu->register_lock, flags);
1707
1708 /* write zero to the tail reg */
1709 writel(0, iommu->reg + DMAR_IQT_REG);
1710
1711 dmar_writeq(iommu->reg + DMAR_IQA_REG, val);
1712
1713 iommu->gcmd |= DMA_GCMD_QIE;
1714 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1715
1716 /* Make sure hardware complete it */
1717 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);
1718
1719 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
1720 }
1721
1722 /*
1723 * Enable Queued Invalidation interface. This is a must to support
1724 * interrupt-remapping. Also used by DMA-remapping, which replaces
1725 * register based IOTLB invalidation.
1726 */
dmar_enable_qi(struct intel_iommu * iommu)1727 int dmar_enable_qi(struct intel_iommu *iommu)
1728 {
1729 struct q_inval *qi;
1730 struct page *desc_page;
1731
1732 if (!ecap_qis(iommu->ecap))
1733 return -ENOENT;
1734
1735 /*
1736 * queued invalidation is already setup and enabled.
1737 */
1738 if (iommu->qi)
1739 return 0;
1740
1741 iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC);
1742 if (!iommu->qi)
1743 return -ENOMEM;
1744
1745 qi = iommu->qi;
1746
1747 /*
1748 * Need two pages to accommodate 256 descriptors of 256 bits each
1749 * if the remapping hardware supports scalable mode translation.
1750 */
1751 desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO,
1752 !!ecap_smts(iommu->ecap));
1753 if (!desc_page) {
1754 kfree(qi);
1755 iommu->qi = NULL;
1756 return -ENOMEM;
1757 }
1758
1759 qi->desc = page_address(desc_page);
1760
1761 qi->desc_status = kcalloc(QI_LENGTH, sizeof(int), GFP_ATOMIC);
1762 if (!qi->desc_status) {
1763 free_page((unsigned long) qi->desc);
1764 kfree(qi);
1765 iommu->qi = NULL;
1766 return -ENOMEM;
1767 }
1768
1769 raw_spin_lock_init(&qi->q_lock);
1770
1771 __dmar_enable_qi(iommu);
1772
1773 return 0;
1774 }
1775
1776 /* iommu interrupt handling. Most stuff are MSI-like. */
1777
1778 enum faulttype {
1779 DMA_REMAP,
1780 INTR_REMAP,
1781 UNKNOWN,
1782 };
1783
1784 static const char *dma_remap_fault_reasons[] =
1785 {
1786 "Software",
1787 "Present bit in root entry is clear",
1788 "Present bit in context entry is clear",
1789 "Invalid context entry",
1790 "Access beyond MGAW",
1791 "PTE Write access is not set",
1792 "PTE Read access is not set",
1793 "Next page table ptr is invalid",
1794 "Root table address invalid",
1795 "Context table ptr is invalid",
1796 "non-zero reserved fields in RTP",
1797 "non-zero reserved fields in CTP",
1798 "non-zero reserved fields in PTE",
1799 "PCE for translation request specifies blocking",
1800 };
1801
1802 static const char * const dma_remap_sm_fault_reasons[] = {
1803 "SM: Invalid Root Table Address",
1804 "SM: TTM 0 for request with PASID",
1805 "SM: TTM 0 for page group request",
1806 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x33-0x37 */
1807 "SM: Error attempting to access Root Entry",
1808 "SM: Present bit in Root Entry is clear",
1809 "SM: Non-zero reserved field set in Root Entry",
1810 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x3B-0x3F */
1811 "SM: Error attempting to access Context Entry",
1812 "SM: Present bit in Context Entry is clear",
1813 "SM: Non-zero reserved field set in the Context Entry",
1814 "SM: Invalid Context Entry",
1815 "SM: DTE field in Context Entry is clear",
1816 "SM: PASID Enable field in Context Entry is clear",
1817 "SM: PASID is larger than the max in Context Entry",
1818 "SM: PRE field in Context-Entry is clear",
1819 "SM: RID_PASID field error in Context-Entry",
1820 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x49-0x4F */
1821 "SM: Error attempting to access the PASID Directory Entry",
1822 "SM: Present bit in Directory Entry is clear",
1823 "SM: Non-zero reserved field set in PASID Directory Entry",
1824 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x53-0x57 */
1825 "SM: Error attempting to access PASID Table Entry",
1826 "SM: Present bit in PASID Table Entry is clear",
1827 "SM: Non-zero reserved field set in PASID Table Entry",
1828 "SM: Invalid Scalable-Mode PASID Table Entry",
1829 "SM: ERE field is clear in PASID Table Entry",
1830 "SM: SRE field is clear in PASID Table Entry",
1831 "Unknown", "Unknown",/* 0x5E-0x5F */
1832 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x60-0x67 */
1833 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x68-0x6F */
1834 "SM: Error attempting to access first-level paging entry",
1835 "SM: Present bit in first-level paging entry is clear",
1836 "SM: Non-zero reserved field set in first-level paging entry",
1837 "SM: Error attempting to access FL-PML4 entry",
1838 "SM: First-level entry address beyond MGAW in Nested translation",
1839 "SM: Read permission error in FL-PML4 entry in Nested translation",
1840 "SM: Read permission error in first-level paging entry in Nested translation",
1841 "SM: Write permission error in first-level paging entry in Nested translation",
1842 "SM: Error attempting to access second-level paging entry",
1843 "SM: Read/Write permission error in second-level paging entry",
1844 "SM: Non-zero reserved field set in second-level paging entry",
1845 "SM: Invalid second-level page table pointer",
1846 "SM: A/D bit update needed in second-level entry when set up in no snoop",
1847 "Unknown", "Unknown", "Unknown", /* 0x7D-0x7F */
1848 "SM: Address in first-level translation is not canonical",
1849 "SM: U/S set 0 for first-level translation with user privilege",
1850 "SM: No execute permission for request with PASID and ER=1",
1851 "SM: Address beyond the DMA hardware max",
1852 "SM: Second-level entry address beyond the max",
1853 "SM: No write permission for Write/AtomicOp request",
1854 "SM: No read permission for Read/AtomicOp request",
1855 "SM: Invalid address-interrupt address",
1856 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x88-0x8F */
1857 "SM: A/D bit update needed in first-level entry when set up in no snoop",
1858 };
1859
1860 static const char *irq_remap_fault_reasons[] =
1861 {
1862 "Detected reserved fields in the decoded interrupt-remapped request",
1863 "Interrupt index exceeded the interrupt-remapping table size",
1864 "Present field in the IRTE entry is clear",
1865 "Error accessing interrupt-remapping table pointed by IRTA_REG",
1866 "Detected reserved fields in the IRTE entry",
1867 "Blocked a compatibility format interrupt request",
1868 "Blocked an interrupt request due to source-id verification failure",
1869 };
1870
dmar_get_fault_reason(u8 fault_reason,int * fault_type)1871 static const char *dmar_get_fault_reason(u8 fault_reason, int *fault_type)
1872 {
1873 if (fault_reason >= 0x20 && (fault_reason - 0x20 <
1874 ARRAY_SIZE(irq_remap_fault_reasons))) {
1875 *fault_type = INTR_REMAP;
1876 return irq_remap_fault_reasons[fault_reason - 0x20];
1877 } else if (fault_reason >= 0x30 && (fault_reason - 0x30 <
1878 ARRAY_SIZE(dma_remap_sm_fault_reasons))) {
1879 *fault_type = DMA_REMAP;
1880 return dma_remap_sm_fault_reasons[fault_reason - 0x30];
1881 } else if (fault_reason < ARRAY_SIZE(dma_remap_fault_reasons)) {
1882 *fault_type = DMA_REMAP;
1883 return dma_remap_fault_reasons[fault_reason];
1884 } else {
1885 *fault_type = UNKNOWN;
1886 return "Unknown";
1887 }
1888 }
1889
1890
dmar_msi_reg(struct intel_iommu * iommu,int irq)1891 static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq)
1892 {
1893 if (iommu->irq == irq)
1894 return DMAR_FECTL_REG;
1895 else if (iommu->pr_irq == irq)
1896 return DMAR_PECTL_REG;
1897 else
1898 BUG();
1899 }
1900
dmar_msi_unmask(struct irq_data * data)1901 void dmar_msi_unmask(struct irq_data *data)
1902 {
1903 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1904 int reg = dmar_msi_reg(iommu, data->irq);
1905 unsigned long flag;
1906
1907 /* unmask it */
1908 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1909 writel(0, iommu->reg + reg);
1910 /* Read a reg to force flush the post write */
1911 readl(iommu->reg + reg);
1912 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1913 }
1914
dmar_msi_mask(struct irq_data * data)1915 void dmar_msi_mask(struct irq_data *data)
1916 {
1917 struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
1918 int reg = dmar_msi_reg(iommu, data->irq);
1919 unsigned long flag;
1920
1921 /* mask it */
1922 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1923 writel(DMA_FECTL_IM, iommu->reg + reg);
1924 /* Read a reg to force flush the post write */
1925 readl(iommu->reg + reg);
1926 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1927 }
1928
dmar_msi_write(int irq,struct msi_msg * msg)1929 void dmar_msi_write(int irq, struct msi_msg *msg)
1930 {
1931 struct intel_iommu *iommu = irq_get_handler_data(irq);
1932 int reg = dmar_msi_reg(iommu, irq);
1933 unsigned long flag;
1934
1935 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1936 writel(msg->data, iommu->reg + reg + 4);
1937 writel(msg->address_lo, iommu->reg + reg + 8);
1938 writel(msg->address_hi, iommu->reg + reg + 12);
1939 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1940 }
1941
dmar_msi_read(int irq,struct msi_msg * msg)1942 void dmar_msi_read(int irq, struct msi_msg *msg)
1943 {
1944 struct intel_iommu *iommu = irq_get_handler_data(irq);
1945 int reg = dmar_msi_reg(iommu, irq);
1946 unsigned long flag;
1947
1948 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1949 msg->data = readl(iommu->reg + reg + 4);
1950 msg->address_lo = readl(iommu->reg + reg + 8);
1951 msg->address_hi = readl(iommu->reg + reg + 12);
1952 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
1953 }
1954
dmar_fault_do_one(struct intel_iommu * iommu,int type,u8 fault_reason,u32 pasid,u16 source_id,unsigned long long addr)1955 static int dmar_fault_do_one(struct intel_iommu *iommu, int type,
1956 u8 fault_reason, u32 pasid, u16 source_id,
1957 unsigned long long addr)
1958 {
1959 const char *reason;
1960 int fault_type;
1961
1962 reason = dmar_get_fault_reason(fault_reason, &fault_type);
1963
1964 if (fault_type == INTR_REMAP)
1965 pr_err("[INTR-REMAP] Request device [%02x:%02x.%d] fault index 0x%llx [fault reason 0x%02x] %s\n",
1966 source_id >> 8, PCI_SLOT(source_id & 0xFF),
1967 PCI_FUNC(source_id & 0xFF), addr >> 48,
1968 fault_reason, reason);
1969 else if (pasid == INVALID_IOASID)
1970 pr_err("[%s NO_PASID] Request device [%02x:%02x.%d] fault addr 0x%llx [fault reason 0x%02x] %s\n",
1971 type ? "DMA Read" : "DMA Write",
1972 source_id >> 8, PCI_SLOT(source_id & 0xFF),
1973 PCI_FUNC(source_id & 0xFF), addr,
1974 fault_reason, reason);
1975 else
1976 pr_err("[%s PASID 0x%x] Request device [%02x:%02x.%d] fault addr 0x%llx [fault reason 0x%02x] %s\n",
1977 type ? "DMA Read" : "DMA Write", pasid,
1978 source_id >> 8, PCI_SLOT(source_id & 0xFF),
1979 PCI_FUNC(source_id & 0xFF), addr,
1980 fault_reason, reason);
1981
1982 return 0;
1983 }
1984
1985 #define PRIMARY_FAULT_REG_LEN (16)
dmar_fault(int irq,void * dev_id)1986 irqreturn_t dmar_fault(int irq, void *dev_id)
1987 {
1988 struct intel_iommu *iommu = dev_id;
1989 int reg, fault_index;
1990 u32 fault_status;
1991 unsigned long flag;
1992 static DEFINE_RATELIMIT_STATE(rs,
1993 DEFAULT_RATELIMIT_INTERVAL,
1994 DEFAULT_RATELIMIT_BURST);
1995
1996 raw_spin_lock_irqsave(&iommu->register_lock, flag);
1997 fault_status = readl(iommu->reg + DMAR_FSTS_REG);
1998 if (fault_status && __ratelimit(&rs))
1999 pr_err("DRHD: handling fault status reg %x\n", fault_status);
2000
2001 /* TBD: ignore advanced fault log currently */
2002 if (!(fault_status & DMA_FSTS_PPF))
2003 goto unlock_exit;
2004
2005 fault_index = dma_fsts_fault_record_index(fault_status);
2006 reg = cap_fault_reg_offset(iommu->cap);
2007 while (1) {
2008 /* Disable printing, simply clear the fault when ratelimited */
2009 bool ratelimited = !__ratelimit(&rs);
2010 u8 fault_reason;
2011 u16 source_id;
2012 u64 guest_addr;
2013 u32 pasid;
2014 int type;
2015 u32 data;
2016 bool pasid_present;
2017
2018 /* highest 32 bits */
2019 data = readl(iommu->reg + reg +
2020 fault_index * PRIMARY_FAULT_REG_LEN + 12);
2021 if (!(data & DMA_FRCD_F))
2022 break;
2023
2024 if (!ratelimited) {
2025 fault_reason = dma_frcd_fault_reason(data);
2026 type = dma_frcd_type(data);
2027
2028 pasid = dma_frcd_pasid_value(data);
2029 data = readl(iommu->reg + reg +
2030 fault_index * PRIMARY_FAULT_REG_LEN + 8);
2031 source_id = dma_frcd_source_id(data);
2032
2033 pasid_present = dma_frcd_pasid_present(data);
2034 guest_addr = dmar_readq(iommu->reg + reg +
2035 fault_index * PRIMARY_FAULT_REG_LEN);
2036 guest_addr = dma_frcd_page_addr(guest_addr);
2037 }
2038
2039 /* clear the fault */
2040 writel(DMA_FRCD_F, iommu->reg + reg +
2041 fault_index * PRIMARY_FAULT_REG_LEN + 12);
2042
2043 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
2044
2045 if (!ratelimited)
2046 /* Using pasid -1 if pasid is not present */
2047 dmar_fault_do_one(iommu, type, fault_reason,
2048 pasid_present ? pasid : INVALID_IOASID,
2049 source_id, guest_addr);
2050
2051 fault_index++;
2052 if (fault_index >= cap_num_fault_regs(iommu->cap))
2053 fault_index = 0;
2054 raw_spin_lock_irqsave(&iommu->register_lock, flag);
2055 }
2056
2057 writel(DMA_FSTS_PFO | DMA_FSTS_PPF | DMA_FSTS_PRO,
2058 iommu->reg + DMAR_FSTS_REG);
2059
2060 unlock_exit:
2061 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
2062 return IRQ_HANDLED;
2063 }
2064
dmar_set_interrupt(struct intel_iommu * iommu)2065 int dmar_set_interrupt(struct intel_iommu *iommu)
2066 {
2067 int irq, ret;
2068
2069 /*
2070 * Check if the fault interrupt is already initialized.
2071 */
2072 if (iommu->irq)
2073 return 0;
2074
2075 irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu);
2076 if (irq > 0) {
2077 iommu->irq = irq;
2078 } else {
2079 pr_err("No free IRQ vectors\n");
2080 return -EINVAL;
2081 }
2082
2083 ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu);
2084 if (ret)
2085 pr_err("Can't request irq\n");
2086 return ret;
2087 }
2088
enable_drhd_fault_handling(void)2089 int __init enable_drhd_fault_handling(void)
2090 {
2091 struct dmar_drhd_unit *drhd;
2092 struct intel_iommu *iommu;
2093
2094 /*
2095 * Enable fault control interrupt.
2096 */
2097 for_each_iommu(iommu, drhd) {
2098 u32 fault_status;
2099 int ret = dmar_set_interrupt(iommu);
2100
2101 if (ret) {
2102 pr_err("DRHD %Lx: failed to enable fault, interrupt, ret %d\n",
2103 (unsigned long long)drhd->reg_base_addr, ret);
2104 return -1;
2105 }
2106
2107 /*
2108 * Clear any previous faults.
2109 */
2110 dmar_fault(iommu->irq, iommu);
2111 fault_status = readl(iommu->reg + DMAR_FSTS_REG);
2112 writel(fault_status, iommu->reg + DMAR_FSTS_REG);
2113 }
2114
2115 return 0;
2116 }
2117
2118 /*
2119 * Re-enable Queued Invalidation interface.
2120 */
dmar_reenable_qi(struct intel_iommu * iommu)2121 int dmar_reenable_qi(struct intel_iommu *iommu)
2122 {
2123 if (!ecap_qis(iommu->ecap))
2124 return -ENOENT;
2125
2126 if (!iommu->qi)
2127 return -ENOENT;
2128
2129 /*
2130 * First disable queued invalidation.
2131 */
2132 dmar_disable_qi(iommu);
2133 /*
2134 * Then enable queued invalidation again. Since there is no pending
2135 * invalidation requests now, it's safe to re-enable queued
2136 * invalidation.
2137 */
2138 __dmar_enable_qi(iommu);
2139
2140 return 0;
2141 }
2142
2143 /*
2144 * Check interrupt remapping support in DMAR table description.
2145 */
dmar_ir_support(void)2146 int __init dmar_ir_support(void)
2147 {
2148 struct acpi_table_dmar *dmar;
2149 dmar = (struct acpi_table_dmar *)dmar_tbl;
2150 if (!dmar)
2151 return 0;
2152 return dmar->flags & 0x1;
2153 }
2154
2155 /* Check whether DMAR units are in use */
dmar_in_use(void)2156 static inline bool dmar_in_use(void)
2157 {
2158 return irq_remapping_enabled || intel_iommu_enabled;
2159 }
2160
dmar_free_unused_resources(void)2161 static int __init dmar_free_unused_resources(void)
2162 {
2163 struct dmar_drhd_unit *dmaru, *dmaru_n;
2164
2165 if (dmar_in_use())
2166 return 0;
2167
2168 if (dmar_dev_scope_status != 1 && !list_empty(&dmar_drhd_units))
2169 bus_unregister_notifier(&pci_bus_type, &dmar_pci_bus_nb);
2170
2171 down_write(&dmar_global_lock);
2172 list_for_each_entry_safe(dmaru, dmaru_n, &dmar_drhd_units, list) {
2173 list_del(&dmaru->list);
2174 dmar_free_drhd(dmaru);
2175 }
2176 up_write(&dmar_global_lock);
2177
2178 return 0;
2179 }
2180
2181 late_initcall(dmar_free_unused_resources);
2182 IOMMU_INIT_POST(detect_intel_iommu);
2183
2184 /*
2185 * DMAR Hotplug Support
2186 * For more details, please refer to Intel(R) Virtualization Technology
2187 * for Directed-IO Architecture Specifiction, Rev 2.2, Section 8.8
2188 * "Remapping Hardware Unit Hot Plug".
2189 */
2190 static guid_t dmar_hp_guid =
2191 GUID_INIT(0xD8C1A3A6, 0xBE9B, 0x4C9B,
2192 0x91, 0xBF, 0xC3, 0xCB, 0x81, 0xFC, 0x5D, 0xAF);
2193
2194 /*
2195 * Currently there's only one revision and BIOS will not check the revision id,
2196 * so use 0 for safety.
2197 */
2198 #define DMAR_DSM_REV_ID 0
2199 #define DMAR_DSM_FUNC_DRHD 1
2200 #define DMAR_DSM_FUNC_ATSR 2
2201 #define DMAR_DSM_FUNC_RHSA 3
2202 #define DMAR_DSM_FUNC_SATC 4
2203
dmar_detect_dsm(acpi_handle handle,int func)2204 static inline bool dmar_detect_dsm(acpi_handle handle, int func)
2205 {
2206 return acpi_check_dsm(handle, &dmar_hp_guid, DMAR_DSM_REV_ID, 1 << func);
2207 }
2208
dmar_walk_dsm_resource(acpi_handle handle,int func,dmar_res_handler_t handler,void * arg)2209 static int dmar_walk_dsm_resource(acpi_handle handle, int func,
2210 dmar_res_handler_t handler, void *arg)
2211 {
2212 int ret = -ENODEV;
2213 union acpi_object *obj;
2214 struct acpi_dmar_header *start;
2215 struct dmar_res_callback callback;
2216 static int res_type[] = {
2217 [DMAR_DSM_FUNC_DRHD] = ACPI_DMAR_TYPE_HARDWARE_UNIT,
2218 [DMAR_DSM_FUNC_ATSR] = ACPI_DMAR_TYPE_ROOT_ATS,
2219 [DMAR_DSM_FUNC_RHSA] = ACPI_DMAR_TYPE_HARDWARE_AFFINITY,
2220 [DMAR_DSM_FUNC_SATC] = ACPI_DMAR_TYPE_SATC,
2221 };
2222
2223 if (!dmar_detect_dsm(handle, func))
2224 return 0;
2225
2226 obj = acpi_evaluate_dsm_typed(handle, &dmar_hp_guid, DMAR_DSM_REV_ID,
2227 func, NULL, ACPI_TYPE_BUFFER);
2228 if (!obj)
2229 return -ENODEV;
2230
2231 memset(&callback, 0, sizeof(callback));
2232 callback.cb[res_type[func]] = handler;
2233 callback.arg[res_type[func]] = arg;
2234 start = (struct acpi_dmar_header *)obj->buffer.pointer;
2235 ret = dmar_walk_remapping_entries(start, obj->buffer.length, &callback);
2236
2237 ACPI_FREE(obj);
2238
2239 return ret;
2240 }
2241
dmar_hp_add_drhd(struct acpi_dmar_header * header,void * arg)2242 static int dmar_hp_add_drhd(struct acpi_dmar_header *header, void *arg)
2243 {
2244 int ret;
2245 struct dmar_drhd_unit *dmaru;
2246
2247 dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
2248 if (!dmaru)
2249 return -ENODEV;
2250
2251 ret = dmar_ir_hotplug(dmaru, true);
2252 if (ret == 0)
2253 ret = dmar_iommu_hotplug(dmaru, true);
2254
2255 return ret;
2256 }
2257
dmar_hp_remove_drhd(struct acpi_dmar_header * header,void * arg)2258 static int dmar_hp_remove_drhd(struct acpi_dmar_header *header, void *arg)
2259 {
2260 int i, ret;
2261 struct device *dev;
2262 struct dmar_drhd_unit *dmaru;
2263
2264 dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
2265 if (!dmaru)
2266 return 0;
2267
2268 /*
2269 * All PCI devices managed by this unit should have been destroyed.
2270 */
2271 if (!dmaru->include_all && dmaru->devices && dmaru->devices_cnt) {
2272 for_each_active_dev_scope(dmaru->devices,
2273 dmaru->devices_cnt, i, dev)
2274 return -EBUSY;
2275 }
2276
2277 ret = dmar_ir_hotplug(dmaru, false);
2278 if (ret == 0)
2279 ret = dmar_iommu_hotplug(dmaru, false);
2280
2281 return ret;
2282 }
2283
dmar_hp_release_drhd(struct acpi_dmar_header * header,void * arg)2284 static int dmar_hp_release_drhd(struct acpi_dmar_header *header, void *arg)
2285 {
2286 struct dmar_drhd_unit *dmaru;
2287
2288 dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header);
2289 if (dmaru) {
2290 list_del_rcu(&dmaru->list);
2291 synchronize_rcu();
2292 dmar_free_drhd(dmaru);
2293 }
2294
2295 return 0;
2296 }
2297
dmar_hotplug_insert(acpi_handle handle)2298 static int dmar_hotplug_insert(acpi_handle handle)
2299 {
2300 int ret;
2301 int drhd_count = 0;
2302
2303 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2304 &dmar_validate_one_drhd, (void *)1);
2305 if (ret)
2306 goto out;
2307
2308 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2309 &dmar_parse_one_drhd, (void *)&drhd_count);
2310 if (ret == 0 && drhd_count == 0) {
2311 pr_warn(FW_BUG "No DRHD structures in buffer returned by _DSM method\n");
2312 goto out;
2313 } else if (ret) {
2314 goto release_drhd;
2315 }
2316
2317 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_RHSA,
2318 &dmar_parse_one_rhsa, NULL);
2319 if (ret)
2320 goto release_drhd;
2321
2322 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2323 &dmar_parse_one_atsr, NULL);
2324 if (ret)
2325 goto release_atsr;
2326
2327 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2328 &dmar_hp_add_drhd, NULL);
2329 if (!ret)
2330 return 0;
2331
2332 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2333 &dmar_hp_remove_drhd, NULL);
2334 release_atsr:
2335 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2336 &dmar_release_one_atsr, NULL);
2337 release_drhd:
2338 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2339 &dmar_hp_release_drhd, NULL);
2340 out:
2341 return ret;
2342 }
2343
dmar_hotplug_remove(acpi_handle handle)2344 static int dmar_hotplug_remove(acpi_handle handle)
2345 {
2346 int ret;
2347
2348 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2349 &dmar_check_one_atsr, NULL);
2350 if (ret)
2351 return ret;
2352
2353 ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2354 &dmar_hp_remove_drhd, NULL);
2355 if (ret == 0) {
2356 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR,
2357 &dmar_release_one_atsr, NULL));
2358 WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2359 &dmar_hp_release_drhd, NULL));
2360 } else {
2361 dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD,
2362 &dmar_hp_add_drhd, NULL);
2363 }
2364
2365 return ret;
2366 }
2367
dmar_get_dsm_handle(acpi_handle handle,u32 lvl,void * context,void ** retval)2368 static acpi_status dmar_get_dsm_handle(acpi_handle handle, u32 lvl,
2369 void *context, void **retval)
2370 {
2371 acpi_handle *phdl = retval;
2372
2373 if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
2374 *phdl = handle;
2375 return AE_CTRL_TERMINATE;
2376 }
2377
2378 return AE_OK;
2379 }
2380
dmar_device_hotplug(acpi_handle handle,bool insert)2381 static int dmar_device_hotplug(acpi_handle handle, bool insert)
2382 {
2383 int ret;
2384 acpi_handle tmp = NULL;
2385 acpi_status status;
2386
2387 if (!dmar_in_use())
2388 return 0;
2389
2390 if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) {
2391 tmp = handle;
2392 } else {
2393 status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle,
2394 ACPI_UINT32_MAX,
2395 dmar_get_dsm_handle,
2396 NULL, NULL, &tmp);
2397 if (ACPI_FAILURE(status)) {
2398 pr_warn("Failed to locate _DSM method.\n");
2399 return -ENXIO;
2400 }
2401 }
2402 if (tmp == NULL)
2403 return 0;
2404
2405 down_write(&dmar_global_lock);
2406 if (insert)
2407 ret = dmar_hotplug_insert(tmp);
2408 else
2409 ret = dmar_hotplug_remove(tmp);
2410 up_write(&dmar_global_lock);
2411
2412 return ret;
2413 }
2414
dmar_device_add(acpi_handle handle)2415 int dmar_device_add(acpi_handle handle)
2416 {
2417 return dmar_device_hotplug(handle, true);
2418 }
2419
dmar_device_remove(acpi_handle handle)2420 int dmar_device_remove(acpi_handle handle)
2421 {
2422 return dmar_device_hotplug(handle, false);
2423 }
2424
2425 /*
2426 * dmar_platform_optin - Is %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in DMAR table
2427 *
2428 * Returns true if the platform has %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in
2429 * the ACPI DMAR table. This means that the platform boot firmware has made
2430 * sure no device can issue DMA outside of RMRR regions.
2431 */
dmar_platform_optin(void)2432 bool dmar_platform_optin(void)
2433 {
2434 struct acpi_table_dmar *dmar;
2435 acpi_status status;
2436 bool ret;
2437
2438 status = acpi_get_table(ACPI_SIG_DMAR, 0,
2439 (struct acpi_table_header **)&dmar);
2440 if (ACPI_FAILURE(status))
2441 return false;
2442
2443 ret = !!(dmar->flags & DMAR_PLATFORM_OPT_IN);
2444 acpi_put_table((struct acpi_table_header *)dmar);
2445
2446 return ret;
2447 }
2448 EXPORT_SYMBOL_GPL(dmar_platform_optin);
2449