1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Monk.liu@amd.com
23 */
24 #ifndef AMDGPU_VIRT_H
25 #define AMDGPU_VIRT_H
26
27 #include "amdgv_sriovmsg.h"
28
29 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */
30 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */
31 #define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */
32 #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */
33 #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */
34 #define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */
35
36 /* all asic after AI use this offset */
37 #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5
38 /* tonga/fiji use this offset */
39 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503
40
41 enum amdgpu_sriov_vf_mode {
42 SRIOV_VF_MODE_BARE_METAL = 0,
43 SRIOV_VF_MODE_ONE_VF,
44 SRIOV_VF_MODE_MULTI_VF,
45 };
46
47 struct amdgpu_mm_table {
48 struct amdgpu_bo *bo;
49 uint32_t *cpu_addr;
50 uint64_t gpu_addr;
51 };
52
53 #define AMDGPU_VF_ERROR_ENTRY_SIZE 16
54
55 /* struct error_entry - amdgpu VF error information. */
56 struct amdgpu_vf_error_buffer {
57 struct mutex lock;
58 int read_count;
59 int write_count;
60 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE];
61 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE];
62 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
63 };
64
65 enum idh_request;
66
67 /**
68 * struct amdgpu_virt_ops - amdgpu device virt operations
69 */
70 struct amdgpu_virt_ops {
71 int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
72 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
73 int (*req_init_data)(struct amdgpu_device *adev);
74 int (*reset_gpu)(struct amdgpu_device *adev);
75 int (*wait_reset)(struct amdgpu_device *adev);
76 void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req,
77 u32 data1, u32 data2, u32 data3);
78 };
79
80 /*
81 * Firmware Reserve Frame buffer
82 */
83 struct amdgpu_virt_fw_reserve {
84 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf;
85 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
86 unsigned int checksum_key;
87 };
88
89 /*
90 * Legacy GIM header
91 *
92 * Defination between PF and VF
93 * Structures forcibly aligned to 4 to keep the same style as PF.
94 */
95 #define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024)
96
97 #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \
98 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))
99
100 enum AMDGIM_FEATURE_FLAG {
101 /* GIM supports feature of Error log collecting */
102 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1,
103 /* GIM supports feature of loading uCodes */
104 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2,
105 /* VRAM LOST by GIM */
106 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4,
107 /* MM bandwidth */
108 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8,
109 /* PP ONE VF MODE in GIM */
110 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
111 /* Indirect Reg Access enabled */
112 AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5),
113 };
114
115 enum AMDGIM_REG_ACCESS_FLAG {
116 /* Use PSP to program IH_RB_CNTL */
117 AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0),
118 /* Use RLC to program MMHUB regs */
119 AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1),
120 /* Use RLC to program GC regs */
121 AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2),
122 };
123
124 struct amdgim_pf2vf_info_v1 {
125 /* header contains size and version */
126 struct amd_sriov_msg_pf2vf_info_header header;
127 /* max_width * max_height */
128 unsigned int uvd_enc_max_pixels_count;
129 /* 16x16 pixels/sec, codec independent */
130 unsigned int uvd_enc_max_bandwidth;
131 /* max_width * max_height */
132 unsigned int vce_enc_max_pixels_count;
133 /* 16x16 pixels/sec, codec independent */
134 unsigned int vce_enc_max_bandwidth;
135 /* MEC FW position in kb from the start of visible frame buffer */
136 unsigned int mecfw_kboffset;
137 /* The features flags of the GIM driver supports. */
138 unsigned int feature_flags;
139 /* use private key from mailbox 2 to create chueksum */
140 unsigned int checksum;
141 } __aligned(4);
142
143 struct amdgim_vf2pf_info_v1 {
144 /* header contains size and version */
145 struct amd_sriov_msg_vf2pf_info_header header;
146 /* driver version */
147 char driver_version[64];
148 /* driver certification, 1=WHQL, 0=None */
149 unsigned int driver_cert;
150 /* guest OS type and version: need a define */
151 unsigned int os_info;
152 /* in the unit of 1M */
153 unsigned int fb_usage;
154 /* guest gfx engine usage percentage */
155 unsigned int gfx_usage;
156 /* guest gfx engine health percentage */
157 unsigned int gfx_health;
158 /* guest compute engine usage percentage */
159 unsigned int compute_usage;
160 /* guest compute engine health percentage */
161 unsigned int compute_health;
162 /* guest vce engine usage percentage. 0xffff means N/A. */
163 unsigned int vce_enc_usage;
164 /* guest vce engine health percentage. 0xffff means N/A. */
165 unsigned int vce_enc_health;
166 /* guest uvd engine usage percentage. 0xffff means N/A. */
167 unsigned int uvd_enc_usage;
168 /* guest uvd engine usage percentage. 0xffff means N/A. */
169 unsigned int uvd_enc_health;
170 unsigned int checksum;
171 } __aligned(4);
172
173 struct amdgim_vf2pf_info_v2 {
174 /* header contains size and version */
175 struct amd_sriov_msg_vf2pf_info_header header;
176 uint32_t checksum;
177 /* driver version */
178 uint8_t driver_version[64];
179 /* driver certification, 1=WHQL, 0=None */
180 uint32_t driver_cert;
181 /* guest OS type and version: need a define */
182 uint32_t os_info;
183 /* in the unit of 1M */
184 uint32_t fb_usage;
185 /* guest gfx engine usage percentage */
186 uint32_t gfx_usage;
187 /* guest gfx engine health percentage */
188 uint32_t gfx_health;
189 /* guest compute engine usage percentage */
190 uint32_t compute_usage;
191 /* guest compute engine health percentage */
192 uint32_t compute_health;
193 /* guest vce engine usage percentage. 0xffff means N/A. */
194 uint32_t vce_enc_usage;
195 /* guest vce engine health percentage. 0xffff means N/A. */
196 uint32_t vce_enc_health;
197 /* guest uvd engine usage percentage. 0xffff means N/A. */
198 uint32_t uvd_enc_usage;
199 /* guest uvd engine usage percentage. 0xffff means N/A. */
200 uint32_t uvd_enc_health;
201 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)];
202 } __aligned(4);
203
204 struct amdgpu_virt_ras_err_handler_data {
205 /* point to bad page records array */
206 struct eeprom_table_record *bps;
207 /* point to reserved bo array */
208 struct amdgpu_bo **bps_bo;
209 /* the count of entries */
210 int count;
211 /* last reserved entry's index + 1 */
212 int last_reserved;
213 };
214
215 /* GPU virtualization */
216 struct amdgpu_virt {
217 uint32_t caps;
218 struct amdgpu_bo *csa_obj;
219 void *csa_cpu_addr;
220 bool chained_ib_support;
221 uint32_t reg_val_offs;
222 struct amdgpu_irq_src ack_irq;
223 struct amdgpu_irq_src rcv_irq;
224 struct work_struct flr_work;
225 struct amdgpu_mm_table mm_table;
226 const struct amdgpu_virt_ops *ops;
227 struct amdgpu_vf_error_buffer vf_errors;
228 struct amdgpu_virt_fw_reserve fw_reserve;
229 uint32_t gim_feature;
230 uint32_t reg_access_mode;
231 int req_init_data_ver;
232 bool tdr_debug;
233 struct amdgpu_virt_ras_err_handler_data *virt_eh_data;
234 bool ras_init_done;
235 uint32_t reg_access;
236
237 /* vf2pf message */
238 struct delayed_work vf2pf_work;
239 uint32_t vf2pf_update_interval_ms;
240
241 /* multimedia bandwidth config */
242 bool is_mm_bw_enabled;
243 uint32_t decode_max_dimension_pixels;
244 uint32_t decode_max_frame_pixels;
245 uint32_t encode_max_dimension_pixels;
246 uint32_t encode_max_frame_pixels;
247 };
248
249 struct amdgpu_video_codec_info;
250
251 #define amdgpu_sriov_enabled(adev) \
252 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
253
254 #define amdgpu_sriov_vf(adev) \
255 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF)
256
257 #define amdgpu_sriov_bios(adev) \
258 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)
259
260 #define amdgpu_sriov_runtime(adev) \
261 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)
262
263 #define amdgpu_sriov_fullaccess(adev) \
264 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
265
266 #define amdgpu_sriov_reg_indirect_en(adev) \
267 (amdgpu_sriov_vf((adev)) && \
268 ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS)))
269
270 #define amdgpu_sriov_reg_indirect_ih(adev) \
271 (amdgpu_sriov_vf((adev)) && \
272 ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN)))
273
274 #define amdgpu_sriov_reg_indirect_mmhub(adev) \
275 (amdgpu_sriov_vf((adev)) && \
276 ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN)))
277
278 #define amdgpu_sriov_reg_indirect_gc(adev) \
279 (amdgpu_sriov_vf((adev)) && \
280 ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN)))
281
282 #define amdgpu_passthrough(adev) \
283 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
284
285 #define amdgpu_sriov_vf_mmio_access_protection(adev) \
286 ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT)
287
is_virtual_machine(void)288 static inline bool is_virtual_machine(void)
289 {
290 #ifdef CONFIG_X86
291 return boot_cpu_has(X86_FEATURE_HYPERVISOR);
292 #else
293 return false;
294 #endif
295 }
296
297 #define amdgpu_sriov_is_pp_one_vf(adev) \
298 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
299 #define amdgpu_sriov_is_debug(adev) \
300 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
301 #define amdgpu_sriov_is_normal(adev) \
302 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
303
304 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
305 void amdgpu_virt_init_setting(struct amdgpu_device *adev);
306 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
307 uint32_t reg0, uint32_t rreg1,
308 uint32_t ref, uint32_t mask);
309 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
310 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
311 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
312 void amdgpu_virt_request_init_data(struct amdgpu_device *adev);
313 int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
314 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
315 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
316 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
317 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
318 void amdgpu_virt_exchange_data(struct amdgpu_device *adev);
319 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);
320 void amdgpu_detect_virtualization(struct amdgpu_device *adev);
321
322 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
323 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
324 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);
325
326 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev);
327
328 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
329 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
330 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size);
331 #endif
332