1 // SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
2 /*
3 * Copyright(c) 2015 - 2017 Intel Corporation.
4 */
5
6 #include <linux/firmware.h>
7 #include <linux/mutex.h>
8 #include <linux/module.h>
9 #include <linux/delay.h>
10 #include <linux/crc32.h>
11
12 #include "hfi.h"
13 #include "trace.h"
14
15 /*
16 * Make it easy to toggle firmware file name and if it gets loaded by
17 * editing the following. This may be something we do while in development
18 * but not necessarily something a user would ever need to use.
19 */
20 #define DEFAULT_FW_8051_NAME_FPGA "hfi_dc8051.bin"
21 #define DEFAULT_FW_8051_NAME_ASIC "hfi1_dc8051.fw"
22 #define DEFAULT_FW_FABRIC_NAME "hfi1_fabric.fw"
23 #define DEFAULT_FW_SBUS_NAME "hfi1_sbus.fw"
24 #define DEFAULT_FW_PCIE_NAME "hfi1_pcie.fw"
25 #define ALT_FW_8051_NAME_ASIC "hfi1_dc8051_d.fw"
26 #define ALT_FW_FABRIC_NAME "hfi1_fabric_d.fw"
27 #define ALT_FW_SBUS_NAME "hfi1_sbus_d.fw"
28 #define ALT_FW_PCIE_NAME "hfi1_pcie_d.fw"
29
30 MODULE_FIRMWARE(DEFAULT_FW_8051_NAME_ASIC);
31 MODULE_FIRMWARE(DEFAULT_FW_FABRIC_NAME);
32 MODULE_FIRMWARE(DEFAULT_FW_SBUS_NAME);
33 MODULE_FIRMWARE(DEFAULT_FW_PCIE_NAME);
34
35 static uint fw_8051_load = 1;
36 static uint fw_fabric_serdes_load = 1;
37 static uint fw_pcie_serdes_load = 1;
38 static uint fw_sbus_load = 1;
39
40 /* Firmware file names get set in hfi1_firmware_init() based on the above */
41 static char *fw_8051_name;
42 static char *fw_fabric_serdes_name;
43 static char *fw_sbus_name;
44 static char *fw_pcie_serdes_name;
45
46 #define SBUS_MAX_POLL_COUNT 100
47 #define SBUS_COUNTER(reg, name) \
48 (((reg) >> ASIC_STS_SBUS_COUNTERS_##name##_CNT_SHIFT) & \
49 ASIC_STS_SBUS_COUNTERS_##name##_CNT_MASK)
50
51 /*
52 * Firmware security header.
53 */
54 struct css_header {
55 u32 module_type;
56 u32 header_len;
57 u32 header_version;
58 u32 module_id;
59 u32 module_vendor;
60 u32 date; /* BCD yyyymmdd */
61 u32 size; /* in DWORDs */
62 u32 key_size; /* in DWORDs */
63 u32 modulus_size; /* in DWORDs */
64 u32 exponent_size; /* in DWORDs */
65 u32 reserved[22];
66 };
67
68 /* expected field values */
69 #define CSS_MODULE_TYPE 0x00000006
70 #define CSS_HEADER_LEN 0x000000a1
71 #define CSS_HEADER_VERSION 0x00010000
72 #define CSS_MODULE_VENDOR 0x00008086
73
74 #define KEY_SIZE 256
75 #define MU_SIZE 8
76 #define EXPONENT_SIZE 4
77
78 /* size of platform configuration partition */
79 #define MAX_PLATFORM_CONFIG_FILE_SIZE 4096
80
81 /* size of file of plaform configuration encoded in format version 4 */
82 #define PLATFORM_CONFIG_FORMAT_4_FILE_SIZE 528
83
84 /* the file itself */
85 struct firmware_file {
86 struct css_header css_header;
87 u8 modulus[KEY_SIZE];
88 u8 exponent[EXPONENT_SIZE];
89 u8 signature[KEY_SIZE];
90 u8 firmware[];
91 };
92
93 struct augmented_firmware_file {
94 struct css_header css_header;
95 u8 modulus[KEY_SIZE];
96 u8 exponent[EXPONENT_SIZE];
97 u8 signature[KEY_SIZE];
98 u8 r2[KEY_SIZE];
99 u8 mu[MU_SIZE];
100 u8 firmware[];
101 };
102
103 /* augmented file size difference */
104 #define AUGMENT_SIZE (sizeof(struct augmented_firmware_file) - \
105 sizeof(struct firmware_file))
106
107 struct firmware_details {
108 /* Linux core piece */
109 const struct firmware *fw;
110
111 struct css_header *css_header;
112 u8 *firmware_ptr; /* pointer to binary data */
113 u32 firmware_len; /* length in bytes */
114 u8 *modulus; /* pointer to the modulus */
115 u8 *exponent; /* pointer to the exponent */
116 u8 *signature; /* pointer to the signature */
117 u8 *r2; /* pointer to r2 */
118 u8 *mu; /* pointer to mu */
119 struct augmented_firmware_file dummy_header;
120 };
121
122 /*
123 * The mutex protects fw_state, fw_err, and all of the firmware_details
124 * variables.
125 */
126 static DEFINE_MUTEX(fw_mutex);
127 enum fw_state {
128 FW_EMPTY,
129 FW_TRY,
130 FW_FINAL,
131 FW_ERR
132 };
133
134 static enum fw_state fw_state = FW_EMPTY;
135 static int fw_err;
136 static struct firmware_details fw_8051;
137 static struct firmware_details fw_fabric;
138 static struct firmware_details fw_pcie;
139 static struct firmware_details fw_sbus;
140
141 /* flags for turn_off_spicos() */
142 #define SPICO_SBUS 0x1
143 #define SPICO_FABRIC 0x2
144 #define ENABLE_SPICO_SMASK 0x1
145
146 /* security block commands */
147 #define RSA_CMD_INIT 0x1
148 #define RSA_CMD_START 0x2
149
150 /* security block status */
151 #define RSA_STATUS_IDLE 0x0
152 #define RSA_STATUS_ACTIVE 0x1
153 #define RSA_STATUS_DONE 0x2
154 #define RSA_STATUS_FAILED 0x3
155
156 /* RSA engine timeout, in ms */
157 #define RSA_ENGINE_TIMEOUT 100 /* ms */
158
159 /* hardware mutex timeout, in ms */
160 #define HM_TIMEOUT 10 /* ms */
161
162 /* 8051 memory access timeout, in us */
163 #define DC8051_ACCESS_TIMEOUT 100 /* us */
164
165 /* the number of fabric SerDes on the SBus */
166 #define NUM_FABRIC_SERDES 4
167
168 /* ASIC_STS_SBUS_RESULT.RESULT_CODE value */
169 #define SBUS_READ_COMPLETE 0x4
170
171 /* SBus fabric SerDes addresses, one set per HFI */
172 static const u8 fabric_serdes_addrs[2][NUM_FABRIC_SERDES] = {
173 { 0x01, 0x02, 0x03, 0x04 },
174 { 0x28, 0x29, 0x2a, 0x2b }
175 };
176
177 /* SBus PCIe SerDes addresses, one set per HFI */
178 static const u8 pcie_serdes_addrs[2][NUM_PCIE_SERDES] = {
179 { 0x08, 0x0a, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16,
180 0x18, 0x1a, 0x1c, 0x1e, 0x20, 0x22, 0x24, 0x26 },
181 { 0x2f, 0x31, 0x33, 0x35, 0x37, 0x39, 0x3b, 0x3d,
182 0x3f, 0x41, 0x43, 0x45, 0x47, 0x49, 0x4b, 0x4d }
183 };
184
185 /* SBus PCIe PCS addresses, one set per HFI */
186 const u8 pcie_pcs_addrs[2][NUM_PCIE_SERDES] = {
187 { 0x09, 0x0b, 0x0d, 0x0f, 0x11, 0x13, 0x15, 0x17,
188 0x19, 0x1b, 0x1d, 0x1f, 0x21, 0x23, 0x25, 0x27 },
189 { 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e,
190 0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e }
191 };
192
193 /* SBus fabric SerDes broadcast addresses, one per HFI */
194 static const u8 fabric_serdes_broadcast[2] = { 0xe4, 0xe5 };
195 static const u8 all_fabric_serdes_broadcast = 0xe1;
196
197 /* SBus PCIe SerDes broadcast addresses, one per HFI */
198 const u8 pcie_serdes_broadcast[2] = { 0xe2, 0xe3 };
199 static const u8 all_pcie_serdes_broadcast = 0xe0;
200
201 static const u32 platform_config_table_limits[PLATFORM_CONFIG_TABLE_MAX] = {
202 0,
203 SYSTEM_TABLE_MAX,
204 PORT_TABLE_MAX,
205 RX_PRESET_TABLE_MAX,
206 TX_PRESET_TABLE_MAX,
207 QSFP_ATTEN_TABLE_MAX,
208 VARIABLE_SETTINGS_TABLE_MAX
209 };
210
211 /* forwards */
212 static void dispose_one_firmware(struct firmware_details *fdet);
213 static int load_fabric_serdes_firmware(struct hfi1_devdata *dd,
214 struct firmware_details *fdet);
215 static void dump_fw_version(struct hfi1_devdata *dd);
216
217 /*
218 * Read a single 64-bit value from 8051 data memory.
219 *
220 * Expects:
221 * o caller to have already set up data read, no auto increment
222 * o caller to turn off read enable when finished
223 *
224 * The address argument is a byte offset. Bits 0:2 in the address are
225 * ignored - i.e. the hardware will always do aligned 8-byte reads as if
226 * the lower bits are zero.
227 *
228 * Return 0 on success, -ENXIO on a read error (timeout).
229 */
__read_8051_data(struct hfi1_devdata * dd,u32 addr,u64 * result)230 static int __read_8051_data(struct hfi1_devdata *dd, u32 addr, u64 *result)
231 {
232 u64 reg;
233 int count;
234
235 /* step 1: set the address, clear enable */
236 reg = (addr & DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK)
237 << DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT;
238 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg);
239 /* step 2: enable */
240 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL,
241 reg | DC_DC8051_CFG_RAM_ACCESS_CTRL_READ_ENA_SMASK);
242
243 /* wait until ACCESS_COMPLETED is set */
244 count = 0;
245 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS)
246 & DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK)
247 == 0) {
248 count++;
249 if (count > DC8051_ACCESS_TIMEOUT) {
250 dd_dev_err(dd, "timeout reading 8051 data\n");
251 return -ENXIO;
252 }
253 ndelay(10);
254 }
255
256 /* gather the data */
257 *result = read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_RD_DATA);
258
259 return 0;
260 }
261
262 /*
263 * Read 8051 data starting at addr, for len bytes. Will read in 8-byte chunks.
264 * Return 0 on success, -errno on error.
265 */
read_8051_data(struct hfi1_devdata * dd,u32 addr,u32 len,u64 * result)266 int read_8051_data(struct hfi1_devdata *dd, u32 addr, u32 len, u64 *result)
267 {
268 unsigned long flags;
269 u32 done;
270 int ret = 0;
271
272 spin_lock_irqsave(&dd->dc8051_memlock, flags);
273
274 /* data read set-up, no auto-increment */
275 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0);
276
277 for (done = 0; done < len; addr += 8, done += 8, result++) {
278 ret = __read_8051_data(dd, addr, result);
279 if (ret)
280 break;
281 }
282
283 /* turn off read enable */
284 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0);
285
286 spin_unlock_irqrestore(&dd->dc8051_memlock, flags);
287
288 return ret;
289 }
290
291 /*
292 * Write data or code to the 8051 code or data RAM.
293 */
write_8051(struct hfi1_devdata * dd,int code,u32 start,const u8 * data,u32 len)294 static int write_8051(struct hfi1_devdata *dd, int code, u32 start,
295 const u8 *data, u32 len)
296 {
297 u64 reg;
298 u32 offset;
299 int aligned, count;
300
301 /* check alignment */
302 aligned = ((unsigned long)data & 0x7) == 0;
303
304 /* write set-up */
305 reg = (code ? DC_DC8051_CFG_RAM_ACCESS_SETUP_RAM_SEL_SMASK : 0ull)
306 | DC_DC8051_CFG_RAM_ACCESS_SETUP_AUTO_INCR_ADDR_SMASK;
307 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, reg);
308
309 reg = ((start & DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK)
310 << DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT)
311 | DC_DC8051_CFG_RAM_ACCESS_CTRL_WRITE_ENA_SMASK;
312 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg);
313
314 /* write */
315 for (offset = 0; offset < len; offset += 8) {
316 int bytes = len - offset;
317
318 if (bytes < 8) {
319 reg = 0;
320 memcpy(®, &data[offset], bytes);
321 } else if (aligned) {
322 reg = *(u64 *)&data[offset];
323 } else {
324 memcpy(®, &data[offset], 8);
325 }
326 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_WR_DATA, reg);
327
328 /* wait until ACCESS_COMPLETED is set */
329 count = 0;
330 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS)
331 & DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK)
332 == 0) {
333 count++;
334 if (count > DC8051_ACCESS_TIMEOUT) {
335 dd_dev_err(dd, "timeout writing 8051 data\n");
336 return -ENXIO;
337 }
338 udelay(1);
339 }
340 }
341
342 /* turn off write access, auto increment (also sets to data access) */
343 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0);
344 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0);
345
346 return 0;
347 }
348
349 /* return 0 if values match, non-zero and complain otherwise */
invalid_header(struct hfi1_devdata * dd,const char * what,u32 actual,u32 expected)350 static int invalid_header(struct hfi1_devdata *dd, const char *what,
351 u32 actual, u32 expected)
352 {
353 if (actual == expected)
354 return 0;
355
356 dd_dev_err(dd,
357 "invalid firmware header field %s: expected 0x%x, actual 0x%x\n",
358 what, expected, actual);
359 return 1;
360 }
361
362 /*
363 * Verify that the static fields in the CSS header match.
364 */
verify_css_header(struct hfi1_devdata * dd,struct css_header * css)365 static int verify_css_header(struct hfi1_devdata *dd, struct css_header *css)
366 {
367 /* verify CSS header fields (most sizes are in DW, so add /4) */
368 if (invalid_header(dd, "module_type", css->module_type,
369 CSS_MODULE_TYPE) ||
370 invalid_header(dd, "header_len", css->header_len,
371 (sizeof(struct firmware_file) / 4)) ||
372 invalid_header(dd, "header_version", css->header_version,
373 CSS_HEADER_VERSION) ||
374 invalid_header(dd, "module_vendor", css->module_vendor,
375 CSS_MODULE_VENDOR) ||
376 invalid_header(dd, "key_size", css->key_size, KEY_SIZE / 4) ||
377 invalid_header(dd, "modulus_size", css->modulus_size,
378 KEY_SIZE / 4) ||
379 invalid_header(dd, "exponent_size", css->exponent_size,
380 EXPONENT_SIZE / 4)) {
381 return -EINVAL;
382 }
383 return 0;
384 }
385
386 /*
387 * Make sure there are at least some bytes after the prefix.
388 */
payload_check(struct hfi1_devdata * dd,const char * name,long file_size,long prefix_size)389 static int payload_check(struct hfi1_devdata *dd, const char *name,
390 long file_size, long prefix_size)
391 {
392 /* make sure we have some payload */
393 if (prefix_size >= file_size) {
394 dd_dev_err(dd,
395 "firmware \"%s\", size %ld, must be larger than %ld bytes\n",
396 name, file_size, prefix_size);
397 return -EINVAL;
398 }
399
400 return 0;
401 }
402
403 /*
404 * Request the firmware from the system. Extract the pieces and fill in
405 * fdet. If successful, the caller will need to call dispose_one_firmware().
406 * Returns 0 on success, -ERRNO on error.
407 */
obtain_one_firmware(struct hfi1_devdata * dd,const char * name,struct firmware_details * fdet)408 static int obtain_one_firmware(struct hfi1_devdata *dd, const char *name,
409 struct firmware_details *fdet)
410 {
411 struct css_header *css;
412 int ret;
413
414 memset(fdet, 0, sizeof(*fdet));
415
416 ret = request_firmware(&fdet->fw, name, &dd->pcidev->dev);
417 if (ret) {
418 dd_dev_warn(dd, "cannot find firmware \"%s\", err %d\n",
419 name, ret);
420 return ret;
421 }
422
423 /* verify the firmware */
424 if (fdet->fw->size < sizeof(struct css_header)) {
425 dd_dev_err(dd, "firmware \"%s\" is too small\n", name);
426 ret = -EINVAL;
427 goto done;
428 }
429 css = (struct css_header *)fdet->fw->data;
430
431 hfi1_cdbg(FIRMWARE, "Firmware %s details:", name);
432 hfi1_cdbg(FIRMWARE, "file size: 0x%lx bytes", fdet->fw->size);
433 hfi1_cdbg(FIRMWARE, "CSS structure:");
434 hfi1_cdbg(FIRMWARE, " module_type 0x%x", css->module_type);
435 hfi1_cdbg(FIRMWARE, " header_len 0x%03x (0x%03x bytes)",
436 css->header_len, 4 * css->header_len);
437 hfi1_cdbg(FIRMWARE, " header_version 0x%x", css->header_version);
438 hfi1_cdbg(FIRMWARE, " module_id 0x%x", css->module_id);
439 hfi1_cdbg(FIRMWARE, " module_vendor 0x%x", css->module_vendor);
440 hfi1_cdbg(FIRMWARE, " date 0x%x", css->date);
441 hfi1_cdbg(FIRMWARE, " size 0x%03x (0x%03x bytes)",
442 css->size, 4 * css->size);
443 hfi1_cdbg(FIRMWARE, " key_size 0x%03x (0x%03x bytes)",
444 css->key_size, 4 * css->key_size);
445 hfi1_cdbg(FIRMWARE, " modulus_size 0x%03x (0x%03x bytes)",
446 css->modulus_size, 4 * css->modulus_size);
447 hfi1_cdbg(FIRMWARE, " exponent_size 0x%03x (0x%03x bytes)",
448 css->exponent_size, 4 * css->exponent_size);
449 hfi1_cdbg(FIRMWARE, "firmware size: 0x%lx bytes",
450 fdet->fw->size - sizeof(struct firmware_file));
451
452 /*
453 * If the file does not have a valid CSS header, fail.
454 * Otherwise, check the CSS size field for an expected size.
455 * The augmented file has r2 and mu inserted after the header
456 * was generated, so there will be a known difference between
457 * the CSS header size and the actual file size. Use this
458 * difference to identify an augmented file.
459 *
460 * Note: css->size is in DWORDs, multiply by 4 to get bytes.
461 */
462 ret = verify_css_header(dd, css);
463 if (ret) {
464 dd_dev_info(dd, "Invalid CSS header for \"%s\"\n", name);
465 } else if ((css->size * 4) == fdet->fw->size) {
466 /* non-augmented firmware file */
467 struct firmware_file *ff = (struct firmware_file *)
468 fdet->fw->data;
469
470 /* make sure there are bytes in the payload */
471 ret = payload_check(dd, name, fdet->fw->size,
472 sizeof(struct firmware_file));
473 if (ret == 0) {
474 fdet->css_header = css;
475 fdet->modulus = ff->modulus;
476 fdet->exponent = ff->exponent;
477 fdet->signature = ff->signature;
478 fdet->r2 = fdet->dummy_header.r2; /* use dummy space */
479 fdet->mu = fdet->dummy_header.mu; /* use dummy space */
480 fdet->firmware_ptr = ff->firmware;
481 fdet->firmware_len = fdet->fw->size -
482 sizeof(struct firmware_file);
483 /*
484 * Header does not include r2 and mu - generate here.
485 * For now, fail.
486 */
487 dd_dev_err(dd, "driver is unable to validate firmware without r2 and mu (not in firmware file)\n");
488 ret = -EINVAL;
489 }
490 } else if ((css->size * 4) + AUGMENT_SIZE == fdet->fw->size) {
491 /* augmented firmware file */
492 struct augmented_firmware_file *aff =
493 (struct augmented_firmware_file *)fdet->fw->data;
494
495 /* make sure there are bytes in the payload */
496 ret = payload_check(dd, name, fdet->fw->size,
497 sizeof(struct augmented_firmware_file));
498 if (ret == 0) {
499 fdet->css_header = css;
500 fdet->modulus = aff->modulus;
501 fdet->exponent = aff->exponent;
502 fdet->signature = aff->signature;
503 fdet->r2 = aff->r2;
504 fdet->mu = aff->mu;
505 fdet->firmware_ptr = aff->firmware;
506 fdet->firmware_len = fdet->fw->size -
507 sizeof(struct augmented_firmware_file);
508 }
509 } else {
510 /* css->size check failed */
511 dd_dev_err(dd,
512 "invalid firmware header field size: expected 0x%lx or 0x%lx, actual 0x%x\n",
513 fdet->fw->size / 4,
514 (fdet->fw->size - AUGMENT_SIZE) / 4,
515 css->size);
516
517 ret = -EINVAL;
518 }
519
520 done:
521 /* if returning an error, clean up after ourselves */
522 if (ret)
523 dispose_one_firmware(fdet);
524 return ret;
525 }
526
dispose_one_firmware(struct firmware_details * fdet)527 static void dispose_one_firmware(struct firmware_details *fdet)
528 {
529 release_firmware(fdet->fw);
530 /* erase all previous information */
531 memset(fdet, 0, sizeof(*fdet));
532 }
533
534 /*
535 * Obtain the 4 firmwares from the OS. All must be obtained at once or not
536 * at all. If called with the firmware state in FW_TRY, use alternate names.
537 * On exit, this routine will have set the firmware state to one of FW_TRY,
538 * FW_FINAL, or FW_ERR.
539 *
540 * Must be holding fw_mutex.
541 */
__obtain_firmware(struct hfi1_devdata * dd)542 static void __obtain_firmware(struct hfi1_devdata *dd)
543 {
544 int err = 0;
545
546 if (fw_state == FW_FINAL) /* nothing more to obtain */
547 return;
548 if (fw_state == FW_ERR) /* already in error */
549 return;
550
551 /* fw_state is FW_EMPTY or FW_TRY */
552 retry:
553 if (fw_state == FW_TRY) {
554 /*
555 * We tried the original and it failed. Move to the
556 * alternate.
557 */
558 dd_dev_warn(dd, "using alternate firmware names\n");
559 /*
560 * Let others run. Some systems, when missing firmware, does
561 * something that holds for 30 seconds. If we do that twice
562 * in a row it triggers task blocked warning.
563 */
564 cond_resched();
565 if (fw_8051_load)
566 dispose_one_firmware(&fw_8051);
567 if (fw_fabric_serdes_load)
568 dispose_one_firmware(&fw_fabric);
569 if (fw_sbus_load)
570 dispose_one_firmware(&fw_sbus);
571 if (fw_pcie_serdes_load)
572 dispose_one_firmware(&fw_pcie);
573 fw_8051_name = ALT_FW_8051_NAME_ASIC;
574 fw_fabric_serdes_name = ALT_FW_FABRIC_NAME;
575 fw_sbus_name = ALT_FW_SBUS_NAME;
576 fw_pcie_serdes_name = ALT_FW_PCIE_NAME;
577
578 /*
579 * Add a delay before obtaining and loading debug firmware.
580 * Authorization will fail if the delay between firmware
581 * authorization events is shorter than 50us. Add 100us to
582 * make a delay time safe.
583 */
584 usleep_range(100, 120);
585 }
586
587 if (fw_sbus_load) {
588 err = obtain_one_firmware(dd, fw_sbus_name, &fw_sbus);
589 if (err)
590 goto done;
591 }
592
593 if (fw_pcie_serdes_load) {
594 err = obtain_one_firmware(dd, fw_pcie_serdes_name, &fw_pcie);
595 if (err)
596 goto done;
597 }
598
599 if (fw_fabric_serdes_load) {
600 err = obtain_one_firmware(dd, fw_fabric_serdes_name,
601 &fw_fabric);
602 if (err)
603 goto done;
604 }
605
606 if (fw_8051_load) {
607 err = obtain_one_firmware(dd, fw_8051_name, &fw_8051);
608 if (err)
609 goto done;
610 }
611
612 done:
613 if (err) {
614 /* oops, had problems obtaining a firmware */
615 if (fw_state == FW_EMPTY && dd->icode == ICODE_RTL_SILICON) {
616 /* retry with alternate (RTL only) */
617 fw_state = FW_TRY;
618 goto retry;
619 }
620 dd_dev_err(dd, "unable to obtain working firmware\n");
621 fw_state = FW_ERR;
622 fw_err = -ENOENT;
623 } else {
624 /* success */
625 if (fw_state == FW_EMPTY &&
626 dd->icode != ICODE_FUNCTIONAL_SIMULATOR)
627 fw_state = FW_TRY; /* may retry later */
628 else
629 fw_state = FW_FINAL; /* cannot try again */
630 }
631 }
632
633 /*
634 * Called by all HFIs when loading their firmware - i.e. device probe time.
635 * The first one will do the actual firmware load. Use a mutex to resolve
636 * any possible race condition.
637 *
638 * The call to this routine cannot be moved to driver load because the kernel
639 * call request_firmware() requires a device which is only available after
640 * the first device probe.
641 */
obtain_firmware(struct hfi1_devdata * dd)642 static int obtain_firmware(struct hfi1_devdata *dd)
643 {
644 unsigned long timeout;
645
646 mutex_lock(&fw_mutex);
647
648 /* 40s delay due to long delay on missing firmware on some systems */
649 timeout = jiffies + msecs_to_jiffies(40000);
650 while (fw_state == FW_TRY) {
651 /*
652 * Another device is trying the firmware. Wait until it
653 * decides what works (or not).
654 */
655 if (time_after(jiffies, timeout)) {
656 /* waited too long */
657 dd_dev_err(dd, "Timeout waiting for firmware try");
658 fw_state = FW_ERR;
659 fw_err = -ETIMEDOUT;
660 break;
661 }
662 mutex_unlock(&fw_mutex);
663 msleep(20); /* arbitrary delay */
664 mutex_lock(&fw_mutex);
665 }
666 /* not in FW_TRY state */
667
668 /* set fw_state to FW_TRY, FW_FINAL, or FW_ERR, and fw_err */
669 if (fw_state == FW_EMPTY)
670 __obtain_firmware(dd);
671
672 mutex_unlock(&fw_mutex);
673 return fw_err;
674 }
675
676 /*
677 * Called when the driver unloads. The timing is asymmetric with its
678 * counterpart, obtain_firmware(). If called at device remove time,
679 * then it is conceivable that another device could probe while the
680 * firmware is being disposed. The mutexes can be moved to do that
681 * safely, but then the firmware would be requested from the OS multiple
682 * times.
683 *
684 * No mutex is needed as the driver is unloading and there cannot be any
685 * other callers.
686 */
dispose_firmware(void)687 void dispose_firmware(void)
688 {
689 dispose_one_firmware(&fw_8051);
690 dispose_one_firmware(&fw_fabric);
691 dispose_one_firmware(&fw_pcie);
692 dispose_one_firmware(&fw_sbus);
693
694 /* retain the error state, otherwise revert to empty */
695 if (fw_state != FW_ERR)
696 fw_state = FW_EMPTY;
697 }
698
699 /*
700 * Called with the result of a firmware download.
701 *
702 * Return 1 to retry loading the firmware, 0 to stop.
703 */
retry_firmware(struct hfi1_devdata * dd,int load_result)704 static int retry_firmware(struct hfi1_devdata *dd, int load_result)
705 {
706 int retry;
707
708 mutex_lock(&fw_mutex);
709
710 if (load_result == 0) {
711 /*
712 * The load succeeded, so expect all others to do the same.
713 * Do not retry again.
714 */
715 if (fw_state == FW_TRY)
716 fw_state = FW_FINAL;
717 retry = 0; /* do NOT retry */
718 } else if (fw_state == FW_TRY) {
719 /* load failed, obtain alternate firmware */
720 __obtain_firmware(dd);
721 retry = (fw_state == FW_FINAL);
722 } else {
723 /* else in FW_FINAL or FW_ERR, no retry in either case */
724 retry = 0;
725 }
726
727 mutex_unlock(&fw_mutex);
728 return retry;
729 }
730
731 /*
732 * Write a block of data to a given array CSR. All calls will be in
733 * multiples of 8 bytes.
734 */
write_rsa_data(struct hfi1_devdata * dd,int what,const u8 * data,int nbytes)735 static void write_rsa_data(struct hfi1_devdata *dd, int what,
736 const u8 *data, int nbytes)
737 {
738 int qw_size = nbytes / 8;
739 int i;
740
741 if (((unsigned long)data & 0x7) == 0) {
742 /* aligned */
743 u64 *ptr = (u64 *)data;
744
745 for (i = 0; i < qw_size; i++, ptr++)
746 write_csr(dd, what + (8 * i), *ptr);
747 } else {
748 /* not aligned */
749 for (i = 0; i < qw_size; i++, data += 8) {
750 u64 value;
751
752 memcpy(&value, data, 8);
753 write_csr(dd, what + (8 * i), value);
754 }
755 }
756 }
757
758 /*
759 * Write a block of data to a given CSR as a stream of writes. All calls will
760 * be in multiples of 8 bytes.
761 */
write_streamed_rsa_data(struct hfi1_devdata * dd,int what,const u8 * data,int nbytes)762 static void write_streamed_rsa_data(struct hfi1_devdata *dd, int what,
763 const u8 *data, int nbytes)
764 {
765 u64 *ptr = (u64 *)data;
766 int qw_size = nbytes / 8;
767
768 for (; qw_size > 0; qw_size--, ptr++)
769 write_csr(dd, what, *ptr);
770 }
771
772 /*
773 * Download the signature and start the RSA mechanism. Wait for
774 * RSA_ENGINE_TIMEOUT before giving up.
775 */
run_rsa(struct hfi1_devdata * dd,const char * who,const u8 * signature)776 static int run_rsa(struct hfi1_devdata *dd, const char *who,
777 const u8 *signature)
778 {
779 unsigned long timeout;
780 u64 reg;
781 u32 status;
782 int ret = 0;
783
784 /* write the signature */
785 write_rsa_data(dd, MISC_CFG_RSA_SIGNATURE, signature, KEY_SIZE);
786
787 /* initialize RSA */
788 write_csr(dd, MISC_CFG_RSA_CMD, RSA_CMD_INIT);
789
790 /*
791 * Make sure the engine is idle and insert a delay between the two
792 * writes to MISC_CFG_RSA_CMD.
793 */
794 status = (read_csr(dd, MISC_CFG_FW_CTRL)
795 & MISC_CFG_FW_CTRL_RSA_STATUS_SMASK)
796 >> MISC_CFG_FW_CTRL_RSA_STATUS_SHIFT;
797 if (status != RSA_STATUS_IDLE) {
798 dd_dev_err(dd, "%s security engine not idle - giving up\n",
799 who);
800 return -EBUSY;
801 }
802
803 /* start RSA */
804 write_csr(dd, MISC_CFG_RSA_CMD, RSA_CMD_START);
805
806 /*
807 * Look for the result.
808 *
809 * The RSA engine is hooked up to two MISC errors. The driver
810 * masks these errors as they do not respond to the standard
811 * error "clear down" mechanism. Look for these errors here and
812 * clear them when possible. This routine will exit with the
813 * errors of the current run still set.
814 *
815 * MISC_FW_AUTH_FAILED_ERR
816 * Firmware authorization failed. This can be cleared by
817 * re-initializing the RSA engine, then clearing the status bit.
818 * Do not re-init the RSA angine immediately after a successful
819 * run - this will reset the current authorization.
820 *
821 * MISC_KEY_MISMATCH_ERR
822 * Key does not match. The only way to clear this is to load
823 * a matching key then clear the status bit. If this error
824 * is raised, it will persist outside of this routine until a
825 * matching key is loaded.
826 */
827 timeout = msecs_to_jiffies(RSA_ENGINE_TIMEOUT) + jiffies;
828 while (1) {
829 status = (read_csr(dd, MISC_CFG_FW_CTRL)
830 & MISC_CFG_FW_CTRL_RSA_STATUS_SMASK)
831 >> MISC_CFG_FW_CTRL_RSA_STATUS_SHIFT;
832
833 if (status == RSA_STATUS_IDLE) {
834 /* should not happen */
835 dd_dev_err(dd, "%s firmware security bad idle state\n",
836 who);
837 ret = -EINVAL;
838 break;
839 } else if (status == RSA_STATUS_DONE) {
840 /* finished successfully */
841 break;
842 } else if (status == RSA_STATUS_FAILED) {
843 /* finished unsuccessfully */
844 ret = -EINVAL;
845 break;
846 }
847 /* else still active */
848
849 if (time_after(jiffies, timeout)) {
850 /*
851 * Timed out while active. We can't reset the engine
852 * if it is stuck active, but run through the
853 * error code to see what error bits are set.
854 */
855 dd_dev_err(dd, "%s firmware security time out\n", who);
856 ret = -ETIMEDOUT;
857 break;
858 }
859
860 msleep(20);
861 }
862
863 /*
864 * Arrive here on success or failure. Clear all RSA engine
865 * errors. All current errors will stick - the RSA logic is keeping
866 * error high. All previous errors will clear - the RSA logic
867 * is not keeping the error high.
868 */
869 write_csr(dd, MISC_ERR_CLEAR,
870 MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK |
871 MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK);
872 /*
873 * All that is left are the current errors. Print warnings on
874 * authorization failure details, if any. Firmware authorization
875 * can be retried, so these are only warnings.
876 */
877 reg = read_csr(dd, MISC_ERR_STATUS);
878 if (ret) {
879 if (reg & MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK)
880 dd_dev_warn(dd, "%s firmware authorization failed\n",
881 who);
882 if (reg & MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK)
883 dd_dev_warn(dd, "%s firmware key mismatch\n", who);
884 }
885
886 return ret;
887 }
888
load_security_variables(struct hfi1_devdata * dd,struct firmware_details * fdet)889 static void load_security_variables(struct hfi1_devdata *dd,
890 struct firmware_details *fdet)
891 {
892 /* Security variables a. Write the modulus */
893 write_rsa_data(dd, MISC_CFG_RSA_MODULUS, fdet->modulus, KEY_SIZE);
894 /* Security variables b. Write the r2 */
895 write_rsa_data(dd, MISC_CFG_RSA_R2, fdet->r2, KEY_SIZE);
896 /* Security variables c. Write the mu */
897 write_rsa_data(dd, MISC_CFG_RSA_MU, fdet->mu, MU_SIZE);
898 /* Security variables d. Write the header */
899 write_streamed_rsa_data(dd, MISC_CFG_SHA_PRELOAD,
900 (u8 *)fdet->css_header,
901 sizeof(struct css_header));
902 }
903
904 /* return the 8051 firmware state */
get_firmware_state(struct hfi1_devdata * dd)905 static inline u32 get_firmware_state(struct hfi1_devdata *dd)
906 {
907 u64 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE);
908
909 return (reg >> DC_DC8051_STS_CUR_STATE_FIRMWARE_SHIFT)
910 & DC_DC8051_STS_CUR_STATE_FIRMWARE_MASK;
911 }
912
913 /*
914 * Wait until the firmware is up and ready to take host requests.
915 * Return 0 on success, -ETIMEDOUT on timeout.
916 */
wait_fm_ready(struct hfi1_devdata * dd,u32 mstimeout)917 int wait_fm_ready(struct hfi1_devdata *dd, u32 mstimeout)
918 {
919 unsigned long timeout;
920
921 /* in the simulator, the fake 8051 is always ready */
922 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
923 return 0;
924
925 timeout = msecs_to_jiffies(mstimeout) + jiffies;
926 while (1) {
927 if (get_firmware_state(dd) == 0xa0) /* ready */
928 return 0;
929 if (time_after(jiffies, timeout)) /* timed out */
930 return -ETIMEDOUT;
931 usleep_range(1950, 2050); /* sleep 2ms-ish */
932 }
933 }
934
935 /*
936 * Load the 8051 firmware.
937 */
load_8051_firmware(struct hfi1_devdata * dd,struct firmware_details * fdet)938 static int load_8051_firmware(struct hfi1_devdata *dd,
939 struct firmware_details *fdet)
940 {
941 u64 reg;
942 int ret;
943 u8 ver_major;
944 u8 ver_minor;
945 u8 ver_patch;
946
947 /*
948 * DC Reset sequence
949 * Load DC 8051 firmware
950 */
951 /*
952 * DC reset step 1: Reset DC8051
953 */
954 reg = DC_DC8051_CFG_RST_M8051W_SMASK
955 | DC_DC8051_CFG_RST_CRAM_SMASK
956 | DC_DC8051_CFG_RST_DRAM_SMASK
957 | DC_DC8051_CFG_RST_IRAM_SMASK
958 | DC_DC8051_CFG_RST_SFR_SMASK;
959 write_csr(dd, DC_DC8051_CFG_RST, reg);
960
961 /*
962 * DC reset step 2 (optional): Load 8051 data memory with link
963 * configuration
964 */
965
966 /*
967 * DC reset step 3: Load DC8051 firmware
968 */
969 /* release all but the core reset */
970 reg = DC_DC8051_CFG_RST_M8051W_SMASK;
971 write_csr(dd, DC_DC8051_CFG_RST, reg);
972
973 /* Firmware load step 1 */
974 load_security_variables(dd, fdet);
975
976 /*
977 * Firmware load step 2. Clear MISC_CFG_FW_CTRL.FW_8051_LOADED
978 */
979 write_csr(dd, MISC_CFG_FW_CTRL, 0);
980
981 /* Firmware load steps 3-5 */
982 ret = write_8051(dd, 1/*code*/, 0, fdet->firmware_ptr,
983 fdet->firmware_len);
984 if (ret)
985 return ret;
986
987 /*
988 * DC reset step 4. Host starts the DC8051 firmware
989 */
990 /*
991 * Firmware load step 6. Set MISC_CFG_FW_CTRL.FW_8051_LOADED
992 */
993 write_csr(dd, MISC_CFG_FW_CTRL, MISC_CFG_FW_CTRL_FW_8051_LOADED_SMASK);
994
995 /* Firmware load steps 7-10 */
996 ret = run_rsa(dd, "8051", fdet->signature);
997 if (ret)
998 return ret;
999
1000 /* clear all reset bits, releasing the 8051 */
1001 write_csr(dd, DC_DC8051_CFG_RST, 0ull);
1002
1003 /*
1004 * DC reset step 5. Wait for firmware to be ready to accept host
1005 * requests.
1006 */
1007 ret = wait_fm_ready(dd, TIMEOUT_8051_START);
1008 if (ret) { /* timed out */
1009 dd_dev_err(dd, "8051 start timeout, current state 0x%x\n",
1010 get_firmware_state(dd));
1011 return -ETIMEDOUT;
1012 }
1013
1014 read_misc_status(dd, &ver_major, &ver_minor, &ver_patch);
1015 dd_dev_info(dd, "8051 firmware version %d.%d.%d\n",
1016 (int)ver_major, (int)ver_minor, (int)ver_patch);
1017 dd->dc8051_ver = dc8051_ver(ver_major, ver_minor, ver_patch);
1018 ret = write_host_interface_version(dd, HOST_INTERFACE_VERSION);
1019 if (ret != HCMD_SUCCESS) {
1020 dd_dev_err(dd,
1021 "Failed to set host interface version, return 0x%x\n",
1022 ret);
1023 return -EIO;
1024 }
1025
1026 return 0;
1027 }
1028
1029 /*
1030 * Write the SBus request register
1031 *
1032 * No need for masking - the arguments are sized exactly.
1033 */
sbus_request(struct hfi1_devdata * dd,u8 receiver_addr,u8 data_addr,u8 command,u32 data_in)1034 void sbus_request(struct hfi1_devdata *dd,
1035 u8 receiver_addr, u8 data_addr, u8 command, u32 data_in)
1036 {
1037 write_csr(dd, ASIC_CFG_SBUS_REQUEST,
1038 ((u64)data_in << ASIC_CFG_SBUS_REQUEST_DATA_IN_SHIFT) |
1039 ((u64)command << ASIC_CFG_SBUS_REQUEST_COMMAND_SHIFT) |
1040 ((u64)data_addr << ASIC_CFG_SBUS_REQUEST_DATA_ADDR_SHIFT) |
1041 ((u64)receiver_addr <<
1042 ASIC_CFG_SBUS_REQUEST_RECEIVER_ADDR_SHIFT));
1043 }
1044
1045 /*
1046 * Read a value from the SBus.
1047 *
1048 * Requires the caller to be in fast mode
1049 */
sbus_read(struct hfi1_devdata * dd,u8 receiver_addr,u8 data_addr,u32 data_in)1050 static u32 sbus_read(struct hfi1_devdata *dd, u8 receiver_addr, u8 data_addr,
1051 u32 data_in)
1052 {
1053 u64 reg;
1054 int retries;
1055 int success = 0;
1056 u32 result = 0;
1057 u32 result_code = 0;
1058
1059 sbus_request(dd, receiver_addr, data_addr, READ_SBUS_RECEIVER, data_in);
1060
1061 for (retries = 0; retries < 100; retries++) {
1062 usleep_range(1000, 1200); /* arbitrary */
1063 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1064 result_code = (reg >> ASIC_STS_SBUS_RESULT_RESULT_CODE_SHIFT)
1065 & ASIC_STS_SBUS_RESULT_RESULT_CODE_MASK;
1066 if (result_code != SBUS_READ_COMPLETE)
1067 continue;
1068
1069 success = 1;
1070 result = (reg >> ASIC_STS_SBUS_RESULT_DATA_OUT_SHIFT)
1071 & ASIC_STS_SBUS_RESULT_DATA_OUT_MASK;
1072 break;
1073 }
1074
1075 if (!success) {
1076 dd_dev_err(dd, "%s: read failed, result code 0x%x\n", __func__,
1077 result_code);
1078 }
1079
1080 return result;
1081 }
1082
1083 /*
1084 * Turn off the SBus and fabric serdes spicos.
1085 *
1086 * + Must be called with Sbus fast mode turned on.
1087 * + Must be called after fabric serdes broadcast is set up.
1088 * + Must be called before the 8051 is loaded - assumes 8051 is not loaded
1089 * when using MISC_CFG_FW_CTRL.
1090 */
turn_off_spicos(struct hfi1_devdata * dd,int flags)1091 static void turn_off_spicos(struct hfi1_devdata *dd, int flags)
1092 {
1093 /* only needed on A0 */
1094 if (!is_ax(dd))
1095 return;
1096
1097 dd_dev_info(dd, "Turning off spicos:%s%s\n",
1098 flags & SPICO_SBUS ? " SBus" : "",
1099 flags & SPICO_FABRIC ? " fabric" : "");
1100
1101 write_csr(dd, MISC_CFG_FW_CTRL, ENABLE_SPICO_SMASK);
1102 /* disable SBus spico */
1103 if (flags & SPICO_SBUS)
1104 sbus_request(dd, SBUS_MASTER_BROADCAST, 0x01,
1105 WRITE_SBUS_RECEIVER, 0x00000040);
1106
1107 /* disable the fabric serdes spicos */
1108 if (flags & SPICO_FABRIC)
1109 sbus_request(dd, fabric_serdes_broadcast[dd->hfi1_id],
1110 0x07, WRITE_SBUS_RECEIVER, 0x00000000);
1111 write_csr(dd, MISC_CFG_FW_CTRL, 0);
1112 }
1113
1114 /*
1115 * Reset all of the fabric serdes for this HFI in preparation to take the
1116 * link to Polling.
1117 *
1118 * To do a reset, we need to write to to the serdes registers. Unfortunately,
1119 * the fabric serdes download to the other HFI on the ASIC will have turned
1120 * off the firmware validation on this HFI. This means we can't write to the
1121 * registers to reset the serdes. Work around this by performing a complete
1122 * re-download and validation of the fabric serdes firmware. This, as a
1123 * by-product, will reset the serdes. NOTE: the re-download requires that
1124 * the 8051 be in the Offline state. I.e. not actively trying to use the
1125 * serdes. This routine is called at the point where the link is Offline and
1126 * is getting ready to go to Polling.
1127 */
fabric_serdes_reset(struct hfi1_devdata * dd)1128 void fabric_serdes_reset(struct hfi1_devdata *dd)
1129 {
1130 int ret;
1131
1132 if (!fw_fabric_serdes_load)
1133 return;
1134
1135 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
1136 if (ret) {
1137 dd_dev_err(dd,
1138 "Cannot acquire SBus resource to reset fabric SerDes - perhaps you should reboot\n");
1139 return;
1140 }
1141 set_sbus_fast_mode(dd);
1142
1143 if (is_ax(dd)) {
1144 /* A0 serdes do not work with a re-download */
1145 u8 ra = fabric_serdes_broadcast[dd->hfi1_id];
1146
1147 /* place SerDes in reset and disable SPICO */
1148 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000011);
1149 /* wait 100 refclk cycles @ 156.25MHz => 640ns */
1150 udelay(1);
1151 /* remove SerDes reset */
1152 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000010);
1153 /* turn SPICO enable on */
1154 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000002);
1155 } else {
1156 turn_off_spicos(dd, SPICO_FABRIC);
1157 /*
1158 * No need for firmware retry - what to download has already
1159 * been decided.
1160 * No need to pay attention to the load return - the only
1161 * failure is a validation failure, which has already been
1162 * checked by the initial download.
1163 */
1164 (void)load_fabric_serdes_firmware(dd, &fw_fabric);
1165 }
1166
1167 clear_sbus_fast_mode(dd);
1168 release_chip_resource(dd, CR_SBUS);
1169 }
1170
1171 /* Access to the SBus in this routine should probably be serialized */
sbus_request_slow(struct hfi1_devdata * dd,u8 receiver_addr,u8 data_addr,u8 command,u32 data_in)1172 int sbus_request_slow(struct hfi1_devdata *dd,
1173 u8 receiver_addr, u8 data_addr, u8 command, u32 data_in)
1174 {
1175 u64 reg, count = 0;
1176
1177 /* make sure fast mode is clear */
1178 clear_sbus_fast_mode(dd);
1179
1180 sbus_request(dd, receiver_addr, data_addr, command, data_in);
1181 write_csr(dd, ASIC_CFG_SBUS_EXECUTE,
1182 ASIC_CFG_SBUS_EXECUTE_EXECUTE_SMASK);
1183 /* Wait for both DONE and RCV_DATA_VALID to go high */
1184 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1185 while (!((reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) &&
1186 (reg & ASIC_STS_SBUS_RESULT_RCV_DATA_VALID_SMASK))) {
1187 if (count++ >= SBUS_MAX_POLL_COUNT) {
1188 u64 counts = read_csr(dd, ASIC_STS_SBUS_COUNTERS);
1189 /*
1190 * If the loop has timed out, we are OK if DONE bit
1191 * is set and RCV_DATA_VALID and EXECUTE counters
1192 * are the same. If not, we cannot proceed.
1193 */
1194 if ((reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) &&
1195 (SBUS_COUNTER(counts, RCV_DATA_VALID) ==
1196 SBUS_COUNTER(counts, EXECUTE)))
1197 break;
1198 return -ETIMEDOUT;
1199 }
1200 udelay(1);
1201 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1202 }
1203 count = 0;
1204 write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 0);
1205 /* Wait for DONE to clear after EXECUTE is cleared */
1206 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1207 while (reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) {
1208 if (count++ >= SBUS_MAX_POLL_COUNT)
1209 return -ETIME;
1210 udelay(1);
1211 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1212 }
1213 return 0;
1214 }
1215
load_fabric_serdes_firmware(struct hfi1_devdata * dd,struct firmware_details * fdet)1216 static int load_fabric_serdes_firmware(struct hfi1_devdata *dd,
1217 struct firmware_details *fdet)
1218 {
1219 int i, err;
1220 const u8 ra = fabric_serdes_broadcast[dd->hfi1_id]; /* receiver addr */
1221
1222 dd_dev_info(dd, "Downloading fabric firmware\n");
1223
1224 /* step 1: load security variables */
1225 load_security_variables(dd, fdet);
1226 /* step 2: place SerDes in reset and disable SPICO */
1227 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000011);
1228 /* wait 100 refclk cycles @ 156.25MHz => 640ns */
1229 udelay(1);
1230 /* step 3: remove SerDes reset */
1231 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000010);
1232 /* step 4: assert IMEM override */
1233 sbus_request(dd, ra, 0x00, WRITE_SBUS_RECEIVER, 0x40000000);
1234 /* step 5: download SerDes machine code */
1235 for (i = 0; i < fdet->firmware_len; i += 4) {
1236 sbus_request(dd, ra, 0x0a, WRITE_SBUS_RECEIVER,
1237 *(u32 *)&fdet->firmware_ptr[i]);
1238 }
1239 /* step 6: IMEM override off */
1240 sbus_request(dd, ra, 0x00, WRITE_SBUS_RECEIVER, 0x00000000);
1241 /* step 7: turn ECC on */
1242 sbus_request(dd, ra, 0x0b, WRITE_SBUS_RECEIVER, 0x000c0000);
1243
1244 /* steps 8-11: run the RSA engine */
1245 err = run_rsa(dd, "fabric serdes", fdet->signature);
1246 if (err)
1247 return err;
1248
1249 /* step 12: turn SPICO enable on */
1250 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000002);
1251 /* step 13: enable core hardware interrupts */
1252 sbus_request(dd, ra, 0x08, WRITE_SBUS_RECEIVER, 0x00000000);
1253
1254 return 0;
1255 }
1256
load_sbus_firmware(struct hfi1_devdata * dd,struct firmware_details * fdet)1257 static int load_sbus_firmware(struct hfi1_devdata *dd,
1258 struct firmware_details *fdet)
1259 {
1260 int i, err;
1261 const u8 ra = SBUS_MASTER_BROADCAST; /* receiver address */
1262
1263 dd_dev_info(dd, "Downloading SBus firmware\n");
1264
1265 /* step 1: load security variables */
1266 load_security_variables(dd, fdet);
1267 /* step 2: place SPICO into reset and enable off */
1268 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x000000c0);
1269 /* step 3: remove reset, enable off, IMEM_CNTRL_EN on */
1270 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000240);
1271 /* step 4: set starting IMEM address for burst download */
1272 sbus_request(dd, ra, 0x03, WRITE_SBUS_RECEIVER, 0x80000000);
1273 /* step 5: download the SBus Master machine code */
1274 for (i = 0; i < fdet->firmware_len; i += 4) {
1275 sbus_request(dd, ra, 0x14, WRITE_SBUS_RECEIVER,
1276 *(u32 *)&fdet->firmware_ptr[i]);
1277 }
1278 /* step 6: set IMEM_CNTL_EN off */
1279 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000040);
1280 /* step 7: turn ECC on */
1281 sbus_request(dd, ra, 0x16, WRITE_SBUS_RECEIVER, 0x000c0000);
1282
1283 /* steps 8-11: run the RSA engine */
1284 err = run_rsa(dd, "SBus", fdet->signature);
1285 if (err)
1286 return err;
1287
1288 /* step 12: set SPICO_ENABLE on */
1289 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000140);
1290
1291 return 0;
1292 }
1293
load_pcie_serdes_firmware(struct hfi1_devdata * dd,struct firmware_details * fdet)1294 static int load_pcie_serdes_firmware(struct hfi1_devdata *dd,
1295 struct firmware_details *fdet)
1296 {
1297 int i;
1298 const u8 ra = SBUS_MASTER_BROADCAST; /* receiver address */
1299
1300 dd_dev_info(dd, "Downloading PCIe firmware\n");
1301
1302 /* step 1: load security variables */
1303 load_security_variables(dd, fdet);
1304 /* step 2: assert single step (halts the SBus Master spico) */
1305 sbus_request(dd, ra, 0x05, WRITE_SBUS_RECEIVER, 0x00000001);
1306 /* step 3: enable XDMEM access */
1307 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000d40);
1308 /* step 4: load firmware into SBus Master XDMEM */
1309 /*
1310 * NOTE: the dmem address, write_en, and wdata are all pre-packed,
1311 * we only need to pick up the bytes and write them
1312 */
1313 for (i = 0; i < fdet->firmware_len; i += 4) {
1314 sbus_request(dd, ra, 0x04, WRITE_SBUS_RECEIVER,
1315 *(u32 *)&fdet->firmware_ptr[i]);
1316 }
1317 /* step 5: disable XDMEM access */
1318 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000140);
1319 /* step 6: allow SBus Spico to run */
1320 sbus_request(dd, ra, 0x05, WRITE_SBUS_RECEIVER, 0x00000000);
1321
1322 /*
1323 * steps 7-11: run RSA, if it succeeds, firmware is available to
1324 * be swapped
1325 */
1326 return run_rsa(dd, "PCIe serdes", fdet->signature);
1327 }
1328
1329 /*
1330 * Set the given broadcast values on the given list of devices.
1331 */
set_serdes_broadcast(struct hfi1_devdata * dd,u8 bg1,u8 bg2,const u8 * addrs,int count)1332 static void set_serdes_broadcast(struct hfi1_devdata *dd, u8 bg1, u8 bg2,
1333 const u8 *addrs, int count)
1334 {
1335 while (--count >= 0) {
1336 /*
1337 * Set BROADCAST_GROUP_1 and BROADCAST_GROUP_2, leave
1338 * defaults for everything else. Do not read-modify-write,
1339 * per instruction from the manufacturer.
1340 *
1341 * Register 0xfd:
1342 * bits what
1343 * ----- ---------------------------------
1344 * 0 IGNORE_BROADCAST (default 0)
1345 * 11:4 BROADCAST_GROUP_1 (default 0xff)
1346 * 23:16 BROADCAST_GROUP_2 (default 0xff)
1347 */
1348 sbus_request(dd, addrs[count], 0xfd, WRITE_SBUS_RECEIVER,
1349 (u32)bg1 << 4 | (u32)bg2 << 16);
1350 }
1351 }
1352
acquire_hw_mutex(struct hfi1_devdata * dd)1353 int acquire_hw_mutex(struct hfi1_devdata *dd)
1354 {
1355 unsigned long timeout;
1356 int try = 0;
1357 u8 mask = 1 << dd->hfi1_id;
1358 u8 user = (u8)read_csr(dd, ASIC_CFG_MUTEX);
1359
1360 if (user == mask) {
1361 dd_dev_info(dd,
1362 "Hardware mutex already acquired, mutex mask %u\n",
1363 (u32)mask);
1364 return 0;
1365 }
1366
1367 retry:
1368 timeout = msecs_to_jiffies(HM_TIMEOUT) + jiffies;
1369 while (1) {
1370 write_csr(dd, ASIC_CFG_MUTEX, mask);
1371 user = (u8)read_csr(dd, ASIC_CFG_MUTEX);
1372 if (user == mask)
1373 return 0; /* success */
1374 if (time_after(jiffies, timeout))
1375 break; /* timed out */
1376 msleep(20);
1377 }
1378
1379 /* timed out */
1380 dd_dev_err(dd,
1381 "Unable to acquire hardware mutex, mutex mask %u, my mask %u (%s)\n",
1382 (u32)user, (u32)mask, (try == 0) ? "retrying" : "giving up");
1383
1384 if (try == 0) {
1385 /* break mutex and retry */
1386 write_csr(dd, ASIC_CFG_MUTEX, 0);
1387 try++;
1388 goto retry;
1389 }
1390
1391 return -EBUSY;
1392 }
1393
release_hw_mutex(struct hfi1_devdata * dd)1394 void release_hw_mutex(struct hfi1_devdata *dd)
1395 {
1396 u8 mask = 1 << dd->hfi1_id;
1397 u8 user = (u8)read_csr(dd, ASIC_CFG_MUTEX);
1398
1399 if (user != mask)
1400 dd_dev_warn(dd,
1401 "Unable to release hardware mutex, mutex mask %u, my mask %u\n",
1402 (u32)user, (u32)mask);
1403 else
1404 write_csr(dd, ASIC_CFG_MUTEX, 0);
1405 }
1406
1407 /* return the given resource bit(s) as a mask for the given HFI */
resource_mask(u32 hfi1_id,u32 resource)1408 static inline u64 resource_mask(u32 hfi1_id, u32 resource)
1409 {
1410 return ((u64)resource) << (hfi1_id ? CR_DYN_SHIFT : 0);
1411 }
1412
fail_mutex_acquire_message(struct hfi1_devdata * dd,const char * func)1413 static void fail_mutex_acquire_message(struct hfi1_devdata *dd,
1414 const char *func)
1415 {
1416 dd_dev_err(dd,
1417 "%s: hardware mutex stuck - suggest rebooting the machine\n",
1418 func);
1419 }
1420
1421 /*
1422 * Acquire access to a chip resource.
1423 *
1424 * Return 0 on success, -EBUSY if resource busy, -EIO if mutex acquire failed.
1425 */
__acquire_chip_resource(struct hfi1_devdata * dd,u32 resource)1426 static int __acquire_chip_resource(struct hfi1_devdata *dd, u32 resource)
1427 {
1428 u64 scratch0, all_bits, my_bit;
1429 int ret;
1430
1431 if (resource & CR_DYN_MASK) {
1432 /* a dynamic resource is in use if either HFI has set the bit */
1433 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0 &&
1434 (resource & (CR_I2C1 | CR_I2C2))) {
1435 /* discrete devices must serialize across both chains */
1436 all_bits = resource_mask(0, CR_I2C1 | CR_I2C2) |
1437 resource_mask(1, CR_I2C1 | CR_I2C2);
1438 } else {
1439 all_bits = resource_mask(0, resource) |
1440 resource_mask(1, resource);
1441 }
1442 my_bit = resource_mask(dd->hfi1_id, resource);
1443 } else {
1444 /* non-dynamic resources are not split between HFIs */
1445 all_bits = resource;
1446 my_bit = resource;
1447 }
1448
1449 /* lock against other callers within the driver wanting a resource */
1450 mutex_lock(&dd->asic_data->asic_resource_mutex);
1451
1452 ret = acquire_hw_mutex(dd);
1453 if (ret) {
1454 fail_mutex_acquire_message(dd, __func__);
1455 ret = -EIO;
1456 goto done;
1457 }
1458
1459 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
1460 if (scratch0 & all_bits) {
1461 ret = -EBUSY;
1462 } else {
1463 write_csr(dd, ASIC_CFG_SCRATCH, scratch0 | my_bit);
1464 /* force write to be visible to other HFI on another OS */
1465 (void)read_csr(dd, ASIC_CFG_SCRATCH);
1466 }
1467
1468 release_hw_mutex(dd);
1469
1470 done:
1471 mutex_unlock(&dd->asic_data->asic_resource_mutex);
1472 return ret;
1473 }
1474
1475 /*
1476 * Acquire access to a chip resource, wait up to mswait milliseconds for
1477 * the resource to become available.
1478 *
1479 * Return 0 on success, -EBUSY if busy (even after wait), -EIO if mutex
1480 * acquire failed.
1481 */
acquire_chip_resource(struct hfi1_devdata * dd,u32 resource,u32 mswait)1482 int acquire_chip_resource(struct hfi1_devdata *dd, u32 resource, u32 mswait)
1483 {
1484 unsigned long timeout;
1485 int ret;
1486
1487 timeout = jiffies + msecs_to_jiffies(mswait);
1488 while (1) {
1489 ret = __acquire_chip_resource(dd, resource);
1490 if (ret != -EBUSY)
1491 return ret;
1492 /* resource is busy, check our timeout */
1493 if (time_after_eq(jiffies, timeout))
1494 return -EBUSY;
1495 usleep_range(80, 120); /* arbitrary delay */
1496 }
1497 }
1498
1499 /*
1500 * Release access to a chip resource
1501 */
release_chip_resource(struct hfi1_devdata * dd,u32 resource)1502 void release_chip_resource(struct hfi1_devdata *dd, u32 resource)
1503 {
1504 u64 scratch0, bit;
1505
1506 /* only dynamic resources should ever be cleared */
1507 if (!(resource & CR_DYN_MASK)) {
1508 dd_dev_err(dd, "%s: invalid resource 0x%x\n", __func__,
1509 resource);
1510 return;
1511 }
1512 bit = resource_mask(dd->hfi1_id, resource);
1513
1514 /* lock against other callers within the driver wanting a resource */
1515 mutex_lock(&dd->asic_data->asic_resource_mutex);
1516
1517 if (acquire_hw_mutex(dd)) {
1518 fail_mutex_acquire_message(dd, __func__);
1519 goto done;
1520 }
1521
1522 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
1523 if ((scratch0 & bit) != 0) {
1524 scratch0 &= ~bit;
1525 write_csr(dd, ASIC_CFG_SCRATCH, scratch0);
1526 /* force write to be visible to other HFI on another OS */
1527 (void)read_csr(dd, ASIC_CFG_SCRATCH);
1528 } else {
1529 dd_dev_warn(dd, "%s: id %d, resource 0x%x: bit not set\n",
1530 __func__, dd->hfi1_id, resource);
1531 }
1532
1533 release_hw_mutex(dd);
1534
1535 done:
1536 mutex_unlock(&dd->asic_data->asic_resource_mutex);
1537 }
1538
1539 /*
1540 * Return true if resource is set, false otherwise. Print a warning
1541 * if not set and a function is supplied.
1542 */
check_chip_resource(struct hfi1_devdata * dd,u32 resource,const char * func)1543 bool check_chip_resource(struct hfi1_devdata *dd, u32 resource,
1544 const char *func)
1545 {
1546 u64 scratch0, bit;
1547
1548 if (resource & CR_DYN_MASK)
1549 bit = resource_mask(dd->hfi1_id, resource);
1550 else
1551 bit = resource;
1552
1553 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
1554 if ((scratch0 & bit) == 0) {
1555 if (func)
1556 dd_dev_warn(dd,
1557 "%s: id %d, resource 0x%x, not acquired!\n",
1558 func, dd->hfi1_id, resource);
1559 return false;
1560 }
1561 return true;
1562 }
1563
clear_chip_resources(struct hfi1_devdata * dd,const char * func)1564 static void clear_chip_resources(struct hfi1_devdata *dd, const char *func)
1565 {
1566 u64 scratch0;
1567
1568 /* lock against other callers within the driver wanting a resource */
1569 mutex_lock(&dd->asic_data->asic_resource_mutex);
1570
1571 if (acquire_hw_mutex(dd)) {
1572 fail_mutex_acquire_message(dd, func);
1573 goto done;
1574 }
1575
1576 /* clear all dynamic access bits for this HFI */
1577 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
1578 scratch0 &= ~resource_mask(dd->hfi1_id, CR_DYN_MASK);
1579 write_csr(dd, ASIC_CFG_SCRATCH, scratch0);
1580 /* force write to be visible to other HFI on another OS */
1581 (void)read_csr(dd, ASIC_CFG_SCRATCH);
1582
1583 release_hw_mutex(dd);
1584
1585 done:
1586 mutex_unlock(&dd->asic_data->asic_resource_mutex);
1587 }
1588
init_chip_resources(struct hfi1_devdata * dd)1589 void init_chip_resources(struct hfi1_devdata *dd)
1590 {
1591 /* clear any holds left by us */
1592 clear_chip_resources(dd, __func__);
1593 }
1594
finish_chip_resources(struct hfi1_devdata * dd)1595 void finish_chip_resources(struct hfi1_devdata *dd)
1596 {
1597 /* clear any holds left by us */
1598 clear_chip_resources(dd, __func__);
1599 }
1600
set_sbus_fast_mode(struct hfi1_devdata * dd)1601 void set_sbus_fast_mode(struct hfi1_devdata *dd)
1602 {
1603 write_csr(dd, ASIC_CFG_SBUS_EXECUTE,
1604 ASIC_CFG_SBUS_EXECUTE_FAST_MODE_SMASK);
1605 }
1606
clear_sbus_fast_mode(struct hfi1_devdata * dd)1607 void clear_sbus_fast_mode(struct hfi1_devdata *dd)
1608 {
1609 u64 reg, count = 0;
1610
1611 reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS);
1612 while (SBUS_COUNTER(reg, EXECUTE) !=
1613 SBUS_COUNTER(reg, RCV_DATA_VALID)) {
1614 if (count++ >= SBUS_MAX_POLL_COUNT)
1615 break;
1616 udelay(1);
1617 reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS);
1618 }
1619 write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 0);
1620 }
1621
load_firmware(struct hfi1_devdata * dd)1622 int load_firmware(struct hfi1_devdata *dd)
1623 {
1624 int ret;
1625
1626 if (fw_fabric_serdes_load) {
1627 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
1628 if (ret)
1629 return ret;
1630
1631 set_sbus_fast_mode(dd);
1632
1633 set_serdes_broadcast(dd, all_fabric_serdes_broadcast,
1634 fabric_serdes_broadcast[dd->hfi1_id],
1635 fabric_serdes_addrs[dd->hfi1_id],
1636 NUM_FABRIC_SERDES);
1637 turn_off_spicos(dd, SPICO_FABRIC);
1638 do {
1639 ret = load_fabric_serdes_firmware(dd, &fw_fabric);
1640 } while (retry_firmware(dd, ret));
1641
1642 clear_sbus_fast_mode(dd);
1643 release_chip_resource(dd, CR_SBUS);
1644 if (ret)
1645 return ret;
1646 }
1647
1648 if (fw_8051_load) {
1649 do {
1650 ret = load_8051_firmware(dd, &fw_8051);
1651 } while (retry_firmware(dd, ret));
1652 if (ret)
1653 return ret;
1654 }
1655
1656 dump_fw_version(dd);
1657 return 0;
1658 }
1659
hfi1_firmware_init(struct hfi1_devdata * dd)1660 int hfi1_firmware_init(struct hfi1_devdata *dd)
1661 {
1662 /* only RTL can use these */
1663 if (dd->icode != ICODE_RTL_SILICON) {
1664 fw_fabric_serdes_load = 0;
1665 fw_pcie_serdes_load = 0;
1666 fw_sbus_load = 0;
1667 }
1668
1669 /* no 8051 or QSFP on simulator */
1670 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
1671 fw_8051_load = 0;
1672
1673 if (!fw_8051_name) {
1674 if (dd->icode == ICODE_RTL_SILICON)
1675 fw_8051_name = DEFAULT_FW_8051_NAME_ASIC;
1676 else
1677 fw_8051_name = DEFAULT_FW_8051_NAME_FPGA;
1678 }
1679 if (!fw_fabric_serdes_name)
1680 fw_fabric_serdes_name = DEFAULT_FW_FABRIC_NAME;
1681 if (!fw_sbus_name)
1682 fw_sbus_name = DEFAULT_FW_SBUS_NAME;
1683 if (!fw_pcie_serdes_name)
1684 fw_pcie_serdes_name = DEFAULT_FW_PCIE_NAME;
1685
1686 return obtain_firmware(dd);
1687 }
1688
1689 /*
1690 * This function is a helper function for parse_platform_config(...) and
1691 * does not check for validity of the platform configuration cache
1692 * (because we know it is invalid as we are building up the cache).
1693 * As such, this should not be called from anywhere other than
1694 * parse_platform_config
1695 */
check_meta_version(struct hfi1_devdata * dd,u32 * system_table)1696 static int check_meta_version(struct hfi1_devdata *dd, u32 *system_table)
1697 {
1698 u32 meta_ver, meta_ver_meta, ver_start, ver_len, mask;
1699 struct platform_config_cache *pcfgcache = &dd->pcfg_cache;
1700
1701 if (!system_table)
1702 return -EINVAL;
1703
1704 meta_ver_meta =
1705 *(pcfgcache->config_tables[PLATFORM_CONFIG_SYSTEM_TABLE].table_metadata
1706 + SYSTEM_TABLE_META_VERSION);
1707
1708 mask = ((1 << METADATA_TABLE_FIELD_START_LEN_BITS) - 1);
1709 ver_start = meta_ver_meta & mask;
1710
1711 meta_ver_meta >>= METADATA_TABLE_FIELD_LEN_SHIFT;
1712
1713 mask = ((1 << METADATA_TABLE_FIELD_LEN_LEN_BITS) - 1);
1714 ver_len = meta_ver_meta & mask;
1715
1716 ver_start /= 8;
1717 meta_ver = *((u8 *)system_table + ver_start) & ((1 << ver_len) - 1);
1718
1719 if (meta_ver < 4) {
1720 dd_dev_info(
1721 dd, "%s:Please update platform config\n", __func__);
1722 return -EINVAL;
1723 }
1724 return 0;
1725 }
1726
parse_platform_config(struct hfi1_devdata * dd)1727 int parse_platform_config(struct hfi1_devdata *dd)
1728 {
1729 struct platform_config_cache *pcfgcache = &dd->pcfg_cache;
1730 struct hfi1_pportdata *ppd = dd->pport;
1731 u32 *ptr = NULL;
1732 u32 header1 = 0, header2 = 0, magic_num = 0, crc = 0, file_length = 0;
1733 u32 record_idx = 0, table_type = 0, table_length_dwords = 0;
1734 int ret = -EINVAL; /* assume failure */
1735
1736 /*
1737 * For integrated devices that did not fall back to the default file,
1738 * the SI tuning information for active channels is acquired from the
1739 * scratch register bitmap, thus there is no platform config to parse.
1740 * Skip parsing in these situations.
1741 */
1742 if (ppd->config_from_scratch)
1743 return 0;
1744
1745 if (!dd->platform_config.data) {
1746 dd_dev_err(dd, "%s: Missing config file\n", __func__);
1747 ret = -EINVAL;
1748 goto bail;
1749 }
1750 ptr = (u32 *)dd->platform_config.data;
1751
1752 magic_num = *ptr;
1753 ptr++;
1754 if (magic_num != PLATFORM_CONFIG_MAGIC_NUM) {
1755 dd_dev_err(dd, "%s: Bad config file\n", __func__);
1756 ret = -EINVAL;
1757 goto bail;
1758 }
1759
1760 /* Field is file size in DWORDs */
1761 file_length = (*ptr) * 4;
1762
1763 /*
1764 * Length can't be larger than partition size. Assume platform
1765 * config format version 4 is being used. Interpret the file size
1766 * field as header instead by not moving the pointer.
1767 */
1768 if (file_length > MAX_PLATFORM_CONFIG_FILE_SIZE) {
1769 dd_dev_info(dd,
1770 "%s:File length out of bounds, using alternative format\n",
1771 __func__);
1772 file_length = PLATFORM_CONFIG_FORMAT_4_FILE_SIZE;
1773 } else {
1774 ptr++;
1775 }
1776
1777 if (file_length > dd->platform_config.size) {
1778 dd_dev_info(dd, "%s:File claims to be larger than read size\n",
1779 __func__);
1780 ret = -EINVAL;
1781 goto bail;
1782 } else if (file_length < dd->platform_config.size) {
1783 dd_dev_info(dd,
1784 "%s:File claims to be smaller than read size, continuing\n",
1785 __func__);
1786 }
1787 /* exactly equal, perfection */
1788
1789 /*
1790 * In both cases where we proceed, using the self-reported file length
1791 * is the safer option. In case of old format a predefined value is
1792 * being used.
1793 */
1794 while (ptr < (u32 *)(dd->platform_config.data + file_length)) {
1795 header1 = *ptr;
1796 header2 = *(ptr + 1);
1797 if (header1 != ~header2) {
1798 dd_dev_err(dd, "%s: Failed validation at offset %ld\n",
1799 __func__, (ptr - (u32 *)
1800 dd->platform_config.data));
1801 ret = -EINVAL;
1802 goto bail;
1803 }
1804
1805 record_idx = *ptr &
1806 ((1 << PLATFORM_CONFIG_HEADER_RECORD_IDX_LEN_BITS) - 1);
1807
1808 table_length_dwords = (*ptr >>
1809 PLATFORM_CONFIG_HEADER_TABLE_LENGTH_SHIFT) &
1810 ((1 << PLATFORM_CONFIG_HEADER_TABLE_LENGTH_LEN_BITS) - 1);
1811
1812 table_type = (*ptr >> PLATFORM_CONFIG_HEADER_TABLE_TYPE_SHIFT) &
1813 ((1 << PLATFORM_CONFIG_HEADER_TABLE_TYPE_LEN_BITS) - 1);
1814
1815 /* Done with this set of headers */
1816 ptr += 2;
1817
1818 if (record_idx) {
1819 /* data table */
1820 switch (table_type) {
1821 case PLATFORM_CONFIG_SYSTEM_TABLE:
1822 pcfgcache->config_tables[table_type].num_table =
1823 1;
1824 ret = check_meta_version(dd, ptr);
1825 if (ret)
1826 goto bail;
1827 break;
1828 case PLATFORM_CONFIG_PORT_TABLE:
1829 pcfgcache->config_tables[table_type].num_table =
1830 2;
1831 break;
1832 case PLATFORM_CONFIG_RX_PRESET_TABLE:
1833 case PLATFORM_CONFIG_TX_PRESET_TABLE:
1834 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
1835 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
1836 pcfgcache->config_tables[table_type].num_table =
1837 table_length_dwords;
1838 break;
1839 default:
1840 dd_dev_err(dd,
1841 "%s: Unknown data table %d, offset %ld\n",
1842 __func__, table_type,
1843 (ptr - (u32 *)
1844 dd->platform_config.data));
1845 ret = -EINVAL;
1846 goto bail; /* We don't trust this file now */
1847 }
1848 pcfgcache->config_tables[table_type].table = ptr;
1849 } else {
1850 /* metadata table */
1851 switch (table_type) {
1852 case PLATFORM_CONFIG_SYSTEM_TABLE:
1853 case PLATFORM_CONFIG_PORT_TABLE:
1854 case PLATFORM_CONFIG_RX_PRESET_TABLE:
1855 case PLATFORM_CONFIG_TX_PRESET_TABLE:
1856 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
1857 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
1858 break;
1859 default:
1860 dd_dev_err(dd,
1861 "%s: Unknown meta table %d, offset %ld\n",
1862 __func__, table_type,
1863 (ptr -
1864 (u32 *)dd->platform_config.data));
1865 ret = -EINVAL;
1866 goto bail; /* We don't trust this file now */
1867 }
1868 pcfgcache->config_tables[table_type].table_metadata =
1869 ptr;
1870 }
1871
1872 /* Calculate and check table crc */
1873 crc = crc32_le(~(u32)0, (unsigned char const *)ptr,
1874 (table_length_dwords * 4));
1875 crc ^= ~(u32)0;
1876
1877 /* Jump the table */
1878 ptr += table_length_dwords;
1879 if (crc != *ptr) {
1880 dd_dev_err(dd, "%s: Failed CRC check at offset %ld\n",
1881 __func__, (ptr -
1882 (u32 *)dd->platform_config.data));
1883 ret = -EINVAL;
1884 goto bail;
1885 }
1886 /* Jump the CRC DWORD */
1887 ptr++;
1888 }
1889
1890 pcfgcache->cache_valid = 1;
1891 return 0;
1892 bail:
1893 memset(pcfgcache, 0, sizeof(struct platform_config_cache));
1894 return ret;
1895 }
1896
get_integrated_platform_config_field(struct hfi1_devdata * dd,enum platform_config_table_type_encoding table_type,int field_index,u32 * data)1897 static void get_integrated_platform_config_field(
1898 struct hfi1_devdata *dd,
1899 enum platform_config_table_type_encoding table_type,
1900 int field_index, u32 *data)
1901 {
1902 struct hfi1_pportdata *ppd = dd->pport;
1903 u8 *cache = ppd->qsfp_info.cache;
1904 u32 tx_preset = 0;
1905
1906 switch (table_type) {
1907 case PLATFORM_CONFIG_SYSTEM_TABLE:
1908 if (field_index == SYSTEM_TABLE_QSFP_POWER_CLASS_MAX)
1909 *data = ppd->max_power_class;
1910 else if (field_index == SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_25G)
1911 *data = ppd->default_atten;
1912 break;
1913 case PLATFORM_CONFIG_PORT_TABLE:
1914 if (field_index == PORT_TABLE_PORT_TYPE)
1915 *data = ppd->port_type;
1916 else if (field_index == PORT_TABLE_LOCAL_ATTEN_25G)
1917 *data = ppd->local_atten;
1918 else if (field_index == PORT_TABLE_REMOTE_ATTEN_25G)
1919 *data = ppd->remote_atten;
1920 break;
1921 case PLATFORM_CONFIG_RX_PRESET_TABLE:
1922 if (field_index == RX_PRESET_TABLE_QSFP_RX_CDR_APPLY)
1923 *data = (ppd->rx_preset & QSFP_RX_CDR_APPLY_SMASK) >>
1924 QSFP_RX_CDR_APPLY_SHIFT;
1925 else if (field_index == RX_PRESET_TABLE_QSFP_RX_EMP_APPLY)
1926 *data = (ppd->rx_preset & QSFP_RX_EMP_APPLY_SMASK) >>
1927 QSFP_RX_EMP_APPLY_SHIFT;
1928 else if (field_index == RX_PRESET_TABLE_QSFP_RX_AMP_APPLY)
1929 *data = (ppd->rx_preset & QSFP_RX_AMP_APPLY_SMASK) >>
1930 QSFP_RX_AMP_APPLY_SHIFT;
1931 else if (field_index == RX_PRESET_TABLE_QSFP_RX_CDR)
1932 *data = (ppd->rx_preset & QSFP_RX_CDR_SMASK) >>
1933 QSFP_RX_CDR_SHIFT;
1934 else if (field_index == RX_PRESET_TABLE_QSFP_RX_EMP)
1935 *data = (ppd->rx_preset & QSFP_RX_EMP_SMASK) >>
1936 QSFP_RX_EMP_SHIFT;
1937 else if (field_index == RX_PRESET_TABLE_QSFP_RX_AMP)
1938 *data = (ppd->rx_preset & QSFP_RX_AMP_SMASK) >>
1939 QSFP_RX_AMP_SHIFT;
1940 break;
1941 case PLATFORM_CONFIG_TX_PRESET_TABLE:
1942 if (cache[QSFP_EQ_INFO_OFFS] & 0x4)
1943 tx_preset = ppd->tx_preset_eq;
1944 else
1945 tx_preset = ppd->tx_preset_noeq;
1946 if (field_index == TX_PRESET_TABLE_PRECUR)
1947 *data = (tx_preset & TX_PRECUR_SMASK) >>
1948 TX_PRECUR_SHIFT;
1949 else if (field_index == TX_PRESET_TABLE_ATTN)
1950 *data = (tx_preset & TX_ATTN_SMASK) >>
1951 TX_ATTN_SHIFT;
1952 else if (field_index == TX_PRESET_TABLE_POSTCUR)
1953 *data = (tx_preset & TX_POSTCUR_SMASK) >>
1954 TX_POSTCUR_SHIFT;
1955 else if (field_index == TX_PRESET_TABLE_QSFP_TX_CDR_APPLY)
1956 *data = (tx_preset & QSFP_TX_CDR_APPLY_SMASK) >>
1957 QSFP_TX_CDR_APPLY_SHIFT;
1958 else if (field_index == TX_PRESET_TABLE_QSFP_TX_EQ_APPLY)
1959 *data = (tx_preset & QSFP_TX_EQ_APPLY_SMASK) >>
1960 QSFP_TX_EQ_APPLY_SHIFT;
1961 else if (field_index == TX_PRESET_TABLE_QSFP_TX_CDR)
1962 *data = (tx_preset & QSFP_TX_CDR_SMASK) >>
1963 QSFP_TX_CDR_SHIFT;
1964 else if (field_index == TX_PRESET_TABLE_QSFP_TX_EQ)
1965 *data = (tx_preset & QSFP_TX_EQ_SMASK) >>
1966 QSFP_TX_EQ_SHIFT;
1967 break;
1968 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
1969 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
1970 default:
1971 break;
1972 }
1973 }
1974
get_platform_fw_field_metadata(struct hfi1_devdata * dd,int table,int field,u32 * field_len_bits,u32 * field_start_bits)1975 static int get_platform_fw_field_metadata(struct hfi1_devdata *dd, int table,
1976 int field, u32 *field_len_bits,
1977 u32 *field_start_bits)
1978 {
1979 struct platform_config_cache *pcfgcache = &dd->pcfg_cache;
1980 u32 *src_ptr = NULL;
1981
1982 if (!pcfgcache->cache_valid)
1983 return -EINVAL;
1984
1985 switch (table) {
1986 case PLATFORM_CONFIG_SYSTEM_TABLE:
1987 case PLATFORM_CONFIG_PORT_TABLE:
1988 case PLATFORM_CONFIG_RX_PRESET_TABLE:
1989 case PLATFORM_CONFIG_TX_PRESET_TABLE:
1990 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
1991 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
1992 if (field && field < platform_config_table_limits[table])
1993 src_ptr =
1994 pcfgcache->config_tables[table].table_metadata + field;
1995 break;
1996 default:
1997 dd_dev_info(dd, "%s: Unknown table\n", __func__);
1998 break;
1999 }
2000
2001 if (!src_ptr)
2002 return -EINVAL;
2003
2004 if (field_start_bits)
2005 *field_start_bits = *src_ptr &
2006 ((1 << METADATA_TABLE_FIELD_START_LEN_BITS) - 1);
2007
2008 if (field_len_bits)
2009 *field_len_bits = (*src_ptr >> METADATA_TABLE_FIELD_LEN_SHIFT)
2010 & ((1 << METADATA_TABLE_FIELD_LEN_LEN_BITS) - 1);
2011
2012 return 0;
2013 }
2014
2015 /* This is the central interface to getting data out of the platform config
2016 * file. It depends on parse_platform_config() having populated the
2017 * platform_config_cache in hfi1_devdata, and checks the cache_valid member to
2018 * validate the sanity of the cache.
2019 *
2020 * The non-obvious parameters:
2021 * @table_index: Acts as a look up key into which instance of the tables the
2022 * relevant field is fetched from.
2023 *
2024 * This applies to the data tables that have multiple instances. The port table
2025 * is an exception to this rule as each HFI only has one port and thus the
2026 * relevant table can be distinguished by hfi_id.
2027 *
2028 * @data: pointer to memory that will be populated with the field requested.
2029 * @len: length of memory pointed by @data in bytes.
2030 */
get_platform_config_field(struct hfi1_devdata * dd,enum platform_config_table_type_encoding table_type,int table_index,int field_index,u32 * data,u32 len)2031 int get_platform_config_field(struct hfi1_devdata *dd,
2032 enum platform_config_table_type_encoding
2033 table_type, int table_index, int field_index,
2034 u32 *data, u32 len)
2035 {
2036 int ret = 0, wlen = 0, seek = 0;
2037 u32 field_len_bits = 0, field_start_bits = 0, *src_ptr = NULL;
2038 struct platform_config_cache *pcfgcache = &dd->pcfg_cache;
2039 struct hfi1_pportdata *ppd = dd->pport;
2040
2041 if (data)
2042 memset(data, 0, len);
2043 else
2044 return -EINVAL;
2045
2046 if (ppd->config_from_scratch) {
2047 /*
2048 * Use saved configuration from ppd for integrated platforms
2049 */
2050 get_integrated_platform_config_field(dd, table_type,
2051 field_index, data);
2052 return 0;
2053 }
2054
2055 ret = get_platform_fw_field_metadata(dd, table_type, field_index,
2056 &field_len_bits,
2057 &field_start_bits);
2058 if (ret)
2059 return -EINVAL;
2060
2061 /* Convert length to bits */
2062 len *= 8;
2063
2064 /* Our metadata function checked cache_valid and field_index for us */
2065 switch (table_type) {
2066 case PLATFORM_CONFIG_SYSTEM_TABLE:
2067 src_ptr = pcfgcache->config_tables[table_type].table;
2068
2069 if (field_index != SYSTEM_TABLE_QSFP_POWER_CLASS_MAX) {
2070 if (len < field_len_bits)
2071 return -EINVAL;
2072
2073 seek = field_start_bits / 8;
2074 wlen = field_len_bits / 8;
2075
2076 src_ptr = (u32 *)((u8 *)src_ptr + seek);
2077
2078 /*
2079 * We expect the field to be byte aligned and whole byte
2080 * lengths if we are here
2081 */
2082 memcpy(data, src_ptr, wlen);
2083 return 0;
2084 }
2085 break;
2086 case PLATFORM_CONFIG_PORT_TABLE:
2087 /* Port table is 4 DWORDS */
2088 src_ptr = dd->hfi1_id ?
2089 pcfgcache->config_tables[table_type].table + 4 :
2090 pcfgcache->config_tables[table_type].table;
2091 break;
2092 case PLATFORM_CONFIG_RX_PRESET_TABLE:
2093 case PLATFORM_CONFIG_TX_PRESET_TABLE:
2094 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
2095 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
2096 src_ptr = pcfgcache->config_tables[table_type].table;
2097
2098 if (table_index <
2099 pcfgcache->config_tables[table_type].num_table)
2100 src_ptr += table_index;
2101 else
2102 src_ptr = NULL;
2103 break;
2104 default:
2105 dd_dev_info(dd, "%s: Unknown table\n", __func__);
2106 break;
2107 }
2108
2109 if (!src_ptr || len < field_len_bits)
2110 return -EINVAL;
2111
2112 src_ptr += (field_start_bits / 32);
2113 *data = (*src_ptr >> (field_start_bits % 32)) &
2114 ((1 << field_len_bits) - 1);
2115
2116 return 0;
2117 }
2118
2119 /*
2120 * Download the firmware needed for the Gen3 PCIe SerDes. An update
2121 * to the SBus firmware is needed before updating the PCIe firmware.
2122 *
2123 * Note: caller must be holding the SBus resource.
2124 */
load_pcie_firmware(struct hfi1_devdata * dd)2125 int load_pcie_firmware(struct hfi1_devdata *dd)
2126 {
2127 int ret = 0;
2128
2129 /* both firmware loads below use the SBus */
2130 set_sbus_fast_mode(dd);
2131
2132 if (fw_sbus_load) {
2133 turn_off_spicos(dd, SPICO_SBUS);
2134 do {
2135 ret = load_sbus_firmware(dd, &fw_sbus);
2136 } while (retry_firmware(dd, ret));
2137 if (ret)
2138 goto done;
2139 }
2140
2141 if (fw_pcie_serdes_load) {
2142 dd_dev_info(dd, "Setting PCIe SerDes broadcast\n");
2143 set_serdes_broadcast(dd, all_pcie_serdes_broadcast,
2144 pcie_serdes_broadcast[dd->hfi1_id],
2145 pcie_serdes_addrs[dd->hfi1_id],
2146 NUM_PCIE_SERDES);
2147 do {
2148 ret = load_pcie_serdes_firmware(dd, &fw_pcie);
2149 } while (retry_firmware(dd, ret));
2150 if (ret)
2151 goto done;
2152 }
2153
2154 done:
2155 clear_sbus_fast_mode(dd);
2156
2157 return ret;
2158 }
2159
2160 /*
2161 * Read the GUID from the hardware, store it in dd.
2162 */
read_guid(struct hfi1_devdata * dd)2163 void read_guid(struct hfi1_devdata *dd)
2164 {
2165 /* Take the DC out of reset to get a valid GUID value */
2166 write_csr(dd, CCE_DC_CTRL, 0);
2167 (void)read_csr(dd, CCE_DC_CTRL);
2168
2169 dd->base_guid = read_csr(dd, DC_DC8051_CFG_LOCAL_GUID);
2170 dd_dev_info(dd, "GUID %llx",
2171 (unsigned long long)dd->base_guid);
2172 }
2173
2174 /* read and display firmware version info */
dump_fw_version(struct hfi1_devdata * dd)2175 static void dump_fw_version(struct hfi1_devdata *dd)
2176 {
2177 u32 pcie_vers[NUM_PCIE_SERDES];
2178 u32 fabric_vers[NUM_FABRIC_SERDES];
2179 u32 sbus_vers;
2180 int i;
2181 int all_same;
2182 int ret;
2183 u8 rcv_addr;
2184
2185 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
2186 if (ret) {
2187 dd_dev_err(dd, "Unable to acquire SBus to read firmware versions\n");
2188 return;
2189 }
2190
2191 /* set fast mode */
2192 set_sbus_fast_mode(dd);
2193
2194 /* read version for SBus Master */
2195 sbus_request(dd, SBUS_MASTER_BROADCAST, 0x02, WRITE_SBUS_RECEIVER, 0);
2196 sbus_request(dd, SBUS_MASTER_BROADCAST, 0x07, WRITE_SBUS_RECEIVER, 0x1);
2197 /* wait for interrupt to be processed */
2198 usleep_range(10000, 11000);
2199 sbus_vers = sbus_read(dd, SBUS_MASTER_BROADCAST, 0x08, 0x1);
2200 dd_dev_info(dd, "SBus Master firmware version 0x%08x\n", sbus_vers);
2201
2202 /* read version for PCIe SerDes */
2203 all_same = 1;
2204 pcie_vers[0] = 0;
2205 for (i = 0; i < NUM_PCIE_SERDES; i++) {
2206 rcv_addr = pcie_serdes_addrs[dd->hfi1_id][i];
2207 sbus_request(dd, rcv_addr, 0x03, WRITE_SBUS_RECEIVER, 0);
2208 /* wait for interrupt to be processed */
2209 usleep_range(10000, 11000);
2210 pcie_vers[i] = sbus_read(dd, rcv_addr, 0x04, 0x0);
2211 if (i > 0 && pcie_vers[0] != pcie_vers[i])
2212 all_same = 0;
2213 }
2214
2215 if (all_same) {
2216 dd_dev_info(dd, "PCIe SerDes firmware version 0x%x\n",
2217 pcie_vers[0]);
2218 } else {
2219 dd_dev_warn(dd, "PCIe SerDes do not have the same firmware version\n");
2220 for (i = 0; i < NUM_PCIE_SERDES; i++) {
2221 dd_dev_info(dd,
2222 "PCIe SerDes lane %d firmware version 0x%x\n",
2223 i, pcie_vers[i]);
2224 }
2225 }
2226
2227 /* read version for fabric SerDes */
2228 all_same = 1;
2229 fabric_vers[0] = 0;
2230 for (i = 0; i < NUM_FABRIC_SERDES; i++) {
2231 rcv_addr = fabric_serdes_addrs[dd->hfi1_id][i];
2232 sbus_request(dd, rcv_addr, 0x03, WRITE_SBUS_RECEIVER, 0);
2233 /* wait for interrupt to be processed */
2234 usleep_range(10000, 11000);
2235 fabric_vers[i] = sbus_read(dd, rcv_addr, 0x04, 0x0);
2236 if (i > 0 && fabric_vers[0] != fabric_vers[i])
2237 all_same = 0;
2238 }
2239
2240 if (all_same) {
2241 dd_dev_info(dd, "Fabric SerDes firmware version 0x%x\n",
2242 fabric_vers[0]);
2243 } else {
2244 dd_dev_warn(dd, "Fabric SerDes do not have the same firmware version\n");
2245 for (i = 0; i < NUM_FABRIC_SERDES; i++) {
2246 dd_dev_info(dd,
2247 "Fabric SerDes lane %d firmware version 0x%x\n",
2248 i, fabric_vers[i]);
2249 }
2250 }
2251
2252 clear_sbus_fast_mode(dd);
2253 release_chip_resource(dd, CR_SBUS);
2254 }
2255