1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Pin Control and GPIO driver for SuperH Pin Function Controller.
4 *
5 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
6 *
7 * Copyright (C) 2008 Magnus Damm
8 * Copyright (C) 2009 - 2012 Paul Mundt
9 */
10
11 #define DRV_NAME "sh-pfc"
12
13 #include <linux/bitops.h>
14 #include <linux/err.h>
15 #include <linux/errno.h>
16 #include <linux/io.h>
17 #include <linux/ioport.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/pinctrl/machine.h>
23 #include <linux/platform_device.h>
24 #include <linux/psci.h>
25 #include <linux/slab.h>
26 #include <linux/sys_soc.h>
27
28 #include "core.h"
29
sh_pfc_map_resources(struct sh_pfc * pfc,struct platform_device * pdev)30 static int sh_pfc_map_resources(struct sh_pfc *pfc,
31 struct platform_device *pdev)
32 {
33 struct sh_pfc_window *windows;
34 unsigned int *irqs = NULL;
35 unsigned int num_windows;
36 struct resource *res;
37 unsigned int i;
38 int num_irqs;
39
40 /* Count the MEM and IRQ resources. */
41 for (num_windows = 0;; num_windows++) {
42 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
43 if (!res)
44 break;
45 }
46 if (num_windows == 0)
47 return -EINVAL;
48
49 num_irqs = platform_irq_count(pdev);
50 if (num_irqs < 0)
51 return num_irqs;
52
53 /* Allocate memory windows and IRQs arrays. */
54 windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows),
55 GFP_KERNEL);
56 if (windows == NULL)
57 return -ENOMEM;
58
59 pfc->num_windows = num_windows;
60 pfc->windows = windows;
61
62 if (num_irqs) {
63 irqs = devm_kcalloc(pfc->dev, num_irqs, sizeof(*irqs),
64 GFP_KERNEL);
65 if (irqs == NULL)
66 return -ENOMEM;
67
68 pfc->num_irqs = num_irqs;
69 pfc->irqs = irqs;
70 }
71
72 /* Fill them. */
73 for (i = 0; i < num_windows; i++) {
74 windows->virt = devm_platform_get_and_ioremap_resource(pdev, i, &res);
75 if (IS_ERR(windows->virt))
76 return -ENOMEM;
77 windows->phys = res->start;
78 windows->size = resource_size(res);
79 windows++;
80 }
81 for (i = 0; i < num_irqs; i++)
82 *irqs++ = platform_get_irq(pdev, i);
83
84 return 0;
85 }
86
sh_pfc_phys_to_virt(struct sh_pfc * pfc,u32 reg)87 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
88 {
89 struct sh_pfc_window *window;
90 phys_addr_t address = reg;
91 unsigned int i;
92
93 /* scan through physical windows and convert address */
94 for (i = 0; i < pfc->num_windows; i++) {
95 window = pfc->windows + i;
96
97 if (address < window->phys)
98 continue;
99
100 if (address >= (window->phys + window->size))
101 continue;
102
103 return window->virt + (address - window->phys);
104 }
105
106 BUG();
107 return NULL;
108 }
109
sh_pfc_get_pin_index(struct sh_pfc * pfc,unsigned int pin)110 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
111 {
112 unsigned int offset;
113 unsigned int i;
114
115 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
116 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
117
118 if (pin <= range->end)
119 return pin >= range->start
120 ? offset + pin - range->start : -1;
121
122 offset += range->end - range->start + 1;
123 }
124
125 return -EINVAL;
126 }
127
sh_pfc_enum_in_range(u16 enum_id,const struct pinmux_range * r)128 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
129 {
130 if (enum_id < r->begin)
131 return 0;
132
133 if (enum_id > r->end)
134 return 0;
135
136 return 1;
137 }
138
sh_pfc_read_raw_reg(void __iomem * mapped_reg,unsigned int reg_width)139 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
140 {
141 switch (reg_width) {
142 case 8:
143 return ioread8(mapped_reg);
144 case 16:
145 return ioread16(mapped_reg);
146 case 32:
147 return ioread32(mapped_reg);
148 }
149
150 BUG();
151 return 0;
152 }
153
sh_pfc_write_raw_reg(void __iomem * mapped_reg,unsigned int reg_width,u32 data)154 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
155 u32 data)
156 {
157 switch (reg_width) {
158 case 8:
159 iowrite8(data, mapped_reg);
160 return;
161 case 16:
162 iowrite16(data, mapped_reg);
163 return;
164 case 32:
165 iowrite32(data, mapped_reg);
166 return;
167 }
168
169 BUG();
170 }
171
sh_pfc_read(struct sh_pfc * pfc,u32 reg)172 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
173 {
174 return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
175 }
176
sh_pfc_unlock_reg(struct sh_pfc * pfc,u32 reg,u32 data)177 static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data)
178 {
179 u32 unlock;
180
181 if (!pfc->info->unlock_reg)
182 return;
183
184 if (pfc->info->unlock_reg >= 0x80000000UL)
185 unlock = pfc->info->unlock_reg;
186 else
187 /* unlock_reg is a mask */
188 unlock = reg & ~pfc->info->unlock_reg;
189
190 sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, unlock), 32, ~data);
191 }
192
sh_pfc_write(struct sh_pfc * pfc,u32 reg,u32 data)193 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
194 {
195 sh_pfc_unlock_reg(pfc, reg, data);
196 sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
197 }
198
sh_pfc_config_reg_helper(struct sh_pfc * pfc,const struct pinmux_cfg_reg * crp,unsigned int in_pos,void __iomem ** mapped_regp,u32 * maskp,unsigned int * posp)199 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
200 const struct pinmux_cfg_reg *crp,
201 unsigned int in_pos,
202 void __iomem **mapped_regp, u32 *maskp,
203 unsigned int *posp)
204 {
205 unsigned int k;
206
207 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
208
209 if (crp->field_width) {
210 *maskp = (1 << crp->field_width) - 1;
211 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
212 } else {
213 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
214 *posp = crp->reg_width;
215 for (k = 0; k <= in_pos; k++)
216 *posp -= crp->var_field_width[k];
217 }
218 }
219
sh_pfc_write_config_reg(struct sh_pfc * pfc,const struct pinmux_cfg_reg * crp,unsigned int field,u32 value)220 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
221 const struct pinmux_cfg_reg *crp,
222 unsigned int field, u32 value)
223 {
224 void __iomem *mapped_reg;
225 unsigned int pos;
226 u32 mask, data;
227
228 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
229
230 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
231 "r_width = %u, f_width = %u\n",
232 crp->reg, value, field, crp->reg_width, hweight32(mask));
233
234 mask = ~(mask << pos);
235 value = value << pos;
236
237 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
238 data &= mask;
239 data |= value;
240
241 sh_pfc_unlock_reg(pfc, crp->reg, data);
242 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
243 }
244
sh_pfc_get_config_reg(struct sh_pfc * pfc,u16 enum_id,const struct pinmux_cfg_reg ** crp,unsigned int * fieldp,u32 * valuep)245 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
246 const struct pinmux_cfg_reg **crp,
247 unsigned int *fieldp, u32 *valuep)
248 {
249 unsigned int k = 0;
250
251 while (1) {
252 const struct pinmux_cfg_reg *config_reg =
253 pfc->info->cfg_regs + k;
254 unsigned int r_width = config_reg->reg_width;
255 unsigned int f_width = config_reg->field_width;
256 unsigned int curr_width;
257 unsigned int bit_pos;
258 unsigned int pos = 0;
259 unsigned int m = 0;
260
261 if (!r_width)
262 break;
263
264 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
265 u32 ncomb;
266 u32 n;
267
268 if (f_width)
269 curr_width = f_width;
270 else
271 curr_width = config_reg->var_field_width[m];
272
273 ncomb = 1 << curr_width;
274 for (n = 0; n < ncomb; n++) {
275 if (config_reg->enum_ids[pos + n] == enum_id) {
276 *crp = config_reg;
277 *fieldp = m;
278 *valuep = n;
279 return 0;
280 }
281 }
282 pos += ncomb;
283 m++;
284 }
285 k++;
286 }
287
288 return -EINVAL;
289 }
290
sh_pfc_mark_to_enum(struct sh_pfc * pfc,u16 mark,int pos,u16 * enum_idp)291 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
292 u16 *enum_idp)
293 {
294 const u16 *data = pfc->info->pinmux_data;
295 unsigned int k;
296
297 if (pos) {
298 *enum_idp = data[pos + 1];
299 return pos + 1;
300 }
301
302 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
303 if (data[k] == mark) {
304 *enum_idp = data[k + 1];
305 return k + 1;
306 }
307 }
308
309 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
310 mark);
311 return -EINVAL;
312 }
313
sh_pfc_config_mux(struct sh_pfc * pfc,unsigned mark,int pinmux_type)314 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
315 {
316 const struct pinmux_range *range;
317 int pos = 0;
318
319 switch (pinmux_type) {
320 case PINMUX_TYPE_GPIO:
321 case PINMUX_TYPE_FUNCTION:
322 range = NULL;
323 break;
324
325 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
326 case PINMUX_TYPE_OUTPUT:
327 range = &pfc->info->output;
328 break;
329
330 case PINMUX_TYPE_INPUT:
331 range = &pfc->info->input;
332 break;
333 #endif /* CONFIG_PINCTRL_SH_PFC_GPIO */
334
335 default:
336 return -EINVAL;
337 }
338
339 /* Iterate over all the configuration fields we need to update. */
340 while (1) {
341 const struct pinmux_cfg_reg *cr;
342 unsigned int field;
343 u16 enum_id;
344 u32 value;
345 int in_range;
346 int ret;
347
348 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
349 if (pos < 0)
350 return pos;
351
352 if (!enum_id)
353 break;
354
355 /* Check if the configuration field selects a function. If it
356 * doesn't, skip the field if it's not applicable to the
357 * requested pinmux type.
358 */
359 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
360 if (!in_range) {
361 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
362 /* Functions are allowed to modify all
363 * fields.
364 */
365 in_range = 1;
366 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
367 /* Input/output types can only modify fields
368 * that correspond to their respective ranges.
369 */
370 in_range = sh_pfc_enum_in_range(enum_id, range);
371
372 /*
373 * special case pass through for fixed
374 * input-only or output-only pins without
375 * function enum register association.
376 */
377 if (in_range && enum_id == range->force)
378 continue;
379 }
380 /* GPIOs are only allowed to modify function fields. */
381 }
382
383 if (!in_range)
384 continue;
385
386 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
387 if (ret < 0)
388 return ret;
389
390 sh_pfc_write_config_reg(pfc, cr, field, value);
391 }
392
393 return 0;
394 }
395
sh_pfc_init_ranges(struct sh_pfc * pfc)396 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
397 {
398 struct sh_pfc_pin_range *range;
399 unsigned int nr_ranges;
400 unsigned int i;
401
402 if (pfc->info->pins[0].pin == (u16)-1) {
403 /* Pin number -1 denotes that the SoC doesn't report pin numbers
404 * in its pin arrays yet. Consider the pin numbers range as
405 * continuous and allocate a single range.
406 */
407 pfc->nr_ranges = 1;
408 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
409 GFP_KERNEL);
410 if (pfc->ranges == NULL)
411 return -ENOMEM;
412
413 pfc->ranges->start = 0;
414 pfc->ranges->end = pfc->info->nr_pins - 1;
415 pfc->nr_gpio_pins = pfc->info->nr_pins;
416
417 return 0;
418 }
419
420 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
421 * be sorted by pin numbers, and pins without a GPIO port must come
422 * last.
423 */
424 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
425 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
426 nr_ranges++;
427 }
428
429 pfc->nr_ranges = nr_ranges;
430 pfc->ranges = devm_kcalloc(pfc->dev, nr_ranges, sizeof(*pfc->ranges),
431 GFP_KERNEL);
432 if (pfc->ranges == NULL)
433 return -ENOMEM;
434
435 range = pfc->ranges;
436 range->start = pfc->info->pins[0].pin;
437
438 for (i = 1; i < pfc->info->nr_pins; ++i) {
439 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
440 continue;
441
442 range->end = pfc->info->pins[i-1].pin;
443 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
444 pfc->nr_gpio_pins = range->end + 1;
445
446 range++;
447 range->start = pfc->info->pins[i].pin;
448 }
449
450 range->end = pfc->info->pins[i-1].pin;
451 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
452 pfc->nr_gpio_pins = range->end + 1;
453
454 return 0;
455 }
456
457 #ifdef CONFIG_OF
458 static const struct of_device_id sh_pfc_of_table[] = {
459 #ifdef CONFIG_PINCTRL_PFC_EMEV2
460 {
461 .compatible = "renesas,pfc-emev2",
462 .data = &emev2_pinmux_info,
463 },
464 #endif
465 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
466 {
467 .compatible = "renesas,pfc-r8a73a4",
468 .data = &r8a73a4_pinmux_info,
469 },
470 #endif
471 #ifdef CONFIG_PINCTRL_PFC_R8A7740
472 {
473 .compatible = "renesas,pfc-r8a7740",
474 .data = &r8a7740_pinmux_info,
475 },
476 #endif
477 #ifdef CONFIG_PINCTRL_PFC_R8A7742
478 {
479 .compatible = "renesas,pfc-r8a7742",
480 .data = &r8a7742_pinmux_info,
481 },
482 #endif
483 #ifdef CONFIG_PINCTRL_PFC_R8A7743
484 {
485 .compatible = "renesas,pfc-r8a7743",
486 .data = &r8a7743_pinmux_info,
487 },
488 #endif
489 #ifdef CONFIG_PINCTRL_PFC_R8A7744
490 {
491 .compatible = "renesas,pfc-r8a7744",
492 .data = &r8a7744_pinmux_info,
493 },
494 #endif
495 #ifdef CONFIG_PINCTRL_PFC_R8A7745
496 {
497 .compatible = "renesas,pfc-r8a7745",
498 .data = &r8a7745_pinmux_info,
499 },
500 #endif
501 #ifdef CONFIG_PINCTRL_PFC_R8A77470
502 {
503 .compatible = "renesas,pfc-r8a77470",
504 .data = &r8a77470_pinmux_info,
505 },
506 #endif
507 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
508 {
509 .compatible = "renesas,pfc-r8a774a1",
510 .data = &r8a774a1_pinmux_info,
511 },
512 #endif
513 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
514 {
515 .compatible = "renesas,pfc-r8a774b1",
516 .data = &r8a774b1_pinmux_info,
517 },
518 #endif
519 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
520 {
521 .compatible = "renesas,pfc-r8a774c0",
522 .data = &r8a774c0_pinmux_info,
523 },
524 #endif
525 #ifdef CONFIG_PINCTRL_PFC_R8A774E1
526 {
527 .compatible = "renesas,pfc-r8a774e1",
528 .data = &r8a774e1_pinmux_info,
529 },
530 #endif
531 #ifdef CONFIG_PINCTRL_PFC_R8A7778
532 {
533 .compatible = "renesas,pfc-r8a7778",
534 .data = &r8a7778_pinmux_info,
535 },
536 #endif
537 #ifdef CONFIG_PINCTRL_PFC_R8A7779
538 {
539 .compatible = "renesas,pfc-r8a7779",
540 .data = &r8a7779_pinmux_info,
541 },
542 #endif
543 #ifdef CONFIG_PINCTRL_PFC_R8A7790
544 {
545 .compatible = "renesas,pfc-r8a7790",
546 .data = &r8a7790_pinmux_info,
547 },
548 #endif
549 #ifdef CONFIG_PINCTRL_PFC_R8A7791
550 {
551 .compatible = "renesas,pfc-r8a7791",
552 .data = &r8a7791_pinmux_info,
553 },
554 #endif
555 #ifdef CONFIG_PINCTRL_PFC_R8A7792
556 {
557 .compatible = "renesas,pfc-r8a7792",
558 .data = &r8a7792_pinmux_info,
559 },
560 #endif
561 #ifdef CONFIG_PINCTRL_PFC_R8A7793
562 {
563 .compatible = "renesas,pfc-r8a7793",
564 .data = &r8a7793_pinmux_info,
565 },
566 #endif
567 #ifdef CONFIG_PINCTRL_PFC_R8A7794
568 {
569 .compatible = "renesas,pfc-r8a7794",
570 .data = &r8a7794_pinmux_info,
571 },
572 #endif
573 /*
574 * Both r8a7795 entries must be present to make sanity checks work, but only
575 * the first entry is actually used.
576 * R-Car H3 ES1.x is matched using soc_device_match() instead.
577 */
578 #ifdef CONFIG_PINCTRL_PFC_R8A77951
579 {
580 .compatible = "renesas,pfc-r8a7795",
581 .data = &r8a77951_pinmux_info,
582 },
583 #endif
584 #ifdef CONFIG_PINCTRL_PFC_R8A77950
585 {
586 .compatible = "renesas,pfc-r8a7795",
587 .data = &r8a77950_pinmux_info,
588 },
589 #endif
590 #ifdef CONFIG_PINCTRL_PFC_R8A77960
591 {
592 .compatible = "renesas,pfc-r8a7796",
593 .data = &r8a77960_pinmux_info,
594 },
595 #endif
596 #ifdef CONFIG_PINCTRL_PFC_R8A77961
597 {
598 .compatible = "renesas,pfc-r8a77961",
599 .data = &r8a77961_pinmux_info,
600 },
601 #endif
602 #ifdef CONFIG_PINCTRL_PFC_R8A77965
603 {
604 .compatible = "renesas,pfc-r8a77965",
605 .data = &r8a77965_pinmux_info,
606 },
607 #endif
608 #ifdef CONFIG_PINCTRL_PFC_R8A77970
609 {
610 .compatible = "renesas,pfc-r8a77970",
611 .data = &r8a77970_pinmux_info,
612 },
613 #endif
614 #ifdef CONFIG_PINCTRL_PFC_R8A77980
615 {
616 .compatible = "renesas,pfc-r8a77980",
617 .data = &r8a77980_pinmux_info,
618 },
619 #endif
620 #ifdef CONFIG_PINCTRL_PFC_R8A77990
621 {
622 .compatible = "renesas,pfc-r8a77990",
623 .data = &r8a77990_pinmux_info,
624 },
625 #endif
626 #ifdef CONFIG_PINCTRL_PFC_R8A77995
627 {
628 .compatible = "renesas,pfc-r8a77995",
629 .data = &r8a77995_pinmux_info,
630 },
631 #endif
632 #ifdef CONFIG_PINCTRL_PFC_R8A779A0
633 {
634 .compatible = "renesas,pfc-r8a779a0",
635 .data = &r8a779a0_pinmux_info,
636 },
637 #endif
638 #ifdef CONFIG_PINCTRL_PFC_SH73A0
639 {
640 .compatible = "renesas,pfc-sh73a0",
641 .data = &sh73a0_pinmux_info,
642 },
643 #endif
644 { },
645 };
646 #endif
647
648 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
sh_pfc_nop_reg(struct sh_pfc * pfc,u32 reg,unsigned int idx)649 static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
650 {
651 }
652
sh_pfc_save_reg(struct sh_pfc * pfc,u32 reg,unsigned int idx)653 static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
654 {
655 pfc->saved_regs[idx] = sh_pfc_read(pfc, reg);
656 }
657
sh_pfc_restore_reg(struct sh_pfc * pfc,u32 reg,unsigned int idx)658 static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
659 {
660 sh_pfc_write(pfc, reg, pfc->saved_regs[idx]);
661 }
662
sh_pfc_walk_regs(struct sh_pfc * pfc,void (* do_reg)(struct sh_pfc * pfc,u32 reg,unsigned int idx))663 static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
664 void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx))
665 {
666 unsigned int i, n = 0;
667
668 if (pfc->info->cfg_regs)
669 for (i = 0; pfc->info->cfg_regs[i].reg; i++)
670 do_reg(pfc, pfc->info->cfg_regs[i].reg, n++);
671
672 if (pfc->info->drive_regs)
673 for (i = 0; pfc->info->drive_regs[i].reg; i++)
674 do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
675
676 if (pfc->info->bias_regs)
677 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
678 do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
679 if (pfc->info->bias_regs[i].pud)
680 do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
681 }
682
683 if (pfc->info->ioctrl_regs)
684 for (i = 0; pfc->info->ioctrl_regs[i].reg; i++)
685 do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++);
686
687 return n;
688 }
689
sh_pfc_suspend_init(struct sh_pfc * pfc)690 static int sh_pfc_suspend_init(struct sh_pfc *pfc)
691 {
692 unsigned int n;
693
694 /* This is the best we can do to check for the presence of PSCI */
695 if (!psci_ops.cpu_suspend)
696 return 0;
697
698 n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg);
699 if (!n)
700 return 0;
701
702 pfc->saved_regs = devm_kmalloc_array(pfc->dev, n,
703 sizeof(*pfc->saved_regs),
704 GFP_KERNEL);
705 if (!pfc->saved_regs)
706 return -ENOMEM;
707
708 dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n);
709 return 0;
710 }
711
sh_pfc_suspend_noirq(struct device * dev)712 static int sh_pfc_suspend_noirq(struct device *dev)
713 {
714 struct sh_pfc *pfc = dev_get_drvdata(dev);
715
716 if (pfc->saved_regs)
717 sh_pfc_walk_regs(pfc, sh_pfc_save_reg);
718 return 0;
719 }
720
sh_pfc_resume_noirq(struct device * dev)721 static int sh_pfc_resume_noirq(struct device *dev)
722 {
723 struct sh_pfc *pfc = dev_get_drvdata(dev);
724
725 if (pfc->saved_regs)
726 sh_pfc_walk_regs(pfc, sh_pfc_restore_reg);
727 return 0;
728 }
729
730 static const struct dev_pm_ops sh_pfc_pm = {
731 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq)
732 };
733 #define DEV_PM_OPS &sh_pfc_pm
734 #else
sh_pfc_suspend_init(struct sh_pfc * pfc)735 static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
736 #define DEV_PM_OPS NULL
737 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
738
739 #ifdef DEBUG
740 #define SH_PFC_MAX_REGS 300
741 #define SH_PFC_MAX_ENUMS 5000
742
743 static unsigned int sh_pfc_errors __initdata = 0;
744 static unsigned int sh_pfc_warnings __initdata = 0;
745 static u32 *sh_pfc_regs __initdata = NULL;
746 static u32 sh_pfc_num_regs __initdata = 0;
747 static u16 *sh_pfc_enums __initdata = NULL;
748 static u32 sh_pfc_num_enums __initdata = 0;
749
750 #define sh_pfc_err(fmt, ...) \
751 do { \
752 pr_err("%s: " fmt, drvname, ##__VA_ARGS__); \
753 sh_pfc_errors++; \
754 } while (0)
755 #define sh_pfc_warn(fmt, ...) \
756 do { \
757 pr_warn("%s: " fmt, drvname, ##__VA_ARGS__); \
758 sh_pfc_warnings++; \
759 } while (0)
760
is0s(const u16 * enum_ids,unsigned int n)761 static bool __init is0s(const u16 *enum_ids, unsigned int n)
762 {
763 unsigned int i;
764
765 for (i = 0; i < n; i++)
766 if (enum_ids[i])
767 return false;
768
769 return true;
770 }
771
same_name(const char * a,const char * b)772 static bool __init same_name(const char *a, const char *b)
773 {
774 if (!a || !b)
775 return false;
776
777 return !strcmp(a, b);
778 }
779
sh_pfc_check_reg(const char * drvname,u32 reg)780 static void __init sh_pfc_check_reg(const char *drvname, u32 reg)
781 {
782 unsigned int i;
783
784 for (i = 0; i < sh_pfc_num_regs; i++)
785 if (reg == sh_pfc_regs[i]) {
786 sh_pfc_err("reg 0x%x conflict\n", reg);
787 return;
788 }
789
790 if (sh_pfc_num_regs == SH_PFC_MAX_REGS) {
791 pr_warn_once("%s: Please increase SH_PFC_MAX_REGS\n", drvname);
792 return;
793 }
794
795 sh_pfc_regs[sh_pfc_num_regs++] = reg;
796 }
797
sh_pfc_check_enum(const char * drvname,u16 enum_id)798 static int __init sh_pfc_check_enum(const char *drvname, u16 enum_id)
799 {
800 unsigned int i;
801
802 for (i = 0; i < sh_pfc_num_enums; i++) {
803 if (enum_id == sh_pfc_enums[i])
804 return -EINVAL;
805 }
806
807 if (sh_pfc_num_enums == SH_PFC_MAX_ENUMS) {
808 pr_warn_once("%s: Please increase SH_PFC_MAX_ENUMS\n", drvname);
809 return 0;
810 }
811
812 sh_pfc_enums[sh_pfc_num_enums++] = enum_id;
813 return 0;
814 }
815
sh_pfc_check_reg_enums(const char * drvname,u32 reg,const u16 * enums,unsigned int n)816 static void __init sh_pfc_check_reg_enums(const char *drvname, u32 reg,
817 const u16 *enums, unsigned int n)
818 {
819 unsigned int i;
820
821 for (i = 0; i < n; i++) {
822 if (enums[i] && sh_pfc_check_enum(drvname, enums[i]))
823 sh_pfc_err("reg 0x%x enum_id %u conflict\n", reg,
824 enums[i]);
825 }
826 }
827
sh_pfc_check_pin(const struct sh_pfc_soc_info * info,u32 reg,unsigned int pin)828 static void __init sh_pfc_check_pin(const struct sh_pfc_soc_info *info,
829 u32 reg, unsigned int pin)
830 {
831 const char *drvname = info->name;
832 unsigned int i;
833
834 if (pin == SH_PFC_PIN_NONE)
835 return;
836
837 for (i = 0; i < info->nr_pins; i++) {
838 if (pin == info->pins[i].pin)
839 return;
840 }
841
842 sh_pfc_err("reg 0x%x: pin %u not found\n", reg, pin);
843 }
844
sh_pfc_check_cfg_reg(const char * drvname,const struct pinmux_cfg_reg * cfg_reg)845 static void __init sh_pfc_check_cfg_reg(const char *drvname,
846 const struct pinmux_cfg_reg *cfg_reg)
847 {
848 unsigned int i, n, rw, fw;
849
850 sh_pfc_check_reg(drvname, cfg_reg->reg);
851
852 if (cfg_reg->field_width) {
853 fw = cfg_reg->field_width;
854 n = (cfg_reg->reg_width / fw) << fw;
855 /* Skip field checks (done at build time) */
856 goto check_enum_ids;
857 }
858
859 for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) {
860 if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw))
861 sh_pfc_warn("reg 0x%x: reserved field [%u:%u] can be split to reduce table size\n",
862 cfg_reg->reg, rw, rw + fw - 1);
863 n += 1 << fw;
864 rw += fw;
865 }
866
867 if (rw != cfg_reg->reg_width)
868 sh_pfc_err("reg 0x%x: var_field_width declares %u instead of %u bits\n",
869 cfg_reg->reg, rw, cfg_reg->reg_width);
870
871 if (n != cfg_reg->nr_enum_ids)
872 sh_pfc_err("reg 0x%x: enum_ids[] has %u instead of %u values\n",
873 cfg_reg->reg, cfg_reg->nr_enum_ids, n);
874
875 check_enum_ids:
876 sh_pfc_check_reg_enums(drvname, cfg_reg->reg, cfg_reg->enum_ids, n);
877 }
878
sh_pfc_check_drive_reg(const struct sh_pfc_soc_info * info,const struct pinmux_drive_reg * drive)879 static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info,
880 const struct pinmux_drive_reg *drive)
881 {
882 const char *drvname = info->name;
883 unsigned long seen = 0, mask;
884 unsigned int i;
885
886 sh_pfc_check_reg(info->name, drive->reg);
887 for (i = 0; i < ARRAY_SIZE(drive->fields); i++) {
888 const struct pinmux_drive_reg_field *field = &drive->fields[i];
889
890 if (!field->pin && !field->offset && !field->size)
891 continue;
892
893 mask = GENMASK(field->offset + field->size - 1, field->offset);
894 if (mask & seen)
895 sh_pfc_err("drive_reg 0x%x: field %u overlap\n",
896 drive->reg, i);
897 seen |= mask;
898
899 sh_pfc_check_pin(info, drive->reg, field->pin);
900 }
901 }
902
sh_pfc_check_bias_reg(const struct sh_pfc_soc_info * info,const struct pinmux_bias_reg * bias)903 static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info,
904 const struct pinmux_bias_reg *bias)
905 {
906 unsigned int i;
907
908 sh_pfc_check_reg(info->name, bias->puen);
909 if (bias->pud)
910 sh_pfc_check_reg(info->name, bias->pud);
911 for (i = 0; i < ARRAY_SIZE(bias->pins); i++)
912 sh_pfc_check_pin(info, bias->puen, bias->pins[i]);
913 }
914
sh_pfc_check_info(const struct sh_pfc_soc_info * info)915 static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
916 {
917 const char *drvname = info->name;
918 unsigned int *refcnts;
919 unsigned int i, j, k;
920
921 pr_info("Checking %s\n", drvname);
922 sh_pfc_num_regs = 0;
923 sh_pfc_num_enums = 0;
924
925 /* Check pins */
926 for (i = 0; i < info->nr_pins; i++) {
927 const struct sh_pfc_pin *pin = &info->pins[i];
928
929 if (!pin->name) {
930 sh_pfc_err("empty pin %u\n", i);
931 continue;
932 }
933 for (j = 0; j < i; j++) {
934 const struct sh_pfc_pin *pin2 = &info->pins[j];
935
936 if (same_name(pin->name, pin2->name))
937 sh_pfc_err("pin %s: name conflict\n",
938 pin->name);
939
940 if (pin->pin != (u16)-1 && pin->pin == pin2->pin)
941 sh_pfc_err("pin %s/%s: pin %u conflict\n",
942 pin->name, pin2->name, pin->pin);
943
944 if (pin->enum_id && pin->enum_id == pin2->enum_id)
945 sh_pfc_err("pin %s/%s: enum_id %u conflict\n",
946 pin->name, pin2->name,
947 pin->enum_id);
948 }
949 }
950
951 /* Check groups and functions */
952 refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);
953 if (!refcnts)
954 return;
955
956 for (i = 0; i < info->nr_functions; i++) {
957 const struct sh_pfc_function *func = &info->functions[i];
958
959 if (!func->name) {
960 sh_pfc_err("empty function %u\n", i);
961 continue;
962 }
963 for (j = 0; j < i; j++) {
964 if (same_name(func->name, info->functions[j].name))
965 sh_pfc_err("function %s: name conflict\n",
966 func->name);
967 }
968 for (j = 0; j < func->nr_groups; j++) {
969 for (k = 0; k < info->nr_groups; k++) {
970 if (same_name(func->groups[j],
971 info->groups[k].name)) {
972 refcnts[k]++;
973 break;
974 }
975 }
976
977 if (k == info->nr_groups)
978 sh_pfc_err("function %s: group %s not found\n",
979 func->name, func->groups[j]);
980 }
981 }
982
983 for (i = 0; i < info->nr_groups; i++) {
984 const struct sh_pfc_pin_group *group = &info->groups[i];
985
986 if (!group->name) {
987 sh_pfc_err("empty group %u\n", i);
988 continue;
989 }
990 for (j = 0; j < i; j++) {
991 if (same_name(group->name, info->groups[j].name))
992 sh_pfc_err("group %s: name conflict\n",
993 group->name);
994 }
995 if (!refcnts[i])
996 sh_pfc_err("orphan group %s\n", group->name);
997 else if (refcnts[i] > 1)
998 sh_pfc_warn("group %s referenced by %u functions\n",
999 group->name, refcnts[i]);
1000 }
1001
1002 kfree(refcnts);
1003
1004 /* Check config register descriptions */
1005 for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++)
1006 sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
1007
1008 /* Check drive strength registers */
1009 for (i = 0; info->drive_regs && info->drive_regs[i].reg; i++)
1010 sh_pfc_check_drive_reg(info, &info->drive_regs[i]);
1011
1012 /* Check bias registers */
1013 for (i = 0; info->bias_regs && info->bias_regs[i].puen; i++)
1014 sh_pfc_check_bias_reg(info, &info->bias_regs[i]);
1015
1016 /* Check ioctrl registers */
1017 for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++)
1018 sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg);
1019
1020 /* Check data registers */
1021 for (i = 0; info->data_regs && info->data_regs[i].reg; i++) {
1022 sh_pfc_check_reg(drvname, info->data_regs[i].reg);
1023 sh_pfc_check_reg_enums(drvname, info->data_regs[i].reg,
1024 info->data_regs[i].enum_ids,
1025 info->data_regs[i].reg_width);
1026 }
1027
1028 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
1029 /* Check function GPIOs */
1030 for (i = 0; i < info->nr_func_gpios; i++) {
1031 const struct pinmux_func *func = &info->func_gpios[i];
1032
1033 if (!func->name) {
1034 sh_pfc_err("empty function gpio %u\n", i);
1035 continue;
1036 }
1037 for (j = 0; j < i; j++) {
1038 if (same_name(func->name, info->func_gpios[j].name))
1039 sh_pfc_err("func_gpio %s: name conflict\n",
1040 func->name);
1041 }
1042 if (sh_pfc_check_enum(drvname, func->enum_id))
1043 sh_pfc_err("%s enum_id %u conflict\n", func->name,
1044 func->enum_id);
1045 }
1046 #endif
1047 }
1048
sh_pfc_check_driver(const struct platform_driver * pdrv)1049 static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
1050 {
1051 unsigned int i;
1052
1053 if (!IS_ENABLED(CONFIG_SUPERH) &&
1054 !of_find_matching_node(NULL, pdrv->driver.of_match_table))
1055 return;
1056
1057 sh_pfc_regs = kcalloc(SH_PFC_MAX_REGS, sizeof(*sh_pfc_regs),
1058 GFP_KERNEL);
1059 if (!sh_pfc_regs)
1060 return;
1061
1062 sh_pfc_enums = kcalloc(SH_PFC_MAX_ENUMS, sizeof(*sh_pfc_enums),
1063 GFP_KERNEL);
1064 if (!sh_pfc_enums)
1065 goto free_regs;
1066
1067 pr_warn("Checking builtin pinmux tables\n");
1068
1069 for (i = 0; pdrv->id_table[i].name[0]; i++)
1070 sh_pfc_check_info((void *)pdrv->id_table[i].driver_data);
1071
1072 #ifdef CONFIG_OF
1073 for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++)
1074 sh_pfc_check_info(pdrv->driver.of_match_table[i].data);
1075 #endif
1076
1077 pr_warn("Detected %u errors and %u warnings\n", sh_pfc_errors,
1078 sh_pfc_warnings);
1079
1080 kfree(sh_pfc_enums);
1081 free_regs:
1082 kfree(sh_pfc_regs);
1083 }
1084
1085 #else /* !DEBUG */
sh_pfc_check_driver(struct platform_driver * pdrv)1086 static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
1087 #endif /* !DEBUG */
1088
1089 #ifdef CONFIG_OF
sh_pfc_quirk_match(void)1090 static const void *sh_pfc_quirk_match(void)
1091 {
1092 #ifdef CONFIG_PINCTRL_PFC_R8A77950
1093 const struct soc_device_attribute *match;
1094 static const struct soc_device_attribute quirks[] = {
1095 {
1096 .soc_id = "r8a7795", .revision = "ES1.*",
1097 .data = &r8a77950_pinmux_info,
1098 },
1099 { /* sentinel */ }
1100 };
1101
1102 match = soc_device_match(quirks);
1103 if (match)
1104 return match->data;
1105 #endif /* CONFIG_PINCTRL_PFC_R8A77950 */
1106
1107 return NULL;
1108 }
1109 #endif /* CONFIG_OF */
1110
sh_pfc_probe(struct platform_device * pdev)1111 static int sh_pfc_probe(struct platform_device *pdev)
1112 {
1113 const struct sh_pfc_soc_info *info;
1114 struct sh_pfc *pfc;
1115 int ret;
1116
1117 #ifdef CONFIG_OF
1118 if (pdev->dev.of_node) {
1119 info = sh_pfc_quirk_match();
1120 if (!info)
1121 info = of_device_get_match_data(&pdev->dev);
1122 } else
1123 #endif
1124 info = (const void *)platform_get_device_id(pdev)->driver_data;
1125
1126 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
1127 if (pfc == NULL)
1128 return -ENOMEM;
1129
1130 pfc->info = info;
1131 pfc->dev = &pdev->dev;
1132
1133 ret = sh_pfc_map_resources(pfc, pdev);
1134 if (unlikely(ret < 0))
1135 return ret;
1136
1137 spin_lock_init(&pfc->lock);
1138
1139 if (info->ops && info->ops->init) {
1140 ret = info->ops->init(pfc);
1141 if (ret < 0)
1142 return ret;
1143
1144 /* .init() may have overridden pfc->info */
1145 info = pfc->info;
1146 }
1147
1148 ret = sh_pfc_suspend_init(pfc);
1149 if (ret)
1150 return ret;
1151
1152 /* Enable dummy states for those platforms without pinctrl support */
1153 if (!of_have_populated_dt())
1154 pinctrl_provide_dummies();
1155
1156 ret = sh_pfc_init_ranges(pfc);
1157 if (ret < 0)
1158 return ret;
1159
1160 /*
1161 * Initialize pinctrl bindings first
1162 */
1163 ret = sh_pfc_register_pinctrl(pfc);
1164 if (unlikely(ret != 0))
1165 return ret;
1166
1167 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
1168 /*
1169 * Then the GPIO chip
1170 */
1171 ret = sh_pfc_register_gpiochip(pfc);
1172 if (unlikely(ret != 0)) {
1173 /*
1174 * If the GPIO chip fails to come up we still leave the
1175 * PFC state as it is, given that there are already
1176 * extant users of it that have succeeded by this point.
1177 */
1178 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
1179 }
1180 #endif
1181
1182 platform_set_drvdata(pdev, pfc);
1183
1184 dev_info(pfc->dev, "%s support registered\n", info->name);
1185
1186 return 0;
1187 }
1188
1189 static const struct platform_device_id sh_pfc_id_table[] = {
1190 #ifdef CONFIG_PINCTRL_PFC_SH7203
1191 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
1192 #endif
1193 #ifdef CONFIG_PINCTRL_PFC_SH7264
1194 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
1195 #endif
1196 #ifdef CONFIG_PINCTRL_PFC_SH7269
1197 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
1198 #endif
1199 #ifdef CONFIG_PINCTRL_PFC_SH7720
1200 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
1201 #endif
1202 #ifdef CONFIG_PINCTRL_PFC_SH7722
1203 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
1204 #endif
1205 #ifdef CONFIG_PINCTRL_PFC_SH7723
1206 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
1207 #endif
1208 #ifdef CONFIG_PINCTRL_PFC_SH7724
1209 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
1210 #endif
1211 #ifdef CONFIG_PINCTRL_PFC_SH7734
1212 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
1213 #endif
1214 #ifdef CONFIG_PINCTRL_PFC_SH7757
1215 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
1216 #endif
1217 #ifdef CONFIG_PINCTRL_PFC_SH7785
1218 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
1219 #endif
1220 #ifdef CONFIG_PINCTRL_PFC_SH7786
1221 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
1222 #endif
1223 #ifdef CONFIG_PINCTRL_PFC_SHX3
1224 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
1225 #endif
1226 { },
1227 };
1228
1229 static struct platform_driver sh_pfc_driver = {
1230 .probe = sh_pfc_probe,
1231 .id_table = sh_pfc_id_table,
1232 .driver = {
1233 .name = DRV_NAME,
1234 .of_match_table = of_match_ptr(sh_pfc_of_table),
1235 .pm = DEV_PM_OPS,
1236 },
1237 };
1238
sh_pfc_init(void)1239 static int __init sh_pfc_init(void)
1240 {
1241 sh_pfc_check_driver(&sh_pfc_driver);
1242 return platform_driver_register(&sh_pfc_driver);
1243 }
1244 postcore_initcall(sh_pfc_init);
1245