1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 *
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
8 *
9 * See MAINTAINERS file for support contact information.
10 */
11
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/ethtool.h>
19 #include <linux/phy.h>
20 #include <linux/if_vlan.h>
21 #include <linux/in.h>
22 #include <linux/io.h>
23 #include <linux/ip.h>
24 #include <linux/tcp.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/bitfield.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <asm/unaligned.h>
32 #include <net/ip6_checksum.h>
33
34 #include "r8169.h"
35 #include "r8169_firmware.h"
36
37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
39 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
40 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
41 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
42 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
43 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
44 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
45 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
46 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
47 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
48 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
49 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
50 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
51 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
52 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
54 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
55 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
56 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
57 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
58 #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw"
59
60 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
61 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
62 #define MC_FILTER_LIMIT 32
63
64 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
65 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
66
67 #define R8169_REGS_SIZE 256
68 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
69 #define NUM_TX_DESC 256 /* Number of Tx descriptor registers */
70 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
71 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
72 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
73
74 #define OCP_STD_PHY_BASE 0xa400
75
76 #define RTL_CFG_NO_GBIT 1
77
78 /* write/read MMIO register */
79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
85
86 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
87 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
88 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
89 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
90
91 static const struct {
92 const char *name;
93 const char *fw_name;
94 } rtl_chip_infos[] = {
95 /* PCI devices. */
96 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
97 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
98 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
99 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
100 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
101 /* PCI-E devices. */
102 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
103 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
104 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" },
105 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
106 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
107 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
108 [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e" },
109 [RTL_GIGA_MAC_VER_14] = {"RTL8401" },
110 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
111 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
112 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
113 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
114 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
115 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
116 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
117 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
118 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
119 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
120 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
121 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
122 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
123 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
124 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
125 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
126 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
127 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
128 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
129 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
130 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
131 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
132 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
133 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
134 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
135 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
136 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3},
137 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2},
138 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 },
139 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
140 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
141 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
142 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
143 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
144 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
145 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
146 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3},
147 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", },
148 [RTL_GIGA_MAC_VER_60] = {"RTL8125A" },
149 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3},
150 /* reserve 62 for CFG_METHOD_4 in the vendor driver */
151 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2},
152 };
153
154 static const struct pci_device_id rtl8169_pci_tbl[] = {
155 { PCI_VDEVICE(REALTEK, 0x2502) },
156 { PCI_VDEVICE(REALTEK, 0x2600) },
157 { PCI_VDEVICE(REALTEK, 0x8129) },
158 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
159 { PCI_VDEVICE(REALTEK, 0x8161) },
160 { PCI_VDEVICE(REALTEK, 0x8162) },
161 { PCI_VDEVICE(REALTEK, 0x8167) },
162 { PCI_VDEVICE(REALTEK, 0x8168) },
163 { PCI_VDEVICE(NCUBE, 0x8168) },
164 { PCI_VDEVICE(REALTEK, 0x8169) },
165 { PCI_VENDOR_ID_DLINK, 0x4300,
166 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
167 { PCI_VDEVICE(DLINK, 0x4300) },
168 { PCI_VDEVICE(DLINK, 0x4302) },
169 { PCI_VDEVICE(AT, 0xc107) },
170 { PCI_VDEVICE(USR, 0x0116) },
171 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
172 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
173 { PCI_VDEVICE(REALTEK, 0x8125) },
174 { PCI_VDEVICE(REALTEK, 0x3000) },
175 {}
176 };
177
178 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
179
180 enum rtl_registers {
181 MAC0 = 0, /* Ethernet hardware address. */
182 MAC4 = 4,
183 MAR0 = 8, /* Multicast filter. */
184 CounterAddrLow = 0x10,
185 CounterAddrHigh = 0x14,
186 TxDescStartAddrLow = 0x20,
187 TxDescStartAddrHigh = 0x24,
188 TxHDescStartAddrLow = 0x28,
189 TxHDescStartAddrHigh = 0x2c,
190 FLASH = 0x30,
191 ERSR = 0x36,
192 ChipCmd = 0x37,
193 TxPoll = 0x38,
194 IntrMask = 0x3c,
195 IntrStatus = 0x3e,
196
197 TxConfig = 0x40,
198 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
199 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
200
201 RxConfig = 0x44,
202 #define RX128_INT_EN (1 << 15) /* 8111c and later */
203 #define RX_MULTI_EN (1 << 14) /* 8111c only */
204 #define RXCFG_FIFO_SHIFT 13
205 /* No threshold before first PCI xfer */
206 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
207 #define RX_EARLY_OFF (1 << 11)
208 #define RX_PAUSE_SLOT_ON (1 << 11) /* 8125b and later */
209 #define RXCFG_DMA_SHIFT 8
210 /* Unlimited maximum PCI burst. */
211 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
212
213 Cfg9346 = 0x50,
214 Config0 = 0x51,
215 Config1 = 0x52,
216 Config2 = 0x53,
217 #define PME_SIGNAL (1 << 5) /* 8168c and later */
218
219 Config3 = 0x54,
220 Config4 = 0x55,
221 Config5 = 0x56,
222 PHYAR = 0x60,
223 PHYstatus = 0x6c,
224 RxMaxSize = 0xda,
225 CPlusCmd = 0xe0,
226 IntrMitigate = 0xe2,
227
228 #define RTL_COALESCE_TX_USECS GENMASK(15, 12)
229 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8)
230 #define RTL_COALESCE_RX_USECS GENMASK(7, 4)
231 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0)
232
233 #define RTL_COALESCE_T_MAX 0x0fU
234 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4)
235
236 RxDescAddrLow = 0xe4,
237 RxDescAddrHigh = 0xe8,
238 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
239
240 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
241
242 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
243
244 #define TxPacketMax (8064 >> 7)
245 #define EarlySize 0x27
246
247 FuncEvent = 0xf0,
248 FuncEventMask = 0xf4,
249 FuncPresetState = 0xf8,
250 IBCR0 = 0xf8,
251 IBCR2 = 0xf9,
252 IBIMR0 = 0xfa,
253 IBISR0 = 0xfb,
254 FuncForceEvent = 0xfc,
255 };
256
257 enum rtl8168_8101_registers {
258 CSIDR = 0x64,
259 CSIAR = 0x68,
260 #define CSIAR_FLAG 0x80000000
261 #define CSIAR_WRITE_CMD 0x80000000
262 #define CSIAR_BYTE_ENABLE 0x0000f000
263 #define CSIAR_ADDR_MASK 0x00000fff
264 PMCH = 0x6f,
265 #define D3COLD_NO_PLL_DOWN BIT(7)
266 #define D3HOT_NO_PLL_DOWN BIT(6)
267 #define D3_NO_PLL_DOWN (BIT(7) | BIT(6))
268 EPHYAR = 0x80,
269 #define EPHYAR_FLAG 0x80000000
270 #define EPHYAR_WRITE_CMD 0x80000000
271 #define EPHYAR_REG_MASK 0x1f
272 #define EPHYAR_REG_SHIFT 16
273 #define EPHYAR_DATA_MASK 0xffff
274 DLLPR = 0xd0,
275 #define PFM_EN (1 << 6)
276 #define TX_10M_PS_EN (1 << 7)
277 DBG_REG = 0xd1,
278 #define FIX_NAK_1 (1 << 4)
279 #define FIX_NAK_2 (1 << 3)
280 TWSI = 0xd2,
281 MCU = 0xd3,
282 #define NOW_IS_OOB (1 << 7)
283 #define TX_EMPTY (1 << 5)
284 #define RX_EMPTY (1 << 4)
285 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
286 #define EN_NDP (1 << 3)
287 #define EN_OOB_RESET (1 << 2)
288 #define LINK_LIST_RDY (1 << 1)
289 EFUSEAR = 0xdc,
290 #define EFUSEAR_FLAG 0x80000000
291 #define EFUSEAR_WRITE_CMD 0x80000000
292 #define EFUSEAR_READ_CMD 0x00000000
293 #define EFUSEAR_REG_MASK 0x03ff
294 #define EFUSEAR_REG_SHIFT 8
295 #define EFUSEAR_DATA_MASK 0xff
296 MISC_1 = 0xf2,
297 #define PFM_D3COLD_EN (1 << 6)
298 };
299
300 enum rtl8168_registers {
301 LED_FREQ = 0x1a,
302 EEE_LED = 0x1b,
303 ERIDR = 0x70,
304 ERIAR = 0x74,
305 #define ERIAR_FLAG 0x80000000
306 #define ERIAR_WRITE_CMD 0x80000000
307 #define ERIAR_READ_CMD 0x00000000
308 #define ERIAR_ADDR_BYTE_ALIGN 4
309 #define ERIAR_TYPE_SHIFT 16
310 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
311 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
312 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
313 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
314 #define ERIAR_MASK_SHIFT 12
315 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
316 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
317 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
318 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
319 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
320 EPHY_RXER_NUM = 0x7c,
321 OCPDR = 0xb0, /* OCP GPHY access */
322 #define OCPDR_WRITE_CMD 0x80000000
323 #define OCPDR_READ_CMD 0x00000000
324 #define OCPDR_REG_MASK 0x7f
325 #define OCPDR_GPHY_REG_SHIFT 16
326 #define OCPDR_DATA_MASK 0xffff
327 OCPAR = 0xb4,
328 #define OCPAR_FLAG 0x80000000
329 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
330 #define OCPAR_GPHY_READ_CMD 0x0000f060
331 GPHY_OCP = 0xb8,
332 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
333 MISC = 0xf0, /* 8168e only. */
334 #define TXPLA_RST (1 << 29)
335 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
336 #define PWM_EN (1 << 22)
337 #define RXDV_GATED_EN (1 << 19)
338 #define EARLY_TALLY_EN (1 << 16)
339 };
340
341 enum rtl8125_registers {
342 IntrMask_8125 = 0x38,
343 IntrStatus_8125 = 0x3c,
344 TxPoll_8125 = 0x90,
345 MAC0_BKP = 0x19e0,
346 EEE_TXIDLE_TIMER_8125 = 0x6048,
347 };
348
349 #define RX_VLAN_INNER_8125 BIT(22)
350 #define RX_VLAN_OUTER_8125 BIT(23)
351 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
352
353 #define RX_FETCH_DFLT_8125 (8 << 27)
354
355 enum rtl_register_content {
356 /* InterruptStatusBits */
357 SYSErr = 0x8000,
358 PCSTimeout = 0x4000,
359 SWInt = 0x0100,
360 TxDescUnavail = 0x0080,
361 RxFIFOOver = 0x0040,
362 LinkChg = 0x0020,
363 RxOverflow = 0x0010,
364 TxErr = 0x0008,
365 TxOK = 0x0004,
366 RxErr = 0x0002,
367 RxOK = 0x0001,
368
369 /* RxStatusDesc */
370 RxRWT = (1 << 22),
371 RxRES = (1 << 21),
372 RxRUNT = (1 << 20),
373 RxCRC = (1 << 19),
374
375 /* ChipCmdBits */
376 StopReq = 0x80,
377 CmdReset = 0x10,
378 CmdRxEnb = 0x08,
379 CmdTxEnb = 0x04,
380 RxBufEmpty = 0x01,
381
382 /* TXPoll register p.5 */
383 HPQ = 0x80, /* Poll cmd on the high prio queue */
384 NPQ = 0x40, /* Poll cmd on the low prio queue */
385 FSWInt = 0x01, /* Forced software interrupt */
386
387 /* Cfg9346Bits */
388 Cfg9346_Lock = 0x00,
389 Cfg9346_Unlock = 0xc0,
390
391 /* rx_mode_bits */
392 AcceptErr = 0x20,
393 AcceptRunt = 0x10,
394 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30
395 AcceptBroadcast = 0x08,
396 AcceptMulticast = 0x04,
397 AcceptMyPhys = 0x02,
398 AcceptAllPhys = 0x01,
399 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f
400 #define RX_CONFIG_ACCEPT_MASK 0x3f
401
402 /* TxConfigBits */
403 TxInterFrameGapShift = 24,
404 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
405
406 /* Config1 register p.24 */
407 LEDS1 = (1 << 7),
408 LEDS0 = (1 << 6),
409 Speed_down = (1 << 4),
410 MEMMAP = (1 << 3),
411 IOMAP = (1 << 2),
412 VPD = (1 << 1),
413 PMEnable = (1 << 0), /* Power Management Enable */
414
415 /* Config2 register p. 25 */
416 ClkReqEn = (1 << 7), /* Clock Request Enable */
417 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
418 PCI_Clock_66MHz = 0x01,
419 PCI_Clock_33MHz = 0x00,
420
421 /* Config3 register p.25 */
422 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
423 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
424 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
425 Rdy_to_L23 = (1 << 1), /* L23 Enable */
426 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
427
428 /* Config4 register */
429 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
430
431 /* Config5 register p.27 */
432 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
433 MWF = (1 << 5), /* Accept Multicast wakeup frame */
434 UWF = (1 << 4), /* Accept Unicast wakeup frame */
435 Spi_en = (1 << 3),
436 LanWake = (1 << 1), /* LanWake enable/disable */
437 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
438 ASPM_en = (1 << 0), /* ASPM enable */
439
440 /* CPlusCmd p.31 */
441 EnableBist = (1 << 15), // 8168 8101
442 Mac_dbgo_oe = (1 << 14), // 8168 8101
443 EnAnaPLL = (1 << 14), // 8169
444 Normal_mode = (1 << 13), // unused
445 Force_half_dup = (1 << 12), // 8168 8101
446 Force_rxflow_en = (1 << 11), // 8168 8101
447 Force_txflow_en = (1 << 10), // 8168 8101
448 Cxpl_dbg_sel = (1 << 9), // 8168 8101
449 ASF = (1 << 8), // 8168 8101
450 PktCntrDisable = (1 << 7), // 8168 8101
451 Mac_dbgo_sel = 0x001c, // 8168
452 RxVlan = (1 << 6),
453 RxChkSum = (1 << 5),
454 PCIDAC = (1 << 4),
455 PCIMulRW = (1 << 3),
456 #define INTT_MASK GENMASK(1, 0)
457 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
458
459 /* rtl8169_PHYstatus */
460 TBI_Enable = 0x80,
461 TxFlowCtrl = 0x40,
462 RxFlowCtrl = 0x20,
463 _1000bpsF = 0x10,
464 _100bps = 0x08,
465 _10bps = 0x04,
466 LinkStatus = 0x02,
467 FullDup = 0x01,
468
469 /* ResetCounterCommand */
470 CounterReset = 0x1,
471
472 /* DumpCounterCommand */
473 CounterDump = 0x8,
474
475 /* magic enable v2 */
476 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
477 };
478
479 enum rtl_desc_bit {
480 /* First doubleword. */
481 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
482 RingEnd = (1 << 30), /* End of descriptor ring */
483 FirstFrag = (1 << 29), /* First segment of a packet */
484 LastFrag = (1 << 28), /* Final segment of a packet */
485 };
486
487 /* Generic case. */
488 enum rtl_tx_desc_bit {
489 /* First doubleword. */
490 TD_LSO = (1 << 27), /* Large Send Offload */
491 #define TD_MSS_MAX 0x07ffu /* MSS value */
492
493 /* Second doubleword. */
494 TxVlanTag = (1 << 17), /* Add VLAN tag */
495 };
496
497 /* 8169, 8168b and 810x except 8102e. */
498 enum rtl_tx_desc_bit_0 {
499 /* First doubleword. */
500 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
501 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
502 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
503 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
504 };
505
506 /* 8102e, 8168c and beyond. */
507 enum rtl_tx_desc_bit_1 {
508 /* First doubleword. */
509 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
510 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
511 #define GTTCPHO_SHIFT 18
512 #define GTTCPHO_MAX 0x7f
513
514 /* Second doubleword. */
515 #define TCPHO_SHIFT 18
516 #define TCPHO_MAX 0x3ff
517 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
518 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
519 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
520 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
521 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
522 };
523
524 enum rtl_rx_desc_bit {
525 /* Rx private */
526 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
527 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
528
529 #define RxProtoUDP (PID1)
530 #define RxProtoTCP (PID0)
531 #define RxProtoIP (PID1 | PID0)
532 #define RxProtoMask RxProtoIP
533
534 IPFail = (1 << 16), /* IP checksum failed */
535 UDPFail = (1 << 15), /* UDP/IP checksum failed */
536 TCPFail = (1 << 14), /* TCP/IP checksum failed */
537
538 #define RxCSFailMask (IPFail | UDPFail | TCPFail)
539
540 RxVlanTag = (1 << 16), /* VLAN tag available */
541 };
542
543 #define RTL_GSO_MAX_SIZE_V1 32000
544 #define RTL_GSO_MAX_SEGS_V1 24
545 #define RTL_GSO_MAX_SIZE_V2 64000
546 #define RTL_GSO_MAX_SEGS_V2 64
547
548 struct TxDesc {
549 __le32 opts1;
550 __le32 opts2;
551 __le64 addr;
552 };
553
554 struct RxDesc {
555 __le32 opts1;
556 __le32 opts2;
557 __le64 addr;
558 };
559
560 struct ring_info {
561 struct sk_buff *skb;
562 u32 len;
563 };
564
565 struct rtl8169_counters {
566 __le64 tx_packets;
567 __le64 rx_packets;
568 __le64 tx_errors;
569 __le32 rx_errors;
570 __le16 rx_missed;
571 __le16 align_errors;
572 __le32 tx_one_collision;
573 __le32 tx_multi_collision;
574 __le64 rx_unicast;
575 __le64 rx_broadcast;
576 __le32 rx_multicast;
577 __le16 tx_aborted;
578 __le16 tx_underun;
579 };
580
581 struct rtl8169_tc_offsets {
582 bool inited;
583 __le64 tx_errors;
584 __le32 tx_multi_collision;
585 __le16 tx_aborted;
586 __le16 rx_missed;
587 };
588
589 enum rtl_flag {
590 RTL_FLAG_TASK_ENABLED = 0,
591 RTL_FLAG_TASK_RESET_PENDING,
592 RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE,
593 RTL_FLAG_TASK_TX_TIMEOUT,
594 RTL_FLAG_MAX
595 };
596
597 enum rtl_dash_type {
598 RTL_DASH_NONE,
599 RTL_DASH_DP,
600 RTL_DASH_EP,
601 };
602
603 struct rtl8169_private {
604 void __iomem *mmio_addr; /* memory map physical address */
605 struct pci_dev *pci_dev;
606 struct net_device *dev;
607 struct phy_device *phydev;
608 struct napi_struct napi;
609 enum mac_version mac_version;
610 enum rtl_dash_type dash_type;
611 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
612 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
613 u32 dirty_tx;
614 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
615 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
616 dma_addr_t TxPhyAddr;
617 dma_addr_t RxPhyAddr;
618 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
619 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
620 u16 cp_cmd;
621 u32 irq_mask;
622 struct clk *clk;
623
624 struct {
625 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
626 struct work_struct work;
627 } wk;
628
629 unsigned supports_gmii:1;
630 unsigned aspm_manageable:1;
631 dma_addr_t counters_phys_addr;
632 struct rtl8169_counters *counters;
633 struct rtl8169_tc_offsets tc_offset;
634 u32 saved_wolopts;
635 int eee_adv;
636
637 const char *fw_name;
638 struct rtl_fw *rtl_fw;
639
640 u32 ocp_base;
641 };
642
643 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
644
645 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
646 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
647 MODULE_SOFTDEP("pre: realtek");
648 MODULE_LICENSE("GPL");
649 MODULE_FIRMWARE(FIRMWARE_8168D_1);
650 MODULE_FIRMWARE(FIRMWARE_8168D_2);
651 MODULE_FIRMWARE(FIRMWARE_8168E_1);
652 MODULE_FIRMWARE(FIRMWARE_8168E_2);
653 MODULE_FIRMWARE(FIRMWARE_8168E_3);
654 MODULE_FIRMWARE(FIRMWARE_8105E_1);
655 MODULE_FIRMWARE(FIRMWARE_8168F_1);
656 MODULE_FIRMWARE(FIRMWARE_8168F_2);
657 MODULE_FIRMWARE(FIRMWARE_8402_1);
658 MODULE_FIRMWARE(FIRMWARE_8411_1);
659 MODULE_FIRMWARE(FIRMWARE_8411_2);
660 MODULE_FIRMWARE(FIRMWARE_8106E_1);
661 MODULE_FIRMWARE(FIRMWARE_8106E_2);
662 MODULE_FIRMWARE(FIRMWARE_8168G_2);
663 MODULE_FIRMWARE(FIRMWARE_8168G_3);
664 MODULE_FIRMWARE(FIRMWARE_8168H_1);
665 MODULE_FIRMWARE(FIRMWARE_8168H_2);
666 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
667 MODULE_FIRMWARE(FIRMWARE_8107E_1);
668 MODULE_FIRMWARE(FIRMWARE_8107E_2);
669 MODULE_FIRMWARE(FIRMWARE_8125A_3);
670 MODULE_FIRMWARE(FIRMWARE_8125B_2);
671
tp_to_dev(struct rtl8169_private * tp)672 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
673 {
674 return &tp->pci_dev->dev;
675 }
676
rtl_lock_config_regs(struct rtl8169_private * tp)677 static void rtl_lock_config_regs(struct rtl8169_private *tp)
678 {
679 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
680 }
681
rtl_unlock_config_regs(struct rtl8169_private * tp)682 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
683 {
684 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
685 }
686
rtl_pci_commit(struct rtl8169_private * tp)687 static void rtl_pci_commit(struct rtl8169_private *tp)
688 {
689 /* Read an arbitrary register to commit a preceding PCI write */
690 RTL_R8(tp, ChipCmd);
691 }
692
rtl_is_8125(struct rtl8169_private * tp)693 static bool rtl_is_8125(struct rtl8169_private *tp)
694 {
695 return tp->mac_version >= RTL_GIGA_MAC_VER_60;
696 }
697
rtl_is_8168evl_up(struct rtl8169_private * tp)698 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
699 {
700 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
701 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
702 tp->mac_version <= RTL_GIGA_MAC_VER_53;
703 }
704
rtl_supports_eee(struct rtl8169_private * tp)705 static bool rtl_supports_eee(struct rtl8169_private *tp)
706 {
707 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
708 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
709 tp->mac_version != RTL_GIGA_MAC_VER_39;
710 }
711
rtl_read_mac_from_reg(struct rtl8169_private * tp,u8 * mac,int reg)712 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
713 {
714 int i;
715
716 for (i = 0; i < ETH_ALEN; i++)
717 mac[i] = RTL_R8(tp, reg + i);
718 }
719
720 struct rtl_cond {
721 bool (*check)(struct rtl8169_private *);
722 const char *msg;
723 };
724
rtl_loop_wait(struct rtl8169_private * tp,const struct rtl_cond * c,unsigned long usecs,int n,bool high)725 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
726 unsigned long usecs, int n, bool high)
727 {
728 int i;
729
730 for (i = 0; i < n; i++) {
731 if (c->check(tp) == high)
732 return true;
733 fsleep(usecs);
734 }
735
736 if (net_ratelimit())
737 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
738 c->msg, !high, n, usecs);
739 return false;
740 }
741
rtl_loop_wait_high(struct rtl8169_private * tp,const struct rtl_cond * c,unsigned long d,int n)742 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
743 const struct rtl_cond *c,
744 unsigned long d, int n)
745 {
746 return rtl_loop_wait(tp, c, d, n, true);
747 }
748
rtl_loop_wait_low(struct rtl8169_private * tp,const struct rtl_cond * c,unsigned long d,int n)749 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
750 const struct rtl_cond *c,
751 unsigned long d, int n)
752 {
753 return rtl_loop_wait(tp, c, d, n, false);
754 }
755
756 #define DECLARE_RTL_COND(name) \
757 static bool name ## _check(struct rtl8169_private *); \
758 \
759 static const struct rtl_cond name = { \
760 .check = name ## _check, \
761 .msg = #name \
762 }; \
763 \
764 static bool name ## _check(struct rtl8169_private *tp)
765
r8168fp_adjust_ocp_cmd(struct rtl8169_private * tp,u32 * cmd,int type)766 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
767 {
768 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */
769 if (type == ERIAR_OOB &&
770 (tp->mac_version == RTL_GIGA_MAC_VER_52 ||
771 tp->mac_version == RTL_GIGA_MAC_VER_53))
772 *cmd |= 0xf70 << 18;
773 }
774
DECLARE_RTL_COND(rtl_eriar_cond)775 DECLARE_RTL_COND(rtl_eriar_cond)
776 {
777 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
778 }
779
_rtl_eri_write(struct rtl8169_private * tp,int addr,u32 mask,u32 val,int type)780 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
781 u32 val, int type)
782 {
783 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
784
785 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
786 return;
787
788 RTL_W32(tp, ERIDR, val);
789 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
790 RTL_W32(tp, ERIAR, cmd);
791
792 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
793 }
794
rtl_eri_write(struct rtl8169_private * tp,int addr,u32 mask,u32 val)795 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
796 u32 val)
797 {
798 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
799 }
800
_rtl_eri_read(struct rtl8169_private * tp,int addr,int type)801 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
802 {
803 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
804
805 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
806 RTL_W32(tp, ERIAR, cmd);
807
808 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
809 RTL_R32(tp, ERIDR) : ~0;
810 }
811
rtl_eri_read(struct rtl8169_private * tp,int addr)812 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
813 {
814 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
815 }
816
rtl_w0w1_eri(struct rtl8169_private * tp,int addr,u32 p,u32 m)817 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
818 {
819 u32 val = rtl_eri_read(tp, addr);
820
821 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
822 }
823
rtl_eri_set_bits(struct rtl8169_private * tp,int addr,u32 p)824 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
825 {
826 rtl_w0w1_eri(tp, addr, p, 0);
827 }
828
rtl_eri_clear_bits(struct rtl8169_private * tp,int addr,u32 m)829 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
830 {
831 rtl_w0w1_eri(tp, addr, 0, m);
832 }
833
rtl_ocp_reg_failure(u32 reg)834 static bool rtl_ocp_reg_failure(u32 reg)
835 {
836 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
837 }
838
DECLARE_RTL_COND(rtl_ocp_gphy_cond)839 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
840 {
841 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
842 }
843
r8168_phy_ocp_write(struct rtl8169_private * tp,u32 reg,u32 data)844 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
845 {
846 if (rtl_ocp_reg_failure(reg))
847 return;
848
849 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
850
851 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
852 }
853
r8168_phy_ocp_read(struct rtl8169_private * tp,u32 reg)854 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
855 {
856 if (rtl_ocp_reg_failure(reg))
857 return 0;
858
859 RTL_W32(tp, GPHY_OCP, reg << 15);
860
861 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
862 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
863 }
864
r8168_mac_ocp_write(struct rtl8169_private * tp,u32 reg,u32 data)865 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
866 {
867 if (rtl_ocp_reg_failure(reg))
868 return;
869
870 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
871 }
872
r8168_mac_ocp_read(struct rtl8169_private * tp,u32 reg)873 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
874 {
875 if (rtl_ocp_reg_failure(reg))
876 return 0;
877
878 RTL_W32(tp, OCPDR, reg << 15);
879
880 return RTL_R32(tp, OCPDR);
881 }
882
r8168_mac_ocp_modify(struct rtl8169_private * tp,u32 reg,u16 mask,u16 set)883 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
884 u16 set)
885 {
886 u16 data = r8168_mac_ocp_read(tp, reg);
887
888 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
889 }
890
891 /* Work around a hw issue with RTL8168g PHY, the quirk disables
892 * PHY MCU interrupts before PHY power-down.
893 */
rtl8168g_phy_suspend_quirk(struct rtl8169_private * tp,int value)894 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
895 {
896 switch (tp->mac_version) {
897 case RTL_GIGA_MAC_VER_40:
898 case RTL_GIGA_MAC_VER_41:
899 case RTL_GIGA_MAC_VER_49:
900 if (value & BMCR_RESET || !(value & BMCR_PDOWN))
901 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
902 else
903 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
904 break;
905 default:
906 break;
907 }
908 };
909
r8168g_mdio_write(struct rtl8169_private * tp,int reg,int value)910 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
911 {
912 if (reg == 0x1f) {
913 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
914 return;
915 }
916
917 if (tp->ocp_base != OCP_STD_PHY_BASE)
918 reg -= 0x10;
919
920 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
921 rtl8168g_phy_suspend_quirk(tp, value);
922
923 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
924 }
925
r8168g_mdio_read(struct rtl8169_private * tp,int reg)926 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
927 {
928 if (reg == 0x1f)
929 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
930
931 if (tp->ocp_base != OCP_STD_PHY_BASE)
932 reg -= 0x10;
933
934 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
935 }
936
mac_mcu_write(struct rtl8169_private * tp,int reg,int value)937 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
938 {
939 if (reg == 0x1f) {
940 tp->ocp_base = value << 4;
941 return;
942 }
943
944 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
945 }
946
mac_mcu_read(struct rtl8169_private * tp,int reg)947 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
948 {
949 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
950 }
951
DECLARE_RTL_COND(rtl_phyar_cond)952 DECLARE_RTL_COND(rtl_phyar_cond)
953 {
954 return RTL_R32(tp, PHYAR) & 0x80000000;
955 }
956
r8169_mdio_write(struct rtl8169_private * tp,int reg,int value)957 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
958 {
959 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
960
961 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
962 /*
963 * According to hardware specs a 20us delay is required after write
964 * complete indication, but before sending next command.
965 */
966 udelay(20);
967 }
968
r8169_mdio_read(struct rtl8169_private * tp,int reg)969 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
970 {
971 int value;
972
973 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
974
975 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
976 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
977
978 /*
979 * According to hardware specs a 20us delay is required after read
980 * complete indication, but before sending next command.
981 */
982 udelay(20);
983
984 return value;
985 }
986
DECLARE_RTL_COND(rtl_ocpar_cond)987 DECLARE_RTL_COND(rtl_ocpar_cond)
988 {
989 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
990 }
991
r8168dp_1_mdio_access(struct rtl8169_private * tp,int reg,u32 data)992 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
993 {
994 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
995 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
996 RTL_W32(tp, EPHY_RXER_NUM, 0);
997
998 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
999 }
1000
r8168dp_1_mdio_write(struct rtl8169_private * tp,int reg,int value)1001 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1002 {
1003 r8168dp_1_mdio_access(tp, reg,
1004 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1005 }
1006
r8168dp_1_mdio_read(struct rtl8169_private * tp,int reg)1007 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1008 {
1009 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1010
1011 mdelay(1);
1012 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1013 RTL_W32(tp, EPHY_RXER_NUM, 0);
1014
1015 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1016 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
1017 }
1018
1019 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1020
r8168dp_2_mdio_start(struct rtl8169_private * tp)1021 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1022 {
1023 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1024 }
1025
r8168dp_2_mdio_stop(struct rtl8169_private * tp)1026 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1027 {
1028 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1029 }
1030
r8168dp_2_mdio_write(struct rtl8169_private * tp,int reg,int value)1031 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1032 {
1033 r8168dp_2_mdio_start(tp);
1034
1035 r8169_mdio_write(tp, reg, value);
1036
1037 r8168dp_2_mdio_stop(tp);
1038 }
1039
r8168dp_2_mdio_read(struct rtl8169_private * tp,int reg)1040 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1041 {
1042 int value;
1043
1044 /* Work around issue with chip reporting wrong PHY ID */
1045 if (reg == MII_PHYSID2)
1046 return 0xc912;
1047
1048 r8168dp_2_mdio_start(tp);
1049
1050 value = r8169_mdio_read(tp, reg);
1051
1052 r8168dp_2_mdio_stop(tp);
1053
1054 return value;
1055 }
1056
rtl_writephy(struct rtl8169_private * tp,int location,int val)1057 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1058 {
1059 switch (tp->mac_version) {
1060 case RTL_GIGA_MAC_VER_27:
1061 r8168dp_1_mdio_write(tp, location, val);
1062 break;
1063 case RTL_GIGA_MAC_VER_28:
1064 case RTL_GIGA_MAC_VER_31:
1065 r8168dp_2_mdio_write(tp, location, val);
1066 break;
1067 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1068 r8168g_mdio_write(tp, location, val);
1069 break;
1070 default:
1071 r8169_mdio_write(tp, location, val);
1072 break;
1073 }
1074 }
1075
rtl_readphy(struct rtl8169_private * tp,int location)1076 static int rtl_readphy(struct rtl8169_private *tp, int location)
1077 {
1078 switch (tp->mac_version) {
1079 case RTL_GIGA_MAC_VER_27:
1080 return r8168dp_1_mdio_read(tp, location);
1081 case RTL_GIGA_MAC_VER_28:
1082 case RTL_GIGA_MAC_VER_31:
1083 return r8168dp_2_mdio_read(tp, location);
1084 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1085 return r8168g_mdio_read(tp, location);
1086 default:
1087 return r8169_mdio_read(tp, location);
1088 }
1089 }
1090
DECLARE_RTL_COND(rtl_ephyar_cond)1091 DECLARE_RTL_COND(rtl_ephyar_cond)
1092 {
1093 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1094 }
1095
rtl_ephy_write(struct rtl8169_private * tp,int reg_addr,int value)1096 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1097 {
1098 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1099 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1100
1101 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1102
1103 udelay(10);
1104 }
1105
rtl_ephy_read(struct rtl8169_private * tp,int reg_addr)1106 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1107 {
1108 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1109
1110 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1111 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1112 }
1113
r8168dp_ocp_read(struct rtl8169_private * tp,u16 reg)1114 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1115 {
1116 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1117 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1118 RTL_R32(tp, OCPDR) : ~0;
1119 }
1120
r8168ep_ocp_read(struct rtl8169_private * tp,u16 reg)1121 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1122 {
1123 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1124 }
1125
r8168dp_ocp_write(struct rtl8169_private * tp,u8 mask,u16 reg,u32 data)1126 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1127 u32 data)
1128 {
1129 RTL_W32(tp, OCPDR, data);
1130 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1131 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1132 }
1133
r8168ep_ocp_write(struct rtl8169_private * tp,u8 mask,u16 reg,u32 data)1134 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1135 u32 data)
1136 {
1137 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1138 data, ERIAR_OOB);
1139 }
1140
r8168dp_oob_notify(struct rtl8169_private * tp,u8 cmd)1141 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1142 {
1143 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1144
1145 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1146 }
1147
1148 #define OOB_CMD_RESET 0x00
1149 #define OOB_CMD_DRIVER_START 0x05
1150 #define OOB_CMD_DRIVER_STOP 0x06
1151
rtl8168_get_ocp_reg(struct rtl8169_private * tp)1152 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1153 {
1154 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1155 }
1156
DECLARE_RTL_COND(rtl_dp_ocp_read_cond)1157 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1158 {
1159 u16 reg;
1160
1161 reg = rtl8168_get_ocp_reg(tp);
1162
1163 return r8168dp_ocp_read(tp, reg) & 0x00000800;
1164 }
1165
DECLARE_RTL_COND(rtl_ep_ocp_read_cond)1166 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1167 {
1168 return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1169 }
1170
DECLARE_RTL_COND(rtl_ocp_tx_cond)1171 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1172 {
1173 return RTL_R8(tp, IBISR0) & 0x20;
1174 }
1175
rtl8168ep_stop_cmac(struct rtl8169_private * tp)1176 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1177 {
1178 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1179 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1180 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1181 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1182 }
1183
rtl8168dp_driver_start(struct rtl8169_private * tp)1184 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1185 {
1186 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1187 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1188 }
1189
rtl8168ep_driver_start(struct rtl8169_private * tp)1190 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1191 {
1192 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1193 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1194 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30);
1195 }
1196
rtl8168_driver_start(struct rtl8169_private * tp)1197 static void rtl8168_driver_start(struct rtl8169_private *tp)
1198 {
1199 if (tp->dash_type == RTL_DASH_DP)
1200 rtl8168dp_driver_start(tp);
1201 else
1202 rtl8168ep_driver_start(tp);
1203 }
1204
rtl8168dp_driver_stop(struct rtl8169_private * tp)1205 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1206 {
1207 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1208 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1209 }
1210
rtl8168ep_driver_stop(struct rtl8169_private * tp)1211 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1212 {
1213 rtl8168ep_stop_cmac(tp);
1214 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1215 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1216 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1217 }
1218
rtl8168_driver_stop(struct rtl8169_private * tp)1219 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1220 {
1221 if (tp->dash_type == RTL_DASH_DP)
1222 rtl8168dp_driver_stop(tp);
1223 else
1224 rtl8168ep_driver_stop(tp);
1225 }
1226
r8168dp_check_dash(struct rtl8169_private * tp)1227 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1228 {
1229 u16 reg = rtl8168_get_ocp_reg(tp);
1230
1231 return r8168dp_ocp_read(tp, reg) & BIT(15);
1232 }
1233
r8168ep_check_dash(struct rtl8169_private * tp)1234 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1235 {
1236 return r8168ep_ocp_read(tp, 0x128) & BIT(0);
1237 }
1238
rtl_check_dash(struct rtl8169_private * tp)1239 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp)
1240 {
1241 switch (tp->mac_version) {
1242 case RTL_GIGA_MAC_VER_27:
1243 case RTL_GIGA_MAC_VER_28:
1244 case RTL_GIGA_MAC_VER_31:
1245 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE;
1246 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53:
1247 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE;
1248 default:
1249 return RTL_DASH_NONE;
1250 }
1251 }
1252
rtl_set_d3_pll_down(struct rtl8169_private * tp,bool enable)1253 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1254 {
1255 switch (tp->mac_version) {
1256 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
1257 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
1258 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
1259 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1260 if (enable)
1261 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
1262 else
1263 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);
1264 break;
1265 default:
1266 break;
1267 }
1268 }
1269
rtl_reset_packet_filter(struct rtl8169_private * tp)1270 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1271 {
1272 rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1273 rtl_eri_set_bits(tp, 0xdc, BIT(0));
1274 }
1275
DECLARE_RTL_COND(rtl_efusear_cond)1276 DECLARE_RTL_COND(rtl_efusear_cond)
1277 {
1278 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1279 }
1280
rtl8168d_efuse_read(struct rtl8169_private * tp,int reg_addr)1281 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1282 {
1283 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1284
1285 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1286 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1287 }
1288
rtl_get_events(struct rtl8169_private * tp)1289 static u32 rtl_get_events(struct rtl8169_private *tp)
1290 {
1291 if (rtl_is_8125(tp))
1292 return RTL_R32(tp, IntrStatus_8125);
1293 else
1294 return RTL_R16(tp, IntrStatus);
1295 }
1296
rtl_ack_events(struct rtl8169_private * tp,u32 bits)1297 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1298 {
1299 if (rtl_is_8125(tp))
1300 RTL_W32(tp, IntrStatus_8125, bits);
1301 else
1302 RTL_W16(tp, IntrStatus, bits);
1303 }
1304
rtl_irq_disable(struct rtl8169_private * tp)1305 static void rtl_irq_disable(struct rtl8169_private *tp)
1306 {
1307 if (rtl_is_8125(tp))
1308 RTL_W32(tp, IntrMask_8125, 0);
1309 else
1310 RTL_W16(tp, IntrMask, 0);
1311 }
1312
rtl_irq_enable(struct rtl8169_private * tp)1313 static void rtl_irq_enable(struct rtl8169_private *tp)
1314 {
1315 if (rtl_is_8125(tp))
1316 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1317 else
1318 RTL_W16(tp, IntrMask, tp->irq_mask);
1319 }
1320
rtl8169_irq_mask_and_ack(struct rtl8169_private * tp)1321 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1322 {
1323 rtl_irq_disable(tp);
1324 rtl_ack_events(tp, 0xffffffff);
1325 rtl_pci_commit(tp);
1326 }
1327
rtl_link_chg_patch(struct rtl8169_private * tp)1328 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1329 {
1330 struct phy_device *phydev = tp->phydev;
1331
1332 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1333 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1334 if (phydev->speed == SPEED_1000) {
1335 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1336 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1337 } else if (phydev->speed == SPEED_100) {
1338 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1339 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1340 } else {
1341 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1342 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1343 }
1344 rtl_reset_packet_filter(tp);
1345 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1346 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1347 if (phydev->speed == SPEED_1000) {
1348 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1349 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1350 } else {
1351 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1352 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1353 }
1354 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1355 if (phydev->speed == SPEED_10) {
1356 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1357 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1358 } else {
1359 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1360 }
1361 }
1362 }
1363
1364 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1365
rtl8169_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)1366 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1367 {
1368 struct rtl8169_private *tp = netdev_priv(dev);
1369
1370 wol->supported = WAKE_ANY;
1371 wol->wolopts = tp->saved_wolopts;
1372 }
1373
__rtl8169_set_wol(struct rtl8169_private * tp,u32 wolopts)1374 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1375 {
1376 static const struct {
1377 u32 opt;
1378 u16 reg;
1379 u8 mask;
1380 } cfg[] = {
1381 { WAKE_PHY, Config3, LinkUp },
1382 { WAKE_UCAST, Config5, UWF },
1383 { WAKE_BCAST, Config5, BWF },
1384 { WAKE_MCAST, Config5, MWF },
1385 { WAKE_ANY, Config5, LanWake },
1386 { WAKE_MAGIC, Config3, MagicPacket }
1387 };
1388 unsigned int i, tmp = ARRAY_SIZE(cfg);
1389 u8 options;
1390
1391 rtl_unlock_config_regs(tp);
1392
1393 if (rtl_is_8168evl_up(tp)) {
1394 tmp--;
1395 if (wolopts & WAKE_MAGIC)
1396 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1397 else
1398 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1399 } else if (rtl_is_8125(tp)) {
1400 tmp--;
1401 if (wolopts & WAKE_MAGIC)
1402 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1403 else
1404 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1405 }
1406
1407 for (i = 0; i < tmp; i++) {
1408 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1409 if (wolopts & cfg[i].opt)
1410 options |= cfg[i].mask;
1411 RTL_W8(tp, cfg[i].reg, options);
1412 }
1413
1414 switch (tp->mac_version) {
1415 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1416 options = RTL_R8(tp, Config1) & ~PMEnable;
1417 if (wolopts)
1418 options |= PMEnable;
1419 RTL_W8(tp, Config1, options);
1420 break;
1421 case RTL_GIGA_MAC_VER_34:
1422 case RTL_GIGA_MAC_VER_37:
1423 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1424 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1425 if (wolopts)
1426 options |= PME_SIGNAL;
1427 RTL_W8(tp, Config2, options);
1428 break;
1429 default:
1430 break;
1431 }
1432
1433 rtl_lock_config_regs(tp);
1434
1435 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1436 rtl_set_d3_pll_down(tp, !wolopts);
1437 tp->dev->wol_enabled = wolopts ? 1 : 0;
1438 }
1439
rtl8169_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)1440 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1441 {
1442 struct rtl8169_private *tp = netdev_priv(dev);
1443
1444 if (wol->wolopts & ~WAKE_ANY)
1445 return -EINVAL;
1446
1447 tp->saved_wolopts = wol->wolopts;
1448 __rtl8169_set_wol(tp, tp->saved_wolopts);
1449
1450 return 0;
1451 }
1452
rtl8169_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1453 static void rtl8169_get_drvinfo(struct net_device *dev,
1454 struct ethtool_drvinfo *info)
1455 {
1456 struct rtl8169_private *tp = netdev_priv(dev);
1457 struct rtl_fw *rtl_fw = tp->rtl_fw;
1458
1459 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1460 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1461 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1462 if (rtl_fw)
1463 strlcpy(info->fw_version, rtl_fw->version,
1464 sizeof(info->fw_version));
1465 }
1466
rtl8169_get_regs_len(struct net_device * dev)1467 static int rtl8169_get_regs_len(struct net_device *dev)
1468 {
1469 return R8169_REGS_SIZE;
1470 }
1471
rtl8169_fix_features(struct net_device * dev,netdev_features_t features)1472 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1473 netdev_features_t features)
1474 {
1475 struct rtl8169_private *tp = netdev_priv(dev);
1476
1477 if (dev->mtu > TD_MSS_MAX)
1478 features &= ~NETIF_F_ALL_TSO;
1479
1480 if (dev->mtu > ETH_DATA_LEN &&
1481 tp->mac_version > RTL_GIGA_MAC_VER_06)
1482 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1483
1484 return features;
1485 }
1486
rtl_set_rx_config_features(struct rtl8169_private * tp,netdev_features_t features)1487 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1488 netdev_features_t features)
1489 {
1490 u32 rx_config = RTL_R32(tp, RxConfig);
1491
1492 if (features & NETIF_F_RXALL)
1493 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1494 else
1495 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1496
1497 if (rtl_is_8125(tp)) {
1498 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1499 rx_config |= RX_VLAN_8125;
1500 else
1501 rx_config &= ~RX_VLAN_8125;
1502 }
1503
1504 RTL_W32(tp, RxConfig, rx_config);
1505 }
1506
rtl8169_set_features(struct net_device * dev,netdev_features_t features)1507 static int rtl8169_set_features(struct net_device *dev,
1508 netdev_features_t features)
1509 {
1510 struct rtl8169_private *tp = netdev_priv(dev);
1511
1512 rtl_set_rx_config_features(tp, features);
1513
1514 if (features & NETIF_F_RXCSUM)
1515 tp->cp_cmd |= RxChkSum;
1516 else
1517 tp->cp_cmd &= ~RxChkSum;
1518
1519 if (!rtl_is_8125(tp)) {
1520 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1521 tp->cp_cmd |= RxVlan;
1522 else
1523 tp->cp_cmd &= ~RxVlan;
1524 }
1525
1526 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1527 rtl_pci_commit(tp);
1528
1529 return 0;
1530 }
1531
rtl8169_tx_vlan_tag(struct sk_buff * skb)1532 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1533 {
1534 return (skb_vlan_tag_present(skb)) ?
1535 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1536 }
1537
rtl8169_rx_vlan_tag(struct RxDesc * desc,struct sk_buff * skb)1538 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1539 {
1540 u32 opts2 = le32_to_cpu(desc->opts2);
1541
1542 if (opts2 & RxVlanTag)
1543 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1544 }
1545
rtl8169_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * p)1546 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1547 void *p)
1548 {
1549 struct rtl8169_private *tp = netdev_priv(dev);
1550 u32 __iomem *data = tp->mmio_addr;
1551 u32 *dw = p;
1552 int i;
1553
1554 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1555 memcpy_fromio(dw++, data++, 4);
1556 }
1557
1558 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1559 "tx_packets",
1560 "rx_packets",
1561 "tx_errors",
1562 "rx_errors",
1563 "rx_missed",
1564 "align_errors",
1565 "tx_single_collisions",
1566 "tx_multi_collisions",
1567 "unicast",
1568 "broadcast",
1569 "multicast",
1570 "tx_aborted",
1571 "tx_underrun",
1572 };
1573
rtl8169_get_sset_count(struct net_device * dev,int sset)1574 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1575 {
1576 switch (sset) {
1577 case ETH_SS_STATS:
1578 return ARRAY_SIZE(rtl8169_gstrings);
1579 default:
1580 return -EOPNOTSUPP;
1581 }
1582 }
1583
DECLARE_RTL_COND(rtl_counters_cond)1584 DECLARE_RTL_COND(rtl_counters_cond)
1585 {
1586 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1587 }
1588
rtl8169_do_counters(struct rtl8169_private * tp,u32 counter_cmd)1589 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1590 {
1591 u32 cmd = lower_32_bits(tp->counters_phys_addr);
1592
1593 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
1594 rtl_pci_commit(tp);
1595 RTL_W32(tp, CounterAddrLow, cmd);
1596 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1597
1598 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1599 }
1600
rtl8169_update_counters(struct rtl8169_private * tp)1601 static void rtl8169_update_counters(struct rtl8169_private *tp)
1602 {
1603 u8 val = RTL_R8(tp, ChipCmd);
1604
1605 /*
1606 * Some chips are unable to dump tally counters when the receiver
1607 * is disabled. If 0xff chip may be in a PCI power-save state.
1608 */
1609 if (val & CmdRxEnb && val != 0xff)
1610 rtl8169_do_counters(tp, CounterDump);
1611 }
1612
rtl8169_init_counter_offsets(struct rtl8169_private * tp)1613 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1614 {
1615 struct rtl8169_counters *counters = tp->counters;
1616
1617 /*
1618 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1619 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1620 * reset by a power cycle, while the counter values collected by the
1621 * driver are reset at every driver unload/load cycle.
1622 *
1623 * To make sure the HW values returned by @get_stats64 match the SW
1624 * values, we collect the initial values at first open(*) and use them
1625 * as offsets to normalize the values returned by @get_stats64.
1626 *
1627 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1628 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1629 * set at open time by rtl_hw_start.
1630 */
1631
1632 if (tp->tc_offset.inited)
1633 return;
1634
1635 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1636 rtl8169_do_counters(tp, CounterReset);
1637 } else {
1638 rtl8169_update_counters(tp);
1639 tp->tc_offset.tx_errors = counters->tx_errors;
1640 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1641 tp->tc_offset.tx_aborted = counters->tx_aborted;
1642 tp->tc_offset.rx_missed = counters->rx_missed;
1643 }
1644
1645 tp->tc_offset.inited = true;
1646 }
1647
rtl8169_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)1648 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1649 struct ethtool_stats *stats, u64 *data)
1650 {
1651 struct rtl8169_private *tp = netdev_priv(dev);
1652 struct rtl8169_counters *counters;
1653
1654 counters = tp->counters;
1655 rtl8169_update_counters(tp);
1656
1657 data[0] = le64_to_cpu(counters->tx_packets);
1658 data[1] = le64_to_cpu(counters->rx_packets);
1659 data[2] = le64_to_cpu(counters->tx_errors);
1660 data[3] = le32_to_cpu(counters->rx_errors);
1661 data[4] = le16_to_cpu(counters->rx_missed);
1662 data[5] = le16_to_cpu(counters->align_errors);
1663 data[6] = le32_to_cpu(counters->tx_one_collision);
1664 data[7] = le32_to_cpu(counters->tx_multi_collision);
1665 data[8] = le64_to_cpu(counters->rx_unicast);
1666 data[9] = le64_to_cpu(counters->rx_broadcast);
1667 data[10] = le32_to_cpu(counters->rx_multicast);
1668 data[11] = le16_to_cpu(counters->tx_aborted);
1669 data[12] = le16_to_cpu(counters->tx_underun);
1670 }
1671
rtl8169_get_strings(struct net_device * dev,u32 stringset,u8 * data)1672 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1673 {
1674 switch(stringset) {
1675 case ETH_SS_STATS:
1676 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
1677 break;
1678 }
1679 }
1680
1681 /*
1682 * Interrupt coalescing
1683 *
1684 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1685 * > 8169, 8168 and 810x line of chipsets
1686 *
1687 * 8169, 8168, and 8136(810x) serial chipsets support it.
1688 *
1689 * > 2 - the Tx timer unit at gigabit speed
1690 *
1691 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1692 * (0xe0) bit 1 and bit 0.
1693 *
1694 * For 8169
1695 * bit[1:0] \ speed 1000M 100M 10M
1696 * 0 0 320ns 2.56us 40.96us
1697 * 0 1 2.56us 20.48us 327.7us
1698 * 1 0 5.12us 40.96us 655.4us
1699 * 1 1 10.24us 81.92us 1.31ms
1700 *
1701 * For the other
1702 * bit[1:0] \ speed 1000M 100M 10M
1703 * 0 0 5us 2.56us 40.96us
1704 * 0 1 40us 20.48us 327.7us
1705 * 1 0 80us 40.96us 655.4us
1706 * 1 1 160us 81.92us 1.31ms
1707 */
1708
1709 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1710 struct rtl_coalesce_info {
1711 u32 speed;
1712 u32 scale_nsecs[4];
1713 };
1714
1715 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1716 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1717
1718 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1719 { SPEED_1000, COALESCE_DELAY(320) },
1720 { SPEED_100, COALESCE_DELAY(2560) },
1721 { SPEED_10, COALESCE_DELAY(40960) },
1722 { 0 },
1723 };
1724
1725 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1726 { SPEED_1000, COALESCE_DELAY(5000) },
1727 { SPEED_100, COALESCE_DELAY(2560) },
1728 { SPEED_10, COALESCE_DELAY(40960) },
1729 { 0 },
1730 };
1731 #undef COALESCE_DELAY
1732
1733 /* get rx/tx scale vector corresponding to current speed */
1734 static const struct rtl_coalesce_info *
rtl_coalesce_info(struct rtl8169_private * tp)1735 rtl_coalesce_info(struct rtl8169_private *tp)
1736 {
1737 const struct rtl_coalesce_info *ci;
1738
1739 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1740 ci = rtl_coalesce_info_8169;
1741 else
1742 ci = rtl_coalesce_info_8168_8136;
1743
1744 /* if speed is unknown assume highest one */
1745 if (tp->phydev->speed == SPEED_UNKNOWN)
1746 return ci;
1747
1748 for (; ci->speed; ci++) {
1749 if (tp->phydev->speed == ci->speed)
1750 return ci;
1751 }
1752
1753 return ERR_PTR(-ELNRNG);
1754 }
1755
rtl_get_coalesce(struct net_device * dev,struct ethtool_coalesce * ec,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)1756 static int rtl_get_coalesce(struct net_device *dev,
1757 struct ethtool_coalesce *ec,
1758 struct kernel_ethtool_coalesce *kernel_coal,
1759 struct netlink_ext_ack *extack)
1760 {
1761 struct rtl8169_private *tp = netdev_priv(dev);
1762 const struct rtl_coalesce_info *ci;
1763 u32 scale, c_us, c_fr;
1764 u16 intrmit;
1765
1766 if (rtl_is_8125(tp))
1767 return -EOPNOTSUPP;
1768
1769 memset(ec, 0, sizeof(*ec));
1770
1771 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1772 ci = rtl_coalesce_info(tp);
1773 if (IS_ERR(ci))
1774 return PTR_ERR(ci);
1775
1776 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1777
1778 intrmit = RTL_R16(tp, IntrMitigate);
1779
1780 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1781 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1782
1783 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1784 /* ethtool_coalesce states usecs and max_frames must not both be 0 */
1785 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1786
1787 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1788 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1789
1790 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1791 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1792
1793 return 0;
1794 }
1795
1796 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
rtl_coalesce_choose_scale(struct rtl8169_private * tp,u32 usec,u16 * cp01)1797 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1798 u16 *cp01)
1799 {
1800 const struct rtl_coalesce_info *ci;
1801 u16 i;
1802
1803 ci = rtl_coalesce_info(tp);
1804 if (IS_ERR(ci))
1805 return PTR_ERR(ci);
1806
1807 for (i = 0; i < 4; i++) {
1808 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1809 *cp01 = i;
1810 return ci->scale_nsecs[i];
1811 }
1812 }
1813
1814 return -ERANGE;
1815 }
1816
rtl_set_coalesce(struct net_device * dev,struct ethtool_coalesce * ec,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)1817 static int rtl_set_coalesce(struct net_device *dev,
1818 struct ethtool_coalesce *ec,
1819 struct kernel_ethtool_coalesce *kernel_coal,
1820 struct netlink_ext_ack *extack)
1821 {
1822 struct rtl8169_private *tp = netdev_priv(dev);
1823 u32 tx_fr = ec->tx_max_coalesced_frames;
1824 u32 rx_fr = ec->rx_max_coalesced_frames;
1825 u32 coal_usec_max, units;
1826 u16 w = 0, cp01 = 0;
1827 int scale;
1828
1829 if (rtl_is_8125(tp))
1830 return -EOPNOTSUPP;
1831
1832 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1833 return -ERANGE;
1834
1835 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1836 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1837 if (scale < 0)
1838 return scale;
1839
1840 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
1841 * not only when usecs=0 because of e.g. the following scenario:
1842 *
1843 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1844 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1845 * - then user does `ethtool -C eth0 rx-usecs 100`
1846 *
1847 * Since ethtool sends to kernel whole ethtool_coalesce settings,
1848 * if we want to ignore rx_frames then it has to be set to 0.
1849 */
1850 if (rx_fr == 1)
1851 rx_fr = 0;
1852 if (tx_fr == 1)
1853 tx_fr = 0;
1854
1855 /* HW requires time limit to be set if frame limit is set */
1856 if ((tx_fr && !ec->tx_coalesce_usecs) ||
1857 (rx_fr && !ec->rx_coalesce_usecs))
1858 return -EINVAL;
1859
1860 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
1861 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
1862
1863 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
1864 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
1865 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
1866 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
1867
1868 RTL_W16(tp, IntrMitigate, w);
1869
1870 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
1871 if (rtl_is_8168evl_up(tp)) {
1872 if (!rx_fr && !tx_fr)
1873 /* disable packet counter */
1874 tp->cp_cmd |= PktCntrDisable;
1875 else
1876 tp->cp_cmd &= ~PktCntrDisable;
1877 }
1878
1879 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1880 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1881 rtl_pci_commit(tp);
1882
1883 return 0;
1884 }
1885
rtl8169_get_eee(struct net_device * dev,struct ethtool_eee * data)1886 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1887 {
1888 struct rtl8169_private *tp = netdev_priv(dev);
1889
1890 if (!rtl_supports_eee(tp))
1891 return -EOPNOTSUPP;
1892
1893 return phy_ethtool_get_eee(tp->phydev, data);
1894 }
1895
rtl8169_set_eee(struct net_device * dev,struct ethtool_eee * data)1896 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1897 {
1898 struct rtl8169_private *tp = netdev_priv(dev);
1899 int ret;
1900
1901 if (!rtl_supports_eee(tp))
1902 return -EOPNOTSUPP;
1903
1904 ret = phy_ethtool_set_eee(tp->phydev, data);
1905
1906 if (!ret)
1907 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1908 MDIO_AN_EEE_ADV);
1909 return ret;
1910 }
1911
rtl8169_get_ringparam(struct net_device * dev,struct ethtool_ringparam * data)1912 static void rtl8169_get_ringparam(struct net_device *dev,
1913 struct ethtool_ringparam *data)
1914 {
1915 data->rx_max_pending = NUM_RX_DESC;
1916 data->rx_pending = NUM_RX_DESC;
1917 data->tx_max_pending = NUM_TX_DESC;
1918 data->tx_pending = NUM_TX_DESC;
1919 }
1920
rtl8169_get_pauseparam(struct net_device * dev,struct ethtool_pauseparam * data)1921 static void rtl8169_get_pauseparam(struct net_device *dev,
1922 struct ethtool_pauseparam *data)
1923 {
1924 struct rtl8169_private *tp = netdev_priv(dev);
1925 bool tx_pause, rx_pause;
1926
1927 phy_get_pause(tp->phydev, &tx_pause, &rx_pause);
1928
1929 data->autoneg = tp->phydev->autoneg;
1930 data->tx_pause = tx_pause ? 1 : 0;
1931 data->rx_pause = rx_pause ? 1 : 0;
1932 }
1933
rtl8169_set_pauseparam(struct net_device * dev,struct ethtool_pauseparam * data)1934 static int rtl8169_set_pauseparam(struct net_device *dev,
1935 struct ethtool_pauseparam *data)
1936 {
1937 struct rtl8169_private *tp = netdev_priv(dev);
1938
1939 if (dev->mtu > ETH_DATA_LEN)
1940 return -EOPNOTSUPP;
1941
1942 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause);
1943
1944 return 0;
1945 }
1946
1947 static const struct ethtool_ops rtl8169_ethtool_ops = {
1948 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1949 ETHTOOL_COALESCE_MAX_FRAMES,
1950 .get_drvinfo = rtl8169_get_drvinfo,
1951 .get_regs_len = rtl8169_get_regs_len,
1952 .get_link = ethtool_op_get_link,
1953 .get_coalesce = rtl_get_coalesce,
1954 .set_coalesce = rtl_set_coalesce,
1955 .get_regs = rtl8169_get_regs,
1956 .get_wol = rtl8169_get_wol,
1957 .set_wol = rtl8169_set_wol,
1958 .get_strings = rtl8169_get_strings,
1959 .get_sset_count = rtl8169_get_sset_count,
1960 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1961 .get_ts_info = ethtool_op_get_ts_info,
1962 .nway_reset = phy_ethtool_nway_reset,
1963 .get_eee = rtl8169_get_eee,
1964 .set_eee = rtl8169_set_eee,
1965 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1966 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1967 .get_ringparam = rtl8169_get_ringparam,
1968 .get_pauseparam = rtl8169_get_pauseparam,
1969 .set_pauseparam = rtl8169_set_pauseparam,
1970 };
1971
rtl_enable_eee(struct rtl8169_private * tp)1972 static void rtl_enable_eee(struct rtl8169_private *tp)
1973 {
1974 struct phy_device *phydev = tp->phydev;
1975 int adv;
1976
1977 /* respect EEE advertisement the user may have set */
1978 if (tp->eee_adv >= 0)
1979 adv = tp->eee_adv;
1980 else
1981 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1982
1983 if (adv >= 0)
1984 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
1985 }
1986
rtl8169_get_mac_version(u16 xid,bool gmii)1987 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
1988 {
1989 /*
1990 * The driver currently handles the 8168Bf and the 8168Be identically
1991 * but they can be identified more specifically through the test below
1992 * if needed:
1993 *
1994 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1995 *
1996 * Same thing for the 8101Eb and the 8101Ec:
1997 *
1998 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1999 */
2000 static const struct rtl_mac_info {
2001 u16 mask;
2002 u16 val;
2003 enum mac_version ver;
2004 } mac_info[] = {
2005 /* 8125B family. */
2006 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
2007
2008 /* 8125A family. */
2009 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
2010 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
2011
2012 /* RTL8117 */
2013 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 },
2014 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
2015
2016 /* 8168EP family. */
2017 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2018 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2019 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2020
2021 /* 8168H family. */
2022 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2023 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2024
2025 /* 8168G family. */
2026 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2027 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2028 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2029 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2030
2031 /* 8168F family. */
2032 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2033 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2034 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2035
2036 /* 8168E family. */
2037 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2038 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2039 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2040
2041 /* 8168D family. */
2042 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2043 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2044
2045 /* 8168DP family. */
2046 /* It seems this early RTL8168dp version never made it to
2047 * the wild. Let's see whether somebody complains, if not
2048 * we'll remove support for this chip version completely.
2049 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2050 */
2051 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2052 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2053
2054 /* 8168C family. */
2055 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2056 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2057 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2058 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2059 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2060 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2061 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2062
2063 /* 8168B family. */
2064 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2065 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2066 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2067
2068 /* 8101 family. */
2069 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2070 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2071 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2072 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2073 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2074 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2075 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2076 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2077 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2078 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2079 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2080 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2081 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2082 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2083 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2084 /* FIXME: where did these entries come from ? -- FR
2085 * Not even r8101 vendor driver knows these id's,
2086 * so let's disable detection for now. -- HK
2087 * { 0xfc8, 0x388, RTL_GIGA_MAC_VER_13 },
2088 * { 0xfc8, 0x308, RTL_GIGA_MAC_VER_13 },
2089 */
2090
2091 /* 8110 family. */
2092 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2093 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2094 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2095 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2096 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2097
2098 /* Catch-all */
2099 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2100 };
2101 const struct rtl_mac_info *p = mac_info;
2102 enum mac_version ver;
2103
2104 while ((xid & p->mask) != p->val)
2105 p++;
2106 ver = p->ver;
2107
2108 if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2109 if (ver == RTL_GIGA_MAC_VER_42)
2110 ver = RTL_GIGA_MAC_VER_43;
2111 else if (ver == RTL_GIGA_MAC_VER_45)
2112 ver = RTL_GIGA_MAC_VER_47;
2113 else if (ver == RTL_GIGA_MAC_VER_46)
2114 ver = RTL_GIGA_MAC_VER_48;
2115 }
2116
2117 return ver;
2118 }
2119
rtl_release_firmware(struct rtl8169_private * tp)2120 static void rtl_release_firmware(struct rtl8169_private *tp)
2121 {
2122 if (tp->rtl_fw) {
2123 rtl_fw_release_firmware(tp->rtl_fw);
2124 kfree(tp->rtl_fw);
2125 tp->rtl_fw = NULL;
2126 }
2127 }
2128
r8169_apply_firmware(struct rtl8169_private * tp)2129 void r8169_apply_firmware(struct rtl8169_private *tp)
2130 {
2131 int val;
2132
2133 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2134 if (tp->rtl_fw) {
2135 rtl_fw_write_firmware(tp, tp->rtl_fw);
2136 /* At least one firmware doesn't reset tp->ocp_base. */
2137 tp->ocp_base = OCP_STD_PHY_BASE;
2138
2139 /* PHY soft reset may still be in progress */
2140 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2141 !(val & BMCR_RESET),
2142 50000, 600000, true);
2143 }
2144 }
2145
rtl8168_config_eee_mac(struct rtl8169_private * tp)2146 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2147 {
2148 /* Adjust EEE LED frequency */
2149 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2150 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2151
2152 rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2153 }
2154
rtl8125a_config_eee_mac(struct rtl8169_private * tp)2155 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2156 {
2157 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2158 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2159 }
2160
rtl8125_set_eee_txidle_timer(struct rtl8169_private * tp)2161 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2162 {
2163 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2164 }
2165
rtl8125b_config_eee_mac(struct rtl8169_private * tp)2166 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2167 {
2168 rtl8125_set_eee_txidle_timer(tp);
2169 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2170 }
2171
rtl_rar_exgmac_set(struct rtl8169_private * tp,const u8 * addr)2172 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
2173 {
2174 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));
2175 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));
2176 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);
2177 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));
2178 }
2179
rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private * tp)2180 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2181 {
2182 u16 data1, data2, ioffset;
2183
2184 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2185 data1 = r8168_mac_ocp_read(tp, 0xdd02);
2186 data2 = r8168_mac_ocp_read(tp, 0xdd00);
2187
2188 ioffset = (data2 >> 1) & 0x7ff8;
2189 ioffset |= data2 & 0x0007;
2190 if (data1 & BIT(7))
2191 ioffset |= BIT(15);
2192
2193 return ioffset;
2194 }
2195
rtl_schedule_task(struct rtl8169_private * tp,enum rtl_flag flag)2196 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2197 {
2198 set_bit(flag, tp->wk.flags);
2199 schedule_work(&tp->wk.work);
2200 }
2201
rtl8169_init_phy(struct rtl8169_private * tp)2202 static void rtl8169_init_phy(struct rtl8169_private *tp)
2203 {
2204 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2205
2206 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2207 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2208 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2209 /* set undocumented MAC Reg C+CR Offset 0x82h */
2210 RTL_W8(tp, 0x82, 0x01);
2211 }
2212
2213 if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2214 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2215 tp->pci_dev->subsystem_device == 0xe000)
2216 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2217
2218 /* We may have called phy_speed_down before */
2219 phy_speed_up(tp->phydev);
2220
2221 if (rtl_supports_eee(tp))
2222 rtl_enable_eee(tp);
2223
2224 genphy_soft_reset(tp->phydev);
2225 }
2226
rtl_rar_set(struct rtl8169_private * tp,const u8 * addr)2227 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
2228 {
2229 rtl_unlock_config_regs(tp);
2230
2231 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2232 rtl_pci_commit(tp);
2233
2234 RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2235 rtl_pci_commit(tp);
2236
2237 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2238 rtl_rar_exgmac_set(tp, addr);
2239
2240 rtl_lock_config_regs(tp);
2241 }
2242
rtl_set_mac_address(struct net_device * dev,void * p)2243 static int rtl_set_mac_address(struct net_device *dev, void *p)
2244 {
2245 struct rtl8169_private *tp = netdev_priv(dev);
2246 int ret;
2247
2248 ret = eth_mac_addr(dev, p);
2249 if (ret)
2250 return ret;
2251
2252 rtl_rar_set(tp, dev->dev_addr);
2253
2254 return 0;
2255 }
2256
rtl_init_rxcfg(struct rtl8169_private * tp)2257 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2258 {
2259 switch (tp->mac_version) {
2260 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2261 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2262 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2263 break;
2264 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2265 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2266 case RTL_GIGA_MAC_VER_38:
2267 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2268 break;
2269 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2270 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2271 break;
2272 case RTL_GIGA_MAC_VER_61:
2273 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2274 break;
2275 case RTL_GIGA_MAC_VER_63:
2276 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |
2277 RX_PAUSE_SLOT_ON);
2278 break;
2279 default:
2280 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2281 break;
2282 }
2283 }
2284
rtl8169_init_ring_indexes(struct rtl8169_private * tp)2285 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2286 {
2287 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2288 }
2289
r8168c_hw_jumbo_enable(struct rtl8169_private * tp)2290 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2291 {
2292 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2293 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2294 }
2295
r8168c_hw_jumbo_disable(struct rtl8169_private * tp)2296 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2297 {
2298 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2299 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2300 }
2301
r8168dp_hw_jumbo_enable(struct rtl8169_private * tp)2302 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2303 {
2304 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2305 }
2306
r8168dp_hw_jumbo_disable(struct rtl8169_private * tp)2307 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2308 {
2309 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2310 }
2311
r8168e_hw_jumbo_enable(struct rtl8169_private * tp)2312 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2313 {
2314 RTL_W8(tp, MaxTxPacketSize, 0x24);
2315 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2316 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2317 }
2318
r8168e_hw_jumbo_disable(struct rtl8169_private * tp)2319 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2320 {
2321 RTL_W8(tp, MaxTxPacketSize, 0x3f);
2322 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2323 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2324 }
2325
r8168b_1_hw_jumbo_enable(struct rtl8169_private * tp)2326 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2327 {
2328 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2329 }
2330
r8168b_1_hw_jumbo_disable(struct rtl8169_private * tp)2331 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2332 {
2333 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2334 }
2335
rtl_jumbo_config(struct rtl8169_private * tp)2336 static void rtl_jumbo_config(struct rtl8169_private *tp)
2337 {
2338 bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2339 int readrq = 4096;
2340
2341 rtl_unlock_config_regs(tp);
2342 switch (tp->mac_version) {
2343 case RTL_GIGA_MAC_VER_12:
2344 case RTL_GIGA_MAC_VER_17:
2345 if (jumbo) {
2346 readrq = 512;
2347 r8168b_1_hw_jumbo_enable(tp);
2348 } else {
2349 r8168b_1_hw_jumbo_disable(tp);
2350 }
2351 break;
2352 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2353 if (jumbo) {
2354 readrq = 512;
2355 r8168c_hw_jumbo_enable(tp);
2356 } else {
2357 r8168c_hw_jumbo_disable(tp);
2358 }
2359 break;
2360 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
2361 if (jumbo)
2362 r8168dp_hw_jumbo_enable(tp);
2363 else
2364 r8168dp_hw_jumbo_disable(tp);
2365 break;
2366 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2367 if (jumbo)
2368 r8168e_hw_jumbo_enable(tp);
2369 else
2370 r8168e_hw_jumbo_disable(tp);
2371 break;
2372 default:
2373 break;
2374 }
2375 rtl_lock_config_regs(tp);
2376
2377 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2378 pcie_set_readrq(tp->pci_dev, readrq);
2379
2380 /* Chip doesn't support pause in jumbo mode */
2381 if (jumbo) {
2382 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2383 tp->phydev->advertising);
2384 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2385 tp->phydev->advertising);
2386 phy_start_aneg(tp->phydev);
2387 }
2388 }
2389
DECLARE_RTL_COND(rtl_chipcmd_cond)2390 DECLARE_RTL_COND(rtl_chipcmd_cond)
2391 {
2392 return RTL_R8(tp, ChipCmd) & CmdReset;
2393 }
2394
rtl_hw_reset(struct rtl8169_private * tp)2395 static void rtl_hw_reset(struct rtl8169_private *tp)
2396 {
2397 RTL_W8(tp, ChipCmd, CmdReset);
2398
2399 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2400 }
2401
rtl_request_firmware(struct rtl8169_private * tp)2402 static void rtl_request_firmware(struct rtl8169_private *tp)
2403 {
2404 struct rtl_fw *rtl_fw;
2405
2406 /* firmware loaded already or no firmware available */
2407 if (tp->rtl_fw || !tp->fw_name)
2408 return;
2409
2410 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2411 if (!rtl_fw)
2412 return;
2413
2414 rtl_fw->phy_write = rtl_writephy;
2415 rtl_fw->phy_read = rtl_readphy;
2416 rtl_fw->mac_mcu_write = mac_mcu_write;
2417 rtl_fw->mac_mcu_read = mac_mcu_read;
2418 rtl_fw->fw_name = tp->fw_name;
2419 rtl_fw->dev = tp_to_dev(tp);
2420
2421 if (rtl_fw_request_firmware(rtl_fw))
2422 kfree(rtl_fw);
2423 else
2424 tp->rtl_fw = rtl_fw;
2425 }
2426
rtl_rx_close(struct rtl8169_private * tp)2427 static void rtl_rx_close(struct rtl8169_private *tp)
2428 {
2429 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2430 }
2431
DECLARE_RTL_COND(rtl_npq_cond)2432 DECLARE_RTL_COND(rtl_npq_cond)
2433 {
2434 return RTL_R8(tp, TxPoll) & NPQ;
2435 }
2436
DECLARE_RTL_COND(rtl_txcfg_empty_cond)2437 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2438 {
2439 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2440 }
2441
DECLARE_RTL_COND(rtl_rxtx_empty_cond)2442 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2443 {
2444 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2445 }
2446
DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)2447 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2448 {
2449 /* IntrMitigate has new functionality on RTL8125 */
2450 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2451 }
2452
rtl_wait_txrx_fifo_empty(struct rtl8169_private * tp)2453 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2454 {
2455 switch (tp->mac_version) {
2456 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2457 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2458 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2459 break;
2460 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
2461 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2462 break;
2463 case RTL_GIGA_MAC_VER_63:
2464 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2465 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2466 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2467 break;
2468 default:
2469 break;
2470 }
2471 }
2472
rtl_enable_rxdvgate(struct rtl8169_private * tp)2473 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2474 {
2475 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2476 fsleep(2000);
2477 rtl_wait_txrx_fifo_empty(tp);
2478 }
2479
rtl_wol_enable_rx(struct rtl8169_private * tp)2480 static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2481 {
2482 if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2483 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2484 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2485 }
2486
rtl_prepare_power_down(struct rtl8169_private * tp)2487 static void rtl_prepare_power_down(struct rtl8169_private *tp)
2488 {
2489 if (tp->dash_type != RTL_DASH_NONE)
2490 return;
2491
2492 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2493 tp->mac_version == RTL_GIGA_MAC_VER_33)
2494 rtl_ephy_write(tp, 0x19, 0xff64);
2495
2496 if (device_may_wakeup(tp_to_dev(tp))) {
2497 phy_speed_down(tp->phydev, false);
2498 rtl_wol_enable_rx(tp);
2499 }
2500 }
2501
rtl_set_tx_config_registers(struct rtl8169_private * tp)2502 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2503 {
2504 u32 val = TX_DMA_BURST << TxDMAShift |
2505 InterFrameGap << TxInterFrameGapShift;
2506
2507 if (rtl_is_8168evl_up(tp))
2508 val |= TXCFG_AUTO_FIFO;
2509
2510 RTL_W32(tp, TxConfig, val);
2511 }
2512
rtl_set_rx_max_size(struct rtl8169_private * tp)2513 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2514 {
2515 /* Low hurts. Let's disable the filtering. */
2516 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2517 }
2518
rtl_set_rx_tx_desc_registers(struct rtl8169_private * tp)2519 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2520 {
2521 /*
2522 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2523 * register to be written before TxDescAddrLow to work.
2524 * Switching from MMIO to I/O access fixes the issue as well.
2525 */
2526 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2527 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2528 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2529 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2530 }
2531
rtl8169_set_magic_reg(struct rtl8169_private * tp)2532 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2533 {
2534 u32 val;
2535
2536 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2537 val = 0x000fff00;
2538 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2539 val = 0x00ffff00;
2540 else
2541 return;
2542
2543 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2544 val |= 0xff;
2545
2546 RTL_W32(tp, 0x7c, val);
2547 }
2548
rtl_set_rx_mode(struct net_device * dev)2549 static void rtl_set_rx_mode(struct net_device *dev)
2550 {
2551 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2552 /* Multicast hash filter */
2553 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2554 struct rtl8169_private *tp = netdev_priv(dev);
2555 u32 tmp;
2556
2557 if (dev->flags & IFF_PROMISC) {
2558 rx_mode |= AcceptAllPhys;
2559 } else if (!(dev->flags & IFF_MULTICAST)) {
2560 rx_mode &= ~AcceptMulticast;
2561 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2562 dev->flags & IFF_ALLMULTI ||
2563 tp->mac_version == RTL_GIGA_MAC_VER_35) {
2564 /* accept all multicasts */
2565 } else if (netdev_mc_empty(dev)) {
2566 rx_mode &= ~AcceptMulticast;
2567 } else {
2568 struct netdev_hw_addr *ha;
2569
2570 mc_filter[1] = mc_filter[0] = 0;
2571 netdev_for_each_mc_addr(ha, dev) {
2572 u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2573 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2574 }
2575
2576 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2577 tmp = mc_filter[0];
2578 mc_filter[0] = swab32(mc_filter[1]);
2579 mc_filter[1] = swab32(tmp);
2580 }
2581 }
2582
2583 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2584 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2585
2586 tmp = RTL_R32(tp, RxConfig);
2587 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2588 }
2589
DECLARE_RTL_COND(rtl_csiar_cond)2590 DECLARE_RTL_COND(rtl_csiar_cond)
2591 {
2592 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2593 }
2594
rtl_csi_write(struct rtl8169_private * tp,int addr,int value)2595 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2596 {
2597 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2598
2599 RTL_W32(tp, CSIDR, value);
2600 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2601 CSIAR_BYTE_ENABLE | func << 16);
2602
2603 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2604 }
2605
rtl_csi_read(struct rtl8169_private * tp,int addr)2606 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2607 {
2608 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2609
2610 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2611 CSIAR_BYTE_ENABLE);
2612
2613 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2614 RTL_R32(tp, CSIDR) : ~0;
2615 }
2616
rtl_set_aspm_entry_latency(struct rtl8169_private * tp,u8 val)2617 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
2618 {
2619 struct pci_dev *pdev = tp->pci_dev;
2620 u32 csi;
2621
2622 /* According to Realtek the value at config space address 0x070f
2623 * controls the L0s/L1 entrance latency. We try standard ECAM access
2624 * first and if it fails fall back to CSI.
2625 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo)
2626 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us
2627 */
2628 if (pdev->cfg_size > 0x070f &&
2629 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2630 return;
2631
2632 netdev_notice_once(tp->dev,
2633 "No native access to PCI extended config space, falling back to CSI\n");
2634 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2635 rtl_csi_write(tp, 0x070c, csi | val << 24);
2636 }
2637
rtl_set_def_aspm_entry_latency(struct rtl8169_private * tp)2638 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2639 {
2640 /* L0 7us, L1 16us */
2641 rtl_set_aspm_entry_latency(tp, 0x27);
2642 }
2643
2644 struct ephy_info {
2645 unsigned int offset;
2646 u16 mask;
2647 u16 bits;
2648 };
2649
__rtl_ephy_init(struct rtl8169_private * tp,const struct ephy_info * e,int len)2650 static void __rtl_ephy_init(struct rtl8169_private *tp,
2651 const struct ephy_info *e, int len)
2652 {
2653 u16 w;
2654
2655 while (len-- > 0) {
2656 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2657 rtl_ephy_write(tp, e->offset, w);
2658 e++;
2659 }
2660 }
2661
2662 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2663
rtl_disable_clock_request(struct rtl8169_private * tp)2664 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2665 {
2666 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2667 PCI_EXP_LNKCTL_CLKREQ_EN);
2668 }
2669
rtl_enable_clock_request(struct rtl8169_private * tp)2670 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2671 {
2672 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2673 PCI_EXP_LNKCTL_CLKREQ_EN);
2674 }
2675
rtl_pcie_state_l2l3_disable(struct rtl8169_private * tp)2676 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2677 {
2678 /* work around an issue when PCI reset occurs during L2/L3 state */
2679 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2680 }
2681
rtl_enable_exit_l1(struct rtl8169_private * tp)2682 static void rtl_enable_exit_l1(struct rtl8169_private *tp)
2683 {
2684 /* Bits control which events trigger ASPM L1 exit:
2685 * Bit 12: rxdv
2686 * Bit 11: ltr_msg
2687 * Bit 10: txdma_poll
2688 * Bit 9: xadm
2689 * Bit 8: pktavi
2690 * Bit 7: txpla
2691 */
2692 switch (tp->mac_version) {
2693 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2694 rtl_eri_set_bits(tp, 0xd4, 0x1f00);
2695 break;
2696 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
2697 rtl_eri_set_bits(tp, 0xd4, 0x0c00);
2698 break;
2699 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2700 rtl_eri_set_bits(tp, 0xd4, 0x1f80);
2701 break;
2702 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
2703 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
2704 break;
2705 default:
2706 break;
2707 }
2708 }
2709
rtl_hw_aspm_clkreq_enable(struct rtl8169_private * tp,bool enable)2710 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2711 {
2712 /* Don't enable ASPM in the chip if OS can't control ASPM */
2713 if (enable && tp->aspm_manageable) {
2714 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
2715 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
2716 } else {
2717 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
2718 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
2719 }
2720
2721 udelay(10);
2722 }
2723
rtl_set_fifo_size(struct rtl8169_private * tp,u16 rx_stat,u16 tx_stat,u16 rx_dyn,u16 tx_dyn)2724 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2725 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2726 {
2727 /* Usage of dynamic vs. static FIFO is controlled by bit
2728 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2729 */
2730 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2731 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2732 }
2733
rtl8168g_set_pause_thresholds(struct rtl8169_private * tp,u8 low,u8 high)2734 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2735 u8 low, u8 high)
2736 {
2737 /* FIFO thresholds for pause flow control */
2738 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2739 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2740 }
2741
rtl_hw_start_8168b(struct rtl8169_private * tp)2742 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2743 {
2744 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2745 }
2746
__rtl_hw_start_8168cp(struct rtl8169_private * tp)2747 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2748 {
2749 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2750
2751 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2752
2753 rtl_disable_clock_request(tp);
2754 }
2755
rtl_hw_start_8168cp_1(struct rtl8169_private * tp)2756 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2757 {
2758 static const struct ephy_info e_info_8168cp[] = {
2759 { 0x01, 0, 0x0001 },
2760 { 0x02, 0x0800, 0x1000 },
2761 { 0x03, 0, 0x0042 },
2762 { 0x06, 0x0080, 0x0000 },
2763 { 0x07, 0, 0x2000 }
2764 };
2765
2766 rtl_set_def_aspm_entry_latency(tp);
2767
2768 rtl_ephy_init(tp, e_info_8168cp);
2769
2770 __rtl_hw_start_8168cp(tp);
2771 }
2772
rtl_hw_start_8168cp_2(struct rtl8169_private * tp)2773 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2774 {
2775 rtl_set_def_aspm_entry_latency(tp);
2776
2777 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2778 }
2779
rtl_hw_start_8168cp_3(struct rtl8169_private * tp)2780 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2781 {
2782 rtl_set_def_aspm_entry_latency(tp);
2783
2784 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2785
2786 /* Magic. */
2787 RTL_W8(tp, DBG_REG, 0x20);
2788 }
2789
rtl_hw_start_8168c_1(struct rtl8169_private * tp)2790 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2791 {
2792 static const struct ephy_info e_info_8168c_1[] = {
2793 { 0x02, 0x0800, 0x1000 },
2794 { 0x03, 0, 0x0002 },
2795 { 0x06, 0x0080, 0x0000 }
2796 };
2797
2798 rtl_set_def_aspm_entry_latency(tp);
2799
2800 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2801
2802 rtl_ephy_init(tp, e_info_8168c_1);
2803
2804 __rtl_hw_start_8168cp(tp);
2805 }
2806
rtl_hw_start_8168c_2(struct rtl8169_private * tp)2807 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2808 {
2809 static const struct ephy_info e_info_8168c_2[] = {
2810 { 0x01, 0, 0x0001 },
2811 { 0x03, 0x0400, 0x0020 }
2812 };
2813
2814 rtl_set_def_aspm_entry_latency(tp);
2815
2816 rtl_ephy_init(tp, e_info_8168c_2);
2817
2818 __rtl_hw_start_8168cp(tp);
2819 }
2820
rtl_hw_start_8168c_4(struct rtl8169_private * tp)2821 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2822 {
2823 rtl_set_def_aspm_entry_latency(tp);
2824
2825 __rtl_hw_start_8168cp(tp);
2826 }
2827
rtl_hw_start_8168d(struct rtl8169_private * tp)2828 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2829 {
2830 rtl_set_def_aspm_entry_latency(tp);
2831
2832 rtl_disable_clock_request(tp);
2833 }
2834
rtl_hw_start_8168d_4(struct rtl8169_private * tp)2835 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2836 {
2837 static const struct ephy_info e_info_8168d_4[] = {
2838 { 0x0b, 0x0000, 0x0048 },
2839 { 0x19, 0x0020, 0x0050 },
2840 { 0x0c, 0x0100, 0x0020 },
2841 { 0x10, 0x0004, 0x0000 },
2842 };
2843
2844 rtl_set_def_aspm_entry_latency(tp);
2845
2846 rtl_ephy_init(tp, e_info_8168d_4);
2847
2848 rtl_enable_clock_request(tp);
2849 }
2850
rtl_hw_start_8168e_1(struct rtl8169_private * tp)2851 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2852 {
2853 static const struct ephy_info e_info_8168e_1[] = {
2854 { 0x00, 0x0200, 0x0100 },
2855 { 0x00, 0x0000, 0x0004 },
2856 { 0x06, 0x0002, 0x0001 },
2857 { 0x06, 0x0000, 0x0030 },
2858 { 0x07, 0x0000, 0x2000 },
2859 { 0x00, 0x0000, 0x0020 },
2860 { 0x03, 0x5800, 0x2000 },
2861 { 0x03, 0x0000, 0x0001 },
2862 { 0x01, 0x0800, 0x1000 },
2863 { 0x07, 0x0000, 0x4000 },
2864 { 0x1e, 0x0000, 0x2000 },
2865 { 0x19, 0xffff, 0xfe6c },
2866 { 0x0a, 0x0000, 0x0040 }
2867 };
2868
2869 rtl_set_def_aspm_entry_latency(tp);
2870
2871 rtl_ephy_init(tp, e_info_8168e_1);
2872
2873 rtl_disable_clock_request(tp);
2874
2875 /* Reset tx FIFO pointer */
2876 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2877 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2878
2879 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2880 }
2881
rtl_hw_start_8168e_2(struct rtl8169_private * tp)2882 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2883 {
2884 static const struct ephy_info e_info_8168e_2[] = {
2885 { 0x09, 0x0000, 0x0080 },
2886 { 0x19, 0x0000, 0x0224 },
2887 { 0x00, 0x0000, 0x0004 },
2888 { 0x0c, 0x3df0, 0x0200 },
2889 };
2890
2891 rtl_set_def_aspm_entry_latency(tp);
2892
2893 rtl_ephy_init(tp, e_info_8168e_2);
2894
2895 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2896 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2897 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2898 rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2899 rtl_reset_packet_filter(tp);
2900 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2901 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2902 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2903
2904 rtl_disable_clock_request(tp);
2905
2906 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2907
2908 rtl8168_config_eee_mac(tp);
2909
2910 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2911 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2912 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2913
2914 rtl_hw_aspm_clkreq_enable(tp, true);
2915 }
2916
rtl_hw_start_8168f(struct rtl8169_private * tp)2917 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2918 {
2919 rtl_set_def_aspm_entry_latency(tp);
2920
2921 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2922 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2923 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2924 rtl_reset_packet_filter(tp);
2925 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2926 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
2927 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2928 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
2929
2930 rtl_disable_clock_request(tp);
2931
2932 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2933 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2934 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2935 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2936
2937 rtl8168_config_eee_mac(tp);
2938 }
2939
rtl_hw_start_8168f_1(struct rtl8169_private * tp)2940 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
2941 {
2942 static const struct ephy_info e_info_8168f_1[] = {
2943 { 0x06, 0x00c0, 0x0020 },
2944 { 0x08, 0x0001, 0x0002 },
2945 { 0x09, 0x0000, 0x0080 },
2946 { 0x19, 0x0000, 0x0224 },
2947 { 0x00, 0x0000, 0x0008 },
2948 { 0x0c, 0x3df0, 0x0200 },
2949 };
2950
2951 rtl_hw_start_8168f(tp);
2952
2953 rtl_ephy_init(tp, e_info_8168f_1);
2954 }
2955
rtl_hw_start_8411(struct rtl8169_private * tp)2956 static void rtl_hw_start_8411(struct rtl8169_private *tp)
2957 {
2958 static const struct ephy_info e_info_8168f_1[] = {
2959 { 0x06, 0x00c0, 0x0020 },
2960 { 0x0f, 0xffff, 0x5200 },
2961 { 0x19, 0x0000, 0x0224 },
2962 { 0x00, 0x0000, 0x0008 },
2963 { 0x0c, 0x3df0, 0x0200 },
2964 };
2965
2966 rtl_hw_start_8168f(tp);
2967 rtl_pcie_state_l2l3_disable(tp);
2968
2969 rtl_ephy_init(tp, e_info_8168f_1);
2970 }
2971
rtl_hw_start_8168g(struct rtl8169_private * tp)2972 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
2973 {
2974 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
2975 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
2976
2977 rtl_set_def_aspm_entry_latency(tp);
2978
2979 rtl_reset_packet_filter(tp);
2980 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
2981
2982 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2983
2984 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2985 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
2986
2987 rtl8168_config_eee_mac(tp);
2988
2989 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
2990 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
2991
2992 rtl_pcie_state_l2l3_disable(tp);
2993 }
2994
rtl_hw_start_8168g_1(struct rtl8169_private * tp)2995 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
2996 {
2997 static const struct ephy_info e_info_8168g_1[] = {
2998 { 0x00, 0x0008, 0x0000 },
2999 { 0x0c, 0x3ff0, 0x0820 },
3000 { 0x1e, 0x0000, 0x0001 },
3001 { 0x19, 0x8000, 0x0000 }
3002 };
3003
3004 rtl_hw_start_8168g(tp);
3005
3006 /* disable aspm and clock request before access ephy */
3007 rtl_hw_aspm_clkreq_enable(tp, false);
3008 rtl_ephy_init(tp, e_info_8168g_1);
3009 rtl_hw_aspm_clkreq_enable(tp, true);
3010 }
3011
rtl_hw_start_8168g_2(struct rtl8169_private * tp)3012 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3013 {
3014 static const struct ephy_info e_info_8168g_2[] = {
3015 { 0x00, 0x0008, 0x0000 },
3016 { 0x0c, 0x3ff0, 0x0820 },
3017 { 0x19, 0xffff, 0x7c00 },
3018 { 0x1e, 0xffff, 0x20eb },
3019 { 0x0d, 0xffff, 0x1666 },
3020 { 0x00, 0xffff, 0x10a3 },
3021 { 0x06, 0xffff, 0xf050 },
3022 { 0x04, 0x0000, 0x0010 },
3023 { 0x1d, 0x4000, 0x0000 },
3024 };
3025
3026 rtl_hw_start_8168g(tp);
3027
3028 /* disable aspm and clock request before access ephy */
3029 rtl_hw_aspm_clkreq_enable(tp, false);
3030 rtl_ephy_init(tp, e_info_8168g_2);
3031 }
3032
rtl_hw_start_8411_2(struct rtl8169_private * tp)3033 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3034 {
3035 static const struct ephy_info e_info_8411_2[] = {
3036 { 0x00, 0x0008, 0x0000 },
3037 { 0x0c, 0x37d0, 0x0820 },
3038 { 0x1e, 0x0000, 0x0001 },
3039 { 0x19, 0x8021, 0x0000 },
3040 { 0x1e, 0x0000, 0x2000 },
3041 { 0x0d, 0x0100, 0x0200 },
3042 { 0x00, 0x0000, 0x0080 },
3043 { 0x06, 0x0000, 0x0010 },
3044 { 0x04, 0x0000, 0x0010 },
3045 { 0x1d, 0x0000, 0x4000 },
3046 };
3047
3048 rtl_hw_start_8168g(tp);
3049
3050 /* disable aspm and clock request before access ephy */
3051 rtl_hw_aspm_clkreq_enable(tp, false);
3052 rtl_ephy_init(tp, e_info_8411_2);
3053
3054 /* The following Realtek-provided magic fixes an issue with the RX unit
3055 * getting confused after the PHY having been powered-down.
3056 */
3057 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3058 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3059 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3060 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3061 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3062 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3063 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3064 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3065 mdelay(3);
3066 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3067
3068 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3069 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3070 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3071 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3072 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3073 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3074 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3075 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3076 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3077 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3078 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3079 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3080 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3081 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3082 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3083 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3084 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3085 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3086 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3087 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3088 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3089 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3090 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3091 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3092 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3093 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3094 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3095 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3096 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3097 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3098 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3099 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3100 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3101 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3102 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3103 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3104 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3105 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3106 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3107 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3108 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3109 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3110 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3111 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3112 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3113 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3114 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3115 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3116 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3117 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3118 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3119 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3120 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3121 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3122 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3123 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3124 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3125 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3126 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3127 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3128 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3129 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3130 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3131 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3132 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3133 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3134 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3135 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3136 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3137 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3138 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3139 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3140 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3141 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3142 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3143 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3144 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3145 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3146 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3147 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3148 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3149 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3150 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3151 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3152 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3153 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3154 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3155 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3156 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3157 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3158 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3159 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3160 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3161 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3162 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3163 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3164 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3165 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3166 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3167 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3168 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3169 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3170 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3171 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3172 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3173 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3174 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3175 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3176 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3177 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3178 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3179
3180 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3181
3182 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3183 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3184 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3185 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3186 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3187 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3188 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3189
3190 rtl_hw_aspm_clkreq_enable(tp, true);
3191 }
3192
rtl_hw_start_8168h_1(struct rtl8169_private * tp)3193 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3194 {
3195 static const struct ephy_info e_info_8168h_1[] = {
3196 { 0x1e, 0x0800, 0x0001 },
3197 { 0x1d, 0x0000, 0x0800 },
3198 { 0x05, 0xffff, 0x2089 },
3199 { 0x06, 0xffff, 0x5881 },
3200 { 0x04, 0xffff, 0x854a },
3201 { 0x01, 0xffff, 0x068b }
3202 };
3203 int rg_saw_cnt;
3204
3205 /* disable aspm and clock request before access ephy */
3206 rtl_hw_aspm_clkreq_enable(tp, false);
3207 rtl_ephy_init(tp, e_info_8168h_1);
3208
3209 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3210 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3211
3212 rtl_set_def_aspm_entry_latency(tp);
3213
3214 rtl_reset_packet_filter(tp);
3215
3216 rtl_eri_set_bits(tp, 0xdc, 0x001c);
3217
3218 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3219
3220 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3221
3222 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3223 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3224
3225 rtl8168_config_eee_mac(tp);
3226
3227 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3228 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3229
3230 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3231
3232 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3233
3234 rtl_pcie_state_l2l3_disable(tp);
3235
3236 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3237 if (rg_saw_cnt > 0) {
3238 u16 sw_cnt_1ms_ini;
3239
3240 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3241 sw_cnt_1ms_ini &= 0x0fff;
3242 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3243 }
3244
3245 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3246 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3247 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3248 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3249
3250 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3251 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3252 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3253 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3254
3255 rtl_hw_aspm_clkreq_enable(tp, true);
3256 }
3257
rtl_hw_start_8168ep(struct rtl8169_private * tp)3258 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3259 {
3260 rtl8168ep_stop_cmac(tp);
3261
3262 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3263 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3264
3265 rtl_set_def_aspm_entry_latency(tp);
3266
3267 rtl_reset_packet_filter(tp);
3268
3269 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3270
3271 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3272
3273 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3274 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3275
3276 rtl8168_config_eee_mac(tp);
3277
3278 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3279
3280 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3281
3282 rtl_pcie_state_l2l3_disable(tp);
3283 }
3284
rtl_hw_start_8168ep_1(struct rtl8169_private * tp)3285 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
3286 {
3287 static const struct ephy_info e_info_8168ep_1[] = {
3288 { 0x00, 0xffff, 0x10ab },
3289 { 0x06, 0xffff, 0xf030 },
3290 { 0x08, 0xffff, 0x2006 },
3291 { 0x0d, 0xffff, 0x1666 },
3292 { 0x0c, 0x3ff0, 0x0000 }
3293 };
3294
3295 /* disable aspm and clock request before access ephy */
3296 rtl_hw_aspm_clkreq_enable(tp, false);
3297 rtl_ephy_init(tp, e_info_8168ep_1);
3298
3299 rtl_hw_start_8168ep(tp);
3300
3301 rtl_hw_aspm_clkreq_enable(tp, true);
3302 }
3303
rtl_hw_start_8168ep_2(struct rtl8169_private * tp)3304 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
3305 {
3306 static const struct ephy_info e_info_8168ep_2[] = {
3307 { 0x00, 0xffff, 0x10a3 },
3308 { 0x19, 0xffff, 0xfc00 },
3309 { 0x1e, 0xffff, 0x20ea }
3310 };
3311
3312 /* disable aspm and clock request before access ephy */
3313 rtl_hw_aspm_clkreq_enable(tp, false);
3314 rtl_ephy_init(tp, e_info_8168ep_2);
3315
3316 rtl_hw_start_8168ep(tp);
3317
3318 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3319 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3320
3321 rtl_hw_aspm_clkreq_enable(tp, true);
3322 }
3323
rtl_hw_start_8168ep_3(struct rtl8169_private * tp)3324 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3325 {
3326 static const struct ephy_info e_info_8168ep_3[] = {
3327 { 0x00, 0x0000, 0x0080 },
3328 { 0x0d, 0x0100, 0x0200 },
3329 { 0x19, 0x8021, 0x0000 },
3330 { 0x1e, 0x0000, 0x2000 },
3331 };
3332
3333 /* disable aspm and clock request before access ephy */
3334 rtl_hw_aspm_clkreq_enable(tp, false);
3335 rtl_ephy_init(tp, e_info_8168ep_3);
3336
3337 rtl_hw_start_8168ep(tp);
3338
3339 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3340 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3341
3342 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3343 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3344 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3345
3346 rtl_hw_aspm_clkreq_enable(tp, true);
3347 }
3348
rtl_hw_start_8117(struct rtl8169_private * tp)3349 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3350 {
3351 static const struct ephy_info e_info_8117[] = {
3352 { 0x19, 0x0040, 0x1100 },
3353 { 0x59, 0x0040, 0x1100 },
3354 };
3355 int rg_saw_cnt;
3356
3357 rtl8168ep_stop_cmac(tp);
3358
3359 /* disable aspm and clock request before access ephy */
3360 rtl_hw_aspm_clkreq_enable(tp, false);
3361 rtl_ephy_init(tp, e_info_8117);
3362
3363 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3364 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3365
3366 rtl_set_def_aspm_entry_latency(tp);
3367
3368 rtl_reset_packet_filter(tp);
3369
3370 rtl_eri_set_bits(tp, 0xd4, 0x0010);
3371
3372 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3373
3374 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3375
3376 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3377 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3378
3379 rtl8168_config_eee_mac(tp);
3380
3381 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3382 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3383
3384 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3385
3386 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3387
3388 rtl_pcie_state_l2l3_disable(tp);
3389
3390 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3391 if (rg_saw_cnt > 0) {
3392 u16 sw_cnt_1ms_ini;
3393
3394 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3395 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3396 }
3397
3398 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3399 r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3400 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3401 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3402
3403 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3404 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3405 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3406 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3407
3408 /* firmware is for MAC only */
3409 r8169_apply_firmware(tp);
3410
3411 rtl_hw_aspm_clkreq_enable(tp, true);
3412 }
3413
rtl_hw_start_8102e_1(struct rtl8169_private * tp)3414 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3415 {
3416 static const struct ephy_info e_info_8102e_1[] = {
3417 { 0x01, 0, 0x6e65 },
3418 { 0x02, 0, 0x091f },
3419 { 0x03, 0, 0xc2f9 },
3420 { 0x06, 0, 0xafb5 },
3421 { 0x07, 0, 0x0e00 },
3422 { 0x19, 0, 0xec80 },
3423 { 0x01, 0, 0x2e65 },
3424 { 0x01, 0, 0x6e65 }
3425 };
3426 u8 cfg1;
3427
3428 rtl_set_def_aspm_entry_latency(tp);
3429
3430 RTL_W8(tp, DBG_REG, FIX_NAK_1);
3431
3432 RTL_W8(tp, Config1,
3433 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3434 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3435
3436 cfg1 = RTL_R8(tp, Config1);
3437 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3438 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3439
3440 rtl_ephy_init(tp, e_info_8102e_1);
3441 }
3442
rtl_hw_start_8102e_2(struct rtl8169_private * tp)3443 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3444 {
3445 rtl_set_def_aspm_entry_latency(tp);
3446
3447 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3448 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3449 }
3450
rtl_hw_start_8102e_3(struct rtl8169_private * tp)3451 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3452 {
3453 rtl_hw_start_8102e_2(tp);
3454
3455 rtl_ephy_write(tp, 0x03, 0xc2f9);
3456 }
3457
rtl_hw_start_8401(struct rtl8169_private * tp)3458 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3459 {
3460 static const struct ephy_info e_info_8401[] = {
3461 { 0x01, 0xffff, 0x6fe5 },
3462 { 0x03, 0xffff, 0x0599 },
3463 { 0x06, 0xffff, 0xaf25 },
3464 { 0x07, 0xffff, 0x8e68 },
3465 };
3466
3467 rtl_ephy_init(tp, e_info_8401);
3468 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3469 }
3470
rtl_hw_start_8105e_1(struct rtl8169_private * tp)3471 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3472 {
3473 static const struct ephy_info e_info_8105e_1[] = {
3474 { 0x07, 0, 0x4000 },
3475 { 0x19, 0, 0x0200 },
3476 { 0x19, 0, 0x0020 },
3477 { 0x1e, 0, 0x2000 },
3478 { 0x03, 0, 0x0001 },
3479 { 0x19, 0, 0x0100 },
3480 { 0x19, 0, 0x0004 },
3481 { 0x0a, 0, 0x0020 }
3482 };
3483
3484 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3485 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3486
3487 /* Disable Early Tally Counter */
3488 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3489
3490 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3491 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3492
3493 rtl_ephy_init(tp, e_info_8105e_1);
3494
3495 rtl_pcie_state_l2l3_disable(tp);
3496 }
3497
rtl_hw_start_8105e_2(struct rtl8169_private * tp)3498 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3499 {
3500 rtl_hw_start_8105e_1(tp);
3501 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3502 }
3503
rtl_hw_start_8402(struct rtl8169_private * tp)3504 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3505 {
3506 static const struct ephy_info e_info_8402[] = {
3507 { 0x19, 0xffff, 0xff64 },
3508 { 0x1e, 0, 0x4000 }
3509 };
3510
3511 rtl_set_def_aspm_entry_latency(tp);
3512
3513 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3514 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3515
3516 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3517
3518 rtl_ephy_init(tp, e_info_8402);
3519
3520 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3521 rtl_reset_packet_filter(tp);
3522 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3523 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3524 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3525
3526 /* disable EEE */
3527 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3528
3529 rtl_pcie_state_l2l3_disable(tp);
3530 }
3531
rtl_hw_start_8106(struct rtl8169_private * tp)3532 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3533 {
3534 rtl_hw_aspm_clkreq_enable(tp, false);
3535
3536 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3537 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3538
3539 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3540 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3541 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3542
3543 /* L0 7us, L1 32us - needed to avoid issues with link-up detection */
3544 rtl_set_aspm_entry_latency(tp, 0x2f);
3545
3546 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3547
3548 /* disable EEE */
3549 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3550
3551 rtl_pcie_state_l2l3_disable(tp);
3552 rtl_hw_aspm_clkreq_enable(tp, true);
3553 }
3554
DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)3555 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3556 {
3557 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3558 }
3559
rtl_hw_start_8125_common(struct rtl8169_private * tp)3560 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3561 {
3562 rtl_pcie_state_l2l3_disable(tp);
3563
3564 RTL_W16(tp, 0x382, 0x221b);
3565 RTL_W8(tp, 0x4500, 0);
3566 RTL_W16(tp, 0x4800, 0);
3567
3568 /* disable UPS */
3569 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3570
3571 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3572
3573 r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3574 r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3575
3576 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3577 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3578 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3579
3580 /* disable new tx descriptor format */
3581 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3582
3583 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3584 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3585 else
3586 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3587
3588 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3589 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3590 else
3591 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3592
3593 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3594 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3595 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3596 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3597 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3598 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3599 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3600 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3601 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3602
3603 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3604 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3605 udelay(1);
3606 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3607 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3608
3609 r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3610
3611 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3612
3613 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3614 rtl8125b_config_eee_mac(tp);
3615 else
3616 rtl8125a_config_eee_mac(tp);
3617
3618 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3619 udelay(10);
3620 }
3621
rtl_hw_start_8125a_1(struct rtl8169_private * tp)3622 static void rtl_hw_start_8125a_1(struct rtl8169_private *tp)
3623 {
3624 static const struct ephy_info e_info_8125a_1[] = {
3625 { 0x01, 0xffff, 0xa812 },
3626 { 0x09, 0xffff, 0x520c },
3627 { 0x04, 0xffff, 0xd000 },
3628 { 0x0d, 0xffff, 0xf702 },
3629 { 0x0a, 0xffff, 0x8653 },
3630 { 0x06, 0xffff, 0x001e },
3631 { 0x08, 0xffff, 0x3595 },
3632 { 0x20, 0xffff, 0x9455 },
3633 { 0x21, 0xffff, 0x99ff },
3634 { 0x02, 0xffff, 0x6046 },
3635 { 0x29, 0xffff, 0xfe00 },
3636 { 0x23, 0xffff, 0xab62 },
3637
3638 { 0x41, 0xffff, 0xa80c },
3639 { 0x49, 0xffff, 0x520c },
3640 { 0x44, 0xffff, 0xd000 },
3641 { 0x4d, 0xffff, 0xf702 },
3642 { 0x4a, 0xffff, 0x8653 },
3643 { 0x46, 0xffff, 0x001e },
3644 { 0x48, 0xffff, 0x3595 },
3645 { 0x60, 0xffff, 0x9455 },
3646 { 0x61, 0xffff, 0x99ff },
3647 { 0x42, 0xffff, 0x6046 },
3648 { 0x69, 0xffff, 0xfe00 },
3649 { 0x63, 0xffff, 0xab62 },
3650 };
3651
3652 rtl_set_def_aspm_entry_latency(tp);
3653
3654 /* disable aspm and clock request before access ephy */
3655 rtl_hw_aspm_clkreq_enable(tp, false);
3656 rtl_ephy_init(tp, e_info_8125a_1);
3657
3658 rtl_hw_start_8125_common(tp);
3659 rtl_hw_aspm_clkreq_enable(tp, true);
3660 }
3661
rtl_hw_start_8125a_2(struct rtl8169_private * tp)3662 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3663 {
3664 static const struct ephy_info e_info_8125a_2[] = {
3665 { 0x04, 0xffff, 0xd000 },
3666 { 0x0a, 0xffff, 0x8653 },
3667 { 0x23, 0xffff, 0xab66 },
3668 { 0x20, 0xffff, 0x9455 },
3669 { 0x21, 0xffff, 0x99ff },
3670 { 0x29, 0xffff, 0xfe04 },
3671
3672 { 0x44, 0xffff, 0xd000 },
3673 { 0x4a, 0xffff, 0x8653 },
3674 { 0x63, 0xffff, 0xab66 },
3675 { 0x60, 0xffff, 0x9455 },
3676 { 0x61, 0xffff, 0x99ff },
3677 { 0x69, 0xffff, 0xfe04 },
3678 };
3679
3680 rtl_set_def_aspm_entry_latency(tp);
3681
3682 /* disable aspm and clock request before access ephy */
3683 rtl_hw_aspm_clkreq_enable(tp, false);
3684 rtl_ephy_init(tp, e_info_8125a_2);
3685
3686 rtl_hw_start_8125_common(tp);
3687 rtl_hw_aspm_clkreq_enable(tp, true);
3688 }
3689
rtl_hw_start_8125b(struct rtl8169_private * tp)3690 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3691 {
3692 static const struct ephy_info e_info_8125b[] = {
3693 { 0x0b, 0xffff, 0xa908 },
3694 { 0x1e, 0xffff, 0x20eb },
3695 { 0x4b, 0xffff, 0xa908 },
3696 { 0x5e, 0xffff, 0x20eb },
3697 { 0x22, 0x0030, 0x0020 },
3698 { 0x62, 0x0030, 0x0020 },
3699 };
3700
3701 rtl_set_def_aspm_entry_latency(tp);
3702 rtl_hw_aspm_clkreq_enable(tp, false);
3703
3704 rtl_ephy_init(tp, e_info_8125b);
3705 rtl_hw_start_8125_common(tp);
3706
3707 rtl_hw_aspm_clkreq_enable(tp, true);
3708 }
3709
rtl_hw_config(struct rtl8169_private * tp)3710 static void rtl_hw_config(struct rtl8169_private *tp)
3711 {
3712 static const rtl_generic_fct hw_configs[] = {
3713 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3714 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3715 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3716 [RTL_GIGA_MAC_VER_10] = NULL,
3717 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3718 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b,
3719 [RTL_GIGA_MAC_VER_13] = NULL,
3720 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3721 [RTL_GIGA_MAC_VER_16] = NULL,
3722 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3723 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3724 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3725 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3726 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2,
3727 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3728 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3729 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3730 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3731 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3732 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
3733 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3734 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3735 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3736 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3737 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3738 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3739 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3740 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3741 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3742 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3743 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3744 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3745 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3746 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
3747 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3748 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3749 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3750 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
3751 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3752 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
3753 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3754 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
3755 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
3756 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3757 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3758 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
3759 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1,
3760 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3761 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3762 };
3763
3764 if (hw_configs[tp->mac_version])
3765 hw_configs[tp->mac_version](tp);
3766 }
3767
rtl_hw_start_8125(struct rtl8169_private * tp)3768 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3769 {
3770 int i;
3771
3772 /* disable interrupt coalescing */
3773 for (i = 0xa00; i < 0xb00; i += 4)
3774 RTL_W32(tp, i, 0);
3775
3776 rtl_hw_config(tp);
3777 }
3778
rtl_hw_start_8168(struct rtl8169_private * tp)3779 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3780 {
3781 if (rtl_is_8168evl_up(tp))
3782 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3783 else
3784 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3785
3786 rtl_hw_config(tp);
3787
3788 /* disable interrupt coalescing */
3789 RTL_W16(tp, IntrMitigate, 0x0000);
3790 }
3791
rtl_hw_start_8169(struct rtl8169_private * tp)3792 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3793 {
3794 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3795
3796 tp->cp_cmd |= PCIMulRW;
3797
3798 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3799 tp->mac_version == RTL_GIGA_MAC_VER_03)
3800 tp->cp_cmd |= EnAnaPLL;
3801
3802 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3803
3804 rtl8169_set_magic_reg(tp);
3805
3806 /* disable interrupt coalescing */
3807 RTL_W16(tp, IntrMitigate, 0x0000);
3808 }
3809
rtl_hw_start(struct rtl8169_private * tp)3810 static void rtl_hw_start(struct rtl8169_private *tp)
3811 {
3812 rtl_unlock_config_regs(tp);
3813
3814 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3815
3816 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3817 rtl_hw_start_8169(tp);
3818 else if (rtl_is_8125(tp))
3819 rtl_hw_start_8125(tp);
3820 else
3821 rtl_hw_start_8168(tp);
3822
3823 rtl_enable_exit_l1(tp);
3824 rtl_set_rx_max_size(tp);
3825 rtl_set_rx_tx_desc_registers(tp);
3826 rtl_lock_config_regs(tp);
3827
3828 rtl_jumbo_config(tp);
3829
3830 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3831 rtl_pci_commit(tp);
3832
3833 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3834 rtl_init_rxcfg(tp);
3835 rtl_set_tx_config_registers(tp);
3836 rtl_set_rx_config_features(tp, tp->dev->features);
3837 rtl_set_rx_mode(tp->dev);
3838 rtl_irq_enable(tp);
3839 }
3840
rtl8169_change_mtu(struct net_device * dev,int new_mtu)3841 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3842 {
3843 struct rtl8169_private *tp = netdev_priv(dev);
3844
3845 dev->mtu = new_mtu;
3846 netdev_update_features(dev);
3847 rtl_jumbo_config(tp);
3848
3849 switch (tp->mac_version) {
3850 case RTL_GIGA_MAC_VER_61:
3851 case RTL_GIGA_MAC_VER_63:
3852 rtl8125_set_eee_txidle_timer(tp);
3853 break;
3854 default:
3855 break;
3856 }
3857
3858 return 0;
3859 }
3860
rtl8169_mark_to_asic(struct RxDesc * desc)3861 static void rtl8169_mark_to_asic(struct RxDesc *desc)
3862 {
3863 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3864
3865 desc->opts2 = 0;
3866 /* Force memory writes to complete before releasing descriptor */
3867 dma_wmb();
3868 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3869 }
3870
rtl8169_alloc_rx_data(struct rtl8169_private * tp,struct RxDesc * desc)3871 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3872 struct RxDesc *desc)
3873 {
3874 struct device *d = tp_to_dev(tp);
3875 int node = dev_to_node(d);
3876 dma_addr_t mapping;
3877 struct page *data;
3878
3879 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3880 if (!data)
3881 return NULL;
3882
3883 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3884 if (unlikely(dma_mapping_error(d, mapping))) {
3885 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3886 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3887 return NULL;
3888 }
3889
3890 desc->addr = cpu_to_le64(mapping);
3891 rtl8169_mark_to_asic(desc);
3892
3893 return data;
3894 }
3895
rtl8169_rx_clear(struct rtl8169_private * tp)3896 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3897 {
3898 int i;
3899
3900 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3901 dma_unmap_page(tp_to_dev(tp),
3902 le64_to_cpu(tp->RxDescArray[i].addr),
3903 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3904 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3905 tp->Rx_databuff[i] = NULL;
3906 tp->RxDescArray[i].addr = 0;
3907 tp->RxDescArray[i].opts1 = 0;
3908 }
3909 }
3910
rtl8169_rx_fill(struct rtl8169_private * tp)3911 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3912 {
3913 int i;
3914
3915 for (i = 0; i < NUM_RX_DESC; i++) {
3916 struct page *data;
3917
3918 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3919 if (!data) {
3920 rtl8169_rx_clear(tp);
3921 return -ENOMEM;
3922 }
3923 tp->Rx_databuff[i] = data;
3924 }
3925
3926 /* mark as last descriptor in the ring */
3927 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3928
3929 return 0;
3930 }
3931
rtl8169_init_ring(struct rtl8169_private * tp)3932 static int rtl8169_init_ring(struct rtl8169_private *tp)
3933 {
3934 rtl8169_init_ring_indexes(tp);
3935
3936 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3937 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3938
3939 return rtl8169_rx_fill(tp);
3940 }
3941
rtl8169_unmap_tx_skb(struct rtl8169_private * tp,unsigned int entry)3942 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3943 {
3944 struct ring_info *tx_skb = tp->tx_skb + entry;
3945 struct TxDesc *desc = tp->TxDescArray + entry;
3946
3947 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3948 DMA_TO_DEVICE);
3949 memset(desc, 0, sizeof(*desc));
3950 memset(tx_skb, 0, sizeof(*tx_skb));
3951 }
3952
rtl8169_tx_clear_range(struct rtl8169_private * tp,u32 start,unsigned int n)3953 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3954 unsigned int n)
3955 {
3956 unsigned int i;
3957
3958 for (i = 0; i < n; i++) {
3959 unsigned int entry = (start + i) % NUM_TX_DESC;
3960 struct ring_info *tx_skb = tp->tx_skb + entry;
3961 unsigned int len = tx_skb->len;
3962
3963 if (len) {
3964 struct sk_buff *skb = tx_skb->skb;
3965
3966 rtl8169_unmap_tx_skb(tp, entry);
3967 if (skb)
3968 dev_consume_skb_any(skb);
3969 }
3970 }
3971 }
3972
rtl8169_tx_clear(struct rtl8169_private * tp)3973 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3974 {
3975 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3976 netdev_reset_queue(tp->dev);
3977 }
3978
rtl8169_cleanup(struct rtl8169_private * tp,bool going_down)3979 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
3980 {
3981 napi_disable(&tp->napi);
3982
3983 /* Give a racing hard_start_xmit a few cycles to complete. */
3984 synchronize_net();
3985
3986 /* Disable interrupts */
3987 rtl8169_irq_mask_and_ack(tp);
3988
3989 rtl_rx_close(tp);
3990
3991 if (going_down && tp->dev->wol_enabled)
3992 goto no_reset;
3993
3994 switch (tp->mac_version) {
3995 case RTL_GIGA_MAC_VER_27:
3996 case RTL_GIGA_MAC_VER_28:
3997 case RTL_GIGA_MAC_VER_31:
3998 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3999 break;
4000 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4001 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4002 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4003 break;
4004 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
4005 rtl_enable_rxdvgate(tp);
4006 fsleep(2000);
4007 break;
4008 default:
4009 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4010 fsleep(100);
4011 break;
4012 }
4013
4014 rtl_hw_reset(tp);
4015 no_reset:
4016 rtl8169_tx_clear(tp);
4017 rtl8169_init_ring_indexes(tp);
4018 }
4019
rtl_reset_work(struct rtl8169_private * tp)4020 static void rtl_reset_work(struct rtl8169_private *tp)
4021 {
4022 int i;
4023
4024 netif_stop_queue(tp->dev);
4025
4026 rtl8169_cleanup(tp, false);
4027
4028 for (i = 0; i < NUM_RX_DESC; i++)
4029 rtl8169_mark_to_asic(tp->RxDescArray + i);
4030
4031 napi_enable(&tp->napi);
4032 rtl_hw_start(tp);
4033 }
4034
rtl8169_tx_timeout(struct net_device * dev,unsigned int txqueue)4035 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
4036 {
4037 struct rtl8169_private *tp = netdev_priv(dev);
4038
4039 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT);
4040 }
4041
rtl8169_tx_map(struct rtl8169_private * tp,const u32 * opts,u32 len,void * addr,unsigned int entry,bool desc_own)4042 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
4043 void *addr, unsigned int entry, bool desc_own)
4044 {
4045 struct TxDesc *txd = tp->TxDescArray + entry;
4046 struct device *d = tp_to_dev(tp);
4047 dma_addr_t mapping;
4048 u32 opts1;
4049 int ret;
4050
4051 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4052 ret = dma_mapping_error(d, mapping);
4053 if (unlikely(ret)) {
4054 if (net_ratelimit())
4055 netdev_err(tp->dev, "Failed to map TX data!\n");
4056 return ret;
4057 }
4058
4059 txd->addr = cpu_to_le64(mapping);
4060 txd->opts2 = cpu_to_le32(opts[1]);
4061
4062 opts1 = opts[0] | len;
4063 if (entry == NUM_TX_DESC - 1)
4064 opts1 |= RingEnd;
4065 if (desc_own)
4066 opts1 |= DescOwn;
4067 txd->opts1 = cpu_to_le32(opts1);
4068
4069 tp->tx_skb[entry].len = len;
4070
4071 return 0;
4072 }
4073
rtl8169_xmit_frags(struct rtl8169_private * tp,struct sk_buff * skb,const u32 * opts,unsigned int entry)4074 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4075 const u32 *opts, unsigned int entry)
4076 {
4077 struct skb_shared_info *info = skb_shinfo(skb);
4078 unsigned int cur_frag;
4079
4080 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4081 const skb_frag_t *frag = info->frags + cur_frag;
4082 void *addr = skb_frag_address(frag);
4083 u32 len = skb_frag_size(frag);
4084
4085 entry = (entry + 1) % NUM_TX_DESC;
4086
4087 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4088 goto err_out;
4089 }
4090
4091 return 0;
4092
4093 err_out:
4094 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4095 return -EIO;
4096 }
4097
rtl_skb_is_udp(struct sk_buff * skb)4098 static bool rtl_skb_is_udp(struct sk_buff *skb)
4099 {
4100 int no = skb_network_offset(skb);
4101 struct ipv6hdr *i6h, _i6h;
4102 struct iphdr *ih, _ih;
4103
4104 switch (vlan_get_protocol(skb)) {
4105 case htons(ETH_P_IP):
4106 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih);
4107 return ih && ih->protocol == IPPROTO_UDP;
4108 case htons(ETH_P_IPV6):
4109 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h);
4110 return i6h && i6h->nexthdr == IPPROTO_UDP;
4111 default:
4112 return false;
4113 }
4114 }
4115
4116 #define RTL_MIN_PATCH_LEN 47
4117
4118 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
rtl8125_quirk_udp_padto(struct rtl8169_private * tp,struct sk_buff * skb)4119 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4120 struct sk_buff *skb)
4121 {
4122 unsigned int padto = 0, len = skb->len;
4123
4124 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&
4125 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) {
4126 unsigned int trans_data_len = skb_tail_pointer(skb) -
4127 skb_transport_header(skb);
4128
4129 if (trans_data_len >= offsetof(struct udphdr, len) &&
4130 trans_data_len < RTL_MIN_PATCH_LEN) {
4131 u16 dest = ntohs(udp_hdr(skb)->dest);
4132
4133 /* dest is a standard PTP port */
4134 if (dest == 319 || dest == 320)
4135 padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4136 }
4137
4138 if (trans_data_len < sizeof(struct udphdr))
4139 padto = max_t(unsigned int, padto,
4140 len + sizeof(struct udphdr) - trans_data_len);
4141 }
4142
4143 return padto;
4144 }
4145
rtl_quirk_packet_padto(struct rtl8169_private * tp,struct sk_buff * skb)4146 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4147 struct sk_buff *skb)
4148 {
4149 unsigned int padto;
4150
4151 padto = rtl8125_quirk_udp_padto(tp, skb);
4152
4153 switch (tp->mac_version) {
4154 case RTL_GIGA_MAC_VER_34:
4155 case RTL_GIGA_MAC_VER_60:
4156 case RTL_GIGA_MAC_VER_61:
4157 case RTL_GIGA_MAC_VER_63:
4158 padto = max_t(unsigned int, padto, ETH_ZLEN);
4159 break;
4160 default:
4161 break;
4162 }
4163
4164 return padto;
4165 }
4166
rtl8169_tso_csum_v1(struct sk_buff * skb,u32 * opts)4167 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4168 {
4169 u32 mss = skb_shinfo(skb)->gso_size;
4170
4171 if (mss) {
4172 opts[0] |= TD_LSO;
4173 opts[0] |= mss << TD0_MSS_SHIFT;
4174 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4175 const struct iphdr *ip = ip_hdr(skb);
4176
4177 if (ip->protocol == IPPROTO_TCP)
4178 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4179 else if (ip->protocol == IPPROTO_UDP)
4180 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4181 else
4182 WARN_ON_ONCE(1);
4183 }
4184 }
4185
rtl8169_tso_csum_v2(struct rtl8169_private * tp,struct sk_buff * skb,u32 * opts)4186 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4187 struct sk_buff *skb, u32 *opts)
4188 {
4189 struct skb_shared_info *shinfo = skb_shinfo(skb);
4190 u32 mss = shinfo->gso_size;
4191
4192 if (mss) {
4193 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4194 opts[0] |= TD1_GTSENV4;
4195 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4196 if (skb_cow_head(skb, 0))
4197 return false;
4198
4199 tcp_v6_gso_csum_prep(skb);
4200 opts[0] |= TD1_GTSENV6;
4201 } else {
4202 WARN_ON_ONCE(1);
4203 }
4204
4205 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT;
4206 opts[1] |= mss << TD1_MSS_SHIFT;
4207 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4208 u8 ip_protocol;
4209
4210 switch (vlan_get_protocol(skb)) {
4211 case htons(ETH_P_IP):
4212 opts[1] |= TD1_IPv4_CS;
4213 ip_protocol = ip_hdr(skb)->protocol;
4214 break;
4215
4216 case htons(ETH_P_IPV6):
4217 opts[1] |= TD1_IPv6_CS;
4218 ip_protocol = ipv6_hdr(skb)->nexthdr;
4219 break;
4220
4221 default:
4222 ip_protocol = IPPROTO_RAW;
4223 break;
4224 }
4225
4226 if (ip_protocol == IPPROTO_TCP)
4227 opts[1] |= TD1_TCP_CS;
4228 else if (ip_protocol == IPPROTO_UDP)
4229 opts[1] |= TD1_UDP_CS;
4230 else
4231 WARN_ON_ONCE(1);
4232
4233 opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT;
4234 } else {
4235 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4236
4237 /* skb_padto would free the skb on error */
4238 return !__skb_put_padto(skb, padto, false);
4239 }
4240
4241 return true;
4242 }
4243
rtl_tx_slots_avail(struct rtl8169_private * tp)4244 static bool rtl_tx_slots_avail(struct rtl8169_private *tp)
4245 {
4246 unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC
4247 - READ_ONCE(tp->cur_tx);
4248
4249 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
4250 return slots_avail > MAX_SKB_FRAGS;
4251 }
4252
4253 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
rtl_chip_supports_csum_v2(struct rtl8169_private * tp)4254 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4255 {
4256 switch (tp->mac_version) {
4257 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4258 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4259 return false;
4260 default:
4261 return true;
4262 }
4263 }
4264
rtl8169_doorbell(struct rtl8169_private * tp)4265 static void rtl8169_doorbell(struct rtl8169_private *tp)
4266 {
4267 if (rtl_is_8125(tp))
4268 RTL_W16(tp, TxPoll_8125, BIT(0));
4269 else
4270 RTL_W8(tp, TxPoll, NPQ);
4271 }
4272
rtl8169_start_xmit(struct sk_buff * skb,struct net_device * dev)4273 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4274 struct net_device *dev)
4275 {
4276 unsigned int frags = skb_shinfo(skb)->nr_frags;
4277 struct rtl8169_private *tp = netdev_priv(dev);
4278 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4279 struct TxDesc *txd_first, *txd_last;
4280 bool stop_queue, door_bell;
4281 u32 opts[2];
4282
4283 if (unlikely(!rtl_tx_slots_avail(tp))) {
4284 if (net_ratelimit())
4285 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4286 goto err_stop_0;
4287 }
4288
4289 opts[1] = rtl8169_tx_vlan_tag(skb);
4290 opts[0] = 0;
4291
4292 if (!rtl_chip_supports_csum_v2(tp))
4293 rtl8169_tso_csum_v1(skb, opts);
4294 else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4295 goto err_dma_0;
4296
4297 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4298 entry, false)))
4299 goto err_dma_0;
4300
4301 txd_first = tp->TxDescArray + entry;
4302
4303 if (frags) {
4304 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4305 goto err_dma_1;
4306 entry = (entry + frags) % NUM_TX_DESC;
4307 }
4308
4309 txd_last = tp->TxDescArray + entry;
4310 txd_last->opts1 |= cpu_to_le32(LastFrag);
4311 tp->tx_skb[entry].skb = skb;
4312
4313 skb_tx_timestamp(skb);
4314
4315 /* Force memory writes to complete before releasing descriptor */
4316 dma_wmb();
4317
4318 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4319
4320 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4321
4322 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4323 smp_wmb();
4324
4325 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
4326
4327 stop_queue = !rtl_tx_slots_avail(tp);
4328 if (unlikely(stop_queue)) {
4329 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
4330 * not miss a ring update when it notices a stopped queue.
4331 */
4332 smp_wmb();
4333 netif_stop_queue(dev);
4334 /* Sync with rtl_tx:
4335 * - publish queue status and cur_tx ring index (write barrier)
4336 * - refresh dirty_tx ring index (read barrier).
4337 * May the current thread have a pessimistic view of the ring
4338 * status and forget to wake up queue, a racing rtl_tx thread
4339 * can't.
4340 */
4341 smp_mb__after_atomic();
4342 if (rtl_tx_slots_avail(tp))
4343 netif_start_queue(dev);
4344 door_bell = true;
4345 }
4346
4347 if (door_bell)
4348 rtl8169_doorbell(tp);
4349
4350 return NETDEV_TX_OK;
4351
4352 err_dma_1:
4353 rtl8169_unmap_tx_skb(tp, entry);
4354 err_dma_0:
4355 dev_kfree_skb_any(skb);
4356 dev->stats.tx_dropped++;
4357 return NETDEV_TX_OK;
4358
4359 err_stop_0:
4360 netif_stop_queue(dev);
4361 dev->stats.tx_dropped++;
4362 return NETDEV_TX_BUSY;
4363 }
4364
rtl_last_frag_len(struct sk_buff * skb)4365 static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4366 {
4367 struct skb_shared_info *info = skb_shinfo(skb);
4368 unsigned int nr_frags = info->nr_frags;
4369
4370 if (!nr_frags)
4371 return UINT_MAX;
4372
4373 return skb_frag_size(info->frags + nr_frags - 1);
4374 }
4375
4376 /* Workaround for hw issues with TSO on RTL8168evl */
rtl8168evl_fix_tso(struct sk_buff * skb,netdev_features_t features)4377 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4378 netdev_features_t features)
4379 {
4380 /* IPv4 header has options field */
4381 if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4382 ip_hdrlen(skb) > sizeof(struct iphdr))
4383 features &= ~NETIF_F_ALL_TSO;
4384
4385 /* IPv4 TCP header has options field */
4386 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4387 tcp_hdrlen(skb) > sizeof(struct tcphdr))
4388 features &= ~NETIF_F_ALL_TSO;
4389
4390 else if (rtl_last_frag_len(skb) <= 6)
4391 features &= ~NETIF_F_ALL_TSO;
4392
4393 return features;
4394 }
4395
rtl8169_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)4396 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4397 struct net_device *dev,
4398 netdev_features_t features)
4399 {
4400 struct rtl8169_private *tp = netdev_priv(dev);
4401
4402 if (skb_is_gso(skb)) {
4403 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4404 features = rtl8168evl_fix_tso(skb, features);
4405
4406 if (skb_transport_offset(skb) > GTTCPHO_MAX &&
4407 rtl_chip_supports_csum_v2(tp))
4408 features &= ~NETIF_F_ALL_TSO;
4409 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4410 /* work around hw bug on some chip versions */
4411 if (skb->len < ETH_ZLEN)
4412 features &= ~NETIF_F_CSUM_MASK;
4413
4414 if (rtl_quirk_packet_padto(tp, skb))
4415 features &= ~NETIF_F_CSUM_MASK;
4416
4417 if (skb_transport_offset(skb) > TCPHO_MAX &&
4418 rtl_chip_supports_csum_v2(tp))
4419 features &= ~NETIF_F_CSUM_MASK;
4420 }
4421
4422 return vlan_features_check(skb, features);
4423 }
4424
rtl8169_pcierr_interrupt(struct net_device * dev)4425 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4426 {
4427 struct rtl8169_private *tp = netdev_priv(dev);
4428 struct pci_dev *pdev = tp->pci_dev;
4429 int pci_status_errs;
4430 u16 pci_cmd;
4431
4432 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4433
4434 pci_status_errs = pci_status_get_and_clear_errors(pdev);
4435
4436 if (net_ratelimit())
4437 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4438 pci_cmd, pci_status_errs);
4439
4440 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4441 }
4442
rtl_tx(struct net_device * dev,struct rtl8169_private * tp,int budget)4443 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4444 int budget)
4445 {
4446 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
4447 struct sk_buff *skb;
4448
4449 dirty_tx = tp->dirty_tx;
4450
4451 while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4452 unsigned int entry = dirty_tx % NUM_TX_DESC;
4453 u32 status;
4454
4455 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1));
4456 if (status & DescOwn)
4457 break;
4458
4459 skb = tp->tx_skb[entry].skb;
4460 rtl8169_unmap_tx_skb(tp, entry);
4461
4462 if (skb) {
4463 pkts_compl++;
4464 bytes_compl += skb->len;
4465 napi_consume_skb(skb, budget);
4466 }
4467 dirty_tx++;
4468 }
4469
4470 if (tp->dirty_tx != dirty_tx) {
4471 netdev_completed_queue(dev, pkts_compl, bytes_compl);
4472 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl);
4473
4474 /* Sync with rtl8169_start_xmit:
4475 * - publish dirty_tx ring index (write barrier)
4476 * - refresh cur_tx ring index and queue status (read barrier)
4477 * May the current thread miss the stopped queue condition,
4478 * a racing xmit thread can only have a right view of the
4479 * ring status.
4480 */
4481 smp_store_mb(tp->dirty_tx, dirty_tx);
4482 if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp))
4483 netif_wake_queue(dev);
4484 /*
4485 * 8168 hack: TxPoll requests are lost when the Tx packets are
4486 * too close. Let's kick an extra TxPoll request when a burst
4487 * of start_xmit activity is detected (if it is not detected,
4488 * it is slow enough). -- FR
4489 * If skb is NULL then we come here again once a tx irq is
4490 * triggered after the last fragment is marked transmitted.
4491 */
4492 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb)
4493 rtl8169_doorbell(tp);
4494 }
4495 }
4496
rtl8169_fragmented_frame(u32 status)4497 static inline int rtl8169_fragmented_frame(u32 status)
4498 {
4499 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4500 }
4501
rtl8169_rx_csum(struct sk_buff * skb,u32 opts1)4502 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4503 {
4504 u32 status = opts1 & (RxProtoMask | RxCSFailMask);
4505
4506 if (status == RxProtoTCP || status == RxProtoUDP)
4507 skb->ip_summed = CHECKSUM_UNNECESSARY;
4508 else
4509 skb_checksum_none_assert(skb);
4510 }
4511
rtl_rx(struct net_device * dev,struct rtl8169_private * tp,int budget)4512 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
4513 {
4514 struct device *d = tp_to_dev(tp);
4515 int count;
4516
4517 for (count = 0; count < budget; count++, tp->cur_rx++) {
4518 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
4519 struct RxDesc *desc = tp->RxDescArray + entry;
4520 struct sk_buff *skb;
4521 const void *rx_buf;
4522 dma_addr_t addr;
4523 u32 status;
4524
4525 status = le32_to_cpu(READ_ONCE(desc->opts1));
4526 if (status & DescOwn)
4527 break;
4528
4529 /* This barrier is needed to keep us from reading
4530 * any other fields out of the Rx descriptor until
4531 * we know the status of DescOwn
4532 */
4533 dma_rmb();
4534
4535 if (unlikely(status & RxRES)) {
4536 if (net_ratelimit())
4537 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4538 status);
4539 dev->stats.rx_errors++;
4540 if (status & (RxRWT | RxRUNT))
4541 dev->stats.rx_length_errors++;
4542 if (status & RxCRC)
4543 dev->stats.rx_crc_errors++;
4544
4545 if (!(dev->features & NETIF_F_RXALL))
4546 goto release_descriptor;
4547 else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4548 goto release_descriptor;
4549 }
4550
4551 pkt_size = status & GENMASK(13, 0);
4552 if (likely(!(dev->features & NETIF_F_RXFCS)))
4553 pkt_size -= ETH_FCS_LEN;
4554
4555 /* The driver does not support incoming fragmented frames.
4556 * They are seen as a symptom of over-mtu sized frames.
4557 */
4558 if (unlikely(rtl8169_fragmented_frame(status))) {
4559 dev->stats.rx_dropped++;
4560 dev->stats.rx_length_errors++;
4561 goto release_descriptor;
4562 }
4563
4564 skb = napi_alloc_skb(&tp->napi, pkt_size);
4565 if (unlikely(!skb)) {
4566 dev->stats.rx_dropped++;
4567 goto release_descriptor;
4568 }
4569
4570 addr = le64_to_cpu(desc->addr);
4571 rx_buf = page_address(tp->Rx_databuff[entry]);
4572
4573 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4574 prefetch(rx_buf);
4575 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4576 skb->tail += pkt_size;
4577 skb->len = pkt_size;
4578 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4579
4580 rtl8169_rx_csum(skb, status);
4581 skb->protocol = eth_type_trans(skb, dev);
4582
4583 rtl8169_rx_vlan_tag(desc, skb);
4584
4585 if (skb->pkt_type == PACKET_MULTICAST)
4586 dev->stats.multicast++;
4587
4588 napi_gro_receive(&tp->napi, skb);
4589
4590 dev_sw_netstats_rx_add(dev, pkt_size);
4591 release_descriptor:
4592 rtl8169_mark_to_asic(desc);
4593 }
4594
4595 return count;
4596 }
4597
rtl8169_interrupt(int irq,void * dev_instance)4598 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4599 {
4600 struct rtl8169_private *tp = dev_instance;
4601 u32 status = rtl_get_events(tp);
4602
4603 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4604 return IRQ_NONE;
4605
4606 if (unlikely(status & SYSErr)) {
4607 rtl8169_pcierr_interrupt(tp->dev);
4608 goto out;
4609 }
4610
4611 if (status & LinkChg)
4612 phy_mac_interrupt(tp->phydev);
4613
4614 if (unlikely(status & RxFIFOOver &&
4615 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4616 netif_stop_queue(tp->dev);
4617 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4618 }
4619
4620 if (napi_schedule_prep(&tp->napi)) {
4621 rtl_irq_disable(tp);
4622 __napi_schedule(&tp->napi);
4623 }
4624 out:
4625 rtl_ack_events(tp, status);
4626
4627 return IRQ_HANDLED;
4628 }
4629
rtl_task(struct work_struct * work)4630 static void rtl_task(struct work_struct *work)
4631 {
4632 struct rtl8169_private *tp =
4633 container_of(work, struct rtl8169_private, wk.work);
4634 int ret;
4635
4636 rtnl_lock();
4637
4638 if (!netif_running(tp->dev) ||
4639 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4640 goto out_unlock;
4641
4642 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) {
4643 /* ASPM compatibility issues are a typical reason for tx timeouts */
4644 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 |
4645 PCIE_LINK_STATE_L0S);
4646 if (!ret)
4647 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n");
4648 goto reset;
4649 }
4650
4651 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4652 reset:
4653 rtl_reset_work(tp);
4654 netif_wake_queue(tp->dev);
4655 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) {
4656 rtl_reset_work(tp);
4657 }
4658 out_unlock:
4659 rtnl_unlock();
4660 }
4661
rtl8169_poll(struct napi_struct * napi,int budget)4662 static int rtl8169_poll(struct napi_struct *napi, int budget)
4663 {
4664 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4665 struct net_device *dev = tp->dev;
4666 int work_done;
4667
4668 rtl_tx(dev, tp, budget);
4669
4670 work_done = rtl_rx(dev, tp, budget);
4671
4672 if (work_done < budget && napi_complete_done(napi, work_done))
4673 rtl_irq_enable(tp);
4674
4675 return work_done;
4676 }
4677
r8169_phylink_handler(struct net_device * ndev)4678 static void r8169_phylink_handler(struct net_device *ndev)
4679 {
4680 struct rtl8169_private *tp = netdev_priv(ndev);
4681 struct device *d = tp_to_dev(tp);
4682
4683 if (netif_carrier_ok(ndev)) {
4684 rtl_link_chg_patch(tp);
4685 pm_request_resume(d);
4686 netif_wake_queue(tp->dev);
4687 } else {
4688 /* In few cases rx is broken after link-down otherwise */
4689 if (rtl_is_8125(tp))
4690 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE);
4691 pm_runtime_idle(d);
4692 }
4693
4694 if (net_ratelimit())
4695 phy_print_status(tp->phydev);
4696 }
4697
r8169_phy_connect(struct rtl8169_private * tp)4698 static int r8169_phy_connect(struct rtl8169_private *tp)
4699 {
4700 struct phy_device *phydev = tp->phydev;
4701 phy_interface_t phy_mode;
4702 int ret;
4703
4704 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4705 PHY_INTERFACE_MODE_MII;
4706
4707 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4708 phy_mode);
4709 if (ret)
4710 return ret;
4711
4712 if (!tp->supports_gmii)
4713 phy_set_max_speed(phydev, SPEED_100);
4714
4715 phy_attached_info(phydev);
4716
4717 return 0;
4718 }
4719
rtl8169_down(struct rtl8169_private * tp)4720 static void rtl8169_down(struct rtl8169_private *tp)
4721 {
4722 /* Clear all task flags */
4723 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4724
4725 phy_stop(tp->phydev);
4726
4727 rtl8169_update_counters(tp);
4728
4729 pci_clear_master(tp->pci_dev);
4730 rtl_pci_commit(tp);
4731
4732 rtl8169_cleanup(tp, true);
4733
4734 rtl_prepare_power_down(tp);
4735
4736 if (tp->dash_type != RTL_DASH_NONE)
4737 rtl8168_driver_stop(tp);
4738 }
4739
rtl8169_up(struct rtl8169_private * tp)4740 static void rtl8169_up(struct rtl8169_private *tp)
4741 {
4742 if (tp->dash_type != RTL_DASH_NONE)
4743 rtl8168_driver_start(tp);
4744
4745 pci_set_master(tp->pci_dev);
4746 phy_init_hw(tp->phydev);
4747 phy_resume(tp->phydev);
4748 rtl8169_init_phy(tp);
4749 napi_enable(&tp->napi);
4750 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4751 rtl_reset_work(tp);
4752
4753 phy_start(tp->phydev);
4754 }
4755
rtl8169_close(struct net_device * dev)4756 static int rtl8169_close(struct net_device *dev)
4757 {
4758 struct rtl8169_private *tp = netdev_priv(dev);
4759 struct pci_dev *pdev = tp->pci_dev;
4760
4761 pm_runtime_get_sync(&pdev->dev);
4762
4763 netif_stop_queue(dev);
4764 rtl8169_down(tp);
4765 rtl8169_rx_clear(tp);
4766
4767 cancel_work(&tp->wk.work);
4768
4769 free_irq(pci_irq_vector(pdev, 0), tp);
4770
4771 phy_disconnect(tp->phydev);
4772
4773 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4774 tp->RxPhyAddr);
4775 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4776 tp->TxPhyAddr);
4777 tp->TxDescArray = NULL;
4778 tp->RxDescArray = NULL;
4779
4780 pm_runtime_put_sync(&pdev->dev);
4781
4782 return 0;
4783 }
4784
4785 #ifdef CONFIG_NET_POLL_CONTROLLER
rtl8169_netpoll(struct net_device * dev)4786 static void rtl8169_netpoll(struct net_device *dev)
4787 {
4788 struct rtl8169_private *tp = netdev_priv(dev);
4789
4790 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
4791 }
4792 #endif
4793
rtl_open(struct net_device * dev)4794 static int rtl_open(struct net_device *dev)
4795 {
4796 struct rtl8169_private *tp = netdev_priv(dev);
4797 struct pci_dev *pdev = tp->pci_dev;
4798 unsigned long irqflags;
4799 int retval = -ENOMEM;
4800
4801 pm_runtime_get_sync(&pdev->dev);
4802
4803 /*
4804 * Rx and Tx descriptors needs 256 bytes alignment.
4805 * dma_alloc_coherent provides more.
4806 */
4807 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4808 &tp->TxPhyAddr, GFP_KERNEL);
4809 if (!tp->TxDescArray)
4810 goto out;
4811
4812 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4813 &tp->RxPhyAddr, GFP_KERNEL);
4814 if (!tp->RxDescArray)
4815 goto err_free_tx_0;
4816
4817 retval = rtl8169_init_ring(tp);
4818 if (retval < 0)
4819 goto err_free_rx_1;
4820
4821 rtl_request_firmware(tp);
4822
4823 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
4824 retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt,
4825 irqflags, dev->name, tp);
4826 if (retval < 0)
4827 goto err_release_fw_2;
4828
4829 retval = r8169_phy_connect(tp);
4830 if (retval)
4831 goto err_free_irq;
4832
4833 rtl8169_up(tp);
4834 rtl8169_init_counter_offsets(tp);
4835 netif_start_queue(dev);
4836 out:
4837 pm_runtime_put_sync(&pdev->dev);
4838
4839 return retval;
4840
4841 err_free_irq:
4842 free_irq(pci_irq_vector(pdev, 0), tp);
4843 err_release_fw_2:
4844 rtl_release_firmware(tp);
4845 rtl8169_rx_clear(tp);
4846 err_free_rx_1:
4847 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4848 tp->RxPhyAddr);
4849 tp->RxDescArray = NULL;
4850 err_free_tx_0:
4851 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4852 tp->TxPhyAddr);
4853 tp->TxDescArray = NULL;
4854 goto out;
4855 }
4856
4857 static void
rtl8169_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * stats)4858 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4859 {
4860 struct rtl8169_private *tp = netdev_priv(dev);
4861 struct pci_dev *pdev = tp->pci_dev;
4862 struct rtl8169_counters *counters = tp->counters;
4863
4864 pm_runtime_get_noresume(&pdev->dev);
4865
4866 netdev_stats_to_stats64(stats, &dev->stats);
4867 dev_fetch_sw_netstats(stats, dev->tstats);
4868
4869 /*
4870 * Fetch additional counter values missing in stats collected by driver
4871 * from tally counters.
4872 */
4873 if (pm_runtime_active(&pdev->dev))
4874 rtl8169_update_counters(tp);
4875
4876 /*
4877 * Subtract values fetched during initalization.
4878 * See rtl8169_init_counter_offsets for a description why we do that.
4879 */
4880 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4881 le64_to_cpu(tp->tc_offset.tx_errors);
4882 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4883 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4884 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4885 le16_to_cpu(tp->tc_offset.tx_aborted);
4886 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4887 le16_to_cpu(tp->tc_offset.rx_missed);
4888
4889 pm_runtime_put_noidle(&pdev->dev);
4890 }
4891
rtl8169_net_suspend(struct rtl8169_private * tp)4892 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4893 {
4894 netif_device_detach(tp->dev);
4895
4896 if (netif_running(tp->dev))
4897 rtl8169_down(tp);
4898 }
4899
4900 #ifdef CONFIG_PM
4901
rtl8169_runtime_resume(struct device * dev)4902 static int rtl8169_runtime_resume(struct device *dev)
4903 {
4904 struct rtl8169_private *tp = dev_get_drvdata(dev);
4905
4906 rtl_rar_set(tp, tp->dev->dev_addr);
4907 __rtl8169_set_wol(tp, tp->saved_wolopts);
4908
4909 if (tp->TxDescArray)
4910 rtl8169_up(tp);
4911
4912 netif_device_attach(tp->dev);
4913
4914 return 0;
4915 }
4916
rtl8169_suspend(struct device * device)4917 static int __maybe_unused rtl8169_suspend(struct device *device)
4918 {
4919 struct rtl8169_private *tp = dev_get_drvdata(device);
4920
4921 rtnl_lock();
4922 rtl8169_net_suspend(tp);
4923 if (!device_may_wakeup(tp_to_dev(tp)))
4924 clk_disable_unprepare(tp->clk);
4925 rtnl_unlock();
4926
4927 return 0;
4928 }
4929
rtl8169_resume(struct device * device)4930 static int __maybe_unused rtl8169_resume(struct device *device)
4931 {
4932 struct rtl8169_private *tp = dev_get_drvdata(device);
4933
4934 if (!device_may_wakeup(tp_to_dev(tp)))
4935 clk_prepare_enable(tp->clk);
4936
4937 /* Reportedly at least Asus X453MA truncates packets otherwise */
4938 if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4939 rtl_init_rxcfg(tp);
4940
4941 return rtl8169_runtime_resume(device);
4942 }
4943
rtl8169_runtime_suspend(struct device * device)4944 static int rtl8169_runtime_suspend(struct device *device)
4945 {
4946 struct rtl8169_private *tp = dev_get_drvdata(device);
4947
4948 if (!tp->TxDescArray) {
4949 netif_device_detach(tp->dev);
4950 return 0;
4951 }
4952
4953 rtnl_lock();
4954 __rtl8169_set_wol(tp, WAKE_PHY);
4955 rtl8169_net_suspend(tp);
4956 rtnl_unlock();
4957
4958 return 0;
4959 }
4960
rtl8169_runtime_idle(struct device * device)4961 static int rtl8169_runtime_idle(struct device *device)
4962 {
4963 struct rtl8169_private *tp = dev_get_drvdata(device);
4964
4965 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4966 pm_schedule_suspend(device, 10000);
4967
4968 return -EBUSY;
4969 }
4970
4971 static const struct dev_pm_ops rtl8169_pm_ops = {
4972 SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4973 SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4974 rtl8169_runtime_idle)
4975 };
4976
4977 #endif /* CONFIG_PM */
4978
rtl_wol_shutdown_quirk(struct rtl8169_private * tp)4979 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
4980 {
4981 /* WoL fails with 8168b when the receiver is disabled. */
4982 switch (tp->mac_version) {
4983 case RTL_GIGA_MAC_VER_11:
4984 case RTL_GIGA_MAC_VER_12:
4985 case RTL_GIGA_MAC_VER_17:
4986 pci_clear_master(tp->pci_dev);
4987
4988 RTL_W8(tp, ChipCmd, CmdRxEnb);
4989 rtl_pci_commit(tp);
4990 break;
4991 default:
4992 break;
4993 }
4994 }
4995
rtl_shutdown(struct pci_dev * pdev)4996 static void rtl_shutdown(struct pci_dev *pdev)
4997 {
4998 struct rtl8169_private *tp = pci_get_drvdata(pdev);
4999
5000 rtnl_lock();
5001 rtl8169_net_suspend(tp);
5002 rtnl_unlock();
5003
5004 /* Restore original MAC address */
5005 rtl_rar_set(tp, tp->dev->perm_addr);
5006
5007 if (system_state == SYSTEM_POWER_OFF) {
5008 if (tp->saved_wolopts)
5009 rtl_wol_shutdown_quirk(tp);
5010
5011 pci_wake_from_d3(pdev, tp->saved_wolopts);
5012 pci_set_power_state(pdev, PCI_D3hot);
5013 }
5014 }
5015
rtl_remove_one(struct pci_dev * pdev)5016 static void rtl_remove_one(struct pci_dev *pdev)
5017 {
5018 struct rtl8169_private *tp = pci_get_drvdata(pdev);
5019
5020 if (pci_dev_run_wake(pdev))
5021 pm_runtime_get_noresume(&pdev->dev);
5022
5023 cancel_work_sync(&tp->wk.work);
5024
5025 unregister_netdev(tp->dev);
5026
5027 if (tp->dash_type != RTL_DASH_NONE)
5028 rtl8168_driver_stop(tp);
5029
5030 rtl_release_firmware(tp);
5031
5032 /* restore original MAC address */
5033 rtl_rar_set(tp, tp->dev->perm_addr);
5034 }
5035
5036 static const struct net_device_ops rtl_netdev_ops = {
5037 .ndo_open = rtl_open,
5038 .ndo_stop = rtl8169_close,
5039 .ndo_get_stats64 = rtl8169_get_stats64,
5040 .ndo_start_xmit = rtl8169_start_xmit,
5041 .ndo_features_check = rtl8169_features_check,
5042 .ndo_tx_timeout = rtl8169_tx_timeout,
5043 .ndo_validate_addr = eth_validate_addr,
5044 .ndo_change_mtu = rtl8169_change_mtu,
5045 .ndo_fix_features = rtl8169_fix_features,
5046 .ndo_set_features = rtl8169_set_features,
5047 .ndo_set_mac_address = rtl_set_mac_address,
5048 .ndo_eth_ioctl = phy_do_ioctl_running,
5049 .ndo_set_rx_mode = rtl_set_rx_mode,
5050 #ifdef CONFIG_NET_POLL_CONTROLLER
5051 .ndo_poll_controller = rtl8169_netpoll,
5052 #endif
5053
5054 };
5055
rtl_set_irq_mask(struct rtl8169_private * tp)5056 static void rtl_set_irq_mask(struct rtl8169_private *tp)
5057 {
5058 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
5059
5060 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5061 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
5062 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
5063 /* special workaround needed */
5064 tp->irq_mask |= RxFIFOOver;
5065 else
5066 tp->irq_mask |= RxOverflow;
5067 }
5068
rtl_alloc_irq(struct rtl8169_private * tp)5069 static int rtl_alloc_irq(struct rtl8169_private *tp)
5070 {
5071 unsigned int flags;
5072
5073 switch (tp->mac_version) {
5074 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5075 rtl_unlock_config_regs(tp);
5076 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
5077 rtl_lock_config_regs(tp);
5078 fallthrough;
5079 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
5080 flags = PCI_IRQ_LEGACY;
5081 break;
5082 default:
5083 flags = PCI_IRQ_ALL_TYPES;
5084 break;
5085 }
5086
5087 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
5088 }
5089
rtl_read_mac_address(struct rtl8169_private * tp,u8 mac_addr[ETH_ALEN])5090 static void rtl_read_mac_address(struct rtl8169_private *tp,
5091 u8 mac_addr[ETH_ALEN])
5092 {
5093 /* Get MAC address */
5094 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5095 u32 value;
5096
5097 value = rtl_eri_read(tp, 0xe0);
5098 put_unaligned_le32(value, mac_addr);
5099 value = rtl_eri_read(tp, 0xe4);
5100 put_unaligned_le16(value, mac_addr + 4);
5101 } else if (rtl_is_8125(tp)) {
5102 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5103 }
5104 }
5105
DECLARE_RTL_COND(rtl_link_list_ready_cond)5106 DECLARE_RTL_COND(rtl_link_list_ready_cond)
5107 {
5108 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5109 }
5110
r8168g_wait_ll_share_fifo_ready(struct rtl8169_private * tp)5111 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5112 {
5113 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5114 }
5115
r8169_mdio_read_reg(struct mii_bus * mii_bus,int phyaddr,int phyreg)5116 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5117 {
5118 struct rtl8169_private *tp = mii_bus->priv;
5119
5120 if (phyaddr > 0)
5121 return -ENODEV;
5122
5123 return rtl_readphy(tp, phyreg);
5124 }
5125
r8169_mdio_write_reg(struct mii_bus * mii_bus,int phyaddr,int phyreg,u16 val)5126 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5127 int phyreg, u16 val)
5128 {
5129 struct rtl8169_private *tp = mii_bus->priv;
5130
5131 if (phyaddr > 0)
5132 return -ENODEV;
5133
5134 rtl_writephy(tp, phyreg, val);
5135
5136 return 0;
5137 }
5138
r8169_mdio_register(struct rtl8169_private * tp)5139 static int r8169_mdio_register(struct rtl8169_private *tp)
5140 {
5141 struct pci_dev *pdev = tp->pci_dev;
5142 struct mii_bus *new_bus;
5143 int ret;
5144
5145 new_bus = devm_mdiobus_alloc(&pdev->dev);
5146 if (!new_bus)
5147 return -ENOMEM;
5148
5149 new_bus->name = "r8169";
5150 new_bus->priv = tp;
5151 new_bus->parent = &pdev->dev;
5152 new_bus->irq[0] = PHY_MAC_INTERRUPT;
5153 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
5154 pci_domain_nr(pdev->bus), pci_dev_id(pdev));
5155
5156 new_bus->read = r8169_mdio_read_reg;
5157 new_bus->write = r8169_mdio_write_reg;
5158
5159 ret = devm_mdiobus_register(&pdev->dev, new_bus);
5160 if (ret)
5161 return ret;
5162
5163 tp->phydev = mdiobus_get_phy(new_bus, 0);
5164 if (!tp->phydev) {
5165 return -ENODEV;
5166 } else if (!tp->phydev->drv) {
5167 /* Most chip versions fail with the genphy driver.
5168 * Therefore ensure that the dedicated PHY driver is loaded.
5169 */
5170 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5171 tp->phydev->phy_id);
5172 return -EUNATCH;
5173 }
5174
5175 tp->phydev->mac_managed_pm = 1;
5176
5177 phy_support_asym_pause(tp->phydev);
5178
5179 /* PHY will be woken up in rtl_open() */
5180 phy_suspend(tp->phydev);
5181
5182 return 0;
5183 }
5184
rtl_hw_init_8168g(struct rtl8169_private * tp)5185 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5186 {
5187 rtl_enable_rxdvgate(tp);
5188
5189 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5190 msleep(1);
5191 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5192
5193 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5194 r8168g_wait_ll_share_fifo_ready(tp);
5195
5196 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5197 r8168g_wait_ll_share_fifo_ready(tp);
5198 }
5199
rtl_hw_init_8125(struct rtl8169_private * tp)5200 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5201 {
5202 rtl_enable_rxdvgate(tp);
5203
5204 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5205 msleep(1);
5206 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5207
5208 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5209 r8168g_wait_ll_share_fifo_ready(tp);
5210
5211 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5212 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5213 r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5214 r8168g_wait_ll_share_fifo_ready(tp);
5215 }
5216
rtl_hw_initialize(struct rtl8169_private * tp)5217 static void rtl_hw_initialize(struct rtl8169_private *tp)
5218 {
5219 switch (tp->mac_version) {
5220 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53:
5221 rtl8168ep_stop_cmac(tp);
5222 fallthrough;
5223 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5224 rtl_hw_init_8168g(tp);
5225 break;
5226 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
5227 rtl_hw_init_8125(tp);
5228 break;
5229 default:
5230 break;
5231 }
5232 }
5233
rtl_jumbo_max(struct rtl8169_private * tp)5234 static int rtl_jumbo_max(struct rtl8169_private *tp)
5235 {
5236 /* Non-GBit versions don't support jumbo frames */
5237 if (!tp->supports_gmii)
5238 return 0;
5239
5240 switch (tp->mac_version) {
5241 /* RTL8169 */
5242 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5243 return JUMBO_7K;
5244 /* RTL8168b */
5245 case RTL_GIGA_MAC_VER_11:
5246 case RTL_GIGA_MAC_VER_12:
5247 case RTL_GIGA_MAC_VER_17:
5248 return JUMBO_4K;
5249 /* RTL8168c */
5250 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5251 return JUMBO_6K;
5252 default:
5253 return JUMBO_9K;
5254 }
5255 }
5256
rtl_disable_clk(void * data)5257 static void rtl_disable_clk(void *data)
5258 {
5259 clk_disable_unprepare(data);
5260 }
5261
rtl_get_ether_clk(struct rtl8169_private * tp)5262 static int rtl_get_ether_clk(struct rtl8169_private *tp)
5263 {
5264 struct device *d = tp_to_dev(tp);
5265 struct clk *clk;
5266 int rc;
5267
5268 clk = devm_clk_get(d, "ether_clk");
5269 if (IS_ERR(clk)) {
5270 rc = PTR_ERR(clk);
5271 if (rc == -ENOENT)
5272 /* clk-core allows NULL (for suspend / resume) */
5273 rc = 0;
5274 else
5275 dev_err_probe(d, rc, "failed to get clk\n");
5276 } else {
5277 tp->clk = clk;
5278 rc = clk_prepare_enable(clk);
5279 if (rc)
5280 dev_err(d, "failed to enable clk: %d\n", rc);
5281 else
5282 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
5283 }
5284
5285 return rc;
5286 }
5287
rtl_init_mac_address(struct rtl8169_private * tp)5288 static void rtl_init_mac_address(struct rtl8169_private *tp)
5289 {
5290 struct net_device *dev = tp->dev;
5291 u8 *mac_addr = dev->dev_addr;
5292 int rc;
5293
5294 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5295 if (!rc)
5296 goto done;
5297
5298 rtl_read_mac_address(tp, mac_addr);
5299 if (is_valid_ether_addr(mac_addr))
5300 goto done;
5301
5302 rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5303 if (is_valid_ether_addr(mac_addr))
5304 goto done;
5305
5306 eth_hw_addr_random(dev);
5307 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5308 done:
5309 rtl_rar_set(tp, mac_addr);
5310 }
5311
rtl_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)5312 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5313 {
5314 struct rtl8169_private *tp;
5315 int jumbo_max, region, rc;
5316 enum mac_version chipset;
5317 struct net_device *dev;
5318 u16 xid;
5319
5320 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5321 if (!dev)
5322 return -ENOMEM;
5323
5324 SET_NETDEV_DEV(dev, &pdev->dev);
5325 dev->netdev_ops = &rtl_netdev_ops;
5326 tp = netdev_priv(dev);
5327 tp->dev = dev;
5328 tp->pci_dev = pdev;
5329 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5330 tp->eee_adv = -1;
5331 tp->ocp_base = OCP_STD_PHY_BASE;
5332
5333 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev,
5334 struct pcpu_sw_netstats);
5335 if (!dev->tstats)
5336 return -ENOMEM;
5337
5338 /* Get the *optional* external "ether_clk" used on some boards */
5339 rc = rtl_get_ether_clk(tp);
5340 if (rc)
5341 return rc;
5342
5343 /* Disable ASPM L1 as that cause random device stop working
5344 * problems as well as full system hangs for some PCIe devices users.
5345 */
5346 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
5347 tp->aspm_manageable = !rc;
5348
5349 /* enable device (incl. PCI PM wakeup and hotplug setup) */
5350 rc = pcim_enable_device(pdev);
5351 if (rc < 0) {
5352 dev_err(&pdev->dev, "enable failure\n");
5353 return rc;
5354 }
5355
5356 if (pcim_set_mwi(pdev) < 0)
5357 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5358
5359 /* use first MMIO region */
5360 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5361 if (region < 0) {
5362 dev_err(&pdev->dev, "no MMIO resource found\n");
5363 return -ENODEV;
5364 }
5365
5366 /* check for weird/broken PCI region reporting */
5367 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
5368 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
5369 return -ENODEV;
5370 }
5371
5372 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME);
5373 if (rc < 0) {
5374 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
5375 return rc;
5376 }
5377
5378 tp->mmio_addr = pcim_iomap_table(pdev)[region];
5379
5380 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf;
5381
5382 /* Identify chip attached to board */
5383 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5384 if (chipset == RTL_GIGA_MAC_NONE) {
5385 dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid);
5386 return -ENODEV;
5387 }
5388
5389 tp->mac_version = chipset;
5390
5391 tp->dash_type = rtl_check_dash(tp);
5392
5393 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5394
5395 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5396 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5397 dev->features |= NETIF_F_HIGHDMA;
5398
5399 rtl_init_rxcfg(tp);
5400
5401 rtl8169_irq_mask_and_ack(tp);
5402
5403 rtl_hw_initialize(tp);
5404
5405 rtl_hw_reset(tp);
5406
5407 rc = rtl_alloc_irq(tp);
5408 if (rc < 0) {
5409 dev_err(&pdev->dev, "Can't allocate interrupt\n");
5410 return rc;
5411 }
5412
5413 INIT_WORK(&tp->wk.work, rtl_task);
5414
5415 rtl_init_mac_address(tp);
5416
5417 dev->ethtool_ops = &rtl8169_ethtool_ops;
5418
5419 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
5420
5421 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5422 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5423 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5424 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5425
5426 /*
5427 * Pretend we are using VLANs; This bypasses a nasty bug where
5428 * Interrupts stop flowing on high load on 8110SCd controllers.
5429 */
5430 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5431 /* Disallow toggling */
5432 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5433
5434 if (rtl_chip_supports_csum_v2(tp))
5435 dev->hw_features |= NETIF_F_IPV6_CSUM;
5436
5437 dev->features |= dev->hw_features;
5438
5439 /* There has been a number of reports that using SG/TSO results in
5440 * tx timeouts. However for a lot of people SG/TSO works fine.
5441 * Therefore disable both features by default, but allow users to
5442 * enable them. Use at own risk!
5443 */
5444 if (rtl_chip_supports_csum_v2(tp)) {
5445 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5446 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
5447 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
5448 } else {
5449 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5450 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
5451 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
5452 }
5453
5454 dev->hw_features |= NETIF_F_RXALL;
5455 dev->hw_features |= NETIF_F_RXFCS;
5456
5457 /* configure chip for default features */
5458 rtl8169_set_features(dev, dev->features);
5459
5460 rtl_set_d3_pll_down(tp, true);
5461
5462 jumbo_max = rtl_jumbo_max(tp);
5463 if (jumbo_max)
5464 dev->max_mtu = jumbo_max;
5465
5466 rtl_set_irq_mask(tp);
5467
5468 tp->fw_name = rtl_chip_infos[chipset].fw_name;
5469
5470 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5471 &tp->counters_phys_addr,
5472 GFP_KERNEL);
5473 if (!tp->counters)
5474 return -ENOMEM;
5475
5476 pci_set_drvdata(pdev, tp);
5477
5478 rc = r8169_mdio_register(tp);
5479 if (rc)
5480 return rc;
5481
5482 rc = register_netdev(dev);
5483 if (rc)
5484 return rc;
5485
5486 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5487 rtl_chip_infos[chipset].name, dev->dev_addr, xid,
5488 pci_irq_vector(pdev, 0));
5489
5490 if (jumbo_max)
5491 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5492 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5493 "ok" : "ko");
5494
5495 if (tp->dash_type != RTL_DASH_NONE) {
5496 netdev_info(dev, "DASH enabled\n");
5497 rtl8168_driver_start(tp);
5498 }
5499
5500 if (pci_dev_run_wake(pdev))
5501 pm_runtime_put_sync(&pdev->dev);
5502
5503 return 0;
5504 }
5505
5506 static struct pci_driver rtl8169_pci_driver = {
5507 .name = KBUILD_MODNAME,
5508 .id_table = rtl8169_pci_tbl,
5509 .probe = rtl_init_one,
5510 .remove = rtl_remove_one,
5511 .shutdown = rtl_shutdown,
5512 .driver.pm = pm_ptr(&rtl8169_pm_ops),
5513 };
5514
5515 module_pci_driver(rtl8169_pci_driver);
5516