1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Common routines for Tundra Semiconductor TSI108 host bridge.
4 *
5 * 2004-2005 (c) Tundra Semiconductor Corp.
6 * Author: Alex Bounine (alexandreb@tundra.com)
7 * Author: Roy Zang (tie-fei.zang@freescale.com)
8 * Add pci interrupt router host
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
14 #include <linux/irq.h>
15 #include <linux/interrupt.h>
16
17 #include <asm/byteorder.h>
18 #include <asm/io.h>
19 #include <asm/irq.h>
20 #include <linux/uaccess.h>
21 #include <asm/machdep.h>
22 #include <asm/pci-bridge.h>
23 #include <asm/tsi108.h>
24 #include <asm/tsi108_pci.h>
25 #include <asm/tsi108_irq.h>
26 #include <asm/prom.h>
27
28 #undef DEBUG
29 #ifdef DEBUG
30 #define DBG(x...) printk(x)
31 #else
32 #define DBG(x...)
33 #endif
34
35 #define tsi_mk_config_addr(bus, devfunc, offset) \
36 ((((bus)<<16) | ((devfunc)<<8) | (offset & 0xfc)) + tsi108_pci_cfg_base)
37
38 u32 tsi108_pci_cfg_base;
39 static u32 tsi108_pci_cfg_phys;
40 u32 tsi108_csr_vir_base;
41 static struct irq_domain *pci_irq_host;
42
43 extern u32 get_vir_csrbase(void);
44 extern u32 tsi108_read_reg(u32 reg_offset);
45 extern void tsi108_write_reg(u32 reg_offset, u32 val);
46
47 int
tsi108_direct_write_config(struct pci_bus * bus,unsigned int devfunc,int offset,int len,u32 val)48 tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfunc,
49 int offset, int len, u32 val)
50 {
51 volatile unsigned char *cfg_addr;
52 struct pci_controller *hose = pci_bus_to_host(bus);
53
54 if (ppc_md.pci_exclude_device)
55 if (ppc_md.pci_exclude_device(hose, bus->number, devfunc))
56 return PCIBIOS_DEVICE_NOT_FOUND;
57
58 cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
59 devfunc, offset) |
60 (offset & 0x03));
61
62 #ifdef DEBUG
63 printk("PCI CFG write : ");
64 printk("%d:0x%x:0x%x ", bus->number, devfunc, offset);
65 printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
66 printk("data = 0x%08x\n", val);
67 #endif
68
69 switch (len) {
70 case 1:
71 out_8((u8 *) cfg_addr, val);
72 break;
73 case 2:
74 out_le16((u16 *) cfg_addr, val);
75 break;
76 default:
77 out_le32((u32 *) cfg_addr, val);
78 break;
79 }
80
81 return PCIBIOS_SUCCESSFUL;
82 }
83
tsi108_clear_pci_error(u32 pci_cfg_base)84 void tsi108_clear_pci_error(u32 pci_cfg_base)
85 {
86 u32 err_stat, err_addr, pci_stat;
87
88 /*
89 * Quietly clear PB and PCI error flags set as result
90 * of PCI/X configuration read requests.
91 */
92
93 /* Read PB Error Log Registers */
94
95 err_stat = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS);
96 err_addr = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_AERR);
97
98 if (err_stat & TSI108_PB_ERRCS_ES) {
99 /* Clear error flag */
100 tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS,
101 TSI108_PB_ERRCS_ES);
102
103 /* Clear read error reported in PB_ISR */
104 tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ISR,
105 TSI108_PB_ISR_PBS_RD_ERR);
106
107 /* Clear PCI/X bus cfg errors if applicable */
108 if ((err_addr & 0xFF000000) == pci_cfg_base) {
109 pci_stat =
110 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR);
111 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR,
112 pci_stat);
113 }
114 }
115
116 return;
117 }
118
119 #define __tsi108_read_pci_config(x, addr, op) \
120 __asm__ __volatile__( \
121 " "op" %0,0,%1\n" \
122 "1: eieio\n" \
123 "2:\n" \
124 ".section .fixup,\"ax\"\n" \
125 "3: li %0,-1\n" \
126 " b 2b\n" \
127 ".previous\n" \
128 EX_TABLE(1b, 3b) \
129 : "=r"(x) : "r"(addr))
130
131 int
tsi108_direct_read_config(struct pci_bus * bus,unsigned int devfn,int offset,int len,u32 * val)132 tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
133 int len, u32 * val)
134 {
135 volatile unsigned char *cfg_addr;
136 struct pci_controller *hose = pci_bus_to_host(bus);
137 u32 temp;
138
139 if (ppc_md.pci_exclude_device)
140 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
141 return PCIBIOS_DEVICE_NOT_FOUND;
142
143 cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
144 devfn,
145 offset) | (offset &
146 0x03));
147
148 switch (len) {
149 case 1:
150 __tsi108_read_pci_config(temp, cfg_addr, "lbzx");
151 break;
152 case 2:
153 __tsi108_read_pci_config(temp, cfg_addr, "lhbrx");
154 break;
155 default:
156 __tsi108_read_pci_config(temp, cfg_addr, "lwbrx");
157 break;
158 }
159
160 *val = temp;
161
162 #ifdef DEBUG
163 if ((0xFFFFFFFF != temp) && (0xFFFF != temp) && (0xFF != temp)) {
164 printk("PCI CFG read : ");
165 printk("%d:0x%x:0x%x ", bus->number, devfn, offset);
166 printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
167 printk("data = 0x%x\n", *val);
168 }
169 #endif
170 return PCIBIOS_SUCCESSFUL;
171 }
172
tsi108_clear_pci_cfg_error(void)173 void tsi108_clear_pci_cfg_error(void)
174 {
175 tsi108_clear_pci_error(tsi108_pci_cfg_phys);
176 }
177
178 static struct pci_ops tsi108_direct_pci_ops = {
179 .read = tsi108_direct_read_config,
180 .write = tsi108_direct_write_config,
181 };
182
tsi108_setup_pci(struct device_node * dev,u32 cfg_phys,int primary)183 int __init tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary)
184 {
185 int len;
186 struct pci_controller *hose;
187 struct resource rsrc;
188 const int *bus_range;
189 int has_address = 0;
190
191 /* PCI Config mapping */
192 tsi108_pci_cfg_base = (u32)ioremap(cfg_phys, TSI108_PCI_CFG_SIZE);
193 tsi108_pci_cfg_phys = cfg_phys;
194 DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __func__,
195 tsi108_pci_cfg_base);
196
197 /* Fetch host bridge registers address */
198 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
199
200 /* Get bus range if any */
201 bus_range = of_get_property(dev, "bus-range", &len);
202 if (bus_range == NULL || len < 2 * sizeof(int)) {
203 printk(KERN_WARNING "Can't get bus-range for %pOF, assume"
204 " bus 0\n", dev);
205 }
206
207 hose = pcibios_alloc_controller(dev);
208
209 if (!hose) {
210 printk("PCI Host bridge init failed\n");
211 return -ENOMEM;
212 }
213
214 hose->first_busno = bus_range ? bus_range[0] : 0;
215 hose->last_busno = bus_range ? bus_range[1] : 0xff;
216
217 (hose)->ops = &tsi108_direct_pci_ops;
218
219 pr_info("Found tsi108 PCI host bridge at 0x%pa. Firmware bus number: %d->%d\n",
220 &rsrc.start, hose->first_busno, hose->last_busno);
221
222 /* Interpret the "ranges" property */
223 /* This also maps the I/O region and sets isa_io/mem_base */
224 pci_process_bridge_OF_ranges(hose, dev, primary);
225 return 0;
226 }
227
228 /*
229 * Low level utility functions
230 */
231
tsi108_pci_int_mask(u_int irq)232 static void tsi108_pci_int_mask(u_int irq)
233 {
234 u_int irp_cfg;
235 int int_line = (irq - IRQ_PCI_INTAD_BASE);
236
237 irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
238 mb();
239 irp_cfg |= (1 << int_line); /* INTx_DIR = output */
240 irp_cfg &= ~(3 << (8 + (int_line * 2))); /* INTx_TYPE = unused */
241 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
242 mb();
243 irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
244 }
245
tsi108_pci_int_unmask(u_int irq)246 static void tsi108_pci_int_unmask(u_int irq)
247 {
248 u_int irp_cfg;
249 int int_line = (irq - IRQ_PCI_INTAD_BASE);
250
251 irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
252 mb();
253 irp_cfg &= ~(1 << int_line);
254 irp_cfg |= (3 << (8 + (int_line * 2)));
255 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
256 mb();
257 }
258
init_pci_source(void)259 static void init_pci_source(void)
260 {
261 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL,
262 0x0000ff00);
263 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
264 TSI108_PCI_IRP_ENABLE_P_INT);
265 mb();
266 }
267
get_pci_source(void)268 static inline unsigned int get_pci_source(void)
269 {
270 u_int temp = 0;
271 int irq = -1;
272 int i;
273 u_int pci_irp_stat;
274 static int mask = 0;
275
276 /* Read PCI/X block interrupt status register */
277 pci_irp_stat = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
278 mb();
279
280 if (pci_irp_stat & TSI108_PCI_IRP_STAT_P_INT) {
281 /* Process Interrupt from PCI bus INTA# - INTD# lines */
282 temp =
283 tsi108_read_reg(TSI108_PCI_OFFSET +
284 TSI108_PCI_IRP_INTAD) & 0xf;
285 mb();
286 for (i = 0; i < 4; i++, mask++) {
287 if (temp & (1 << mask % 4)) {
288 irq = IRQ_PCI_INTA + mask % 4;
289 mask++;
290 break;
291 }
292 }
293
294 /* Disable interrupts from PCI block */
295 temp = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
296 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
297 temp & ~TSI108_PCI_IRP_ENABLE_P_INT);
298 mb();
299 (void)tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
300 mb();
301 }
302 #ifdef DEBUG
303 else {
304 printk("TSI108_PIC: error in TSI108_PCI_IRP_STAT\n");
305 pci_irp_stat =
306 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
307 temp =
308 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_INTAD);
309 mb();
310 printk(">> stat=0x%08x intad=0x%08x ", pci_irp_stat, temp);
311 temp =
312 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
313 mb();
314 printk("cfg_ctl=0x%08x ", temp);
315 temp =
316 tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
317 mb();
318 printk("irp_enable=0x%08x\n", temp);
319 }
320 #endif /* end of DEBUG */
321
322 return irq;
323 }
324
325
326 /*
327 * Linux descriptor level callbacks
328 */
329
tsi108_pci_irq_unmask(struct irq_data * d)330 static void tsi108_pci_irq_unmask(struct irq_data *d)
331 {
332 tsi108_pci_int_unmask(d->irq);
333
334 /* Enable interrupts from PCI block */
335 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
336 tsi108_read_reg(TSI108_PCI_OFFSET +
337 TSI108_PCI_IRP_ENABLE) |
338 TSI108_PCI_IRP_ENABLE_P_INT);
339 mb();
340 }
341
tsi108_pci_irq_mask(struct irq_data * d)342 static void tsi108_pci_irq_mask(struct irq_data *d)
343 {
344 tsi108_pci_int_mask(d->irq);
345 }
346
tsi108_pci_irq_ack(struct irq_data * d)347 static void tsi108_pci_irq_ack(struct irq_data *d)
348 {
349 tsi108_pci_int_mask(d->irq);
350 }
351
352 /*
353 * Interrupt controller descriptor for cascaded PCI interrupt controller.
354 */
355
356 static struct irq_chip tsi108_pci_irq = {
357 .name = "tsi108_PCI_int",
358 .irq_mask = tsi108_pci_irq_mask,
359 .irq_ack = tsi108_pci_irq_ack,
360 .irq_unmask = tsi108_pci_irq_unmask,
361 };
362
pci_irq_host_xlate(struct irq_domain * h,struct device_node * ct,const u32 * intspec,unsigned int intsize,irq_hw_number_t * out_hwirq,unsigned int * out_flags)363 static int pci_irq_host_xlate(struct irq_domain *h, struct device_node *ct,
364 const u32 *intspec, unsigned int intsize,
365 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
366 {
367 *out_hwirq = intspec[0];
368 *out_flags = IRQ_TYPE_LEVEL_HIGH;
369 return 0;
370 }
371
pci_irq_host_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)372 static int pci_irq_host_map(struct irq_domain *h, unsigned int virq,
373 irq_hw_number_t hw)
374 { unsigned int irq;
375 DBG("%s(%d, 0x%lx)\n", __func__, virq, hw);
376 if ((virq >= 1) && (virq <= 4)){
377 irq = virq + IRQ_PCI_INTAD_BASE - 1;
378 irq_set_status_flags(irq, IRQ_LEVEL);
379 irq_set_chip(irq, &tsi108_pci_irq);
380 }
381 return 0;
382 }
383
384 static const struct irq_domain_ops pci_irq_domain_ops = {
385 .map = pci_irq_host_map,
386 .xlate = pci_irq_host_xlate,
387 };
388
389 /*
390 * Exported functions
391 */
392
393 /*
394 * The Tsi108 PCI interrupts initialization routine.
395 *
396 * The INTA# - INTD# interrupts on the PCI bus are reported by the PCI block
397 * to the MPIC using single interrupt source (IRQ_TSI108_PCI). Therefore the
398 * PCI block has to be treated as a cascaded interrupt controller connected
399 * to the MPIC.
400 */
401
tsi108_pci_int_init(struct device_node * node)402 void __init tsi108_pci_int_init(struct device_node *node)
403 {
404 DBG("Tsi108_pci_int_init: initializing PCI interrupts\n");
405
406 pci_irq_host = irq_domain_add_legacy(node, NR_IRQS_LEGACY, 0, 0,
407 &pci_irq_domain_ops, NULL);
408 if (pci_irq_host == NULL) {
409 printk(KERN_ERR "pci_irq_host: failed to allocate irq domain!\n");
410 return;
411 }
412
413 init_pci_source();
414 }
415
tsi108_irq_cascade(struct irq_desc * desc)416 void tsi108_irq_cascade(struct irq_desc *desc)
417 {
418 struct irq_chip *chip = irq_desc_get_chip(desc);
419 unsigned int cascade_irq = get_pci_source();
420
421 if (cascade_irq)
422 generic_handle_irq(cascade_irq);
423
424 chip->irq_eoi(&desc->irq_data);
425 }
426