1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver core for Samsung SoC onboard UARTs.
4 *
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
6 * http://armlinux.simtec.co.uk/
7 */
8
9 /* Note on 2410 error handling
10 *
11 * The s3c2410 manual has a love/hate affair with the contents of the
12 * UERSTAT register in the UART blocks, and keeps marking some of the
13 * error bits as reserved. Having checked with the s3c2410x01,
14 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
15 * feature from the latter versions of the manual.
16 *
17 * If it becomes aparrent that latter versions of the 2410 remove these
18 * bits, then action will have to be taken to differentiate the versions
19 * and change the policy on BREAK
20 *
21 * BJD, 04-Nov-2004
22 */
23
24 #include <linux/dmaengine.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
28 #include <linux/ioport.h>
29 #include <linux/io.h>
30 #include <linux/platform_device.h>
31 #include <linux/init.h>
32 #include <linux/sysrq.h>
33 #include <linux/console.h>
34 #include <linux/tty.h>
35 #include <linux/tty_flip.h>
36 #include <linux/serial_core.h>
37 #include <linux/serial.h>
38 #include <linux/serial_s3c.h>
39 #include <linux/delay.h>
40 #include <linux/clk.h>
41 #include <linux/cpufreq.h>
42 #include <linux/of.h>
43 #include <asm/irq.h>
44
45 /* UART name and device definitions */
46
47 #define S3C24XX_SERIAL_NAME "ttySAC"
48 #define S3C24XX_SERIAL_MAJOR 204
49 #define S3C24XX_SERIAL_MINOR 64
50
51 #define S3C24XX_TX_PIO 1
52 #define S3C24XX_TX_DMA 2
53 #define S3C24XX_RX_PIO 1
54 #define S3C24XX_RX_DMA 2
55
56 /* flag to ignore all characters coming in */
57 #define RXSTAT_DUMMY_READ (0x10000000)
58
59 enum s3c24xx_port_type {
60 TYPE_S3C24XX,
61 TYPE_S3C6400,
62 TYPE_APPLE_S5L,
63 };
64
65 struct s3c24xx_uart_info {
66 char *name;
67 enum s3c24xx_port_type type;
68 unsigned int has_usi;
69 unsigned int port_type;
70 unsigned int fifosize;
71 unsigned long rx_fifomask;
72 unsigned long rx_fifoshift;
73 unsigned long rx_fifofull;
74 unsigned long tx_fifomask;
75 unsigned long tx_fifoshift;
76 unsigned long tx_fifofull;
77 unsigned int def_clk_sel;
78 unsigned long num_clks;
79 unsigned long clksel_mask;
80 unsigned long clksel_shift;
81 unsigned long ucon_mask;
82
83 /* uart port features */
84
85 unsigned int has_divslot:1;
86 };
87
88 struct s3c24xx_serial_drv_data {
89 struct s3c24xx_uart_info *info;
90 struct s3c2410_uartcfg *def_cfg;
91 unsigned int fifosize[CONFIG_SERIAL_SAMSUNG_UARTS];
92 };
93
94 struct s3c24xx_uart_dma {
95 unsigned int rx_chan_id;
96 unsigned int tx_chan_id;
97
98 struct dma_slave_config rx_conf;
99 struct dma_slave_config tx_conf;
100
101 struct dma_chan *rx_chan;
102 struct dma_chan *tx_chan;
103
104 dma_addr_t rx_addr;
105 dma_addr_t tx_addr;
106
107 dma_cookie_t rx_cookie;
108 dma_cookie_t tx_cookie;
109
110 char *rx_buf;
111
112 dma_addr_t tx_transfer_addr;
113
114 size_t rx_size;
115 size_t tx_size;
116
117 struct dma_async_tx_descriptor *tx_desc;
118 struct dma_async_tx_descriptor *rx_desc;
119
120 int tx_bytes_requested;
121 int rx_bytes_requested;
122 };
123
124 struct s3c24xx_uart_port {
125 unsigned char rx_claimed;
126 unsigned char tx_claimed;
127 unsigned char rx_enabled;
128 unsigned char tx_enabled;
129 unsigned int pm_level;
130 unsigned long baudclk_rate;
131 unsigned int min_dma_size;
132
133 unsigned int rx_irq;
134 unsigned int tx_irq;
135
136 unsigned int tx_in_progress;
137 unsigned int tx_mode;
138 unsigned int rx_mode;
139
140 struct s3c24xx_uart_info *info;
141 struct clk *clk;
142 struct clk *baudclk;
143 struct uart_port port;
144 struct s3c24xx_serial_drv_data *drv_data;
145
146 /* reference to platform data */
147 struct s3c2410_uartcfg *cfg;
148
149 struct s3c24xx_uart_dma *dma;
150
151 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
152 struct notifier_block freq_transition;
153 #endif
154 };
155
156 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport);
157
158 /* conversion functions */
159
160 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
161
162 /* register access controls */
163
164 #define portaddr(port, reg) ((port)->membase + (reg))
165 #define portaddrl(port, reg) \
166 ((unsigned long *)(unsigned long)((port)->membase + (reg)))
167
rd_reg(struct uart_port * port,u32 reg)168 static u32 rd_reg(struct uart_port *port, u32 reg)
169 {
170 switch (port->iotype) {
171 case UPIO_MEM:
172 return readb_relaxed(portaddr(port, reg));
173 case UPIO_MEM32:
174 return readl_relaxed(portaddr(port, reg));
175 default:
176 return 0;
177 }
178 return 0;
179 }
180
181 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
182
wr_reg(struct uart_port * port,u32 reg,u32 val)183 static void wr_reg(struct uart_port *port, u32 reg, u32 val)
184 {
185 switch (port->iotype) {
186 case UPIO_MEM:
187 writeb_relaxed(val, portaddr(port, reg));
188 break;
189 case UPIO_MEM32:
190 writel_relaxed(val, portaddr(port, reg));
191 break;
192 }
193 }
194
195 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
196
197 /* Byte-order aware bit setting/clearing functions. */
198
s3c24xx_set_bit(struct uart_port * port,int idx,unsigned int reg)199 static inline void s3c24xx_set_bit(struct uart_port *port, int idx,
200 unsigned int reg)
201 {
202 unsigned long flags;
203 u32 val;
204
205 local_irq_save(flags);
206 val = rd_regl(port, reg);
207 val |= (1 << idx);
208 wr_regl(port, reg, val);
209 local_irq_restore(flags);
210 }
211
s3c24xx_clear_bit(struct uart_port * port,int idx,unsigned int reg)212 static inline void s3c24xx_clear_bit(struct uart_port *port, int idx,
213 unsigned int reg)
214 {
215 unsigned long flags;
216 u32 val;
217
218 local_irq_save(flags);
219 val = rd_regl(port, reg);
220 val &= ~(1 << idx);
221 wr_regl(port, reg, val);
222 local_irq_restore(flags);
223 }
224
to_ourport(struct uart_port * port)225 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
226 {
227 return container_of(port, struct s3c24xx_uart_port, port);
228 }
229
230 /* translate a port to the device name */
231
s3c24xx_serial_portname(struct uart_port * port)232 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
233 {
234 return to_platform_device(port->dev)->name;
235 }
236
s3c24xx_serial_txempty_nofifo(struct uart_port * port)237 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
238 {
239 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
240 }
241
s3c24xx_serial_rx_enable(struct uart_port * port)242 static void s3c24xx_serial_rx_enable(struct uart_port *port)
243 {
244 struct s3c24xx_uart_port *ourport = to_ourport(port);
245 unsigned long flags;
246 unsigned int ucon, ufcon;
247 int count = 10000;
248
249 spin_lock_irqsave(&port->lock, flags);
250
251 while (--count && !s3c24xx_serial_txempty_nofifo(port))
252 udelay(100);
253
254 ufcon = rd_regl(port, S3C2410_UFCON);
255 ufcon |= S3C2410_UFCON_RESETRX;
256 wr_regl(port, S3C2410_UFCON, ufcon);
257
258 ucon = rd_regl(port, S3C2410_UCON);
259 ucon |= S3C2410_UCON_RXIRQMODE;
260 wr_regl(port, S3C2410_UCON, ucon);
261
262 ourport->rx_enabled = 1;
263 spin_unlock_irqrestore(&port->lock, flags);
264 }
265
s3c24xx_serial_rx_disable(struct uart_port * port)266 static void s3c24xx_serial_rx_disable(struct uart_port *port)
267 {
268 struct s3c24xx_uart_port *ourport = to_ourport(port);
269 unsigned long flags;
270 unsigned int ucon;
271
272 spin_lock_irqsave(&port->lock, flags);
273
274 ucon = rd_regl(port, S3C2410_UCON);
275 ucon &= ~S3C2410_UCON_RXIRQMODE;
276 wr_regl(port, S3C2410_UCON, ucon);
277
278 ourport->rx_enabled = 0;
279 spin_unlock_irqrestore(&port->lock, flags);
280 }
281
s3c24xx_serial_stop_tx(struct uart_port * port)282 static void s3c24xx_serial_stop_tx(struct uart_port *port)
283 {
284 struct s3c24xx_uart_port *ourport = to_ourport(port);
285 struct s3c24xx_uart_dma *dma = ourport->dma;
286 struct circ_buf *xmit = &port->state->xmit;
287 struct dma_tx_state state;
288 int count;
289
290 if (!ourport->tx_enabled)
291 return;
292
293 switch (ourport->info->type) {
294 case TYPE_S3C6400:
295 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
296 break;
297 case TYPE_APPLE_S5L:
298 s3c24xx_clear_bit(port, APPLE_S5L_UCON_TXTHRESH_ENA, S3C2410_UCON);
299 break;
300 default:
301 disable_irq_nosync(ourport->tx_irq);
302 break;
303 }
304
305 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
306 dmaengine_pause(dma->tx_chan);
307 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
308 dmaengine_terminate_all(dma->tx_chan);
309 dma_sync_single_for_cpu(dma->tx_chan->device->dev,
310 dma->tx_transfer_addr, dma->tx_size,
311 DMA_TO_DEVICE);
312 async_tx_ack(dma->tx_desc);
313 count = dma->tx_bytes_requested - state.residue;
314 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
315 port->icount.tx += count;
316 }
317
318 ourport->tx_enabled = 0;
319 ourport->tx_in_progress = 0;
320
321 if (port->flags & UPF_CONS_FLOW)
322 s3c24xx_serial_rx_enable(port);
323
324 ourport->tx_mode = 0;
325 }
326
327 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
328
s3c24xx_serial_tx_dma_complete(void * args)329 static void s3c24xx_serial_tx_dma_complete(void *args)
330 {
331 struct s3c24xx_uart_port *ourport = args;
332 struct uart_port *port = &ourport->port;
333 struct circ_buf *xmit = &port->state->xmit;
334 struct s3c24xx_uart_dma *dma = ourport->dma;
335 struct dma_tx_state state;
336 unsigned long flags;
337 int count;
338
339 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
340 count = dma->tx_bytes_requested - state.residue;
341 async_tx_ack(dma->tx_desc);
342
343 dma_sync_single_for_cpu(dma->tx_chan->device->dev,
344 dma->tx_transfer_addr, dma->tx_size,
345 DMA_TO_DEVICE);
346
347 spin_lock_irqsave(&port->lock, flags);
348
349 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
350 port->icount.tx += count;
351 ourport->tx_in_progress = 0;
352
353 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
354 uart_write_wakeup(port);
355
356 s3c24xx_serial_start_next_tx(ourport);
357 spin_unlock_irqrestore(&port->lock, flags);
358 }
359
enable_tx_dma(struct s3c24xx_uart_port * ourport)360 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
361 {
362 struct uart_port *port = &ourport->port;
363 u32 ucon;
364
365 /* Mask Tx interrupt */
366 switch (ourport->info->type) {
367 case TYPE_S3C6400:
368 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
369 break;
370 case TYPE_APPLE_S5L:
371 WARN_ON(1); // No DMA
372 break;
373 default:
374 disable_irq_nosync(ourport->tx_irq);
375 break;
376 }
377
378 /* Enable tx dma mode */
379 ucon = rd_regl(port, S3C2410_UCON);
380 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
381 ucon |= S3C64XX_UCON_TXBURST_1;
382 ucon |= S3C64XX_UCON_TXMODE_DMA;
383 wr_regl(port, S3C2410_UCON, ucon);
384
385 ourport->tx_mode = S3C24XX_TX_DMA;
386 }
387
enable_tx_pio(struct s3c24xx_uart_port * ourport)388 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
389 {
390 struct uart_port *port = &ourport->port;
391 u32 ucon, ufcon;
392
393 /* Set ufcon txtrig */
394 ourport->tx_in_progress = S3C24XX_TX_PIO;
395 ufcon = rd_regl(port, S3C2410_UFCON);
396 wr_regl(port, S3C2410_UFCON, ufcon);
397
398 /* Enable tx pio mode */
399 ucon = rd_regl(port, S3C2410_UCON);
400 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
401 ucon |= S3C64XX_UCON_TXMODE_CPU;
402 wr_regl(port, S3C2410_UCON, ucon);
403
404 /* Unmask Tx interrupt */
405 switch (ourport->info->type) {
406 case TYPE_S3C6400:
407 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
408 S3C64XX_UINTM);
409 break;
410 case TYPE_APPLE_S5L:
411 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
412 wr_regl(port, S3C2410_UCON, ucon);
413 break;
414 default:
415 enable_irq(ourport->tx_irq);
416 break;
417 }
418
419 ourport->tx_mode = S3C24XX_TX_PIO;
420
421 /*
422 * The Apple version only has edge triggered TX IRQs, so we need
423 * to kick off the process by sending some characters here.
424 */
425 if (ourport->info->type == TYPE_APPLE_S5L)
426 s3c24xx_serial_tx_chars(ourport);
427 }
428
s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port * ourport)429 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
430 {
431 if (ourport->tx_mode != S3C24XX_TX_PIO)
432 enable_tx_pio(ourport);
433 }
434
s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port * ourport,unsigned int count)435 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
436 unsigned int count)
437 {
438 struct uart_port *port = &ourport->port;
439 struct circ_buf *xmit = &port->state->xmit;
440 struct s3c24xx_uart_dma *dma = ourport->dma;
441
442 if (ourport->tx_mode != S3C24XX_TX_DMA)
443 enable_tx_dma(ourport);
444
445 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
446 dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
447
448 dma_sync_single_for_device(dma->tx_chan->device->dev,
449 dma->tx_transfer_addr, dma->tx_size,
450 DMA_TO_DEVICE);
451
452 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
453 dma->tx_transfer_addr, dma->tx_size,
454 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
455 if (!dma->tx_desc) {
456 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
457 return -EIO;
458 }
459
460 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
461 dma->tx_desc->callback_param = ourport;
462 dma->tx_bytes_requested = dma->tx_size;
463
464 ourport->tx_in_progress = S3C24XX_TX_DMA;
465 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
466 dma_async_issue_pending(dma->tx_chan);
467 return 0;
468 }
469
s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port * ourport)470 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
471 {
472 struct uart_port *port = &ourport->port;
473 struct circ_buf *xmit = &port->state->xmit;
474 unsigned long count;
475
476 /* Get data size up to the end of buffer */
477 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
478
479 if (!count) {
480 s3c24xx_serial_stop_tx(port);
481 return;
482 }
483
484 if (!ourport->dma || !ourport->dma->tx_chan ||
485 count < ourport->min_dma_size ||
486 xmit->tail & (dma_get_cache_alignment() - 1))
487 s3c24xx_serial_start_tx_pio(ourport);
488 else
489 s3c24xx_serial_start_tx_dma(ourport, count);
490 }
491
s3c24xx_serial_start_tx(struct uart_port * port)492 static void s3c24xx_serial_start_tx(struct uart_port *port)
493 {
494 struct s3c24xx_uart_port *ourport = to_ourport(port);
495 struct circ_buf *xmit = &port->state->xmit;
496
497 if (!ourport->tx_enabled) {
498 if (port->flags & UPF_CONS_FLOW)
499 s3c24xx_serial_rx_disable(port);
500
501 ourport->tx_enabled = 1;
502 if (!ourport->dma || !ourport->dma->tx_chan)
503 s3c24xx_serial_start_tx_pio(ourport);
504 }
505
506 if (ourport->dma && ourport->dma->tx_chan) {
507 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
508 s3c24xx_serial_start_next_tx(ourport);
509 }
510 }
511
s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port * ourport,struct tty_port * tty,int count)512 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
513 struct tty_port *tty, int count)
514 {
515 struct s3c24xx_uart_dma *dma = ourport->dma;
516 int copied;
517
518 if (!count)
519 return;
520
521 dma_sync_single_for_cpu(dma->rx_chan->device->dev, dma->rx_addr,
522 dma->rx_size, DMA_FROM_DEVICE);
523
524 ourport->port.icount.rx += count;
525 if (!tty) {
526 dev_err(ourport->port.dev, "No tty port\n");
527 return;
528 }
529 copied = tty_insert_flip_string(tty,
530 ((unsigned char *)(ourport->dma->rx_buf)), count);
531 if (copied != count) {
532 WARN_ON(1);
533 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
534 }
535 }
536
s3c24xx_serial_stop_rx(struct uart_port * port)537 static void s3c24xx_serial_stop_rx(struct uart_port *port)
538 {
539 struct s3c24xx_uart_port *ourport = to_ourport(port);
540 struct s3c24xx_uart_dma *dma = ourport->dma;
541 struct tty_port *t = &port->state->port;
542 struct dma_tx_state state;
543 enum dma_status dma_status;
544 unsigned int received;
545
546 if (ourport->rx_enabled) {
547 dev_dbg(port->dev, "stopping rx\n");
548 switch (ourport->info->type) {
549 case TYPE_S3C6400:
550 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
551 S3C64XX_UINTM);
552 break;
553 case TYPE_APPLE_S5L:
554 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
555 s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
556 break;
557 default:
558 disable_irq_nosync(ourport->rx_irq);
559 break;
560 }
561 ourport->rx_enabled = 0;
562 }
563 if (dma && dma->rx_chan) {
564 dmaengine_pause(dma->tx_chan);
565 dma_status = dmaengine_tx_status(dma->rx_chan,
566 dma->rx_cookie, &state);
567 if (dma_status == DMA_IN_PROGRESS ||
568 dma_status == DMA_PAUSED) {
569 received = dma->rx_bytes_requested - state.residue;
570 dmaengine_terminate_all(dma->rx_chan);
571 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
572 }
573 }
574 }
575
576 static inline struct s3c24xx_uart_info
s3c24xx_port_to_info(struct uart_port * port)577 *s3c24xx_port_to_info(struct uart_port *port)
578 {
579 return to_ourport(port)->info;
580 }
581
582 static inline struct s3c2410_uartcfg
s3c24xx_port_to_cfg(struct uart_port * port)583 *s3c24xx_port_to_cfg(struct uart_port *port)
584 {
585 struct s3c24xx_uart_port *ourport;
586
587 if (port->dev == NULL)
588 return NULL;
589
590 ourport = container_of(port, struct s3c24xx_uart_port, port);
591 return ourport->cfg;
592 }
593
s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port * ourport,unsigned long ufstat)594 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
595 unsigned long ufstat)
596 {
597 struct s3c24xx_uart_info *info = ourport->info;
598
599 if (ufstat & info->rx_fifofull)
600 return ourport->port.fifosize;
601
602 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
603 }
604
605 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
s3c24xx_serial_rx_dma_complete(void * args)606 static void s3c24xx_serial_rx_dma_complete(void *args)
607 {
608 struct s3c24xx_uart_port *ourport = args;
609 struct uart_port *port = &ourport->port;
610
611 struct s3c24xx_uart_dma *dma = ourport->dma;
612 struct tty_port *t = &port->state->port;
613 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
614
615 struct dma_tx_state state;
616 unsigned long flags;
617 int received;
618
619 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
620 received = dma->rx_bytes_requested - state.residue;
621 async_tx_ack(dma->rx_desc);
622
623 spin_lock_irqsave(&port->lock, flags);
624
625 if (received)
626 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
627
628 if (tty) {
629 tty_flip_buffer_push(t);
630 tty_kref_put(tty);
631 }
632
633 s3c64xx_start_rx_dma(ourport);
634
635 spin_unlock_irqrestore(&port->lock, flags);
636 }
637
s3c64xx_start_rx_dma(struct s3c24xx_uart_port * ourport)638 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
639 {
640 struct s3c24xx_uart_dma *dma = ourport->dma;
641
642 dma_sync_single_for_device(dma->rx_chan->device->dev, dma->rx_addr,
643 dma->rx_size, DMA_FROM_DEVICE);
644
645 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
646 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
647 DMA_PREP_INTERRUPT);
648 if (!dma->rx_desc) {
649 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
650 return;
651 }
652
653 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
654 dma->rx_desc->callback_param = ourport;
655 dma->rx_bytes_requested = dma->rx_size;
656
657 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
658 dma_async_issue_pending(dma->rx_chan);
659 }
660
661 /* ? - where has parity gone?? */
662 #define S3C2410_UERSTAT_PARITY (0x1000)
663
enable_rx_dma(struct s3c24xx_uart_port * ourport)664 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
665 {
666 struct uart_port *port = &ourport->port;
667 unsigned int ucon;
668
669 /* set Rx mode to DMA mode */
670 ucon = rd_regl(port, S3C2410_UCON);
671 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
672 S3C64XX_UCON_TIMEOUT_MASK |
673 S3C64XX_UCON_EMPTYINT_EN |
674 S3C64XX_UCON_DMASUS_EN |
675 S3C64XX_UCON_TIMEOUT_EN |
676 S3C64XX_UCON_RXMODE_MASK);
677 ucon |= S3C64XX_UCON_RXBURST_1 |
678 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
679 S3C64XX_UCON_EMPTYINT_EN |
680 S3C64XX_UCON_TIMEOUT_EN |
681 S3C64XX_UCON_RXMODE_DMA;
682 wr_regl(port, S3C2410_UCON, ucon);
683
684 ourport->rx_mode = S3C24XX_RX_DMA;
685 }
686
enable_rx_pio(struct s3c24xx_uart_port * ourport)687 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
688 {
689 struct uart_port *port = &ourport->port;
690 unsigned int ucon;
691
692 /* set Rx mode to DMA mode */
693 ucon = rd_regl(port, S3C2410_UCON);
694 ucon &= ~S3C64XX_UCON_RXMODE_MASK;
695 ucon |= S3C64XX_UCON_RXMODE_CPU;
696
697 /* Apple types use these bits for IRQ masks */
698 if (ourport->info->type != TYPE_APPLE_S5L) {
699 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
700 S3C64XX_UCON_EMPTYINT_EN |
701 S3C64XX_UCON_DMASUS_EN |
702 S3C64XX_UCON_TIMEOUT_EN);
703 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
704 S3C64XX_UCON_TIMEOUT_EN;
705 }
706 wr_regl(port, S3C2410_UCON, ucon);
707
708 ourport->rx_mode = S3C24XX_RX_PIO;
709 }
710
711 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
712
s3c24xx_serial_rx_chars_dma(void * dev_id)713 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
714 {
715 unsigned int utrstat, received;
716 struct s3c24xx_uart_port *ourport = dev_id;
717 struct uart_port *port = &ourport->port;
718 struct s3c24xx_uart_dma *dma = ourport->dma;
719 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
720 struct tty_port *t = &port->state->port;
721 struct dma_tx_state state;
722
723 utrstat = rd_regl(port, S3C2410_UTRSTAT);
724 rd_regl(port, S3C2410_UFSTAT);
725
726 spin_lock(&port->lock);
727
728 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
729 s3c64xx_start_rx_dma(ourport);
730 if (ourport->rx_mode == S3C24XX_RX_PIO)
731 enable_rx_dma(ourport);
732 goto finish;
733 }
734
735 if (ourport->rx_mode == S3C24XX_RX_DMA) {
736 dmaengine_pause(dma->rx_chan);
737 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
738 dmaengine_terminate_all(dma->rx_chan);
739 received = dma->rx_bytes_requested - state.residue;
740 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
741
742 enable_rx_pio(ourport);
743 }
744
745 s3c24xx_serial_rx_drain_fifo(ourport);
746
747 if (tty) {
748 tty_flip_buffer_push(t);
749 tty_kref_put(tty);
750 }
751
752 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
753
754 finish:
755 spin_unlock(&port->lock);
756
757 return IRQ_HANDLED;
758 }
759
s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port * ourport)760 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
761 {
762 struct uart_port *port = &ourport->port;
763 unsigned int ufcon, ch, flag, ufstat, uerstat;
764 unsigned int fifocnt = 0;
765 int max_count = port->fifosize;
766
767 while (max_count-- > 0) {
768 /*
769 * Receive all characters known to be in FIFO
770 * before reading FIFO level again
771 */
772 if (fifocnt == 0) {
773 ufstat = rd_regl(port, S3C2410_UFSTAT);
774 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
775 if (fifocnt == 0)
776 break;
777 }
778 fifocnt--;
779
780 uerstat = rd_regl(port, S3C2410_UERSTAT);
781 ch = rd_reg(port, S3C2410_URXH);
782
783 if (port->flags & UPF_CONS_FLOW) {
784 int txe = s3c24xx_serial_txempty_nofifo(port);
785
786 if (ourport->rx_enabled) {
787 if (!txe) {
788 ourport->rx_enabled = 0;
789 continue;
790 }
791 } else {
792 if (txe) {
793 ufcon = rd_regl(port, S3C2410_UFCON);
794 ufcon |= S3C2410_UFCON_RESETRX;
795 wr_regl(port, S3C2410_UFCON, ufcon);
796 ourport->rx_enabled = 1;
797 return;
798 }
799 continue;
800 }
801 }
802
803 /* insert the character into the buffer */
804
805 flag = TTY_NORMAL;
806 port->icount.rx++;
807
808 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
809 dev_dbg(port->dev,
810 "rxerr: port ch=0x%02x, rxs=0x%08x\n",
811 ch, uerstat);
812
813 /* check for break */
814 if (uerstat & S3C2410_UERSTAT_BREAK) {
815 dev_dbg(port->dev, "break!\n");
816 port->icount.brk++;
817 if (uart_handle_break(port))
818 continue; /* Ignore character */
819 }
820
821 if (uerstat & S3C2410_UERSTAT_FRAME)
822 port->icount.frame++;
823 if (uerstat & S3C2410_UERSTAT_OVERRUN)
824 port->icount.overrun++;
825
826 uerstat &= port->read_status_mask;
827
828 if (uerstat & S3C2410_UERSTAT_BREAK)
829 flag = TTY_BREAK;
830 else if (uerstat & S3C2410_UERSTAT_PARITY)
831 flag = TTY_PARITY;
832 else if (uerstat & (S3C2410_UERSTAT_FRAME |
833 S3C2410_UERSTAT_OVERRUN))
834 flag = TTY_FRAME;
835 }
836
837 if (uart_handle_sysrq_char(port, ch))
838 continue; /* Ignore character */
839
840 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
841 ch, flag);
842 }
843
844 tty_flip_buffer_push(&port->state->port);
845 }
846
s3c24xx_serial_rx_chars_pio(void * dev_id)847 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
848 {
849 struct s3c24xx_uart_port *ourport = dev_id;
850 struct uart_port *port = &ourport->port;
851
852 spin_lock(&port->lock);
853 s3c24xx_serial_rx_drain_fifo(ourport);
854 spin_unlock(&port->lock);
855
856 return IRQ_HANDLED;
857 }
858
s3c24xx_serial_rx_irq(int irq,void * dev_id)859 static irqreturn_t s3c24xx_serial_rx_irq(int irq, void *dev_id)
860 {
861 struct s3c24xx_uart_port *ourport = dev_id;
862
863 if (ourport->dma && ourport->dma->rx_chan)
864 return s3c24xx_serial_rx_chars_dma(dev_id);
865 return s3c24xx_serial_rx_chars_pio(dev_id);
866 }
867
s3c24xx_serial_tx_chars(struct s3c24xx_uart_port * ourport)868 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport)
869 {
870 struct uart_port *port = &ourport->port;
871 struct circ_buf *xmit = &port->state->xmit;
872 int count, dma_count = 0;
873
874 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
875
876 if (ourport->dma && ourport->dma->tx_chan &&
877 count >= ourport->min_dma_size) {
878 int align = dma_get_cache_alignment() -
879 (xmit->tail & (dma_get_cache_alignment() - 1));
880 if (count - align >= ourport->min_dma_size) {
881 dma_count = count - align;
882 count = align;
883 }
884 }
885
886 if (port->x_char) {
887 wr_reg(port, S3C2410_UTXH, port->x_char);
888 port->icount.tx++;
889 port->x_char = 0;
890 return;
891 }
892
893 /* if there isn't anything more to transmit, or the uart is now
894 * stopped, disable the uart and exit
895 */
896
897 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
898 s3c24xx_serial_stop_tx(port);
899 return;
900 }
901
902 /* try and drain the buffer... */
903
904 if (count > port->fifosize) {
905 count = port->fifosize;
906 dma_count = 0;
907 }
908
909 while (!uart_circ_empty(xmit) && count > 0) {
910 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
911 break;
912
913 wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
914 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
915 port->icount.tx++;
916 count--;
917 }
918
919 if (!count && dma_count) {
920 s3c24xx_serial_start_tx_dma(ourport, dma_count);
921 return;
922 }
923
924 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
925 uart_write_wakeup(port);
926
927 if (uart_circ_empty(xmit))
928 s3c24xx_serial_stop_tx(port);
929 }
930
s3c24xx_serial_tx_irq(int irq,void * id)931 static irqreturn_t s3c24xx_serial_tx_irq(int irq, void *id)
932 {
933 struct s3c24xx_uart_port *ourport = id;
934 struct uart_port *port = &ourport->port;
935
936 spin_lock(&port->lock);
937
938 s3c24xx_serial_tx_chars(ourport);
939
940 spin_unlock(&port->lock);
941 return IRQ_HANDLED;
942 }
943
944 /* interrupt handler for s3c64xx and later SoC's.*/
s3c64xx_serial_handle_irq(int irq,void * id)945 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
946 {
947 struct s3c24xx_uart_port *ourport = id;
948 struct uart_port *port = &ourport->port;
949 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
950 irqreturn_t ret = IRQ_HANDLED;
951
952 if (pend & S3C64XX_UINTM_RXD_MSK) {
953 ret = s3c24xx_serial_rx_irq(irq, id);
954 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
955 }
956 if (pend & S3C64XX_UINTM_TXD_MSK) {
957 ret = s3c24xx_serial_tx_irq(irq, id);
958 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
959 }
960 return ret;
961 }
962
963 /* interrupt handler for Apple SoC's.*/
apple_serial_handle_irq(int irq,void * id)964 static irqreturn_t apple_serial_handle_irq(int irq, void *id)
965 {
966 struct s3c24xx_uart_port *ourport = id;
967 struct uart_port *port = &ourport->port;
968 unsigned int pend = rd_regl(port, S3C2410_UTRSTAT);
969 irqreturn_t ret = IRQ_NONE;
970
971 if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO)) {
972 wr_regl(port, S3C2410_UTRSTAT,
973 APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO);
974 ret = s3c24xx_serial_rx_irq(irq, id);
975 }
976 if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) {
977 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_TXTHRESH);
978 ret = s3c24xx_serial_tx_irq(irq, id);
979 }
980
981 return ret;
982 }
983
s3c24xx_serial_tx_empty(struct uart_port * port)984 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
985 {
986 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
987 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
988 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
989
990 if (ufcon & S3C2410_UFCON_FIFOMODE) {
991 if ((ufstat & info->tx_fifomask) != 0 ||
992 (ufstat & info->tx_fifofull))
993 return 0;
994
995 return 1;
996 }
997
998 return s3c24xx_serial_txempty_nofifo(port);
999 }
1000
1001 /* no modem control lines */
s3c24xx_serial_get_mctrl(struct uart_port * port)1002 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
1003 {
1004 unsigned int umstat = rd_reg(port, S3C2410_UMSTAT);
1005
1006 if (umstat & S3C2410_UMSTAT_CTS)
1007 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1008 else
1009 return TIOCM_CAR | TIOCM_DSR;
1010 }
1011
s3c24xx_serial_set_mctrl(struct uart_port * port,unsigned int mctrl)1012 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
1013 {
1014 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
1015
1016 if (mctrl & TIOCM_RTS)
1017 umcon |= S3C2410_UMCOM_RTS_LOW;
1018 else
1019 umcon &= ~S3C2410_UMCOM_RTS_LOW;
1020
1021 wr_regl(port, S3C2410_UMCON, umcon);
1022 }
1023
s3c24xx_serial_break_ctl(struct uart_port * port,int break_state)1024 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
1025 {
1026 unsigned long flags;
1027 unsigned int ucon;
1028
1029 spin_lock_irqsave(&port->lock, flags);
1030
1031 ucon = rd_regl(port, S3C2410_UCON);
1032
1033 if (break_state)
1034 ucon |= S3C2410_UCON_SBREAK;
1035 else
1036 ucon &= ~S3C2410_UCON_SBREAK;
1037
1038 wr_regl(port, S3C2410_UCON, ucon);
1039
1040 spin_unlock_irqrestore(&port->lock, flags);
1041 }
1042
s3c24xx_serial_request_dma(struct s3c24xx_uart_port * p)1043 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
1044 {
1045 struct s3c24xx_uart_dma *dma = p->dma;
1046 struct dma_slave_caps dma_caps;
1047 const char *reason = NULL;
1048 int ret;
1049
1050 /* Default slave configuration parameters */
1051 dma->rx_conf.direction = DMA_DEV_TO_MEM;
1052 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1053 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
1054 dma->rx_conf.src_maxburst = 1;
1055
1056 dma->tx_conf.direction = DMA_MEM_TO_DEV;
1057 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1058 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
1059 dma->tx_conf.dst_maxburst = 1;
1060
1061 dma->rx_chan = dma_request_chan(p->port.dev, "rx");
1062
1063 if (IS_ERR(dma->rx_chan)) {
1064 reason = "DMA RX channel request failed";
1065 ret = PTR_ERR(dma->rx_chan);
1066 goto err_warn;
1067 }
1068
1069 ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
1070 if (ret < 0 ||
1071 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1072 reason = "insufficient DMA RX engine capabilities";
1073 ret = -EOPNOTSUPP;
1074 goto err_release_rx;
1075 }
1076
1077 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
1078
1079 dma->tx_chan = dma_request_chan(p->port.dev, "tx");
1080 if (IS_ERR(dma->tx_chan)) {
1081 reason = "DMA TX channel request failed";
1082 ret = PTR_ERR(dma->tx_chan);
1083 goto err_release_rx;
1084 }
1085
1086 ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
1087 if (ret < 0 ||
1088 dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1089 reason = "insufficient DMA TX engine capabilities";
1090 ret = -EOPNOTSUPP;
1091 goto err_release_tx;
1092 }
1093
1094 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
1095
1096 /* RX buffer */
1097 dma->rx_size = PAGE_SIZE;
1098
1099 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
1100 if (!dma->rx_buf) {
1101 ret = -ENOMEM;
1102 goto err_release_tx;
1103 }
1104
1105 dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
1106 dma->rx_size, DMA_FROM_DEVICE);
1107 if (dma_mapping_error(dma->rx_chan->device->dev, dma->rx_addr)) {
1108 reason = "DMA mapping error for RX buffer";
1109 ret = -EIO;
1110 goto err_free_rx;
1111 }
1112
1113 /* TX buffer */
1114 dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
1115 p->port.state->xmit.buf, UART_XMIT_SIZE,
1116 DMA_TO_DEVICE);
1117 if (dma_mapping_error(dma->tx_chan->device->dev, dma->tx_addr)) {
1118 reason = "DMA mapping error for TX buffer";
1119 ret = -EIO;
1120 goto err_unmap_rx;
1121 }
1122
1123 return 0;
1124
1125 err_unmap_rx:
1126 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1127 dma->rx_size, DMA_FROM_DEVICE);
1128 err_free_rx:
1129 kfree(dma->rx_buf);
1130 err_release_tx:
1131 dma_release_channel(dma->tx_chan);
1132 err_release_rx:
1133 dma_release_channel(dma->rx_chan);
1134 err_warn:
1135 if (reason)
1136 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
1137 return ret;
1138 }
1139
s3c24xx_serial_release_dma(struct s3c24xx_uart_port * p)1140 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
1141 {
1142 struct s3c24xx_uart_dma *dma = p->dma;
1143
1144 if (dma->rx_chan) {
1145 dmaengine_terminate_all(dma->rx_chan);
1146 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1147 dma->rx_size, DMA_FROM_DEVICE);
1148 kfree(dma->rx_buf);
1149 dma_release_channel(dma->rx_chan);
1150 dma->rx_chan = NULL;
1151 }
1152
1153 if (dma->tx_chan) {
1154 dmaengine_terminate_all(dma->tx_chan);
1155 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
1156 UART_XMIT_SIZE, DMA_TO_DEVICE);
1157 dma_release_channel(dma->tx_chan);
1158 dma->tx_chan = NULL;
1159 }
1160 }
1161
s3c24xx_serial_shutdown(struct uart_port * port)1162 static void s3c24xx_serial_shutdown(struct uart_port *port)
1163 {
1164 struct s3c24xx_uart_port *ourport = to_ourport(port);
1165
1166 if (ourport->tx_claimed) {
1167 free_irq(ourport->tx_irq, ourport);
1168 ourport->tx_enabled = 0;
1169 ourport->tx_claimed = 0;
1170 ourport->tx_mode = 0;
1171 }
1172
1173 if (ourport->rx_claimed) {
1174 free_irq(ourport->rx_irq, ourport);
1175 ourport->rx_claimed = 0;
1176 ourport->rx_enabled = 0;
1177 }
1178
1179 if (ourport->dma)
1180 s3c24xx_serial_release_dma(ourport);
1181
1182 ourport->tx_in_progress = 0;
1183 }
1184
s3c64xx_serial_shutdown(struct uart_port * port)1185 static void s3c64xx_serial_shutdown(struct uart_port *port)
1186 {
1187 struct s3c24xx_uart_port *ourport = to_ourport(port);
1188
1189 ourport->tx_enabled = 0;
1190 ourport->tx_mode = 0;
1191 ourport->rx_enabled = 0;
1192
1193 free_irq(port->irq, ourport);
1194
1195 wr_regl(port, S3C64XX_UINTP, 0xf);
1196 wr_regl(port, S3C64XX_UINTM, 0xf);
1197
1198 if (ourport->dma)
1199 s3c24xx_serial_release_dma(ourport);
1200
1201 ourport->tx_in_progress = 0;
1202 }
1203
apple_s5l_serial_shutdown(struct uart_port * port)1204 static void apple_s5l_serial_shutdown(struct uart_port *port)
1205 {
1206 struct s3c24xx_uart_port *ourport = to_ourport(port);
1207
1208 unsigned int ucon;
1209
1210 ucon = rd_regl(port, S3C2410_UCON);
1211 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
1212 APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
1213 APPLE_S5L_UCON_RXTO_ENA_MSK);
1214 wr_regl(port, S3C2410_UCON, ucon);
1215
1216 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1217
1218 free_irq(port->irq, ourport);
1219
1220 ourport->tx_enabled = 0;
1221 ourport->tx_mode = 0;
1222 ourport->rx_enabled = 0;
1223
1224 if (ourport->dma)
1225 s3c24xx_serial_release_dma(ourport);
1226
1227 ourport->tx_in_progress = 0;
1228 }
1229
s3c24xx_serial_startup(struct uart_port * port)1230 static int s3c24xx_serial_startup(struct uart_port *port)
1231 {
1232 struct s3c24xx_uart_port *ourport = to_ourport(port);
1233 int ret;
1234
1235 ourport->rx_enabled = 1;
1236
1237 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_irq, 0,
1238 s3c24xx_serial_portname(port), ourport);
1239
1240 if (ret != 0) {
1241 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1242 return ret;
1243 }
1244
1245 ourport->rx_claimed = 1;
1246
1247 dev_dbg(port->dev, "requesting tx irq...\n");
1248
1249 ourport->tx_enabled = 1;
1250
1251 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_irq, 0,
1252 s3c24xx_serial_portname(port), ourport);
1253
1254 if (ret) {
1255 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1256 goto err;
1257 }
1258
1259 ourport->tx_claimed = 1;
1260
1261 /* the port reset code should have done the correct
1262 * register setup for the port controls
1263 */
1264
1265 return ret;
1266
1267 err:
1268 s3c24xx_serial_shutdown(port);
1269 return ret;
1270 }
1271
s3c64xx_serial_startup(struct uart_port * port)1272 static int s3c64xx_serial_startup(struct uart_port *port)
1273 {
1274 struct s3c24xx_uart_port *ourport = to_ourport(port);
1275 unsigned long flags;
1276 unsigned int ufcon;
1277 int ret;
1278
1279 wr_regl(port, S3C64XX_UINTM, 0xf);
1280 if (ourport->dma) {
1281 ret = s3c24xx_serial_request_dma(ourport);
1282 if (ret < 0) {
1283 devm_kfree(port->dev, ourport->dma);
1284 ourport->dma = NULL;
1285 }
1286 }
1287
1288 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1289 s3c24xx_serial_portname(port), ourport);
1290 if (ret) {
1291 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1292 return ret;
1293 }
1294
1295 /* For compatibility with s3c24xx Soc's */
1296 ourport->rx_enabled = 1;
1297 ourport->tx_enabled = 0;
1298
1299 spin_lock_irqsave(&port->lock, flags);
1300
1301 ufcon = rd_regl(port, S3C2410_UFCON);
1302 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1303 if (!uart_console(port))
1304 ufcon |= S3C2410_UFCON_RESETTX;
1305 wr_regl(port, S3C2410_UFCON, ufcon);
1306
1307 enable_rx_pio(ourport);
1308
1309 spin_unlock_irqrestore(&port->lock, flags);
1310
1311 /* Enable Rx Interrupt */
1312 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1313
1314 return ret;
1315 }
1316
apple_s5l_serial_startup(struct uart_port * port)1317 static int apple_s5l_serial_startup(struct uart_port *port)
1318 {
1319 struct s3c24xx_uart_port *ourport = to_ourport(port);
1320 unsigned long flags;
1321 unsigned int ufcon;
1322 int ret;
1323
1324 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1325
1326 ret = request_irq(port->irq, apple_serial_handle_irq, 0,
1327 s3c24xx_serial_portname(port), ourport);
1328 if (ret) {
1329 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1330 return ret;
1331 }
1332
1333 /* For compatibility with s3c24xx Soc's */
1334 ourport->rx_enabled = 1;
1335 ourport->tx_enabled = 0;
1336
1337 spin_lock_irqsave(&port->lock, flags);
1338
1339 ufcon = rd_regl(port, S3C2410_UFCON);
1340 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1341 if (!uart_console(port))
1342 ufcon |= S3C2410_UFCON_RESETTX;
1343 wr_regl(port, S3C2410_UFCON, ufcon);
1344
1345 enable_rx_pio(ourport);
1346
1347 spin_unlock_irqrestore(&port->lock, flags);
1348
1349 /* Enable Rx Interrupt */
1350 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
1351 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
1352
1353 return ret;
1354 }
1355
exynos_usi_init(struct uart_port * port)1356 static void exynos_usi_init(struct uart_port *port)
1357 {
1358 struct s3c24xx_uart_port *ourport = to_ourport(port);
1359 struct s3c24xx_uart_info *info = ourport->info;
1360 unsigned int val;
1361
1362 if (!info->has_usi)
1363 return;
1364
1365 /* Clear the software reset of USI block (it's set at startup) */
1366 val = rd_regl(port, USI_CON);
1367 val &= ~USI_CON_RESET_MASK;
1368 wr_regl(port, USI_CON, val);
1369 udelay(1);
1370
1371 /* Continuously provide the clock to USI IP w/o gating (for Rx mode) */
1372 val = rd_regl(port, USI_OPTION);
1373 val &= ~USI_OPTION_HWACG_MASK;
1374 val |= USI_OPTION_HWACG_CLKREQ_ON;
1375 wr_regl(port, USI_OPTION, val);
1376 }
1377
1378 /* power power management control */
1379
s3c24xx_serial_pm(struct uart_port * port,unsigned int level,unsigned int old)1380 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1381 unsigned int old)
1382 {
1383 struct s3c24xx_uart_port *ourport = to_ourport(port);
1384 int timeout = 10000;
1385
1386 ourport->pm_level = level;
1387
1388 switch (level) {
1389 case 3:
1390 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1391 udelay(100);
1392
1393 if (!IS_ERR(ourport->baudclk))
1394 clk_disable_unprepare(ourport->baudclk);
1395
1396 clk_disable_unprepare(ourport->clk);
1397 break;
1398
1399 case 0:
1400 clk_prepare_enable(ourport->clk);
1401
1402 if (!IS_ERR(ourport->baudclk))
1403 clk_prepare_enable(ourport->baudclk);
1404
1405 exynos_usi_init(port);
1406 break;
1407 default:
1408 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1409 }
1410 }
1411
1412 /* baud rate calculation
1413 *
1414 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1415 * of different sources, including the peripheral clock ("pclk") and an
1416 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1417 * with a programmable extra divisor.
1418 *
1419 * The following code goes through the clock sources, and calculates the
1420 * baud clocks (and the resultant actual baud rates) and then tries to
1421 * pick the closest one and select that.
1422 *
1423 */
1424
1425 #define MAX_CLK_NAME_LENGTH 15
1426
s3c24xx_serial_getsource(struct uart_port * port)1427 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1428 {
1429 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1430 unsigned int ucon;
1431
1432 if (info->num_clks == 1)
1433 return 0;
1434
1435 ucon = rd_regl(port, S3C2410_UCON);
1436 ucon &= info->clksel_mask;
1437 return ucon >> info->clksel_shift;
1438 }
1439
s3c24xx_serial_setsource(struct uart_port * port,unsigned int clk_sel)1440 static void s3c24xx_serial_setsource(struct uart_port *port,
1441 unsigned int clk_sel)
1442 {
1443 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1444 unsigned int ucon;
1445
1446 if (info->num_clks == 1)
1447 return;
1448
1449 ucon = rd_regl(port, S3C2410_UCON);
1450 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1451 return;
1452
1453 ucon &= ~info->clksel_mask;
1454 ucon |= clk_sel << info->clksel_shift;
1455 wr_regl(port, S3C2410_UCON, ucon);
1456 }
1457
s3c24xx_serial_getclk(struct s3c24xx_uart_port * ourport,unsigned int req_baud,struct clk ** best_clk,unsigned int * clk_num)1458 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1459 unsigned int req_baud, struct clk **best_clk,
1460 unsigned int *clk_num)
1461 {
1462 struct s3c24xx_uart_info *info = ourport->info;
1463 struct clk *clk;
1464 unsigned long rate;
1465 unsigned int cnt, baud, quot, best_quot = 0;
1466 char clkname[MAX_CLK_NAME_LENGTH];
1467 int calc_deviation, deviation = (1 << 30) - 1;
1468
1469 for (cnt = 0; cnt < info->num_clks; cnt++) {
1470 /* Keep selected clock if provided */
1471 if (ourport->cfg->clk_sel &&
1472 !(ourport->cfg->clk_sel & (1 << cnt)))
1473 continue;
1474
1475 sprintf(clkname, "clk_uart_baud%d", cnt);
1476 clk = clk_get(ourport->port.dev, clkname);
1477 if (IS_ERR(clk))
1478 continue;
1479
1480 rate = clk_get_rate(clk);
1481 if (!rate) {
1482 dev_err(ourport->port.dev,
1483 "Failed to get clock rate for %s.\n", clkname);
1484 clk_put(clk);
1485 continue;
1486 }
1487
1488 if (ourport->info->has_divslot) {
1489 unsigned long div = rate / req_baud;
1490
1491 /* The UDIVSLOT register on the newer UARTs allows us to
1492 * get a divisor adjustment of 1/16th on the baud clock.
1493 *
1494 * We don't keep the UDIVSLOT value (the 16ths we
1495 * calculated by not multiplying the baud by 16) as it
1496 * is easy enough to recalculate.
1497 */
1498
1499 quot = div / 16;
1500 baud = rate / div;
1501 } else {
1502 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1503 baud = rate / (quot * 16);
1504 }
1505 quot--;
1506
1507 calc_deviation = req_baud - baud;
1508 if (calc_deviation < 0)
1509 calc_deviation = -calc_deviation;
1510
1511 if (calc_deviation < deviation) {
1512 /*
1513 * If we find a better clk, release the previous one, if
1514 * any.
1515 */
1516 if (!IS_ERR(*best_clk))
1517 clk_put(*best_clk);
1518 *best_clk = clk;
1519 best_quot = quot;
1520 *clk_num = cnt;
1521 deviation = calc_deviation;
1522 } else {
1523 clk_put(clk);
1524 }
1525 }
1526
1527 return best_quot;
1528 }
1529
1530 /* udivslot_table[]
1531 *
1532 * This table takes the fractional value of the baud divisor and gives
1533 * the recommended setting for the UDIVSLOT register.
1534 */
1535 static u16 udivslot_table[16] = {
1536 [0] = 0x0000,
1537 [1] = 0x0080,
1538 [2] = 0x0808,
1539 [3] = 0x0888,
1540 [4] = 0x2222,
1541 [5] = 0x4924,
1542 [6] = 0x4A52,
1543 [7] = 0x54AA,
1544 [8] = 0x5555,
1545 [9] = 0xD555,
1546 [10] = 0xD5D5,
1547 [11] = 0xDDD5,
1548 [12] = 0xDDDD,
1549 [13] = 0xDFDD,
1550 [14] = 0xDFDF,
1551 [15] = 0xFFDF,
1552 };
1553
s3c24xx_serial_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)1554 static void s3c24xx_serial_set_termios(struct uart_port *port,
1555 struct ktermios *termios,
1556 struct ktermios *old)
1557 {
1558 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1559 struct s3c24xx_uart_port *ourport = to_ourport(port);
1560 struct clk *clk = ERR_PTR(-EINVAL);
1561 unsigned long flags;
1562 unsigned int baud, quot, clk_sel = 0;
1563 unsigned int ulcon;
1564 unsigned int umcon;
1565 unsigned int udivslot = 0;
1566
1567 /*
1568 * We don't support modem control lines.
1569 */
1570 termios->c_cflag &= ~(HUPCL | CMSPAR);
1571 termios->c_cflag |= CLOCAL;
1572
1573 /*
1574 * Ask the core to calculate the divisor for us.
1575 */
1576
1577 baud = uart_get_baud_rate(port, termios, old, 0, 3000000);
1578 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1579 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1580 quot = port->custom_divisor;
1581 if (IS_ERR(clk))
1582 return;
1583
1584 /* check to see if we need to change clock source */
1585
1586 if (ourport->baudclk != clk) {
1587 clk_prepare_enable(clk);
1588
1589 s3c24xx_serial_setsource(port, clk_sel);
1590
1591 if (!IS_ERR(ourport->baudclk)) {
1592 clk_disable_unprepare(ourport->baudclk);
1593 ourport->baudclk = ERR_PTR(-EINVAL);
1594 }
1595
1596 ourport->baudclk = clk;
1597 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1598 }
1599
1600 if (ourport->info->has_divslot) {
1601 unsigned int div = ourport->baudclk_rate / baud;
1602
1603 if (cfg->has_fracval) {
1604 udivslot = (div & 15);
1605 dev_dbg(port->dev, "fracval = %04x\n", udivslot);
1606 } else {
1607 udivslot = udivslot_table[div & 15];
1608 dev_dbg(port->dev, "udivslot = %04x (div %d)\n",
1609 udivslot, div & 15);
1610 }
1611 }
1612
1613 switch (termios->c_cflag & CSIZE) {
1614 case CS5:
1615 dev_dbg(port->dev, "config: 5bits/char\n");
1616 ulcon = S3C2410_LCON_CS5;
1617 break;
1618 case CS6:
1619 dev_dbg(port->dev, "config: 6bits/char\n");
1620 ulcon = S3C2410_LCON_CS6;
1621 break;
1622 case CS7:
1623 dev_dbg(port->dev, "config: 7bits/char\n");
1624 ulcon = S3C2410_LCON_CS7;
1625 break;
1626 case CS8:
1627 default:
1628 dev_dbg(port->dev, "config: 8bits/char\n");
1629 ulcon = S3C2410_LCON_CS8;
1630 break;
1631 }
1632
1633 /* preserve original lcon IR settings */
1634 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1635
1636 if (termios->c_cflag & CSTOPB)
1637 ulcon |= S3C2410_LCON_STOPB;
1638
1639 if (termios->c_cflag & PARENB) {
1640 if (termios->c_cflag & PARODD)
1641 ulcon |= S3C2410_LCON_PODD;
1642 else
1643 ulcon |= S3C2410_LCON_PEVEN;
1644 } else {
1645 ulcon |= S3C2410_LCON_PNONE;
1646 }
1647
1648 spin_lock_irqsave(&port->lock, flags);
1649
1650 dev_dbg(port->dev,
1651 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1652 ulcon, quot, udivslot);
1653
1654 wr_regl(port, S3C2410_ULCON, ulcon);
1655 wr_regl(port, S3C2410_UBRDIV, quot);
1656
1657 port->status &= ~UPSTAT_AUTOCTS;
1658
1659 umcon = rd_regl(port, S3C2410_UMCON);
1660 if (termios->c_cflag & CRTSCTS) {
1661 umcon |= S3C2410_UMCOM_AFC;
1662 /* Disable RTS when RX FIFO contains 63 bytes */
1663 umcon &= ~S3C2412_UMCON_AFC_8;
1664 port->status = UPSTAT_AUTOCTS;
1665 } else {
1666 umcon &= ~S3C2410_UMCOM_AFC;
1667 }
1668 wr_regl(port, S3C2410_UMCON, umcon);
1669
1670 if (ourport->info->has_divslot)
1671 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1672
1673 dev_dbg(port->dev,
1674 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1675 rd_regl(port, S3C2410_ULCON),
1676 rd_regl(port, S3C2410_UCON),
1677 rd_regl(port, S3C2410_UFCON));
1678
1679 /*
1680 * Update the per-port timeout.
1681 */
1682 uart_update_timeout(port, termios->c_cflag, baud);
1683
1684 /*
1685 * Which character status flags are we interested in?
1686 */
1687 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1688 if (termios->c_iflag & INPCK)
1689 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1690 S3C2410_UERSTAT_PARITY;
1691 /*
1692 * Which character status flags should we ignore?
1693 */
1694 port->ignore_status_mask = 0;
1695 if (termios->c_iflag & IGNPAR)
1696 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1697 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1698 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1699
1700 /*
1701 * Ignore all characters if CREAD is not set.
1702 */
1703 if ((termios->c_cflag & CREAD) == 0)
1704 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1705
1706 spin_unlock_irqrestore(&port->lock, flags);
1707 }
1708
s3c24xx_serial_type(struct uart_port * port)1709 static const char *s3c24xx_serial_type(struct uart_port *port)
1710 {
1711 struct s3c24xx_uart_port *ourport = to_ourport(port);
1712
1713 switch (ourport->info->type) {
1714 case TYPE_S3C24XX:
1715 return "S3C24XX";
1716 case TYPE_S3C6400:
1717 return "S3C6400/10";
1718 case TYPE_APPLE_S5L:
1719 return "APPLE S5L";
1720 default:
1721 return NULL;
1722 }
1723 }
1724
s3c24xx_serial_config_port(struct uart_port * port,int flags)1725 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1726 {
1727 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1728
1729 if (flags & UART_CONFIG_TYPE)
1730 port->type = info->port_type;
1731 }
1732
1733 /*
1734 * verify the new serial_struct (for TIOCSSERIAL).
1735 */
1736 static int
s3c24xx_serial_verify_port(struct uart_port * port,struct serial_struct * ser)1737 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1738 {
1739 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1740
1741 if (ser->type != PORT_UNKNOWN && ser->type != info->port_type)
1742 return -EINVAL;
1743
1744 return 0;
1745 }
1746
1747 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1748
1749 static struct console s3c24xx_serial_console;
1750
s3c24xx_serial_console_init(void)1751 static int __init s3c24xx_serial_console_init(void)
1752 {
1753 register_console(&s3c24xx_serial_console);
1754 return 0;
1755 }
1756 console_initcall(s3c24xx_serial_console_init);
1757
1758 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1759 #else
1760 #define S3C24XX_SERIAL_CONSOLE NULL
1761 #endif
1762
1763 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1764 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1765 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1766 unsigned char c);
1767 #endif
1768
1769 static const struct uart_ops s3c24xx_serial_ops = {
1770 .pm = s3c24xx_serial_pm,
1771 .tx_empty = s3c24xx_serial_tx_empty,
1772 .get_mctrl = s3c24xx_serial_get_mctrl,
1773 .set_mctrl = s3c24xx_serial_set_mctrl,
1774 .stop_tx = s3c24xx_serial_stop_tx,
1775 .start_tx = s3c24xx_serial_start_tx,
1776 .stop_rx = s3c24xx_serial_stop_rx,
1777 .break_ctl = s3c24xx_serial_break_ctl,
1778 .startup = s3c24xx_serial_startup,
1779 .shutdown = s3c24xx_serial_shutdown,
1780 .set_termios = s3c24xx_serial_set_termios,
1781 .type = s3c24xx_serial_type,
1782 .config_port = s3c24xx_serial_config_port,
1783 .verify_port = s3c24xx_serial_verify_port,
1784 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1785 .poll_get_char = s3c24xx_serial_get_poll_char,
1786 .poll_put_char = s3c24xx_serial_put_poll_char,
1787 #endif
1788 };
1789
1790 static const struct uart_ops s3c64xx_serial_ops = {
1791 .pm = s3c24xx_serial_pm,
1792 .tx_empty = s3c24xx_serial_tx_empty,
1793 .get_mctrl = s3c24xx_serial_get_mctrl,
1794 .set_mctrl = s3c24xx_serial_set_mctrl,
1795 .stop_tx = s3c24xx_serial_stop_tx,
1796 .start_tx = s3c24xx_serial_start_tx,
1797 .stop_rx = s3c24xx_serial_stop_rx,
1798 .break_ctl = s3c24xx_serial_break_ctl,
1799 .startup = s3c64xx_serial_startup,
1800 .shutdown = s3c64xx_serial_shutdown,
1801 .set_termios = s3c24xx_serial_set_termios,
1802 .type = s3c24xx_serial_type,
1803 .config_port = s3c24xx_serial_config_port,
1804 .verify_port = s3c24xx_serial_verify_port,
1805 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1806 .poll_get_char = s3c24xx_serial_get_poll_char,
1807 .poll_put_char = s3c24xx_serial_put_poll_char,
1808 #endif
1809 };
1810
1811 static const struct uart_ops apple_s5l_serial_ops = {
1812 .pm = s3c24xx_serial_pm,
1813 .tx_empty = s3c24xx_serial_tx_empty,
1814 .get_mctrl = s3c24xx_serial_get_mctrl,
1815 .set_mctrl = s3c24xx_serial_set_mctrl,
1816 .stop_tx = s3c24xx_serial_stop_tx,
1817 .start_tx = s3c24xx_serial_start_tx,
1818 .stop_rx = s3c24xx_serial_stop_rx,
1819 .break_ctl = s3c24xx_serial_break_ctl,
1820 .startup = apple_s5l_serial_startup,
1821 .shutdown = apple_s5l_serial_shutdown,
1822 .set_termios = s3c24xx_serial_set_termios,
1823 .type = s3c24xx_serial_type,
1824 .config_port = s3c24xx_serial_config_port,
1825 .verify_port = s3c24xx_serial_verify_port,
1826 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1827 .poll_get_char = s3c24xx_serial_get_poll_char,
1828 .poll_put_char = s3c24xx_serial_put_poll_char,
1829 #endif
1830 };
1831
1832 static struct uart_driver s3c24xx_uart_drv = {
1833 .owner = THIS_MODULE,
1834 .driver_name = "s3c2410_serial",
1835 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
1836 .cons = S3C24XX_SERIAL_CONSOLE,
1837 .dev_name = S3C24XX_SERIAL_NAME,
1838 .major = S3C24XX_SERIAL_MAJOR,
1839 .minor = S3C24XX_SERIAL_MINOR,
1840 };
1841
1842 #define __PORT_LOCK_UNLOCKED(i) \
1843 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1844 static struct s3c24xx_uart_port
1845 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1846 [0] = {
1847 .port = {
1848 .lock = __PORT_LOCK_UNLOCKED(0),
1849 .iotype = UPIO_MEM,
1850 .uartclk = 0,
1851 .fifosize = 16,
1852 .ops = &s3c24xx_serial_ops,
1853 .flags = UPF_BOOT_AUTOCONF,
1854 .line = 0,
1855 }
1856 },
1857 [1] = {
1858 .port = {
1859 .lock = __PORT_LOCK_UNLOCKED(1),
1860 .iotype = UPIO_MEM,
1861 .uartclk = 0,
1862 .fifosize = 16,
1863 .ops = &s3c24xx_serial_ops,
1864 .flags = UPF_BOOT_AUTOCONF,
1865 .line = 1,
1866 }
1867 },
1868 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1869 [2] = {
1870 .port = {
1871 .lock = __PORT_LOCK_UNLOCKED(2),
1872 .iotype = UPIO_MEM,
1873 .uartclk = 0,
1874 .fifosize = 16,
1875 .ops = &s3c24xx_serial_ops,
1876 .flags = UPF_BOOT_AUTOCONF,
1877 .line = 2,
1878 }
1879 },
1880 #endif
1881 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1882 [3] = {
1883 .port = {
1884 .lock = __PORT_LOCK_UNLOCKED(3),
1885 .iotype = UPIO_MEM,
1886 .uartclk = 0,
1887 .fifosize = 16,
1888 .ops = &s3c24xx_serial_ops,
1889 .flags = UPF_BOOT_AUTOCONF,
1890 .line = 3,
1891 }
1892 }
1893 #endif
1894 };
1895 #undef __PORT_LOCK_UNLOCKED
1896
1897 /* s3c24xx_serial_resetport
1898 *
1899 * reset the fifos and other the settings.
1900 */
1901
s3c24xx_serial_resetport(struct uart_port * port,struct s3c2410_uartcfg * cfg)1902 static void s3c24xx_serial_resetport(struct uart_port *port,
1903 struct s3c2410_uartcfg *cfg)
1904 {
1905 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1906 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1907
1908 ucon &= (info->clksel_mask | info->ucon_mask);
1909 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1910
1911 /* reset both fifos */
1912 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1913 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1914
1915 /* some delay is required after fifo reset */
1916 udelay(1);
1917 }
1918
1919 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1920
s3c24xx_serial_cpufreq_transition(struct notifier_block * nb,unsigned long val,void * data)1921 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1922 unsigned long val, void *data)
1923 {
1924 struct s3c24xx_uart_port *port;
1925 struct uart_port *uport;
1926
1927 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1928 uport = &port->port;
1929
1930 /* check to see if port is enabled */
1931
1932 if (port->pm_level != 0)
1933 return 0;
1934
1935 /* try and work out if the baudrate is changing, we can detect
1936 * a change in rate, but we do not have support for detecting
1937 * a disturbance in the clock-rate over the change.
1938 */
1939
1940 if (IS_ERR(port->baudclk))
1941 goto exit;
1942
1943 if (port->baudclk_rate == clk_get_rate(port->baudclk))
1944 goto exit;
1945
1946 if (val == CPUFREQ_PRECHANGE) {
1947 /* we should really shut the port down whilst the
1948 * frequency change is in progress.
1949 */
1950
1951 } else if (val == CPUFREQ_POSTCHANGE) {
1952 struct ktermios *termios;
1953 struct tty_struct *tty;
1954
1955 if (uport->state == NULL)
1956 goto exit;
1957
1958 tty = uport->state->port.tty;
1959
1960 if (tty == NULL)
1961 goto exit;
1962
1963 termios = &tty->termios;
1964
1965 if (termios == NULL) {
1966 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1967 goto exit;
1968 }
1969
1970 s3c24xx_serial_set_termios(uport, termios, NULL);
1971 }
1972
1973 exit:
1974 return 0;
1975 }
1976
1977 static inline int
s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port * port)1978 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1979 {
1980 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1981
1982 return cpufreq_register_notifier(&port->freq_transition,
1983 CPUFREQ_TRANSITION_NOTIFIER);
1984 }
1985
1986 static inline void
s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port * port)1987 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1988 {
1989 cpufreq_unregister_notifier(&port->freq_transition,
1990 CPUFREQ_TRANSITION_NOTIFIER);
1991 }
1992
1993 #else
1994 static inline int
s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port * port)1995 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1996 {
1997 return 0;
1998 }
1999
2000 static inline void
s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port * port)2001 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
2002 {
2003 }
2004 #endif
2005
s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port * ourport)2006 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport)
2007 {
2008 struct device *dev = ourport->port.dev;
2009 struct s3c24xx_uart_info *info = ourport->info;
2010 char clk_name[MAX_CLK_NAME_LENGTH];
2011 unsigned int clk_sel;
2012 struct clk *clk;
2013 int clk_num;
2014 int ret;
2015
2016 clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
2017 for (clk_num = 0; clk_num < info->num_clks; clk_num++) {
2018 if (!(clk_sel & (1 << clk_num)))
2019 continue;
2020
2021 sprintf(clk_name, "clk_uart_baud%d", clk_num);
2022 clk = clk_get(dev, clk_name);
2023 if (IS_ERR(clk))
2024 continue;
2025
2026 ret = clk_prepare_enable(clk);
2027 if (ret) {
2028 clk_put(clk);
2029 continue;
2030 }
2031
2032 ourport->baudclk = clk;
2033 ourport->baudclk_rate = clk_get_rate(clk);
2034 s3c24xx_serial_setsource(&ourport->port, clk_num);
2035
2036 return 0;
2037 }
2038
2039 return -EINVAL;
2040 }
2041
2042 /* s3c24xx_serial_init_port
2043 *
2044 * initialise a single serial port from the platform device given
2045 */
2046
s3c24xx_serial_init_port(struct s3c24xx_uart_port * ourport,struct platform_device * platdev)2047 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
2048 struct platform_device *platdev)
2049 {
2050 struct uart_port *port = &ourport->port;
2051 struct s3c2410_uartcfg *cfg = ourport->cfg;
2052 struct resource *res;
2053 int ret;
2054
2055 if (platdev == NULL)
2056 return -ENODEV;
2057
2058 if (port->mapbase != 0)
2059 return -EINVAL;
2060
2061 /* setup info for port */
2062 port->dev = &platdev->dev;
2063
2064 port->uartclk = 1;
2065
2066 if (cfg->uart_flags & UPF_CONS_FLOW) {
2067 dev_dbg(port->dev, "enabling flow control\n");
2068 port->flags |= UPF_CONS_FLOW;
2069 }
2070
2071 /* sort our the physical and virtual addresses for each UART */
2072
2073 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
2074 if (res == NULL) {
2075 dev_err(port->dev, "failed to find memory resource for uart\n");
2076 return -EINVAL;
2077 }
2078
2079 dev_dbg(port->dev, "resource %pR)\n", res);
2080
2081 port->membase = devm_ioremap_resource(port->dev, res);
2082 if (IS_ERR(port->membase)) {
2083 dev_err(port->dev, "failed to remap controller address\n");
2084 return -EBUSY;
2085 }
2086
2087 port->mapbase = res->start;
2088 ret = platform_get_irq(platdev, 0);
2089 if (ret < 0) {
2090 port->irq = 0;
2091 } else {
2092 port->irq = ret;
2093 ourport->rx_irq = ret;
2094 ourport->tx_irq = ret + 1;
2095 }
2096
2097 switch (ourport->info->type) {
2098 case TYPE_S3C24XX:
2099 ret = platform_get_irq(platdev, 1);
2100 if (ret > 0)
2101 ourport->tx_irq = ret;
2102 break;
2103 default:
2104 break;
2105 }
2106
2107 /*
2108 * DMA is currently supported only on DT platforms, if DMA properties
2109 * are specified.
2110 */
2111 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
2112 "dmas", NULL)) {
2113 ourport->dma = devm_kzalloc(port->dev,
2114 sizeof(*ourport->dma),
2115 GFP_KERNEL);
2116 if (!ourport->dma) {
2117 ret = -ENOMEM;
2118 goto err;
2119 }
2120 }
2121
2122 ourport->clk = clk_get(&platdev->dev, "uart");
2123 if (IS_ERR(ourport->clk)) {
2124 pr_err("%s: Controller clock not found\n",
2125 dev_name(&platdev->dev));
2126 ret = PTR_ERR(ourport->clk);
2127 goto err;
2128 }
2129
2130 ret = clk_prepare_enable(ourport->clk);
2131 if (ret) {
2132 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
2133 clk_put(ourport->clk);
2134 goto err;
2135 }
2136
2137 ret = s3c24xx_serial_enable_baudclk(ourport);
2138 if (ret)
2139 pr_warn("uart: failed to enable baudclk\n");
2140
2141 exynos_usi_init(port);
2142
2143 /* Keep all interrupts masked and cleared */
2144 switch (ourport->info->type) {
2145 case TYPE_S3C6400:
2146 wr_regl(port, S3C64XX_UINTM, 0xf);
2147 wr_regl(port, S3C64XX_UINTP, 0xf);
2148 wr_regl(port, S3C64XX_UINTSP, 0xf);
2149 break;
2150 case TYPE_APPLE_S5L: {
2151 unsigned int ucon;
2152
2153 ucon = rd_regl(port, S3C2410_UCON);
2154 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2155 APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2156 APPLE_S5L_UCON_RXTO_ENA_MSK);
2157 wr_regl(port, S3C2410_UCON, ucon);
2158
2159 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
2160 break;
2161 }
2162 default:
2163 break;
2164 }
2165
2166 dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
2167 &port->mapbase, port->membase, port->irq,
2168 ourport->rx_irq, ourport->tx_irq, port->uartclk);
2169
2170 /* reset the fifos (and setup the uart) */
2171 s3c24xx_serial_resetport(port, cfg);
2172
2173 return 0;
2174
2175 err:
2176 port->mapbase = 0;
2177 return ret;
2178 }
2179
2180 /* Device driver serial port probe */
2181
2182 #ifdef CONFIG_OF
2183 static const struct of_device_id s3c24xx_uart_dt_match[];
2184 #endif
2185
2186 static int probe_index;
2187
2188 static inline struct s3c24xx_serial_drv_data *
s3c24xx_get_driver_data(struct platform_device * pdev)2189 s3c24xx_get_driver_data(struct platform_device *pdev)
2190 {
2191 #ifdef CONFIG_OF
2192 if (pdev->dev.of_node) {
2193 const struct of_device_id *match;
2194
2195 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
2196 return (struct s3c24xx_serial_drv_data *)match->data;
2197 }
2198 #endif
2199 return (struct s3c24xx_serial_drv_data *)
2200 platform_get_device_id(pdev)->driver_data;
2201 }
2202
s3c24xx_serial_probe(struct platform_device * pdev)2203 static int s3c24xx_serial_probe(struct platform_device *pdev)
2204 {
2205 struct device_node *np = pdev->dev.of_node;
2206 struct s3c24xx_uart_port *ourport;
2207 int index = probe_index;
2208 int ret, prop = 0;
2209
2210 if (np) {
2211 ret = of_alias_get_id(np, "serial");
2212 if (ret >= 0)
2213 index = ret;
2214 }
2215
2216 if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
2217 dev_err(&pdev->dev, "serial%d out of range\n", index);
2218 return -EINVAL;
2219 }
2220 ourport = &s3c24xx_serial_ports[index];
2221
2222 ourport->drv_data = s3c24xx_get_driver_data(pdev);
2223 if (!ourport->drv_data) {
2224 dev_err(&pdev->dev, "could not find driver data\n");
2225 return -ENODEV;
2226 }
2227
2228 ourport->baudclk = ERR_PTR(-EINVAL);
2229 ourport->info = ourport->drv_data->info;
2230 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
2231 dev_get_platdata(&pdev->dev) :
2232 ourport->drv_data->def_cfg;
2233
2234 switch (ourport->info->type) {
2235 case TYPE_S3C24XX:
2236 ourport->port.ops = &s3c24xx_serial_ops;
2237 break;
2238 case TYPE_S3C6400:
2239 ourport->port.ops = &s3c64xx_serial_ops;
2240 break;
2241 case TYPE_APPLE_S5L:
2242 ourport->port.ops = &apple_s5l_serial_ops;
2243 break;
2244 }
2245
2246 if (np) {
2247 of_property_read_u32(np,
2248 "samsung,uart-fifosize", &ourport->port.fifosize);
2249
2250 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
2251 switch (prop) {
2252 case 1:
2253 ourport->port.iotype = UPIO_MEM;
2254 break;
2255 case 4:
2256 ourport->port.iotype = UPIO_MEM32;
2257 break;
2258 default:
2259 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n",
2260 prop);
2261 return -EINVAL;
2262 }
2263 }
2264 }
2265
2266 if (ourport->drv_data->fifosize[index])
2267 ourport->port.fifosize = ourport->drv_data->fifosize[index];
2268 else if (ourport->info->fifosize)
2269 ourport->port.fifosize = ourport->info->fifosize;
2270 ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE);
2271
2272 /*
2273 * DMA transfers must be aligned at least to cache line size,
2274 * so find minimal transfer size suitable for DMA mode
2275 */
2276 ourport->min_dma_size = max_t(int, ourport->port.fifosize,
2277 dma_get_cache_alignment());
2278
2279 dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport);
2280
2281 ret = s3c24xx_serial_init_port(ourport, pdev);
2282 if (ret < 0)
2283 return ret;
2284
2285 if (!s3c24xx_uart_drv.state) {
2286 ret = uart_register_driver(&s3c24xx_uart_drv);
2287 if (ret < 0) {
2288 pr_err("Failed to register Samsung UART driver\n");
2289 return ret;
2290 }
2291 }
2292
2293 dev_dbg(&pdev->dev, "%s: adding port\n", __func__);
2294 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
2295 platform_set_drvdata(pdev, &ourport->port);
2296
2297 /*
2298 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
2299 * so that a potential re-enablement through the pm-callback overlaps
2300 * and keeps the clock enabled in this case.
2301 */
2302 clk_disable_unprepare(ourport->clk);
2303 if (!IS_ERR(ourport->baudclk))
2304 clk_disable_unprepare(ourport->baudclk);
2305
2306 ret = s3c24xx_serial_cpufreq_register(ourport);
2307 if (ret < 0)
2308 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
2309
2310 probe_index++;
2311
2312 return 0;
2313 }
2314
s3c24xx_serial_remove(struct platform_device * dev)2315 static int s3c24xx_serial_remove(struct platform_device *dev)
2316 {
2317 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
2318
2319 if (port) {
2320 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
2321 uart_remove_one_port(&s3c24xx_uart_drv, port);
2322 }
2323
2324 uart_unregister_driver(&s3c24xx_uart_drv);
2325
2326 return 0;
2327 }
2328
2329 /* UART power management code */
2330 #ifdef CONFIG_PM_SLEEP
s3c24xx_serial_suspend(struct device * dev)2331 static int s3c24xx_serial_suspend(struct device *dev)
2332 {
2333 struct uart_port *port = s3c24xx_dev_to_port(dev);
2334
2335 if (port)
2336 uart_suspend_port(&s3c24xx_uart_drv, port);
2337
2338 return 0;
2339 }
2340
s3c24xx_serial_resume(struct device * dev)2341 static int s3c24xx_serial_resume(struct device *dev)
2342 {
2343 struct uart_port *port = s3c24xx_dev_to_port(dev);
2344 struct s3c24xx_uart_port *ourport = to_ourport(port);
2345
2346 if (port) {
2347 clk_prepare_enable(ourport->clk);
2348 if (!IS_ERR(ourport->baudclk))
2349 clk_prepare_enable(ourport->baudclk);
2350 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
2351 if (!IS_ERR(ourport->baudclk))
2352 clk_disable_unprepare(ourport->baudclk);
2353 clk_disable_unprepare(ourport->clk);
2354
2355 uart_resume_port(&s3c24xx_uart_drv, port);
2356 }
2357
2358 return 0;
2359 }
2360
s3c24xx_serial_resume_noirq(struct device * dev)2361 static int s3c24xx_serial_resume_noirq(struct device *dev)
2362 {
2363 struct uart_port *port = s3c24xx_dev_to_port(dev);
2364 struct s3c24xx_uart_port *ourport = to_ourport(port);
2365
2366 if (port) {
2367 /* restore IRQ mask */
2368 switch (ourport->info->type) {
2369 case TYPE_S3C6400: {
2370 unsigned int uintm = 0xf;
2371
2372 if (ourport->tx_enabled)
2373 uintm &= ~S3C64XX_UINTM_TXD_MSK;
2374 if (ourport->rx_enabled)
2375 uintm &= ~S3C64XX_UINTM_RXD_MSK;
2376 clk_prepare_enable(ourport->clk);
2377 if (!IS_ERR(ourport->baudclk))
2378 clk_prepare_enable(ourport->baudclk);
2379 wr_regl(port, S3C64XX_UINTM, uintm);
2380 if (!IS_ERR(ourport->baudclk))
2381 clk_disable_unprepare(ourport->baudclk);
2382 clk_disable_unprepare(ourport->clk);
2383 break;
2384 }
2385 case TYPE_APPLE_S5L: {
2386 unsigned int ucon;
2387 int ret;
2388
2389 ret = clk_prepare_enable(ourport->clk);
2390 if (ret) {
2391 dev_err(dev, "clk_enable clk failed: %d\n", ret);
2392 return ret;
2393 }
2394 if (!IS_ERR(ourport->baudclk)) {
2395 ret = clk_prepare_enable(ourport->baudclk);
2396 if (ret) {
2397 dev_err(dev, "clk_enable baudclk failed: %d\n", ret);
2398 clk_disable_unprepare(ourport->clk);
2399 return ret;
2400 }
2401 }
2402
2403 ucon = rd_regl(port, S3C2410_UCON);
2404
2405 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2406 APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2407 APPLE_S5L_UCON_RXTO_ENA_MSK);
2408
2409 if (ourport->tx_enabled)
2410 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
2411 if (ourport->rx_enabled)
2412 ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2413 APPLE_S5L_UCON_RXTO_ENA_MSK;
2414
2415 wr_regl(port, S3C2410_UCON, ucon);
2416
2417 if (!IS_ERR(ourport->baudclk))
2418 clk_disable_unprepare(ourport->baudclk);
2419 clk_disable_unprepare(ourport->clk);
2420 break;
2421 }
2422 default:
2423 break;
2424 }
2425 }
2426
2427 return 0;
2428 }
2429
2430 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
2431 .suspend = s3c24xx_serial_suspend,
2432 .resume = s3c24xx_serial_resume,
2433 .resume_noirq = s3c24xx_serial_resume_noirq,
2434 };
2435 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
2436
2437 #else /* !CONFIG_PM_SLEEP */
2438
2439 #define SERIAL_SAMSUNG_PM_OPS NULL
2440 #endif /* CONFIG_PM_SLEEP */
2441
2442 /* Console code */
2443
2444 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2445
2446 static struct uart_port *cons_uart;
2447
2448 static int
s3c24xx_serial_console_txrdy(struct uart_port * port,unsigned int ufcon)2449 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
2450 {
2451 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2452 unsigned long ufstat, utrstat;
2453
2454 if (ufcon & S3C2410_UFCON_FIFOMODE) {
2455 /* fifo mode - check amount of data in fifo registers... */
2456
2457 ufstat = rd_regl(port, S3C2410_UFSTAT);
2458 return (ufstat & info->tx_fifofull) ? 0 : 1;
2459 }
2460
2461 /* in non-fifo mode, we go and use the tx buffer empty */
2462
2463 utrstat = rd_regl(port, S3C2410_UTRSTAT);
2464 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2465 }
2466
2467 static bool
s3c24xx_port_configured(unsigned int ucon)2468 s3c24xx_port_configured(unsigned int ucon)
2469 {
2470 /* consider the serial port configured if the tx/rx mode set */
2471 return (ucon & 0xf) != 0;
2472 }
2473
2474 #ifdef CONFIG_CONSOLE_POLL
2475 /*
2476 * Console polling routines for writing and reading from the uart while
2477 * in an interrupt or debug context.
2478 */
2479
s3c24xx_serial_get_poll_char(struct uart_port * port)2480 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2481 {
2482 struct s3c24xx_uart_port *ourport = to_ourport(port);
2483 unsigned int ufstat;
2484
2485 ufstat = rd_regl(port, S3C2410_UFSTAT);
2486 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2487 return NO_POLL_CHAR;
2488
2489 return rd_reg(port, S3C2410_URXH);
2490 }
2491
s3c24xx_serial_put_poll_char(struct uart_port * port,unsigned char c)2492 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2493 unsigned char c)
2494 {
2495 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2496 unsigned int ucon = rd_regl(port, S3C2410_UCON);
2497
2498 /* not possible to xmit on unconfigured port */
2499 if (!s3c24xx_port_configured(ucon))
2500 return;
2501
2502 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2503 cpu_relax();
2504 wr_reg(port, S3C2410_UTXH, c);
2505 }
2506
2507 #endif /* CONFIG_CONSOLE_POLL */
2508
2509 static void
s3c24xx_serial_console_putchar(struct uart_port * port,int ch)2510 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2511 {
2512 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2513
2514 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2515 cpu_relax();
2516 wr_reg(port, S3C2410_UTXH, ch);
2517 }
2518
2519 static void
s3c24xx_serial_console_write(struct console * co,const char * s,unsigned int count)2520 s3c24xx_serial_console_write(struct console *co, const char *s,
2521 unsigned int count)
2522 {
2523 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2524
2525 /* not possible to xmit on unconfigured port */
2526 if (!s3c24xx_port_configured(ucon))
2527 return;
2528
2529 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2530 }
2531
2532 static void __init
s3c24xx_serial_get_options(struct uart_port * port,int * baud,int * parity,int * bits)2533 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2534 int *parity, int *bits)
2535 {
2536 struct clk *clk;
2537 unsigned int ulcon;
2538 unsigned int ucon;
2539 unsigned int ubrdiv;
2540 unsigned long rate;
2541 unsigned int clk_sel;
2542 char clk_name[MAX_CLK_NAME_LENGTH];
2543
2544 ulcon = rd_regl(port, S3C2410_ULCON);
2545 ucon = rd_regl(port, S3C2410_UCON);
2546 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2547
2548 if (s3c24xx_port_configured(ucon)) {
2549 switch (ulcon & S3C2410_LCON_CSMASK) {
2550 case S3C2410_LCON_CS5:
2551 *bits = 5;
2552 break;
2553 case S3C2410_LCON_CS6:
2554 *bits = 6;
2555 break;
2556 case S3C2410_LCON_CS7:
2557 *bits = 7;
2558 break;
2559 case S3C2410_LCON_CS8:
2560 default:
2561 *bits = 8;
2562 break;
2563 }
2564
2565 switch (ulcon & S3C2410_LCON_PMASK) {
2566 case S3C2410_LCON_PEVEN:
2567 *parity = 'e';
2568 break;
2569
2570 case S3C2410_LCON_PODD:
2571 *parity = 'o';
2572 break;
2573
2574 case S3C2410_LCON_PNONE:
2575 default:
2576 *parity = 'n';
2577 }
2578
2579 /* now calculate the baud rate */
2580
2581 clk_sel = s3c24xx_serial_getsource(port);
2582 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2583
2584 clk = clk_get(port->dev, clk_name);
2585 if (!IS_ERR(clk))
2586 rate = clk_get_rate(clk);
2587 else
2588 rate = 1;
2589
2590 *baud = rate / (16 * (ubrdiv + 1));
2591 dev_dbg(port->dev, "calculated baud %d\n", *baud);
2592 }
2593 }
2594
2595 static int __init
s3c24xx_serial_console_setup(struct console * co,char * options)2596 s3c24xx_serial_console_setup(struct console *co, char *options)
2597 {
2598 struct uart_port *port;
2599 int baud = 9600;
2600 int bits = 8;
2601 int parity = 'n';
2602 int flow = 'n';
2603
2604 /* is this a valid port */
2605
2606 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2607 co->index = 0;
2608
2609 port = &s3c24xx_serial_ports[co->index].port;
2610
2611 /* is the port configured? */
2612
2613 if (port->mapbase == 0x0)
2614 return -ENODEV;
2615
2616 cons_uart = port;
2617
2618 /*
2619 * Check whether an invalid uart number has been specified, and
2620 * if so, search for the first available port that does have
2621 * console support.
2622 */
2623 if (options)
2624 uart_parse_options(options, &baud, &parity, &bits, &flow);
2625 else
2626 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2627
2628 dev_dbg(port->dev, "baud %d\n", baud);
2629
2630 return uart_set_options(port, co, baud, parity, bits, flow);
2631 }
2632
2633 static struct console s3c24xx_serial_console = {
2634 .name = S3C24XX_SERIAL_NAME,
2635 .device = uart_console_device,
2636 .flags = CON_PRINTBUFFER,
2637 .index = -1,
2638 .write = s3c24xx_serial_console_write,
2639 .setup = s3c24xx_serial_console_setup,
2640 .data = &s3c24xx_uart_drv,
2641 };
2642 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2643
2644 #ifdef CONFIG_CPU_S3C2410
2645 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2646 .info = &(struct s3c24xx_uart_info) {
2647 .name = "Samsung S3C2410 UART",
2648 .type = TYPE_S3C24XX,
2649 .port_type = PORT_S3C2410,
2650 .fifosize = 16,
2651 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2652 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2653 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2654 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2655 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2656 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2657 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2658 .num_clks = 2,
2659 .clksel_mask = S3C2410_UCON_CLKMASK,
2660 .clksel_shift = S3C2410_UCON_CLKSHIFT,
2661 },
2662 .def_cfg = &(struct s3c2410_uartcfg) {
2663 .ucon = S3C2410_UCON_DEFAULT,
2664 .ufcon = S3C2410_UFCON_DEFAULT,
2665 },
2666 };
2667 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2668 #else
2669 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2670 #endif
2671
2672 #ifdef CONFIG_CPU_S3C2412
2673 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2674 .info = &(struct s3c24xx_uart_info) {
2675 .name = "Samsung S3C2412 UART",
2676 .type = TYPE_S3C24XX,
2677 .port_type = PORT_S3C2412,
2678 .fifosize = 64,
2679 .has_divslot = 1,
2680 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2681 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2682 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2683 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2684 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2685 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2686 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2687 .num_clks = 4,
2688 .clksel_mask = S3C2412_UCON_CLKMASK,
2689 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2690 },
2691 .def_cfg = &(struct s3c2410_uartcfg) {
2692 .ucon = S3C2410_UCON_DEFAULT,
2693 .ufcon = S3C2410_UFCON_DEFAULT,
2694 },
2695 };
2696 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2697 #else
2698 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2699 #endif
2700
2701 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2702 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2703 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2704 .info = &(struct s3c24xx_uart_info) {
2705 .name = "Samsung S3C2440 UART",
2706 .type = TYPE_S3C24XX,
2707 .port_type = PORT_S3C2440,
2708 .fifosize = 64,
2709 .has_divslot = 1,
2710 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2711 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2712 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2713 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2714 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2715 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2716 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2717 .num_clks = 4,
2718 .clksel_mask = S3C2412_UCON_CLKMASK,
2719 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2720 .ucon_mask = S3C2440_UCON0_DIVMASK,
2721 },
2722 .def_cfg = &(struct s3c2410_uartcfg) {
2723 .ucon = S3C2410_UCON_DEFAULT,
2724 .ufcon = S3C2410_UFCON_DEFAULT,
2725 },
2726 };
2727 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2728 #else
2729 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2730 #endif
2731
2732 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2733 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2734 .info = &(struct s3c24xx_uart_info) {
2735 .name = "Samsung S3C6400 UART",
2736 .type = TYPE_S3C6400,
2737 .port_type = PORT_S3C6400,
2738 .fifosize = 64,
2739 .has_divslot = 1,
2740 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2741 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2742 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2743 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2744 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2745 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2746 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2747 .num_clks = 4,
2748 .clksel_mask = S3C6400_UCON_CLKMASK,
2749 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2750 },
2751 .def_cfg = &(struct s3c2410_uartcfg) {
2752 .ucon = S3C2410_UCON_DEFAULT,
2753 .ufcon = S3C2410_UFCON_DEFAULT,
2754 },
2755 };
2756 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2757 #else
2758 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2759 #endif
2760
2761 #ifdef CONFIG_CPU_S5PV210
2762 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2763 .info = &(struct s3c24xx_uart_info) {
2764 .name = "Samsung S5PV210 UART",
2765 .type = TYPE_S3C6400,
2766 .port_type = PORT_S3C6400,
2767 .has_divslot = 1,
2768 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2769 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2770 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2771 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2772 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2773 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2774 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2775 .num_clks = 2,
2776 .clksel_mask = S5PV210_UCON_CLKMASK,
2777 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2778 },
2779 .def_cfg = &(struct s3c2410_uartcfg) {
2780 .ucon = S5PV210_UCON_DEFAULT,
2781 .ufcon = S5PV210_UFCON_DEFAULT,
2782 },
2783 .fifosize = { 256, 64, 16, 16 },
2784 };
2785 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2786 #else
2787 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2788 #endif
2789
2790 #if defined(CONFIG_ARCH_EXYNOS)
2791 #define EXYNOS_COMMON_SERIAL_DRV_DATA_USI(_has_usi) \
2792 .info = &(struct s3c24xx_uart_info) { \
2793 .name = "Samsung Exynos UART", \
2794 .type = TYPE_S3C6400, \
2795 .has_usi = _has_usi, \
2796 .port_type = PORT_S3C6400, \
2797 .has_divslot = 1, \
2798 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2799 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2800 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2801 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2802 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2803 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2804 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2805 .num_clks = 1, \
2806 .clksel_mask = 0, \
2807 .clksel_shift = 0, \
2808 }, \
2809 .def_cfg = &(struct s3c2410_uartcfg) { \
2810 .ucon = S5PV210_UCON_DEFAULT, \
2811 .ufcon = S5PV210_UFCON_DEFAULT, \
2812 .has_fracval = 1, \
2813 } \
2814
2815 #define EXYNOS_COMMON_SERIAL_DRV_DATA \
2816 EXYNOS_COMMON_SERIAL_DRV_DATA_USI(0)
2817
2818 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2819 EXYNOS_COMMON_SERIAL_DRV_DATA,
2820 .fifosize = { 256, 64, 16, 16 },
2821 };
2822
2823 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2824 EXYNOS_COMMON_SERIAL_DRV_DATA,
2825 .fifosize = { 64, 256, 16, 256 },
2826 };
2827
2828 static struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
2829 EXYNOS_COMMON_SERIAL_DRV_DATA_USI(1),
2830 .fifosize = { 256, 64, 64, 64 },
2831 };
2832
2833 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2834 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2835 #define EXYNOS850_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos850_serial_drv_data)
2836
2837 #else
2838 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)NULL)
2839 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)NULL)
2840 #define EXYNOS850_SERIAL_DRV_DATA ((kernel_ulong_t)NULL)
2841 #endif
2842
2843 #ifdef CONFIG_ARCH_APPLE
2844 static struct s3c24xx_serial_drv_data s5l_serial_drv_data = {
2845 .info = &(struct s3c24xx_uart_info) {
2846 .name = "Apple S5L UART",
2847 .type = TYPE_APPLE_S5L,
2848 .port_type = PORT_8250,
2849 .fifosize = 16,
2850 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2851 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2852 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2853 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2854 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2855 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2856 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2857 .num_clks = 1,
2858 .clksel_mask = 0,
2859 .clksel_shift = 0,
2860 },
2861 .def_cfg = &(struct s3c2410_uartcfg) {
2862 .ucon = APPLE_S5L_UCON_DEFAULT,
2863 .ufcon = S3C2410_UFCON_DEFAULT,
2864 },
2865 };
2866 #define S5L_SERIAL_DRV_DATA ((kernel_ulong_t)&s5l_serial_drv_data)
2867 #else
2868 #define S5L_SERIAL_DRV_DATA ((kernel_ulong_t)NULL)
2869 #endif
2870
2871 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2872 {
2873 .name = "s3c2410-uart",
2874 .driver_data = S3C2410_SERIAL_DRV_DATA,
2875 }, {
2876 .name = "s3c2412-uart",
2877 .driver_data = S3C2412_SERIAL_DRV_DATA,
2878 }, {
2879 .name = "s3c2440-uart",
2880 .driver_data = S3C2440_SERIAL_DRV_DATA,
2881 }, {
2882 .name = "s3c6400-uart",
2883 .driver_data = S3C6400_SERIAL_DRV_DATA,
2884 }, {
2885 .name = "s5pv210-uart",
2886 .driver_data = S5PV210_SERIAL_DRV_DATA,
2887 }, {
2888 .name = "exynos4210-uart",
2889 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
2890 }, {
2891 .name = "exynos5433-uart",
2892 .driver_data = EXYNOS5433_SERIAL_DRV_DATA,
2893 }, {
2894 .name = "s5l-uart",
2895 .driver_data = S5L_SERIAL_DRV_DATA,
2896 }, {
2897 .name = "exynos850-uart",
2898 .driver_data = EXYNOS850_SERIAL_DRV_DATA,
2899 },
2900 { },
2901 };
2902 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2903
2904 #ifdef CONFIG_OF
2905 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2906 { .compatible = "samsung,s3c2410-uart",
2907 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2908 { .compatible = "samsung,s3c2412-uart",
2909 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2910 { .compatible = "samsung,s3c2440-uart",
2911 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2912 { .compatible = "samsung,s3c6400-uart",
2913 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2914 { .compatible = "samsung,s5pv210-uart",
2915 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2916 { .compatible = "samsung,exynos4210-uart",
2917 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2918 { .compatible = "samsung,exynos5433-uart",
2919 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2920 { .compatible = "apple,s5l-uart",
2921 .data = (void *)S5L_SERIAL_DRV_DATA },
2922 { .compatible = "samsung,exynos850-uart",
2923 .data = (void *)EXYNOS850_SERIAL_DRV_DATA },
2924 {},
2925 };
2926 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2927 #endif
2928
2929 static struct platform_driver samsung_serial_driver = {
2930 .probe = s3c24xx_serial_probe,
2931 .remove = s3c24xx_serial_remove,
2932 .id_table = s3c24xx_serial_driver_ids,
2933 .driver = {
2934 .name = "samsung-uart",
2935 .pm = SERIAL_SAMSUNG_PM_OPS,
2936 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2937 },
2938 };
2939
2940 module_platform_driver(samsung_serial_driver);
2941
2942 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2943 /*
2944 * Early console.
2945 */
2946
wr_reg_barrier(struct uart_port * port,u32 reg,u32 val)2947 static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val)
2948 {
2949 switch (port->iotype) {
2950 case UPIO_MEM:
2951 writeb(val, portaddr(port, reg));
2952 break;
2953 case UPIO_MEM32:
2954 writel(val, portaddr(port, reg));
2955 break;
2956 }
2957 }
2958
2959 struct samsung_early_console_data {
2960 u32 txfull_mask;
2961 };
2962
samsung_early_busyuart(struct uart_port * port)2963 static void samsung_early_busyuart(struct uart_port *port)
2964 {
2965 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2966 ;
2967 }
2968
samsung_early_busyuart_fifo(struct uart_port * port)2969 static void samsung_early_busyuart_fifo(struct uart_port *port)
2970 {
2971 struct samsung_early_console_data *data = port->private_data;
2972
2973 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2974 ;
2975 }
2976
samsung_early_putc(struct uart_port * port,int c)2977 static void samsung_early_putc(struct uart_port *port, int c)
2978 {
2979 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2980 samsung_early_busyuart_fifo(port);
2981 else
2982 samsung_early_busyuart(port);
2983
2984 wr_reg_barrier(port, S3C2410_UTXH, c);
2985 }
2986
samsung_early_write(struct console * con,const char * s,unsigned int n)2987 static void samsung_early_write(struct console *con, const char *s,
2988 unsigned int n)
2989 {
2990 struct earlycon_device *dev = con->data;
2991
2992 uart_console_write(&dev->port, s, n, samsung_early_putc);
2993 }
2994
samsung_early_console_setup(struct earlycon_device * device,const char * opt)2995 static int __init samsung_early_console_setup(struct earlycon_device *device,
2996 const char *opt)
2997 {
2998 if (!device->port.membase)
2999 return -ENODEV;
3000
3001 device->con->write = samsung_early_write;
3002 return 0;
3003 }
3004
3005 /* S3C2410 */
3006 static struct samsung_early_console_data s3c2410_early_console_data = {
3007 .txfull_mask = S3C2410_UFSTAT_TXFULL,
3008 };
3009
s3c2410_early_console_setup(struct earlycon_device * device,const char * opt)3010 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
3011 const char *opt)
3012 {
3013 device->port.private_data = &s3c2410_early_console_data;
3014 return samsung_early_console_setup(device, opt);
3015 }
3016
3017 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
3018 s3c2410_early_console_setup);
3019
3020 /* S3C2412, S3C2440, S3C64xx */
3021 static struct samsung_early_console_data s3c2440_early_console_data = {
3022 .txfull_mask = S3C2440_UFSTAT_TXFULL,
3023 };
3024
s3c2440_early_console_setup(struct earlycon_device * device,const char * opt)3025 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
3026 const char *opt)
3027 {
3028 device->port.private_data = &s3c2440_early_console_data;
3029 return samsung_early_console_setup(device, opt);
3030 }
3031
3032 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
3033 s3c2440_early_console_setup);
3034 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
3035 s3c2440_early_console_setup);
3036 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
3037 s3c2440_early_console_setup);
3038
3039 /* S5PV210, Exynos */
3040 static struct samsung_early_console_data s5pv210_early_console_data = {
3041 .txfull_mask = S5PV210_UFSTAT_TXFULL,
3042 };
3043
s5pv210_early_console_setup(struct earlycon_device * device,const char * opt)3044 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
3045 const char *opt)
3046 {
3047 device->port.private_data = &s5pv210_early_console_data;
3048 return samsung_early_console_setup(device, opt);
3049 }
3050
3051 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
3052 s5pv210_early_console_setup);
3053 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
3054 s5pv210_early_console_setup);
3055
3056 /* Apple S5L */
apple_s5l_early_console_setup(struct earlycon_device * device,const char * opt)3057 static int __init apple_s5l_early_console_setup(struct earlycon_device *device,
3058 const char *opt)
3059 {
3060 /* Close enough to S3C2410 for earlycon... */
3061 device->port.private_data = &s3c2410_early_console_data;
3062
3063 #ifdef CONFIG_ARM64
3064 /* ... but we need to override the existing fixmap entry as nGnRnE */
3065 __set_fixmap(FIX_EARLYCON_MEM_BASE, device->port.mapbase,
3066 __pgprot(PROT_DEVICE_nGnRnE));
3067 #endif
3068 return samsung_early_console_setup(device, opt);
3069 }
3070
3071 OF_EARLYCON_DECLARE(s5l, "apple,s5l-uart", apple_s5l_early_console_setup);
3072 #endif
3073
3074 MODULE_ALIAS("platform:samsung-uart");
3075 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
3076 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3077 MODULE_LICENSE("GPL v2");
3078