1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * USB4 specific functionality
4 *
5 * Copyright (C) 2019, Intel Corporation
6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * Rajmohan Mani <rajmohan.mani@intel.com>
8 */
9
10 #include <linux/delay.h>
11 #include <linux/ktime.h>
12
13 #include "sb_regs.h"
14 #include "tb.h"
15
16 #define USB4_DATA_RETRIES 3
17
18 enum usb4_sb_target {
19 USB4_SB_TARGET_ROUTER,
20 USB4_SB_TARGET_PARTNER,
21 USB4_SB_TARGET_RETIMER,
22 };
23
24 #define USB4_NVM_READ_OFFSET_MASK GENMASK(23, 2)
25 #define USB4_NVM_READ_OFFSET_SHIFT 2
26 #define USB4_NVM_READ_LENGTH_MASK GENMASK(27, 24)
27 #define USB4_NVM_READ_LENGTH_SHIFT 24
28
29 #define USB4_NVM_SET_OFFSET_MASK USB4_NVM_READ_OFFSET_MASK
30 #define USB4_NVM_SET_OFFSET_SHIFT USB4_NVM_READ_OFFSET_SHIFT
31
32 #define USB4_DROM_ADDRESS_MASK GENMASK(14, 2)
33 #define USB4_DROM_ADDRESS_SHIFT 2
34 #define USB4_DROM_SIZE_MASK GENMASK(19, 15)
35 #define USB4_DROM_SIZE_SHIFT 15
36
37 #define USB4_NVM_SECTOR_SIZE_MASK GENMASK(23, 0)
38
39 #define USB4_BA_LENGTH_MASK GENMASK(7, 0)
40 #define USB4_BA_INDEX_MASK GENMASK(15, 0)
41
42 enum usb4_ba_index {
43 USB4_BA_MAX_USB3 = 0x1,
44 USB4_BA_MIN_DP_AUX = 0x2,
45 USB4_BA_MIN_DP_MAIN = 0x3,
46 USB4_BA_MAX_PCIE = 0x4,
47 USB4_BA_MAX_HI = 0x5,
48 };
49
50 #define USB4_BA_VALUE_MASK GENMASK(31, 16)
51 #define USB4_BA_VALUE_SHIFT 16
52
usb4_switch_wait_for_bit(struct tb_switch * sw,u32 offset,u32 bit,u32 value,int timeout_msec)53 static int usb4_switch_wait_for_bit(struct tb_switch *sw, u32 offset, u32 bit,
54 u32 value, int timeout_msec)
55 {
56 ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec);
57
58 do {
59 u32 val;
60 int ret;
61
62 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, offset, 1);
63 if (ret)
64 return ret;
65
66 if ((val & bit) == value)
67 return 0;
68
69 usleep_range(50, 100);
70 } while (ktime_before(ktime_get(), timeout));
71
72 return -ETIMEDOUT;
73 }
74
usb4_native_switch_op(struct tb_switch * sw,u16 opcode,u32 * metadata,u8 * status,const void * tx_data,size_t tx_dwords,void * rx_data,size_t rx_dwords)75 static int usb4_native_switch_op(struct tb_switch *sw, u16 opcode,
76 u32 *metadata, u8 *status,
77 const void *tx_data, size_t tx_dwords,
78 void *rx_data, size_t rx_dwords)
79 {
80 u32 val;
81 int ret;
82
83 if (metadata) {
84 ret = tb_sw_write(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
85 if (ret)
86 return ret;
87 }
88 if (tx_dwords) {
89 ret = tb_sw_write(sw, tx_data, TB_CFG_SWITCH, ROUTER_CS_9,
90 tx_dwords);
91 if (ret)
92 return ret;
93 }
94
95 val = opcode | ROUTER_CS_26_OV;
96 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
97 if (ret)
98 return ret;
99
100 ret = usb4_switch_wait_for_bit(sw, ROUTER_CS_26, ROUTER_CS_26_OV, 0, 500);
101 if (ret)
102 return ret;
103
104 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
105 if (ret)
106 return ret;
107
108 if (val & ROUTER_CS_26_ONS)
109 return -EOPNOTSUPP;
110
111 if (status)
112 *status = (val & ROUTER_CS_26_STATUS_MASK) >>
113 ROUTER_CS_26_STATUS_SHIFT;
114
115 if (metadata) {
116 ret = tb_sw_read(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
117 if (ret)
118 return ret;
119 }
120 if (rx_dwords) {
121 ret = tb_sw_read(sw, rx_data, TB_CFG_SWITCH, ROUTER_CS_9,
122 rx_dwords);
123 if (ret)
124 return ret;
125 }
126
127 return 0;
128 }
129
__usb4_switch_op(struct tb_switch * sw,u16 opcode,u32 * metadata,u8 * status,const void * tx_data,size_t tx_dwords,void * rx_data,size_t rx_dwords)130 static int __usb4_switch_op(struct tb_switch *sw, u16 opcode, u32 *metadata,
131 u8 *status, const void *tx_data, size_t tx_dwords,
132 void *rx_data, size_t rx_dwords)
133 {
134 const struct tb_cm_ops *cm_ops = sw->tb->cm_ops;
135
136 if (tx_dwords > NVM_DATA_DWORDS || rx_dwords > NVM_DATA_DWORDS)
137 return -EINVAL;
138
139 /*
140 * If the connection manager implementation provides USB4 router
141 * operation proxy callback, call it here instead of running the
142 * operation natively.
143 */
144 if (cm_ops->usb4_switch_op) {
145 int ret;
146
147 ret = cm_ops->usb4_switch_op(sw, opcode, metadata, status,
148 tx_data, tx_dwords, rx_data,
149 rx_dwords);
150 if (ret != -EOPNOTSUPP)
151 return ret;
152
153 /*
154 * If the proxy was not supported then run the native
155 * router operation instead.
156 */
157 }
158
159 return usb4_native_switch_op(sw, opcode, metadata, status, tx_data,
160 tx_dwords, rx_data, rx_dwords);
161 }
162
usb4_switch_op(struct tb_switch * sw,u16 opcode,u32 * metadata,u8 * status)163 static inline int usb4_switch_op(struct tb_switch *sw, u16 opcode,
164 u32 *metadata, u8 *status)
165 {
166 return __usb4_switch_op(sw, opcode, metadata, status, NULL, 0, NULL, 0);
167 }
168
usb4_switch_op_data(struct tb_switch * sw,u16 opcode,u32 * metadata,u8 * status,const void * tx_data,size_t tx_dwords,void * rx_data,size_t rx_dwords)169 static inline int usb4_switch_op_data(struct tb_switch *sw, u16 opcode,
170 u32 *metadata, u8 *status,
171 const void *tx_data, size_t tx_dwords,
172 void *rx_data, size_t rx_dwords)
173 {
174 return __usb4_switch_op(sw, opcode, metadata, status, tx_data,
175 tx_dwords, rx_data, rx_dwords);
176 }
177
usb4_switch_check_wakes(struct tb_switch * sw)178 static void usb4_switch_check_wakes(struct tb_switch *sw)
179 {
180 struct tb_port *port;
181 bool wakeup = false;
182 u32 val;
183
184 if (!device_may_wakeup(&sw->dev))
185 return;
186
187 if (tb_route(sw)) {
188 if (tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1))
189 return;
190
191 tb_sw_dbg(sw, "PCIe wake: %s, USB3 wake: %s\n",
192 (val & ROUTER_CS_6_WOPS) ? "yes" : "no",
193 (val & ROUTER_CS_6_WOUS) ? "yes" : "no");
194
195 wakeup = val & (ROUTER_CS_6_WOPS | ROUTER_CS_6_WOUS);
196 }
197
198 /* Check for any connected downstream ports for USB4 wake */
199 tb_switch_for_each_port(sw, port) {
200 if (!tb_port_has_remote(port))
201 continue;
202
203 if (tb_port_read(port, &val, TB_CFG_PORT,
204 port->cap_usb4 + PORT_CS_18, 1))
205 break;
206
207 tb_port_dbg(port, "USB4 wake: %s\n",
208 (val & PORT_CS_18_WOU4S) ? "yes" : "no");
209
210 if (val & PORT_CS_18_WOU4S)
211 wakeup = true;
212 }
213
214 if (wakeup)
215 pm_wakeup_event(&sw->dev, 0);
216 }
217
link_is_usb4(struct tb_port * port)218 static bool link_is_usb4(struct tb_port *port)
219 {
220 u32 val;
221
222 if (!port->cap_usb4)
223 return false;
224
225 if (tb_port_read(port, &val, TB_CFG_PORT,
226 port->cap_usb4 + PORT_CS_18, 1))
227 return false;
228
229 return !(val & PORT_CS_18_TCM);
230 }
231
232 /**
233 * usb4_switch_setup() - Additional setup for USB4 device
234 * @sw: USB4 router to setup
235 *
236 * USB4 routers need additional settings in order to enable all the
237 * tunneling. This function enables USB and PCIe tunneling if it can be
238 * enabled (e.g the parent switch also supports them). If USB tunneling
239 * is not available for some reason (like that there is Thunderbolt 3
240 * switch upstream) then the internal xHCI controller is enabled
241 * instead.
242 */
usb4_switch_setup(struct tb_switch * sw)243 int usb4_switch_setup(struct tb_switch *sw)
244 {
245 struct tb_port *downstream_port;
246 struct tb_switch *parent;
247 bool tbt3, xhci;
248 u32 val = 0;
249 int ret;
250
251 usb4_switch_check_wakes(sw);
252
253 if (!tb_route(sw))
254 return 0;
255
256 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1);
257 if (ret)
258 return ret;
259
260 parent = tb_switch_parent(sw);
261 downstream_port = tb_port_at(tb_route(sw), parent);
262 sw->link_usb4 = link_is_usb4(downstream_port);
263 tb_sw_dbg(sw, "link: %s\n", sw->link_usb4 ? "USB4" : "TBT");
264
265 xhci = val & ROUTER_CS_6_HCI;
266 tbt3 = !(val & ROUTER_CS_6_TNS);
267
268 tb_sw_dbg(sw, "TBT3 support: %s, xHCI: %s\n",
269 tbt3 ? "yes" : "no", xhci ? "yes" : "no");
270
271 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
272 if (ret)
273 return ret;
274
275 if (tb_acpi_may_tunnel_usb3() && sw->link_usb4 &&
276 tb_switch_find_port(parent, TB_TYPE_USB3_DOWN)) {
277 val |= ROUTER_CS_5_UTO;
278 xhci = false;
279 }
280
281 /*
282 * Only enable PCIe tunneling if the parent router supports it
283 * and it is not disabled.
284 */
285 if (tb_acpi_may_tunnel_pcie() &&
286 tb_switch_find_port(parent, TB_TYPE_PCIE_DOWN)) {
287 val |= ROUTER_CS_5_PTO;
288 /*
289 * xHCI can be enabled if PCIe tunneling is supported
290 * and the parent does not have any USB3 dowstream
291 * adapters (so we cannot do USB 3.x tunneling).
292 */
293 if (xhci)
294 val |= ROUTER_CS_5_HCO;
295 }
296
297 /* TBT3 supported by the CM */
298 val |= ROUTER_CS_5_C3S;
299 /* Tunneling configuration is ready now */
300 val |= ROUTER_CS_5_CV;
301
302 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
303 if (ret)
304 return ret;
305
306 return usb4_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_CR,
307 ROUTER_CS_6_CR, 50);
308 }
309
310 /**
311 * usb4_switch_read_uid() - Read UID from USB4 router
312 * @sw: USB4 router
313 * @uid: UID is stored here
314 *
315 * Reads 64-bit UID from USB4 router config space.
316 */
usb4_switch_read_uid(struct tb_switch * sw,u64 * uid)317 int usb4_switch_read_uid(struct tb_switch *sw, u64 *uid)
318 {
319 return tb_sw_read(sw, uid, TB_CFG_SWITCH, ROUTER_CS_7, 2);
320 }
321
usb4_switch_drom_read_block(void * data,unsigned int dwaddress,void * buf,size_t dwords)322 static int usb4_switch_drom_read_block(void *data,
323 unsigned int dwaddress, void *buf,
324 size_t dwords)
325 {
326 struct tb_switch *sw = data;
327 u8 status = 0;
328 u32 metadata;
329 int ret;
330
331 metadata = (dwords << USB4_DROM_SIZE_SHIFT) & USB4_DROM_SIZE_MASK;
332 metadata |= (dwaddress << USB4_DROM_ADDRESS_SHIFT) &
333 USB4_DROM_ADDRESS_MASK;
334
335 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_DROM_READ, &metadata,
336 &status, NULL, 0, buf, dwords);
337 if (ret)
338 return ret;
339
340 return status ? -EIO : 0;
341 }
342
343 /**
344 * usb4_switch_drom_read() - Read arbitrary bytes from USB4 router DROM
345 * @sw: USB4 router
346 * @address: Byte address inside DROM to start reading
347 * @buf: Buffer where the DROM content is stored
348 * @size: Number of bytes to read from DROM
349 *
350 * Uses USB4 router operations to read router DROM. For devices this
351 * should always work but for hosts it may return %-EOPNOTSUPP in which
352 * case the host router does not have DROM.
353 */
usb4_switch_drom_read(struct tb_switch * sw,unsigned int address,void * buf,size_t size)354 int usb4_switch_drom_read(struct tb_switch *sw, unsigned int address, void *buf,
355 size_t size)
356 {
357 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
358 usb4_switch_drom_read_block, sw);
359 }
360
361 /**
362 * usb4_switch_lane_bonding_possible() - Are conditions met for lane bonding
363 * @sw: USB4 router
364 *
365 * Checks whether conditions are met so that lane bonding can be
366 * established with the upstream router. Call only for device routers.
367 */
usb4_switch_lane_bonding_possible(struct tb_switch * sw)368 bool usb4_switch_lane_bonding_possible(struct tb_switch *sw)
369 {
370 struct tb_port *up;
371 int ret;
372 u32 val;
373
374 up = tb_upstream_port(sw);
375 ret = tb_port_read(up, &val, TB_CFG_PORT, up->cap_usb4 + PORT_CS_18, 1);
376 if (ret)
377 return false;
378
379 return !!(val & PORT_CS_18_BE);
380 }
381
382 /**
383 * usb4_switch_set_wake() - Enabled/disable wake
384 * @sw: USB4 router
385 * @flags: Wakeup flags (%0 to disable)
386 *
387 * Enables/disables router to wake up from sleep.
388 */
usb4_switch_set_wake(struct tb_switch * sw,unsigned int flags)389 int usb4_switch_set_wake(struct tb_switch *sw, unsigned int flags)
390 {
391 struct tb_port *port;
392 u64 route = tb_route(sw);
393 u32 val;
394 int ret;
395
396 /*
397 * Enable wakes coming from all USB4 downstream ports (from
398 * child routers). For device routers do this also for the
399 * upstream USB4 port.
400 */
401 tb_switch_for_each_port(sw, port) {
402 if (!tb_port_is_null(port))
403 continue;
404 if (!route && tb_is_upstream_port(port))
405 continue;
406 if (!port->cap_usb4)
407 continue;
408
409 ret = tb_port_read(port, &val, TB_CFG_PORT,
410 port->cap_usb4 + PORT_CS_19, 1);
411 if (ret)
412 return ret;
413
414 val &= ~(PORT_CS_19_WOC | PORT_CS_19_WOD | PORT_CS_19_WOU4);
415
416 if (tb_is_upstream_port(port)) {
417 val |= PORT_CS_19_WOU4;
418 } else {
419 bool configured = val & PORT_CS_19_PC;
420
421 if ((flags & TB_WAKE_ON_CONNECT) && !configured)
422 val |= PORT_CS_19_WOC;
423 if ((flags & TB_WAKE_ON_DISCONNECT) && configured)
424 val |= PORT_CS_19_WOD;
425 if ((flags & TB_WAKE_ON_USB4) && configured)
426 val |= PORT_CS_19_WOU4;
427 }
428
429 ret = tb_port_write(port, &val, TB_CFG_PORT,
430 port->cap_usb4 + PORT_CS_19, 1);
431 if (ret)
432 return ret;
433 }
434
435 /*
436 * Enable wakes from PCIe, USB 3.x and DP on this router. Only
437 * needed for device routers.
438 */
439 if (route) {
440 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
441 if (ret)
442 return ret;
443
444 val &= ~(ROUTER_CS_5_WOP | ROUTER_CS_5_WOU | ROUTER_CS_5_WOD);
445 if (flags & TB_WAKE_ON_USB3)
446 val |= ROUTER_CS_5_WOU;
447 if (flags & TB_WAKE_ON_PCIE)
448 val |= ROUTER_CS_5_WOP;
449 if (flags & TB_WAKE_ON_DP)
450 val |= ROUTER_CS_5_WOD;
451
452 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
453 if (ret)
454 return ret;
455 }
456
457 return 0;
458 }
459
460 /**
461 * usb4_switch_set_sleep() - Prepare the router to enter sleep
462 * @sw: USB4 router
463 *
464 * Sets sleep bit for the router. Returns when the router sleep ready
465 * bit has been asserted.
466 */
usb4_switch_set_sleep(struct tb_switch * sw)467 int usb4_switch_set_sleep(struct tb_switch *sw)
468 {
469 int ret;
470 u32 val;
471
472 /* Set sleep bit and wait for sleep ready to be asserted */
473 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
474 if (ret)
475 return ret;
476
477 val |= ROUTER_CS_5_SLP;
478
479 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
480 if (ret)
481 return ret;
482
483 return usb4_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_SLPR,
484 ROUTER_CS_6_SLPR, 500);
485 }
486
487 /**
488 * usb4_switch_nvm_sector_size() - Return router NVM sector size
489 * @sw: USB4 router
490 *
491 * If the router supports NVM operations this function returns the NVM
492 * sector size in bytes. If NVM operations are not supported returns
493 * %-EOPNOTSUPP.
494 */
usb4_switch_nvm_sector_size(struct tb_switch * sw)495 int usb4_switch_nvm_sector_size(struct tb_switch *sw)
496 {
497 u32 metadata;
498 u8 status;
499 int ret;
500
501 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SECTOR_SIZE, &metadata,
502 &status);
503 if (ret)
504 return ret;
505
506 if (status)
507 return status == 0x2 ? -EOPNOTSUPP : -EIO;
508
509 return metadata & USB4_NVM_SECTOR_SIZE_MASK;
510 }
511
usb4_switch_nvm_read_block(void * data,unsigned int dwaddress,void * buf,size_t dwords)512 static int usb4_switch_nvm_read_block(void *data,
513 unsigned int dwaddress, void *buf, size_t dwords)
514 {
515 struct tb_switch *sw = data;
516 u8 status = 0;
517 u32 metadata;
518 int ret;
519
520 metadata = (dwords << USB4_NVM_READ_LENGTH_SHIFT) &
521 USB4_NVM_READ_LENGTH_MASK;
522 metadata |= (dwaddress << USB4_NVM_READ_OFFSET_SHIFT) &
523 USB4_NVM_READ_OFFSET_MASK;
524
525 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_READ, &metadata,
526 &status, NULL, 0, buf, dwords);
527 if (ret)
528 return ret;
529
530 return status ? -EIO : 0;
531 }
532
533 /**
534 * usb4_switch_nvm_read() - Read arbitrary bytes from router NVM
535 * @sw: USB4 router
536 * @address: Starting address in bytes
537 * @buf: Read data is placed here
538 * @size: How many bytes to read
539 *
540 * Reads NVM contents of the router. If NVM is not supported returns
541 * %-EOPNOTSUPP.
542 */
usb4_switch_nvm_read(struct tb_switch * sw,unsigned int address,void * buf,size_t size)543 int usb4_switch_nvm_read(struct tb_switch *sw, unsigned int address, void *buf,
544 size_t size)
545 {
546 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
547 usb4_switch_nvm_read_block, sw);
548 }
549
550 /**
551 * usb4_switch_nvm_set_offset() - Set NVM write offset
552 * @sw: USB4 router
553 * @address: Start offset
554 *
555 * Explicitly sets NVM write offset. Normally when writing to NVM this
556 * is done automatically by usb4_switch_nvm_write().
557 *
558 * Returns %0 in success and negative errno if there was a failure.
559 */
usb4_switch_nvm_set_offset(struct tb_switch * sw,unsigned int address)560 int usb4_switch_nvm_set_offset(struct tb_switch *sw, unsigned int address)
561 {
562 u32 metadata, dwaddress;
563 u8 status = 0;
564 int ret;
565
566 dwaddress = address / 4;
567 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
568 USB4_NVM_SET_OFFSET_MASK;
569
570 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SET_OFFSET, &metadata,
571 &status);
572 if (ret)
573 return ret;
574
575 return status ? -EIO : 0;
576 }
577
usb4_switch_nvm_write_next_block(void * data,unsigned int dwaddress,const void * buf,size_t dwords)578 static int usb4_switch_nvm_write_next_block(void *data, unsigned int dwaddress,
579 const void *buf, size_t dwords)
580 {
581 struct tb_switch *sw = data;
582 u8 status;
583 int ret;
584
585 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_WRITE, NULL, &status,
586 buf, dwords, NULL, 0);
587 if (ret)
588 return ret;
589
590 return status ? -EIO : 0;
591 }
592
593 /**
594 * usb4_switch_nvm_write() - Write to the router NVM
595 * @sw: USB4 router
596 * @address: Start address where to write in bytes
597 * @buf: Pointer to the data to write
598 * @size: Size of @buf in bytes
599 *
600 * Writes @buf to the router NVM using USB4 router operations. If NVM
601 * write is not supported returns %-EOPNOTSUPP.
602 */
usb4_switch_nvm_write(struct tb_switch * sw,unsigned int address,const void * buf,size_t size)603 int usb4_switch_nvm_write(struct tb_switch *sw, unsigned int address,
604 const void *buf, size_t size)
605 {
606 int ret;
607
608 ret = usb4_switch_nvm_set_offset(sw, address);
609 if (ret)
610 return ret;
611
612 return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES,
613 usb4_switch_nvm_write_next_block, sw);
614 }
615
616 /**
617 * usb4_switch_nvm_authenticate() - Authenticate new NVM
618 * @sw: USB4 router
619 *
620 * After the new NVM has been written via usb4_switch_nvm_write(), this
621 * function triggers NVM authentication process. The router gets power
622 * cycled and if the authentication is successful the new NVM starts
623 * running. In case of failure returns negative errno.
624 *
625 * The caller should call usb4_switch_nvm_authenticate_status() to read
626 * the status of the authentication after power cycle. It should be the
627 * first router operation to avoid the status being lost.
628 */
usb4_switch_nvm_authenticate(struct tb_switch * sw)629 int usb4_switch_nvm_authenticate(struct tb_switch *sw)
630 {
631 int ret;
632
633 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_AUTH, NULL, NULL);
634 switch (ret) {
635 /*
636 * The router is power cycled once NVM_AUTH is started so it is
637 * expected to get any of the following errors back.
638 */
639 case -EACCES:
640 case -ENOTCONN:
641 case -ETIMEDOUT:
642 return 0;
643
644 default:
645 return ret;
646 }
647 }
648
649 /**
650 * usb4_switch_nvm_authenticate_status() - Read status of last NVM authenticate
651 * @sw: USB4 router
652 * @status: Status code of the operation
653 *
654 * The function checks if there is status available from the last NVM
655 * authenticate router operation. If there is status then %0 is returned
656 * and the status code is placed in @status. Returns negative errno in case
657 * of failure.
658 *
659 * Must be called before any other router operation.
660 */
usb4_switch_nvm_authenticate_status(struct tb_switch * sw,u32 * status)661 int usb4_switch_nvm_authenticate_status(struct tb_switch *sw, u32 *status)
662 {
663 const struct tb_cm_ops *cm_ops = sw->tb->cm_ops;
664 u16 opcode;
665 u32 val;
666 int ret;
667
668 if (cm_ops->usb4_switch_nvm_authenticate_status) {
669 ret = cm_ops->usb4_switch_nvm_authenticate_status(sw, status);
670 if (ret != -EOPNOTSUPP)
671 return ret;
672 }
673
674 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
675 if (ret)
676 return ret;
677
678 /* Check that the opcode is correct */
679 opcode = val & ROUTER_CS_26_OPCODE_MASK;
680 if (opcode == USB4_SWITCH_OP_NVM_AUTH) {
681 if (val & ROUTER_CS_26_OV)
682 return -EBUSY;
683 if (val & ROUTER_CS_26_ONS)
684 return -EOPNOTSUPP;
685
686 *status = (val & ROUTER_CS_26_STATUS_MASK) >>
687 ROUTER_CS_26_STATUS_SHIFT;
688 } else {
689 *status = 0;
690 }
691
692 return 0;
693 }
694
695 /**
696 * usb4_switch_credits_init() - Read buffer allocation parameters
697 * @sw: USB4 router
698 *
699 * Reads @sw buffer allocation parameters and initializes @sw buffer
700 * allocation fields accordingly. Specifically @sw->credits_allocation
701 * is set to %true if these parameters can be used in tunneling.
702 *
703 * Returns %0 on success and negative errno otherwise.
704 */
usb4_switch_credits_init(struct tb_switch * sw)705 int usb4_switch_credits_init(struct tb_switch *sw)
706 {
707 int max_usb3, min_dp_aux, min_dp_main, max_pcie, max_dma;
708 int ret, length, i, nports;
709 const struct tb_port *port;
710 u32 data[NVM_DATA_DWORDS];
711 u32 metadata = 0;
712 u8 status = 0;
713
714 memset(data, 0, sizeof(data));
715 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_BUFFER_ALLOC, &metadata,
716 &status, NULL, 0, data, ARRAY_SIZE(data));
717 if (ret)
718 return ret;
719 if (status)
720 return -EIO;
721
722 length = metadata & USB4_BA_LENGTH_MASK;
723 if (WARN_ON(length > ARRAY_SIZE(data)))
724 return -EMSGSIZE;
725
726 max_usb3 = -1;
727 min_dp_aux = -1;
728 min_dp_main = -1;
729 max_pcie = -1;
730 max_dma = -1;
731
732 tb_sw_dbg(sw, "credit allocation parameters:\n");
733
734 for (i = 0; i < length; i++) {
735 u16 index, value;
736
737 index = data[i] & USB4_BA_INDEX_MASK;
738 value = (data[i] & USB4_BA_VALUE_MASK) >> USB4_BA_VALUE_SHIFT;
739
740 switch (index) {
741 case USB4_BA_MAX_USB3:
742 tb_sw_dbg(sw, " USB3: %u\n", value);
743 max_usb3 = value;
744 break;
745 case USB4_BA_MIN_DP_AUX:
746 tb_sw_dbg(sw, " DP AUX: %u\n", value);
747 min_dp_aux = value;
748 break;
749 case USB4_BA_MIN_DP_MAIN:
750 tb_sw_dbg(sw, " DP main: %u\n", value);
751 min_dp_main = value;
752 break;
753 case USB4_BA_MAX_PCIE:
754 tb_sw_dbg(sw, " PCIe: %u\n", value);
755 max_pcie = value;
756 break;
757 case USB4_BA_MAX_HI:
758 tb_sw_dbg(sw, " DMA: %u\n", value);
759 max_dma = value;
760 break;
761 default:
762 tb_sw_dbg(sw, " unknown credit allocation index %#x, skipping\n",
763 index);
764 break;
765 }
766 }
767
768 /*
769 * Validate the buffer allocation preferences. If we find
770 * issues, log a warning and fall back using the hard-coded
771 * values.
772 */
773
774 /* Host router must report baMaxHI */
775 if (!tb_route(sw) && max_dma < 0) {
776 tb_sw_warn(sw, "host router is missing baMaxHI\n");
777 goto err_invalid;
778 }
779
780 nports = 0;
781 tb_switch_for_each_port(sw, port) {
782 if (tb_port_is_null(port))
783 nports++;
784 }
785
786 /* Must have DP buffer allocation (multiple USB4 ports) */
787 if (nports > 2 && (min_dp_aux < 0 || min_dp_main < 0)) {
788 tb_sw_warn(sw, "multiple USB4 ports require baMinDPaux/baMinDPmain\n");
789 goto err_invalid;
790 }
791
792 tb_switch_for_each_port(sw, port) {
793 if (tb_port_is_dpout(port) && min_dp_main < 0) {
794 tb_sw_warn(sw, "missing baMinDPmain");
795 goto err_invalid;
796 }
797 if ((tb_port_is_dpin(port) || tb_port_is_dpout(port)) &&
798 min_dp_aux < 0) {
799 tb_sw_warn(sw, "missing baMinDPaux");
800 goto err_invalid;
801 }
802 if ((tb_port_is_usb3_down(port) || tb_port_is_usb3_up(port)) &&
803 max_usb3 < 0) {
804 tb_sw_warn(sw, "missing baMaxUSB3");
805 goto err_invalid;
806 }
807 if ((tb_port_is_pcie_down(port) || tb_port_is_pcie_up(port)) &&
808 max_pcie < 0) {
809 tb_sw_warn(sw, "missing baMaxPCIe");
810 goto err_invalid;
811 }
812 }
813
814 /*
815 * Buffer allocation passed the validation so we can use it in
816 * path creation.
817 */
818 sw->credit_allocation = true;
819 if (max_usb3 > 0)
820 sw->max_usb3_credits = max_usb3;
821 if (min_dp_aux > 0)
822 sw->min_dp_aux_credits = min_dp_aux;
823 if (min_dp_main > 0)
824 sw->min_dp_main_credits = min_dp_main;
825 if (max_pcie > 0)
826 sw->max_pcie_credits = max_pcie;
827 if (max_dma > 0)
828 sw->max_dma_credits = max_dma;
829
830 return 0;
831
832 err_invalid:
833 return -EINVAL;
834 }
835
836 /**
837 * usb4_switch_query_dp_resource() - Query availability of DP IN resource
838 * @sw: USB4 router
839 * @in: DP IN adapter
840 *
841 * For DP tunneling this function can be used to query availability of
842 * DP IN resource. Returns true if the resource is available for DP
843 * tunneling, false otherwise.
844 */
usb4_switch_query_dp_resource(struct tb_switch * sw,struct tb_port * in)845 bool usb4_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in)
846 {
847 u32 metadata = in->port;
848 u8 status;
849 int ret;
850
851 ret = usb4_switch_op(sw, USB4_SWITCH_OP_QUERY_DP_RESOURCE, &metadata,
852 &status);
853 /*
854 * If DP resource allocation is not supported assume it is
855 * always available.
856 */
857 if (ret == -EOPNOTSUPP)
858 return true;
859 else if (ret)
860 return false;
861
862 return !status;
863 }
864
865 /**
866 * usb4_switch_alloc_dp_resource() - Allocate DP IN resource
867 * @sw: USB4 router
868 * @in: DP IN adapter
869 *
870 * Allocates DP IN resource for DP tunneling using USB4 router
871 * operations. If the resource was allocated returns %0. Otherwise
872 * returns negative errno, in particular %-EBUSY if the resource is
873 * already allocated.
874 */
usb4_switch_alloc_dp_resource(struct tb_switch * sw,struct tb_port * in)875 int usb4_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
876 {
877 u32 metadata = in->port;
878 u8 status;
879 int ret;
880
881 ret = usb4_switch_op(sw, USB4_SWITCH_OP_ALLOC_DP_RESOURCE, &metadata,
882 &status);
883 if (ret == -EOPNOTSUPP)
884 return 0;
885 else if (ret)
886 return ret;
887
888 return status ? -EBUSY : 0;
889 }
890
891 /**
892 * usb4_switch_dealloc_dp_resource() - Releases allocated DP IN resource
893 * @sw: USB4 router
894 * @in: DP IN adapter
895 *
896 * Releases the previously allocated DP IN resource.
897 */
usb4_switch_dealloc_dp_resource(struct tb_switch * sw,struct tb_port * in)898 int usb4_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
899 {
900 u32 metadata = in->port;
901 u8 status;
902 int ret;
903
904 ret = usb4_switch_op(sw, USB4_SWITCH_OP_DEALLOC_DP_RESOURCE, &metadata,
905 &status);
906 if (ret == -EOPNOTSUPP)
907 return 0;
908 else if (ret)
909 return ret;
910
911 return status ? -EIO : 0;
912 }
913
usb4_port_idx(const struct tb_switch * sw,const struct tb_port * port)914 static int usb4_port_idx(const struct tb_switch *sw, const struct tb_port *port)
915 {
916 struct tb_port *p;
917 int usb4_idx = 0;
918
919 /* Assume port is primary */
920 tb_switch_for_each_port(sw, p) {
921 if (!tb_port_is_null(p))
922 continue;
923 if (tb_is_upstream_port(p))
924 continue;
925 if (!p->link_nr) {
926 if (p == port)
927 break;
928 usb4_idx++;
929 }
930 }
931
932 return usb4_idx;
933 }
934
935 /**
936 * usb4_switch_map_pcie_down() - Map USB4 port to a PCIe downstream adapter
937 * @sw: USB4 router
938 * @port: USB4 port
939 *
940 * USB4 routers have direct mapping between USB4 ports and PCIe
941 * downstream adapters where the PCIe topology is extended. This
942 * function returns the corresponding downstream PCIe adapter or %NULL
943 * if no such mapping was possible.
944 */
usb4_switch_map_pcie_down(struct tb_switch * sw,const struct tb_port * port)945 struct tb_port *usb4_switch_map_pcie_down(struct tb_switch *sw,
946 const struct tb_port *port)
947 {
948 int usb4_idx = usb4_port_idx(sw, port);
949 struct tb_port *p;
950 int pcie_idx = 0;
951
952 /* Find PCIe down port matching usb4_port */
953 tb_switch_for_each_port(sw, p) {
954 if (!tb_port_is_pcie_down(p))
955 continue;
956
957 if (pcie_idx == usb4_idx)
958 return p;
959
960 pcie_idx++;
961 }
962
963 return NULL;
964 }
965
966 /**
967 * usb4_switch_map_usb3_down() - Map USB4 port to a USB3 downstream adapter
968 * @sw: USB4 router
969 * @port: USB4 port
970 *
971 * USB4 routers have direct mapping between USB4 ports and USB 3.x
972 * downstream adapters where the USB 3.x topology is extended. This
973 * function returns the corresponding downstream USB 3.x adapter or
974 * %NULL if no such mapping was possible.
975 */
usb4_switch_map_usb3_down(struct tb_switch * sw,const struct tb_port * port)976 struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw,
977 const struct tb_port *port)
978 {
979 int usb4_idx = usb4_port_idx(sw, port);
980 struct tb_port *p;
981 int usb_idx = 0;
982
983 /* Find USB3 down port matching usb4_port */
984 tb_switch_for_each_port(sw, p) {
985 if (!tb_port_is_usb3_down(p))
986 continue;
987
988 if (usb_idx == usb4_idx)
989 return p;
990
991 usb_idx++;
992 }
993
994 return NULL;
995 }
996
997 /**
998 * usb4_switch_add_ports() - Add USB4 ports for this router
999 * @sw: USB4 router
1000 *
1001 * For USB4 router finds all USB4 ports and registers devices for each.
1002 * Can be called to any router.
1003 *
1004 * Return %0 in case of success and negative errno in case of failure.
1005 */
usb4_switch_add_ports(struct tb_switch * sw)1006 int usb4_switch_add_ports(struct tb_switch *sw)
1007 {
1008 struct tb_port *port;
1009
1010 if (tb_switch_is_icm(sw) || !tb_switch_is_usb4(sw))
1011 return 0;
1012
1013 tb_switch_for_each_port(sw, port) {
1014 struct usb4_port *usb4;
1015
1016 if (!tb_port_is_null(port))
1017 continue;
1018 if (!port->cap_usb4)
1019 continue;
1020
1021 usb4 = usb4_port_device_add(port);
1022 if (IS_ERR(usb4)) {
1023 usb4_switch_remove_ports(sw);
1024 return PTR_ERR(usb4);
1025 }
1026
1027 port->usb4 = usb4;
1028 }
1029
1030 return 0;
1031 }
1032
1033 /**
1034 * usb4_switch_remove_ports() - Removes USB4 ports from this router
1035 * @sw: USB4 router
1036 *
1037 * Unregisters previously registered USB4 ports.
1038 */
usb4_switch_remove_ports(struct tb_switch * sw)1039 void usb4_switch_remove_ports(struct tb_switch *sw)
1040 {
1041 struct tb_port *port;
1042
1043 tb_switch_for_each_port(sw, port) {
1044 if (port->usb4) {
1045 usb4_port_device_remove(port->usb4);
1046 port->usb4 = NULL;
1047 }
1048 }
1049 }
1050
1051 /**
1052 * usb4_port_unlock() - Unlock USB4 downstream port
1053 * @port: USB4 port to unlock
1054 *
1055 * Unlocks USB4 downstream port so that the connection manager can
1056 * access the router below this port.
1057 */
usb4_port_unlock(struct tb_port * port)1058 int usb4_port_unlock(struct tb_port *port)
1059 {
1060 int ret;
1061 u32 val;
1062
1063 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
1064 if (ret)
1065 return ret;
1066
1067 val &= ~ADP_CS_4_LCK;
1068 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
1069 }
1070
1071 /**
1072 * usb4_port_hotplug_enable() - Enables hotplug for a port
1073 * @port: USB4 port to operate on
1074 *
1075 * Enables hot plug events on a given port. This is only intended
1076 * to be used on lane, DP-IN, and DP-OUT adapters.
1077 */
usb4_port_hotplug_enable(struct tb_port * port)1078 int usb4_port_hotplug_enable(struct tb_port *port)
1079 {
1080 int ret;
1081 u32 val;
1082
1083 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_5, 1);
1084 if (ret)
1085 return ret;
1086
1087 val &= ~ADP_CS_5_DHP;
1088 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_5, 1);
1089 }
1090
usb4_port_set_configured(struct tb_port * port,bool configured)1091 static int usb4_port_set_configured(struct tb_port *port, bool configured)
1092 {
1093 int ret;
1094 u32 val;
1095
1096 if (!port->cap_usb4)
1097 return -EINVAL;
1098
1099 ret = tb_port_read(port, &val, TB_CFG_PORT,
1100 port->cap_usb4 + PORT_CS_19, 1);
1101 if (ret)
1102 return ret;
1103
1104 if (configured)
1105 val |= PORT_CS_19_PC;
1106 else
1107 val &= ~PORT_CS_19_PC;
1108
1109 return tb_port_write(port, &val, TB_CFG_PORT,
1110 port->cap_usb4 + PORT_CS_19, 1);
1111 }
1112
1113 /**
1114 * usb4_port_configure() - Set USB4 port configured
1115 * @port: USB4 router
1116 *
1117 * Sets the USB4 link to be configured for power management purposes.
1118 */
usb4_port_configure(struct tb_port * port)1119 int usb4_port_configure(struct tb_port *port)
1120 {
1121 return usb4_port_set_configured(port, true);
1122 }
1123
1124 /**
1125 * usb4_port_unconfigure() - Set USB4 port unconfigured
1126 * @port: USB4 router
1127 *
1128 * Sets the USB4 link to be unconfigured for power management purposes.
1129 */
usb4_port_unconfigure(struct tb_port * port)1130 void usb4_port_unconfigure(struct tb_port *port)
1131 {
1132 usb4_port_set_configured(port, false);
1133 }
1134
usb4_set_xdomain_configured(struct tb_port * port,bool configured)1135 static int usb4_set_xdomain_configured(struct tb_port *port, bool configured)
1136 {
1137 int ret;
1138 u32 val;
1139
1140 if (!port->cap_usb4)
1141 return -EINVAL;
1142
1143 ret = tb_port_read(port, &val, TB_CFG_PORT,
1144 port->cap_usb4 + PORT_CS_19, 1);
1145 if (ret)
1146 return ret;
1147
1148 if (configured)
1149 val |= PORT_CS_19_PID;
1150 else
1151 val &= ~PORT_CS_19_PID;
1152
1153 return tb_port_write(port, &val, TB_CFG_PORT,
1154 port->cap_usb4 + PORT_CS_19, 1);
1155 }
1156
1157 /**
1158 * usb4_port_configure_xdomain() - Configure port for XDomain
1159 * @port: USB4 port connected to another host
1160 *
1161 * Marks the USB4 port as being connected to another host. Returns %0 in
1162 * success and negative errno in failure.
1163 */
usb4_port_configure_xdomain(struct tb_port * port)1164 int usb4_port_configure_xdomain(struct tb_port *port)
1165 {
1166 return usb4_set_xdomain_configured(port, true);
1167 }
1168
1169 /**
1170 * usb4_port_unconfigure_xdomain() - Unconfigure port for XDomain
1171 * @port: USB4 port that was connected to another host
1172 *
1173 * Clears USB4 port from being marked as XDomain.
1174 */
usb4_port_unconfigure_xdomain(struct tb_port * port)1175 void usb4_port_unconfigure_xdomain(struct tb_port *port)
1176 {
1177 usb4_set_xdomain_configured(port, false);
1178 }
1179
usb4_port_wait_for_bit(struct tb_port * port,u32 offset,u32 bit,u32 value,int timeout_msec)1180 static int usb4_port_wait_for_bit(struct tb_port *port, u32 offset, u32 bit,
1181 u32 value, int timeout_msec)
1182 {
1183 ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec);
1184
1185 do {
1186 u32 val;
1187 int ret;
1188
1189 ret = tb_port_read(port, &val, TB_CFG_PORT, offset, 1);
1190 if (ret)
1191 return ret;
1192
1193 if ((val & bit) == value)
1194 return 0;
1195
1196 usleep_range(50, 100);
1197 } while (ktime_before(ktime_get(), timeout));
1198
1199 return -ETIMEDOUT;
1200 }
1201
usb4_port_read_data(struct tb_port * port,void * data,size_t dwords)1202 static int usb4_port_read_data(struct tb_port *port, void *data, size_t dwords)
1203 {
1204 if (dwords > NVM_DATA_DWORDS)
1205 return -EINVAL;
1206
1207 return tb_port_read(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2,
1208 dwords);
1209 }
1210
usb4_port_write_data(struct tb_port * port,const void * data,size_t dwords)1211 static int usb4_port_write_data(struct tb_port *port, const void *data,
1212 size_t dwords)
1213 {
1214 if (dwords > NVM_DATA_DWORDS)
1215 return -EINVAL;
1216
1217 return tb_port_write(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2,
1218 dwords);
1219 }
1220
usb4_port_sb_read(struct tb_port * port,enum usb4_sb_target target,u8 index,u8 reg,void * buf,u8 size)1221 static int usb4_port_sb_read(struct tb_port *port, enum usb4_sb_target target,
1222 u8 index, u8 reg, void *buf, u8 size)
1223 {
1224 size_t dwords = DIV_ROUND_UP(size, 4);
1225 int ret;
1226 u32 val;
1227
1228 if (!port->cap_usb4)
1229 return -EINVAL;
1230
1231 val = reg;
1232 val |= size << PORT_CS_1_LENGTH_SHIFT;
1233 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
1234 if (target == USB4_SB_TARGET_RETIMER)
1235 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1236 val |= PORT_CS_1_PND;
1237
1238 ret = tb_port_write(port, &val, TB_CFG_PORT,
1239 port->cap_usb4 + PORT_CS_1, 1);
1240 if (ret)
1241 return ret;
1242
1243 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1,
1244 PORT_CS_1_PND, 0, 500);
1245 if (ret)
1246 return ret;
1247
1248 ret = tb_port_read(port, &val, TB_CFG_PORT,
1249 port->cap_usb4 + PORT_CS_1, 1);
1250 if (ret)
1251 return ret;
1252
1253 if (val & PORT_CS_1_NR)
1254 return -ENODEV;
1255 if (val & PORT_CS_1_RC)
1256 return -EIO;
1257
1258 return buf ? usb4_port_read_data(port, buf, dwords) : 0;
1259 }
1260
usb4_port_sb_write(struct tb_port * port,enum usb4_sb_target target,u8 index,u8 reg,const void * buf,u8 size)1261 static int usb4_port_sb_write(struct tb_port *port, enum usb4_sb_target target,
1262 u8 index, u8 reg, const void *buf, u8 size)
1263 {
1264 size_t dwords = DIV_ROUND_UP(size, 4);
1265 int ret;
1266 u32 val;
1267
1268 if (!port->cap_usb4)
1269 return -EINVAL;
1270
1271 if (buf) {
1272 ret = usb4_port_write_data(port, buf, dwords);
1273 if (ret)
1274 return ret;
1275 }
1276
1277 val = reg;
1278 val |= size << PORT_CS_1_LENGTH_SHIFT;
1279 val |= PORT_CS_1_WNR_WRITE;
1280 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
1281 if (target == USB4_SB_TARGET_RETIMER)
1282 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1283 val |= PORT_CS_1_PND;
1284
1285 ret = tb_port_write(port, &val, TB_CFG_PORT,
1286 port->cap_usb4 + PORT_CS_1, 1);
1287 if (ret)
1288 return ret;
1289
1290 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1,
1291 PORT_CS_1_PND, 0, 500);
1292 if (ret)
1293 return ret;
1294
1295 ret = tb_port_read(port, &val, TB_CFG_PORT,
1296 port->cap_usb4 + PORT_CS_1, 1);
1297 if (ret)
1298 return ret;
1299
1300 if (val & PORT_CS_1_NR)
1301 return -ENODEV;
1302 if (val & PORT_CS_1_RC)
1303 return -EIO;
1304
1305 return 0;
1306 }
1307
usb4_port_sb_op(struct tb_port * port,enum usb4_sb_target target,u8 index,enum usb4_sb_opcode opcode,int timeout_msec)1308 static int usb4_port_sb_op(struct tb_port *port, enum usb4_sb_target target,
1309 u8 index, enum usb4_sb_opcode opcode, int timeout_msec)
1310 {
1311 ktime_t timeout;
1312 u32 val;
1313 int ret;
1314
1315 val = opcode;
1316 ret = usb4_port_sb_write(port, target, index, USB4_SB_OPCODE, &val,
1317 sizeof(val));
1318 if (ret)
1319 return ret;
1320
1321 timeout = ktime_add_ms(ktime_get(), timeout_msec);
1322
1323 do {
1324 /* Check results */
1325 ret = usb4_port_sb_read(port, target, index, USB4_SB_OPCODE,
1326 &val, sizeof(val));
1327 if (ret)
1328 return ret;
1329
1330 switch (val) {
1331 case 0:
1332 return 0;
1333
1334 case USB4_SB_OPCODE_ERR:
1335 return -EAGAIN;
1336
1337 case USB4_SB_OPCODE_ONS:
1338 return -EOPNOTSUPP;
1339
1340 default:
1341 if (val != opcode)
1342 return -EIO;
1343 break;
1344 }
1345 } while (ktime_before(ktime_get(), timeout));
1346
1347 return -ETIMEDOUT;
1348 }
1349
usb4_port_set_router_offline(struct tb_port * port,bool offline)1350 static int usb4_port_set_router_offline(struct tb_port *port, bool offline)
1351 {
1352 u32 val = !offline;
1353 int ret;
1354
1355 ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1356 USB4_SB_METADATA, &val, sizeof(val));
1357 if (ret)
1358 return ret;
1359
1360 val = USB4_SB_OPCODE_ROUTER_OFFLINE;
1361 return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1362 USB4_SB_OPCODE, &val, sizeof(val));
1363 }
1364
1365 /**
1366 * usb4_port_router_offline() - Put the USB4 port to offline mode
1367 * @port: USB4 port
1368 *
1369 * This function puts the USB4 port into offline mode. In this mode the
1370 * port does not react on hotplug events anymore. This needs to be
1371 * called before retimer access is done when the USB4 links is not up.
1372 *
1373 * Returns %0 in case of success and negative errno if there was an
1374 * error.
1375 */
usb4_port_router_offline(struct tb_port * port)1376 int usb4_port_router_offline(struct tb_port *port)
1377 {
1378 return usb4_port_set_router_offline(port, true);
1379 }
1380
1381 /**
1382 * usb4_port_router_online() - Put the USB4 port back to online
1383 * @port: USB4 port
1384 *
1385 * Makes the USB4 port functional again.
1386 */
usb4_port_router_online(struct tb_port * port)1387 int usb4_port_router_online(struct tb_port *port)
1388 {
1389 return usb4_port_set_router_offline(port, false);
1390 }
1391
1392 /**
1393 * usb4_port_enumerate_retimers() - Send RT broadcast transaction
1394 * @port: USB4 port
1395 *
1396 * This forces the USB4 port to send broadcast RT transaction which
1397 * makes the retimers on the link to assign index to themselves. Returns
1398 * %0 in case of success and negative errno if there was an error.
1399 */
usb4_port_enumerate_retimers(struct tb_port * port)1400 int usb4_port_enumerate_retimers(struct tb_port *port)
1401 {
1402 u32 val;
1403
1404 val = USB4_SB_OPCODE_ENUMERATE_RETIMERS;
1405 return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1406 USB4_SB_OPCODE, &val, sizeof(val));
1407 }
1408
usb4_port_retimer_op(struct tb_port * port,u8 index,enum usb4_sb_opcode opcode,int timeout_msec)1409 static inline int usb4_port_retimer_op(struct tb_port *port, u8 index,
1410 enum usb4_sb_opcode opcode,
1411 int timeout_msec)
1412 {
1413 return usb4_port_sb_op(port, USB4_SB_TARGET_RETIMER, index, opcode,
1414 timeout_msec);
1415 }
1416
1417 /**
1418 * usb4_port_retimer_set_inbound_sbtx() - Enable sideband channel transactions
1419 * @port: USB4 port
1420 * @index: Retimer index
1421 *
1422 * Enables sideband channel transations on SBTX. Can be used when USB4
1423 * link does not go up, for example if there is no device connected.
1424 */
usb4_port_retimer_set_inbound_sbtx(struct tb_port * port,u8 index)1425 int usb4_port_retimer_set_inbound_sbtx(struct tb_port *port, u8 index)
1426 {
1427 int ret;
1428
1429 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_SET_INBOUND_SBTX,
1430 500);
1431
1432 if (ret != -ENODEV)
1433 return ret;
1434
1435 /*
1436 * Per the USB4 retimer spec, the retimer is not required to
1437 * send an RT (Retimer Transaction) response for the first
1438 * SET_INBOUND_SBTX command
1439 */
1440 return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_SET_INBOUND_SBTX,
1441 500);
1442 }
1443
1444 /**
1445 * usb4_port_retimer_unset_inbound_sbtx() - Disable sideband channel transactions
1446 * @port: USB4 port
1447 * @index: Retimer index
1448 *
1449 * Disables sideband channel transations on SBTX. The reverse of
1450 * usb4_port_retimer_set_inbound_sbtx().
1451 */
usb4_port_retimer_unset_inbound_sbtx(struct tb_port * port,u8 index)1452 int usb4_port_retimer_unset_inbound_sbtx(struct tb_port *port, u8 index)
1453 {
1454 return usb4_port_retimer_op(port, index,
1455 USB4_SB_OPCODE_UNSET_INBOUND_SBTX, 500);
1456 }
1457
1458 /**
1459 * usb4_port_retimer_read() - Read from retimer sideband registers
1460 * @port: USB4 port
1461 * @index: Retimer index
1462 * @reg: Sideband register to read
1463 * @buf: Data from @reg is stored here
1464 * @size: Number of bytes to read
1465 *
1466 * Function reads retimer sideband registers starting from @reg. The
1467 * retimer is connected to @port at @index. Returns %0 in case of
1468 * success, and read data is copied to @buf. If there is no retimer
1469 * present at given @index returns %-ENODEV. In any other failure
1470 * returns negative errno.
1471 */
usb4_port_retimer_read(struct tb_port * port,u8 index,u8 reg,void * buf,u8 size)1472 int usb4_port_retimer_read(struct tb_port *port, u8 index, u8 reg, void *buf,
1473 u8 size)
1474 {
1475 return usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index, reg, buf,
1476 size);
1477 }
1478
1479 /**
1480 * usb4_port_retimer_write() - Write to retimer sideband registers
1481 * @port: USB4 port
1482 * @index: Retimer index
1483 * @reg: Sideband register to write
1484 * @buf: Data that is written starting from @reg
1485 * @size: Number of bytes to write
1486 *
1487 * Writes retimer sideband registers starting from @reg. The retimer is
1488 * connected to @port at @index. Returns %0 in case of success. If there
1489 * is no retimer present at given @index returns %-ENODEV. In any other
1490 * failure returns negative errno.
1491 */
usb4_port_retimer_write(struct tb_port * port,u8 index,u8 reg,const void * buf,u8 size)1492 int usb4_port_retimer_write(struct tb_port *port, u8 index, u8 reg,
1493 const void *buf, u8 size)
1494 {
1495 return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index, reg, buf,
1496 size);
1497 }
1498
1499 /**
1500 * usb4_port_retimer_is_last() - Is the retimer last on-board retimer
1501 * @port: USB4 port
1502 * @index: Retimer index
1503 *
1504 * If the retimer at @index is last one (connected directly to the
1505 * Type-C port) this function returns %1. If it is not returns %0. If
1506 * the retimer is not present returns %-ENODEV. Otherwise returns
1507 * negative errno.
1508 */
usb4_port_retimer_is_last(struct tb_port * port,u8 index)1509 int usb4_port_retimer_is_last(struct tb_port *port, u8 index)
1510 {
1511 u32 metadata;
1512 int ret;
1513
1514 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_QUERY_LAST_RETIMER,
1515 500);
1516 if (ret)
1517 return ret;
1518
1519 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata,
1520 sizeof(metadata));
1521 return ret ? ret : metadata & 1;
1522 }
1523
1524 /**
1525 * usb4_port_retimer_nvm_sector_size() - Read retimer NVM sector size
1526 * @port: USB4 port
1527 * @index: Retimer index
1528 *
1529 * Reads NVM sector size (in bytes) of a retimer at @index. This
1530 * operation can be used to determine whether the retimer supports NVM
1531 * upgrade for example. Returns sector size in bytes or negative errno
1532 * in case of error. Specifically returns %-ENODEV if there is no
1533 * retimer at @index.
1534 */
usb4_port_retimer_nvm_sector_size(struct tb_port * port,u8 index)1535 int usb4_port_retimer_nvm_sector_size(struct tb_port *port, u8 index)
1536 {
1537 u32 metadata;
1538 int ret;
1539
1540 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE,
1541 500);
1542 if (ret)
1543 return ret;
1544
1545 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata,
1546 sizeof(metadata));
1547 return ret ? ret : metadata & USB4_NVM_SECTOR_SIZE_MASK;
1548 }
1549
1550 /**
1551 * usb4_port_retimer_nvm_set_offset() - Set NVM write offset
1552 * @port: USB4 port
1553 * @index: Retimer index
1554 * @address: Start offset
1555 *
1556 * Exlicitly sets NVM write offset. Normally when writing to NVM this is
1557 * done automatically by usb4_port_retimer_nvm_write().
1558 *
1559 * Returns %0 in success and negative errno if there was a failure.
1560 */
usb4_port_retimer_nvm_set_offset(struct tb_port * port,u8 index,unsigned int address)1561 int usb4_port_retimer_nvm_set_offset(struct tb_port *port, u8 index,
1562 unsigned int address)
1563 {
1564 u32 metadata, dwaddress;
1565 int ret;
1566
1567 dwaddress = address / 4;
1568 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
1569 USB4_NVM_SET_OFFSET_MASK;
1570
1571 ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata,
1572 sizeof(metadata));
1573 if (ret)
1574 return ret;
1575
1576 return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_SET_OFFSET,
1577 500);
1578 }
1579
1580 struct retimer_info {
1581 struct tb_port *port;
1582 u8 index;
1583 };
1584
usb4_port_retimer_nvm_write_next_block(void * data,unsigned int dwaddress,const void * buf,size_t dwords)1585 static int usb4_port_retimer_nvm_write_next_block(void *data,
1586 unsigned int dwaddress, const void *buf, size_t dwords)
1587
1588 {
1589 const struct retimer_info *info = data;
1590 struct tb_port *port = info->port;
1591 u8 index = info->index;
1592 int ret;
1593
1594 ret = usb4_port_retimer_write(port, index, USB4_SB_DATA,
1595 buf, dwords * 4);
1596 if (ret)
1597 return ret;
1598
1599 return usb4_port_retimer_op(port, index,
1600 USB4_SB_OPCODE_NVM_BLOCK_WRITE, 1000);
1601 }
1602
1603 /**
1604 * usb4_port_retimer_nvm_write() - Write to retimer NVM
1605 * @port: USB4 port
1606 * @index: Retimer index
1607 * @address: Byte address where to start the write
1608 * @buf: Data to write
1609 * @size: Size in bytes how much to write
1610 *
1611 * Writes @size bytes from @buf to the retimer NVM. Used for NVM
1612 * upgrade. Returns %0 if the data was written successfully and negative
1613 * errno in case of failure. Specifically returns %-ENODEV if there is
1614 * no retimer at @index.
1615 */
usb4_port_retimer_nvm_write(struct tb_port * port,u8 index,unsigned int address,const void * buf,size_t size)1616 int usb4_port_retimer_nvm_write(struct tb_port *port, u8 index, unsigned int address,
1617 const void *buf, size_t size)
1618 {
1619 struct retimer_info info = { .port = port, .index = index };
1620 int ret;
1621
1622 ret = usb4_port_retimer_nvm_set_offset(port, index, address);
1623 if (ret)
1624 return ret;
1625
1626 return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES,
1627 usb4_port_retimer_nvm_write_next_block, &info);
1628 }
1629
1630 /**
1631 * usb4_port_retimer_nvm_authenticate() - Start retimer NVM upgrade
1632 * @port: USB4 port
1633 * @index: Retimer index
1634 *
1635 * After the new NVM image has been written via usb4_port_retimer_nvm_write()
1636 * this function can be used to trigger the NVM upgrade process. If
1637 * successful the retimer restarts with the new NVM and may not have the
1638 * index set so one needs to call usb4_port_enumerate_retimers() to
1639 * force index to be assigned.
1640 */
usb4_port_retimer_nvm_authenticate(struct tb_port * port,u8 index)1641 int usb4_port_retimer_nvm_authenticate(struct tb_port *port, u8 index)
1642 {
1643 u32 val;
1644
1645 /*
1646 * We need to use the raw operation here because once the
1647 * authentication completes the retimer index is not set anymore
1648 * so we do not get back the status now.
1649 */
1650 val = USB4_SB_OPCODE_NVM_AUTH_WRITE;
1651 return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index,
1652 USB4_SB_OPCODE, &val, sizeof(val));
1653 }
1654
1655 /**
1656 * usb4_port_retimer_nvm_authenticate_status() - Read status of NVM upgrade
1657 * @port: USB4 port
1658 * @index: Retimer index
1659 * @status: Raw status code read from metadata
1660 *
1661 * This can be called after usb4_port_retimer_nvm_authenticate() and
1662 * usb4_port_enumerate_retimers() to fetch status of the NVM upgrade.
1663 *
1664 * Returns %0 if the authentication status was successfully read. The
1665 * completion metadata (the result) is then stored into @status. If
1666 * reading the status fails, returns negative errno.
1667 */
usb4_port_retimer_nvm_authenticate_status(struct tb_port * port,u8 index,u32 * status)1668 int usb4_port_retimer_nvm_authenticate_status(struct tb_port *port, u8 index,
1669 u32 *status)
1670 {
1671 u32 metadata, val;
1672 int ret;
1673
1674 ret = usb4_port_retimer_read(port, index, USB4_SB_OPCODE, &val,
1675 sizeof(val));
1676 if (ret)
1677 return ret;
1678
1679 switch (val) {
1680 case 0:
1681 *status = 0;
1682 return 0;
1683
1684 case USB4_SB_OPCODE_ERR:
1685 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA,
1686 &metadata, sizeof(metadata));
1687 if (ret)
1688 return ret;
1689
1690 *status = metadata & USB4_SB_METADATA_NVM_AUTH_WRITE_MASK;
1691 return 0;
1692
1693 case USB4_SB_OPCODE_ONS:
1694 return -EOPNOTSUPP;
1695
1696 default:
1697 return -EIO;
1698 }
1699 }
1700
usb4_port_retimer_nvm_read_block(void * data,unsigned int dwaddress,void * buf,size_t dwords)1701 static int usb4_port_retimer_nvm_read_block(void *data, unsigned int dwaddress,
1702 void *buf, size_t dwords)
1703 {
1704 const struct retimer_info *info = data;
1705 struct tb_port *port = info->port;
1706 u8 index = info->index;
1707 u32 metadata;
1708 int ret;
1709
1710 metadata = dwaddress << USB4_NVM_READ_OFFSET_SHIFT;
1711 if (dwords < NVM_DATA_DWORDS)
1712 metadata |= dwords << USB4_NVM_READ_LENGTH_SHIFT;
1713
1714 ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata,
1715 sizeof(metadata));
1716 if (ret)
1717 return ret;
1718
1719 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_READ, 500);
1720 if (ret)
1721 return ret;
1722
1723 return usb4_port_retimer_read(port, index, USB4_SB_DATA, buf,
1724 dwords * 4);
1725 }
1726
1727 /**
1728 * usb4_port_retimer_nvm_read() - Read contents of retimer NVM
1729 * @port: USB4 port
1730 * @index: Retimer index
1731 * @address: NVM address (in bytes) to start reading
1732 * @buf: Data read from NVM is stored here
1733 * @size: Number of bytes to read
1734 *
1735 * Reads retimer NVM and copies the contents to @buf. Returns %0 if the
1736 * read was successful and negative errno in case of failure.
1737 * Specifically returns %-ENODEV if there is no retimer at @index.
1738 */
usb4_port_retimer_nvm_read(struct tb_port * port,u8 index,unsigned int address,void * buf,size_t size)1739 int usb4_port_retimer_nvm_read(struct tb_port *port, u8 index,
1740 unsigned int address, void *buf, size_t size)
1741 {
1742 struct retimer_info info = { .port = port, .index = index };
1743
1744 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
1745 usb4_port_retimer_nvm_read_block, &info);
1746 }
1747
1748 /**
1749 * usb4_usb3_port_max_link_rate() - Maximum support USB3 link rate
1750 * @port: USB3 adapter port
1751 *
1752 * Return maximum supported link rate of a USB3 adapter in Mb/s.
1753 * Negative errno in case of error.
1754 */
usb4_usb3_port_max_link_rate(struct tb_port * port)1755 int usb4_usb3_port_max_link_rate(struct tb_port *port)
1756 {
1757 int ret, lr;
1758 u32 val;
1759
1760 if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port))
1761 return -EINVAL;
1762
1763 ret = tb_port_read(port, &val, TB_CFG_PORT,
1764 port->cap_adap + ADP_USB3_CS_4, 1);
1765 if (ret)
1766 return ret;
1767
1768 lr = (val & ADP_USB3_CS_4_MSLR_MASK) >> ADP_USB3_CS_4_MSLR_SHIFT;
1769 return lr == ADP_USB3_CS_4_MSLR_20G ? 20000 : 10000;
1770 }
1771
1772 /**
1773 * usb4_usb3_port_actual_link_rate() - Established USB3 link rate
1774 * @port: USB3 adapter port
1775 *
1776 * Return actual established link rate of a USB3 adapter in Mb/s. If the
1777 * link is not up returns %0 and negative errno in case of failure.
1778 */
usb4_usb3_port_actual_link_rate(struct tb_port * port)1779 int usb4_usb3_port_actual_link_rate(struct tb_port *port)
1780 {
1781 int ret, lr;
1782 u32 val;
1783
1784 if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port))
1785 return -EINVAL;
1786
1787 ret = tb_port_read(port, &val, TB_CFG_PORT,
1788 port->cap_adap + ADP_USB3_CS_4, 1);
1789 if (ret)
1790 return ret;
1791
1792 if (!(val & ADP_USB3_CS_4_ULV))
1793 return 0;
1794
1795 lr = val & ADP_USB3_CS_4_ALR_MASK;
1796 return lr == ADP_USB3_CS_4_ALR_20G ? 20000 : 10000;
1797 }
1798
usb4_usb3_port_cm_request(struct tb_port * port,bool request)1799 static int usb4_usb3_port_cm_request(struct tb_port *port, bool request)
1800 {
1801 int ret;
1802 u32 val;
1803
1804 if (!tb_port_is_usb3_down(port))
1805 return -EINVAL;
1806 if (tb_route(port->sw))
1807 return -EINVAL;
1808
1809 ret = tb_port_read(port, &val, TB_CFG_PORT,
1810 port->cap_adap + ADP_USB3_CS_2, 1);
1811 if (ret)
1812 return ret;
1813
1814 if (request)
1815 val |= ADP_USB3_CS_2_CMR;
1816 else
1817 val &= ~ADP_USB3_CS_2_CMR;
1818
1819 ret = tb_port_write(port, &val, TB_CFG_PORT,
1820 port->cap_adap + ADP_USB3_CS_2, 1);
1821 if (ret)
1822 return ret;
1823
1824 /*
1825 * We can use val here directly as the CMR bit is in the same place
1826 * as HCA. Just mask out others.
1827 */
1828 val &= ADP_USB3_CS_2_CMR;
1829 return usb4_port_wait_for_bit(port, port->cap_adap + ADP_USB3_CS_1,
1830 ADP_USB3_CS_1_HCA, val, 1500);
1831 }
1832
usb4_usb3_port_set_cm_request(struct tb_port * port)1833 static inline int usb4_usb3_port_set_cm_request(struct tb_port *port)
1834 {
1835 return usb4_usb3_port_cm_request(port, true);
1836 }
1837
usb4_usb3_port_clear_cm_request(struct tb_port * port)1838 static inline int usb4_usb3_port_clear_cm_request(struct tb_port *port)
1839 {
1840 return usb4_usb3_port_cm_request(port, false);
1841 }
1842
usb3_bw_to_mbps(u32 bw,u8 scale)1843 static unsigned int usb3_bw_to_mbps(u32 bw, u8 scale)
1844 {
1845 unsigned long uframes;
1846
1847 uframes = bw * 512UL << scale;
1848 return DIV_ROUND_CLOSEST(uframes * 8000, 1000 * 1000);
1849 }
1850
mbps_to_usb3_bw(unsigned int mbps,u8 scale)1851 static u32 mbps_to_usb3_bw(unsigned int mbps, u8 scale)
1852 {
1853 unsigned long uframes;
1854
1855 /* 1 uframe is 1/8 ms (125 us) -> 1 / 8000 s */
1856 uframes = ((unsigned long)mbps * 1000 * 1000) / 8000;
1857 return DIV_ROUND_UP(uframes, 512UL << scale);
1858 }
1859
usb4_usb3_port_read_allocated_bandwidth(struct tb_port * port,int * upstream_bw,int * downstream_bw)1860 static int usb4_usb3_port_read_allocated_bandwidth(struct tb_port *port,
1861 int *upstream_bw,
1862 int *downstream_bw)
1863 {
1864 u32 val, bw, scale;
1865 int ret;
1866
1867 ret = tb_port_read(port, &val, TB_CFG_PORT,
1868 port->cap_adap + ADP_USB3_CS_2, 1);
1869 if (ret)
1870 return ret;
1871
1872 ret = tb_port_read(port, &scale, TB_CFG_PORT,
1873 port->cap_adap + ADP_USB3_CS_3, 1);
1874 if (ret)
1875 return ret;
1876
1877 scale &= ADP_USB3_CS_3_SCALE_MASK;
1878
1879 bw = val & ADP_USB3_CS_2_AUBW_MASK;
1880 *upstream_bw = usb3_bw_to_mbps(bw, scale);
1881
1882 bw = (val & ADP_USB3_CS_2_ADBW_MASK) >> ADP_USB3_CS_2_ADBW_SHIFT;
1883 *downstream_bw = usb3_bw_to_mbps(bw, scale);
1884
1885 return 0;
1886 }
1887
1888 /**
1889 * usb4_usb3_port_allocated_bandwidth() - Bandwidth allocated for USB3
1890 * @port: USB3 adapter port
1891 * @upstream_bw: Allocated upstream bandwidth is stored here
1892 * @downstream_bw: Allocated downstream bandwidth is stored here
1893 *
1894 * Stores currently allocated USB3 bandwidth into @upstream_bw and
1895 * @downstream_bw in Mb/s. Returns %0 in case of success and negative
1896 * errno in failure.
1897 */
usb4_usb3_port_allocated_bandwidth(struct tb_port * port,int * upstream_bw,int * downstream_bw)1898 int usb4_usb3_port_allocated_bandwidth(struct tb_port *port, int *upstream_bw,
1899 int *downstream_bw)
1900 {
1901 int ret;
1902
1903 ret = usb4_usb3_port_set_cm_request(port);
1904 if (ret)
1905 return ret;
1906
1907 ret = usb4_usb3_port_read_allocated_bandwidth(port, upstream_bw,
1908 downstream_bw);
1909 usb4_usb3_port_clear_cm_request(port);
1910
1911 return ret;
1912 }
1913
usb4_usb3_port_read_consumed_bandwidth(struct tb_port * port,int * upstream_bw,int * downstream_bw)1914 static int usb4_usb3_port_read_consumed_bandwidth(struct tb_port *port,
1915 int *upstream_bw,
1916 int *downstream_bw)
1917 {
1918 u32 val, bw, scale;
1919 int ret;
1920
1921 ret = tb_port_read(port, &val, TB_CFG_PORT,
1922 port->cap_adap + ADP_USB3_CS_1, 1);
1923 if (ret)
1924 return ret;
1925
1926 ret = tb_port_read(port, &scale, TB_CFG_PORT,
1927 port->cap_adap + ADP_USB3_CS_3, 1);
1928 if (ret)
1929 return ret;
1930
1931 scale &= ADP_USB3_CS_3_SCALE_MASK;
1932
1933 bw = val & ADP_USB3_CS_1_CUBW_MASK;
1934 *upstream_bw = usb3_bw_to_mbps(bw, scale);
1935
1936 bw = (val & ADP_USB3_CS_1_CDBW_MASK) >> ADP_USB3_CS_1_CDBW_SHIFT;
1937 *downstream_bw = usb3_bw_to_mbps(bw, scale);
1938
1939 return 0;
1940 }
1941
usb4_usb3_port_write_allocated_bandwidth(struct tb_port * port,int upstream_bw,int downstream_bw)1942 static int usb4_usb3_port_write_allocated_bandwidth(struct tb_port *port,
1943 int upstream_bw,
1944 int downstream_bw)
1945 {
1946 u32 val, ubw, dbw, scale;
1947 int ret, max_bw;
1948
1949 /* Figure out suitable scale */
1950 scale = 0;
1951 max_bw = max(upstream_bw, downstream_bw);
1952 while (scale < 64) {
1953 if (mbps_to_usb3_bw(max_bw, scale) < 4096)
1954 break;
1955 scale++;
1956 }
1957
1958 if (WARN_ON(scale >= 64))
1959 return -EINVAL;
1960
1961 ret = tb_port_write(port, &scale, TB_CFG_PORT,
1962 port->cap_adap + ADP_USB3_CS_3, 1);
1963 if (ret)
1964 return ret;
1965
1966 ubw = mbps_to_usb3_bw(upstream_bw, scale);
1967 dbw = mbps_to_usb3_bw(downstream_bw, scale);
1968
1969 tb_port_dbg(port, "scaled bandwidth %u/%u, scale %u\n", ubw, dbw, scale);
1970
1971 ret = tb_port_read(port, &val, TB_CFG_PORT,
1972 port->cap_adap + ADP_USB3_CS_2, 1);
1973 if (ret)
1974 return ret;
1975
1976 val &= ~(ADP_USB3_CS_2_AUBW_MASK | ADP_USB3_CS_2_ADBW_MASK);
1977 val |= dbw << ADP_USB3_CS_2_ADBW_SHIFT;
1978 val |= ubw;
1979
1980 return tb_port_write(port, &val, TB_CFG_PORT,
1981 port->cap_adap + ADP_USB3_CS_2, 1);
1982 }
1983
1984 /**
1985 * usb4_usb3_port_allocate_bandwidth() - Allocate bandwidth for USB3
1986 * @port: USB3 adapter port
1987 * @upstream_bw: New upstream bandwidth
1988 * @downstream_bw: New downstream bandwidth
1989 *
1990 * This can be used to set how much bandwidth is allocated for the USB3
1991 * tunneled isochronous traffic. @upstream_bw and @downstream_bw are the
1992 * new values programmed to the USB3 adapter allocation registers. If
1993 * the values are lower than what is currently consumed the allocation
1994 * is set to what is currently consumed instead (consumed bandwidth
1995 * cannot be taken away by CM). The actual new values are returned in
1996 * @upstream_bw and @downstream_bw.
1997 *
1998 * Returns %0 in case of success and negative errno if there was a
1999 * failure.
2000 */
usb4_usb3_port_allocate_bandwidth(struct tb_port * port,int * upstream_bw,int * downstream_bw)2001 int usb4_usb3_port_allocate_bandwidth(struct tb_port *port, int *upstream_bw,
2002 int *downstream_bw)
2003 {
2004 int ret, consumed_up, consumed_down, allocate_up, allocate_down;
2005
2006 ret = usb4_usb3_port_set_cm_request(port);
2007 if (ret)
2008 return ret;
2009
2010 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up,
2011 &consumed_down);
2012 if (ret)
2013 goto err_request;
2014
2015 /* Don't allow it go lower than what is consumed */
2016 allocate_up = max(*upstream_bw, consumed_up);
2017 allocate_down = max(*downstream_bw, consumed_down);
2018
2019 ret = usb4_usb3_port_write_allocated_bandwidth(port, allocate_up,
2020 allocate_down);
2021 if (ret)
2022 goto err_request;
2023
2024 *upstream_bw = allocate_up;
2025 *downstream_bw = allocate_down;
2026
2027 err_request:
2028 usb4_usb3_port_clear_cm_request(port);
2029 return ret;
2030 }
2031
2032 /**
2033 * usb4_usb3_port_release_bandwidth() - Release allocated USB3 bandwidth
2034 * @port: USB3 adapter port
2035 * @upstream_bw: New allocated upstream bandwidth
2036 * @downstream_bw: New allocated downstream bandwidth
2037 *
2038 * Releases USB3 allocated bandwidth down to what is actually consumed.
2039 * The new bandwidth is returned in @upstream_bw and @downstream_bw.
2040 *
2041 * Returns 0% in success and negative errno in case of failure.
2042 */
usb4_usb3_port_release_bandwidth(struct tb_port * port,int * upstream_bw,int * downstream_bw)2043 int usb4_usb3_port_release_bandwidth(struct tb_port *port, int *upstream_bw,
2044 int *downstream_bw)
2045 {
2046 int ret, consumed_up, consumed_down;
2047
2048 ret = usb4_usb3_port_set_cm_request(port);
2049 if (ret)
2050 return ret;
2051
2052 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up,
2053 &consumed_down);
2054 if (ret)
2055 goto err_request;
2056
2057 /*
2058 * Always keep 1000 Mb/s to make sure xHCI has at least some
2059 * bandwidth available for isochronous traffic.
2060 */
2061 if (consumed_up < 1000)
2062 consumed_up = 1000;
2063 if (consumed_down < 1000)
2064 consumed_down = 1000;
2065
2066 ret = usb4_usb3_port_write_allocated_bandwidth(port, consumed_up,
2067 consumed_down);
2068 if (ret)
2069 goto err_request;
2070
2071 *upstream_bw = consumed_up;
2072 *downstream_bw = consumed_down;
2073
2074 err_request:
2075 usb4_usb3_port_clear_cm_request(port);
2076 return ret;
2077 }
2078