| /drivers/gpu/drm/meson/ |
| D | meson_overlay.c | 41 #define VD_X_START(value) FIELD_PREP(GENMASK(14, 0), value) argument
42 #define VD_X_END(value) FIELD_PREP(GENMASK(30, 16), value) argument
45 #define VD_Y_START(value) FIELD_PREP(GENMASK(12, 0), value) argument
46 #define VD_Y_END(value) FIELD_PREP(GENMASK(28, 16), value) argument
49 #define VD_COLOR_MAP(value) FIELD_PREP(GENMASK(1, 0), value) argument
52 #define VD_HORZ_Y_C_RATIO(value) FIELD_PREP(GENMASK(22, 21), value) argument
55 #define VD_VERT_INITIAL_PHASE(value) FIELD_PREP(GENMASK(11, 8), value) argument
56 #define VD_VERT_PHASE_STEP(value) FIELD_PREP(GENMASK(7, 1), value) argument
60 #define VD_H_END(value) FIELD_PREP(GENMASK(11, 0), value) argument
61 #define VD_H_START(value) FIELD_PREP(GENMASK(27, 16), \ argument
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| /drivers/net/wireless/realtek/rtw88/ |
| D | tx.h | 12 #define SET_TX_DESC_TXPKTSIZE(txdesc, value) \ argument
14 #define SET_TX_DESC_OFFSET(txdesc, value) \ argument
16 #define SET_TX_DESC_PKT_OFFSET(txdesc, value) \ argument
18 #define SET_TX_DESC_QSEL(txdesc, value) \ argument
20 #define SET_TX_DESC_BMC(txdesc, value) \ argument
22 #define SET_TX_DESC_RATE_ID(txdesc, value) \ argument
24 #define SET_TX_DESC_DATARATE(txdesc, value) \ argument
26 #define SET_TX_DESC_DISDATAFB(txdesc, value) \ argument
28 #define SET_TX_DESC_USE_RATE(txdesc, value) \ argument
30 #define SET_TX_DESC_SEC_TYPE(txdesc, value) \ argument
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| D | fw.h | 280 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \ argument
282 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \ argument
284 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \ argument
286 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \ argument
296 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ argument
298 #define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \ argument
301 #define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \ argument
303 #define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \ argument
305 #define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \ argument
307 #define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \ argument
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| /drivers/video/fbdev/riva/ |
| D | nvreg.h | 34 #define SetBF(mask,value) ((value) << (0?mask)) argument
37 #define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ argument
47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) argument
51 #define DEVICE_DEF(device,mask,value) \ argument
53 #define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) argument
56 #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) argument
59 #define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value) argument
60 #define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value) argument
63 #define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value) argument
66 #define PFB_Def(mask,value) DEVICE_DEF(PFB,mask,value) argument
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| /drivers/net/ethernet/sfc/falcon/ |
| D | io.h | 67 static inline void _ef4_writeq(struct ef4_nic *efx, __le64 value, in _ef4_writeq()
78 static inline void _ef4_writed(struct ef4_nic *efx, __le32 value, in _ef4_writed()
89 static inline void ef4_writeo(struct ef4_nic *efx, const ef4_oword_t *value, in ef4_writeo()
113 const ef4_qword_t *value, unsigned int index) in ef4_sram_writeq()
133 static inline void ef4_writed(struct ef4_nic *efx, const ef4_dword_t *value, in ef4_writed()
145 static inline void ef4_reado(struct ef4_nic *efx, ef4_oword_t *value, in ef4_reado()
164 ef4_qword_t *value, unsigned int index) in ef4_sram_readq()
184 static inline void ef4_readd(struct ef4_nic *efx, ef4_dword_t *value, in ef4_readd()
195 ef4_writeo_table(struct ef4_nic *efx, const ef4_oword_t *value, in ef4_writeo_table()
202 static inline void ef4_reado_table(struct ef4_nic *efx, ef4_oword_t *value, in ef4_reado_table()
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| /drivers/net/ethernet/sfc/ |
| D | io.h | 84 static inline void _efx_writeq(struct efx_nic *efx, __le64 value, in _efx_writeq()
95 static inline void _efx_writed(struct efx_nic *efx, __le32 value, in _efx_writed()
106 static inline void efx_writeo(struct efx_nic *efx, const efx_oword_t *value, in efx_writeo()
130 const efx_qword_t *value, unsigned int index) in efx_sram_writeq()
150 static inline void efx_writed(struct efx_nic *efx, const efx_dword_t *value, in efx_writed()
162 static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value, in efx_reado()
181 efx_qword_t *value, unsigned int index) in efx_sram_readq()
201 static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value, in efx_readd()
212 efx_writeo_table(struct efx_nic *efx, const efx_oword_t *value, in efx_writeo_table()
219 static inline void efx_reado_table(struct efx_nic *efx, efx_oword_t *value, in efx_reado_table()
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| /drivers/net/ethernet/stmicro/stmmac/ |
| D | dwxgmac2_dma.c | 13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset() local
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init() local
39 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan() local
53 u32 value; in dwxgmac2_dma_init_rx_chan() local
69 u32 value; in dwxgmac2_dma_init_tx_chan() local
83 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_axi() local
145 u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); in dwxgmac2_dma_rx_mode() local
211 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_dma_tx_mode() local
254 u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_enable_dma_irq() local
267 u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_disable_dma_irq() local
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| D | dwmac4_core.c | 28 u32 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_core_init() local
76 u32 value = readl(ioaddr + GMAC_RXQ_CTRL0); in dwmac4_rx_queue_enable() local
92 u32 value; in dwmac4_rx_queue_priority() local
111 u32 value; in dwmac4_tx_queue_priority() local
130 u32 value; in dwmac4_rx_queue_routing() local
163 u32 value = readl(ioaddr + MTL_OPERATION_MODE); in dwmac4_prog_mtl_rx_algorithms() local
184 u32 value = readl(ioaddr + MTL_OPERATION_MODE); in dwmac4_prog_mtl_tx_algorithms() local
211 u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue)); in dwmac4_set_mtl_tx_queue_weight() local
221 u32 value; in dwmac4_map_mtl_dma() local
250 u32 value; in dwmac4_config_cbs() local
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| D | dwxgmac2_core.c | 70 u32 value; in dwxgmac2_rx_ipc() local
86 u32 value; in dwxgmac2_rx_queue_enable() local
100 u32 value, reg; in dwxgmac2_rx_queue_prio() local
117 u32 value, reg; in dwxgmac2_tx_queue_prio() local
134 u32 value; in dwxgmac2_prog_mtl_rx_algorithms() local
157 u32 value; in dwxgmac2_prog_mtl_tx_algorithms() local
202 u32 value, reg; in dwxgmac2_map_mtl_to_dma() local
220 u32 value; in dwxgmac2_config_cbs() local
309 u32 value = XGMAC_TFE; in dwxgmac2_flow_ctrl() local
342 u32 value; in dwxgmac2_set_umac_addr() local
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| D | dwmac_lib.c | 18 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac_dma_reset() local
37 u32 value = readl(ioaddr + DMA_INTR_ENA); in dwmac_enable_dma_irq() local
49 u32 value = readl(ioaddr + DMA_INTR_ENA); in dwmac_disable_dma_irq() local
61 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_start_tx() local
68 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_stop_tx() local
75 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_start_rx() local
82 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_stop_rx() local
209 u32 value = readl(ioaddr + DMA_INTR_ENA); in dwmac_dma_interrupt() local
261 u32 old_val, value; in stmmac_set_mac() local
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| D | dwmac4_lib.c | 17 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac4_dma_reset() local
40 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_start_tx() local
52 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_stop_tx() local
60 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_start_rx() local
73 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_stop_rx() local
91 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_enable_dma_irq() local
103 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac410_enable_dma_irq() local
115 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_disable_dma_irq() local
127 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac410_disable_dma_irq() local
209 u32 value = readl(ioaddr + GMAC_CONFIG); in stmmac_dwmac4_set_mac() local
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| D | dwmac4_dma.c | 19 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); in dwmac4_dma_axi() local
75 u32 value; in dwmac4_dma_init_rx_chan() local
93 u32 value; in dwmac4_dma_init_tx_chan() local
114 u32 value; in dwmac4_dma_init_channel() local
130 u32 value; in dwmac410_dma_init_channel() local
147 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); in dwmac4_dma_init() local
447 u32 value; in dwmac4_enable_tso() local
477 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_set_bfsize() local
487 u32 value = readl(ioaddr + GMAC_EXT_CONFIG); in dwmac4_enable_sph() local
503 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_enable_tbs() local
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| /drivers/media/platform/allegro-dvt/ |
| D | nal-rbsp.c | 99 static inline int rbsp_write_bit(struct rbsp *rbsp, bool value) in rbsp_write_bit()
127 static inline int rbsp_read_bits(struct rbsp *rbsp, int n, unsigned int *value) in rbsp_read_bits()
149 static int rbsp_write_bits(struct rbsp *rbsp, int n, unsigned int value) in rbsp_write_bits()
165 static int rbsp_read_uev(struct rbsp *rbsp, unsigned int *value) in rbsp_read_uev()
188 static int rbsp_write_uev(struct rbsp *rbsp, unsigned int *value) in rbsp_write_uev()
205 static int rbsp_read_sev(struct rbsp *rbsp, int *value) in rbsp_read_sev()
224 static int rbsp_write_sev(struct rbsp *rbsp, int *value) in rbsp_write_sev()
239 static int __rbsp_write_bit(struct rbsp *rbsp, int *value) in __rbsp_write_bit()
244 static int __rbsp_write_bits(struct rbsp *rbsp, int n, unsigned int *value) in __rbsp_write_bits()
256 static int __rbsp_read_bit(struct rbsp *rbsp, int *value) in __rbsp_read_bit()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_opp_csc_v.c | 127 uint32_t value = 0; in program_color_matrix_v() local
145 uint32_t value = 0; in program_color_matrix_v() local
163 uint32_t value = 0; in program_color_matrix_v() local
181 uint32_t value = 0; in program_color_matrix_v() local
199 uint32_t value = 0; in program_color_matrix_v() local
217 uint32_t value = 0; in program_color_matrix_v() local
241 uint32_t value = 0; in program_color_matrix_v() local
259 uint32_t value = 0; in program_color_matrix_v() local
277 uint32_t value = 0; in program_color_matrix_v() local
295 uint32_t value = 0; in program_color_matrix_v() local
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| D | dce110_timing_generator.c | 95 uint32_t value = 0; in dce110_timing_generator_is_in_vertical_blank() local
128 uint32_t value = 0; in dce110_timing_generator_enable_crtc() local
157 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_program_blank_color() local
516 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_get_vblank_counter() local
536 uint32_t value; in dce110_timing_generator_get_position() local
579 uint32_t value = dm_read_reg(tg->ctx, in dce110_timing_generator_get_crtc_scanoutpos() local
614 uint32_t value = 0; in dce110_timing_generator_program_blanking() local
712 uint32_t value; in dce110_timing_generator_set_test_pattern() local
1221 uint32_t value; in dce110_timing_generator_setup_global_swap_lock() local
1322 uint32_t value; in dce110_timing_generator_tear_down_global_swap_lock() local
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| D | dce110_timing_generator_v.c | 59 uint32_t value; in dce110_timing_generator_v_enable_crtc() local
82 uint32_t value; in dce110_timing_generator_v_disable_crtc() local
102 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_blank_crtc() local
122 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_unblank_crtc() local
143 uint32_t value = 0; in dce110_timing_generator_v_is_in_vertical_blank() local
154 uint32_t value; in dce110_timing_generator_v_is_counter_moving() local
254 uint32_t value = 0; in dce110_timing_generator_v_program_blanking() local
389 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_enable_advanced_request() local
455 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_program_blank_color() local
482 uint32_t value = 0; in dce110_timing_generator_v_set_overscan_color_black() local
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| /drivers/dma/dw-edma/ |
| D | dw-edma-v0-core.c | 31 #define SET_32(dw, name, value) \ argument
37 #define SET_RW_32(dw, dir, name, value) \ argument
50 #define SET_BOTH_32(dw, name, value) \ argument
58 #define SET_64(dw, name, value) \ argument
64 #define SET_RW_64(dw, dir, name, value) \ argument
77 #define SET_BOTH_64(dw, name, value) \ argument
85 #define SET_COMPAT(dw, name, value) \ argument
88 #define SET_RW_COMPAT(dw, dir, name, value) \ argument
109 u32 value, void __iomem *addr) in writel_ch()
134 u32 value; in readl_ch() local
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| /drivers/usb/gadget/udc/ |
| D | fotg210-udc.c | 30 u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1); in fotg210_disable_fifo_int() local
41 u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1); in fotg210_enable_fifo_int() local
52 u32 value = ioread32(fotg210->reg + FOTG210_DCFESR); in fotg210_set_cxdone() local
176 u32 value; in fotg210_reset_tseq() local
256 u32 value; in fotg210_enable_dma() local
294 u32 value; in fotg210_wait_dma_done() local
386 u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR0); in fotg210_ep0_queue() local
447 u32 value; in fotg210_set_epnstall() local
468 u32 value; in fotg210_clear_epnstall() local
479 static int fotg210_set_halt_and_wedge(struct usb_ep *_ep, int value, int wedge) in fotg210_set_halt_and_wedge()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | soc15_common.h | 30 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \ argument
61 #define WREG32_SOC15(ip, inst, reg, value) \ argument
65 #define WREG32_SOC15_IP(ip, reg, value) \ argument
68 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \ argument
72 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \ argument
102 #define WREG32_RLC(reg, value) \ argument
105 #define WREG32_RLC_EX(prefix, reg, value) \ argument
130 #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \ argument
137 #define WREG32_RLC_NO_KIQ(reg, value, hwip) \ argument
143 #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \ argument
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| /drivers/gpu/drm/i915/gt/ |
| D | intel_mocs.c | 28 #define _LE_CACHEABILITY(value) ((value) << 0) argument
29 #define _LE_TGT_CACHE(value) ((value) << 2) argument
30 #define LE_LRUM(value) ((value) << 4) argument
31 #define LE_AOM(value) ((value) << 6) argument
32 #define LE_RSC(value) ((value) << 7) argument
33 #define LE_SCC(value) ((value) << 8) argument
34 #define LE_PFM(value) ((value) << 11) argument
35 #define LE_SCF(value) ((value) << 14) argument
36 #define LE_COS(value) ((value) << 15) argument
37 #define LE_SSE(value) ((value) << 17) argument
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| /drivers/misc/habanalabs/goya/ |
| D | goya_hwmgr.c | 37 long value; in goya_get_clk_rate() local
70 long value; in mme_clk_show() local
89 long value; in mme_clk_store() local
119 long value; in tpc_clk_show() local
138 long value; in tpc_clk_store() local
168 long value; in ic_clk_show() local
187 long value; in ic_clk_store() local
217 long value; in mme_clk_curr_show() local
234 long value; in tpc_clk_curr_show() local
251 long value; in ic_clk_curr_show() local
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| /drivers/crypto/qat/qat_common/ |
| D | adf_gen4_hw_data.c | 17 u32 value) in write_csr_ring_head()
28 u32 value) in write_csr_ring_tail()
39 u32 value) in write_csr_ring_config()
51 u32 value) in write_csr_int_flag()
61 static void write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank, u32 value) in write_csr_int_col_en()
67 u32 value) in write_csr_int_col_ctl()
73 u32 value) in write_csr_int_flag_and_col()
79 u32 value) in write_csr_ring_srv_arb_en()
103 static inline void adf_gen4_unpack_ssm_wdtimer(u64 value, u32 *upper, in adf_gen4_unpack_ssm_wdtimer()
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| D | adf_gen2_hw_data.h | 37 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
40 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
51 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \ argument
54 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \ argument
57 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \ argument
67 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \ argument
70 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \ argument
74 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \ argument
87 #define WRITE_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index, value) \ argument
93 #define WRITE_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index, value) \ argument
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| /drivers/xen/xen-pciback/ |
| D | conf_space_header.c | 26 #define is_enable_cmd(value) ((value)&(PCI_COMMAND_MEMORY|PCI_COMMAND_IO)) argument
27 #define is_master_cmd(value) ((value)&PCI_COMMAND_MASTER) argument
51 static int command_read(struct pci_dev *dev, int offset, u16 *value, void *data) in command_read()
62 static int command_write(struct pci_dev *dev, int offset, u16 value, void *data) in command_write()
127 static int rom_write(struct pci_dev *dev, int offset, u32 value, void *data) in rom_write()
160 static int bar_write(struct pci_dev *dev, int offset, u32 value, void *data) in bar_write()
196 static int bar_read(struct pci_dev *dev, int offset, u32 * value, void *data) in bar_read()
256 u16 *value, void *data) in xen_pcibk_read_vendor()
264 u16 *value, void *data) in xen_pcibk_read_device()
271 static int interrupt_read(struct pci_dev *dev, int offset, u8 * value, in interrupt_read()
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| /drivers/rtc/ |
| D | rtc-pcf8523.c | 57 u8 value = 0; in pcf8523_read() local
79 static int pcf8523_write(struct i2c_client *client, u8 reg, u8 value) in pcf8523_write()
99 u8 value; in pcf8523_voltage_low() local
112 u8 value; in pcf8523_load_capacitance() local
143 u8 value; in pcf8523_set_pm() local
162 u8 value; in pcf8523_irq() local
182 u8 value; in pcf8523_stop_rtc() local
200 u8 value; in pcf8523_start_rtc() local
304 u8 value; in pcf8523_rtc_read_alarm() local
343 u8 value; in pcf8523_irq_enable() local
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