1 /*
2 * Copyright (C) 2015 Red Hat, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_damage_helper.h>
28 #include <drm/drm_fourcc.h>
29 #include <drm/drm_plane_helper.h>
30
31 #include "virtgpu_drv.h"
32
33 static const uint32_t virtio_gpu_formats[] = {
34 DRM_FORMAT_XRGB8888,
35 DRM_FORMAT_ARGB8888,
36 DRM_FORMAT_BGRX8888,
37 DRM_FORMAT_BGRA8888,
38 DRM_FORMAT_RGBX8888,
39 DRM_FORMAT_RGBA8888,
40 DRM_FORMAT_XBGR8888,
41 DRM_FORMAT_ABGR8888,
42 };
43
44 static const uint32_t virtio_gpu_cursor_formats[] = {
45 DRM_FORMAT_HOST_ARGB8888,
46 };
47
virtio_gpu_translate_format(uint32_t drm_fourcc)48 uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc)
49 {
50 uint32_t format;
51
52 switch (drm_fourcc) {
53 #ifdef __BIG_ENDIAN
54 case DRM_FORMAT_XRGB8888:
55 format = VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM;
56 break;
57 case DRM_FORMAT_ARGB8888:
58 format = VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM;
59 break;
60 case DRM_FORMAT_BGRX8888:
61 format = VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM;
62 break;
63 case DRM_FORMAT_BGRA8888:
64 format = VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM;
65 break;
66 case DRM_FORMAT_RGBX8888:
67 format = VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM;
68 break;
69 case DRM_FORMAT_RGBA8888:
70 format = VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM;
71 break;
72 case DRM_FORMAT_XBGR8888:
73 format = VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM;
74 break;
75 case DRM_FORMAT_ABGR8888:
76 format = VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM;
77 break;
78 #else
79 case DRM_FORMAT_XRGB8888:
80 format = VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM;
81 break;
82 case DRM_FORMAT_ARGB8888:
83 format = VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM;
84 break;
85 case DRM_FORMAT_BGRX8888:
86 format = VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM;
87 break;
88 case DRM_FORMAT_BGRA8888:
89 format = VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM;
90 break;
91 case DRM_FORMAT_RGBX8888:
92 format = VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM;
93 break;
94 case DRM_FORMAT_RGBA8888:
95 format = VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM;
96 break;
97 case DRM_FORMAT_XBGR8888:
98 format = VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM;
99 break;
100 case DRM_FORMAT_ABGR8888:
101 format = VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM;
102 break;
103 #endif
104 default:
105 /*
106 * This should not happen, we handle everything listed
107 * in virtio_gpu_formats[].
108 */
109 format = 0;
110 break;
111 }
112 WARN_ON(format == 0);
113 return format;
114 }
115
virtio_gpu_plane_destroy(struct drm_plane * plane)116 static void virtio_gpu_plane_destroy(struct drm_plane *plane)
117 {
118 drm_plane_cleanup(plane);
119 kfree(plane);
120 }
121
122 static const struct drm_plane_funcs virtio_gpu_plane_funcs = {
123 .update_plane = drm_atomic_helper_update_plane,
124 .disable_plane = drm_atomic_helper_disable_plane,
125 .destroy = virtio_gpu_plane_destroy,
126 .reset = drm_atomic_helper_plane_reset,
127 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
128 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
129 };
130
virtio_gpu_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)131 static int virtio_gpu_plane_atomic_check(struct drm_plane *plane,
132 struct drm_atomic_state *state)
133 {
134 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
135 plane);
136 bool is_cursor = plane->type == DRM_PLANE_TYPE_CURSOR;
137 struct drm_crtc_state *crtc_state;
138 int ret;
139
140 if (!new_plane_state->fb || WARN_ON(!new_plane_state->crtc))
141 return 0;
142
143 crtc_state = drm_atomic_get_crtc_state(state,
144 new_plane_state->crtc);
145 if (IS_ERR(crtc_state))
146 return PTR_ERR(crtc_state);
147
148 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
149 DRM_PLANE_HELPER_NO_SCALING,
150 DRM_PLANE_HELPER_NO_SCALING,
151 is_cursor, true);
152 return ret;
153 }
154
virtio_gpu_update_dumb_bo(struct virtio_gpu_device * vgdev,struct drm_plane_state * state,struct drm_rect * rect)155 static void virtio_gpu_update_dumb_bo(struct virtio_gpu_device *vgdev,
156 struct drm_plane_state *state,
157 struct drm_rect *rect)
158 {
159 struct virtio_gpu_object *bo =
160 gem_to_virtio_gpu_obj(state->fb->obj[0]);
161 struct virtio_gpu_object_array *objs;
162 uint32_t w = rect->x2 - rect->x1;
163 uint32_t h = rect->y2 - rect->y1;
164 uint32_t x = rect->x1;
165 uint32_t y = rect->y1;
166 uint32_t off = x * state->fb->format->cpp[0] +
167 y * state->fb->pitches[0];
168
169 objs = virtio_gpu_array_alloc(1);
170 if (!objs)
171 return;
172 virtio_gpu_array_add_obj(objs, &bo->base.base);
173
174 virtio_gpu_cmd_transfer_to_host_2d(vgdev, off, w, h, x, y,
175 objs, NULL);
176 }
177
virtio_gpu_resource_flush(struct drm_plane * plane,uint32_t x,uint32_t y,uint32_t width,uint32_t height)178 static void virtio_gpu_resource_flush(struct drm_plane *plane,
179 uint32_t x, uint32_t y,
180 uint32_t width, uint32_t height)
181 {
182 struct drm_device *dev = plane->dev;
183 struct virtio_gpu_device *vgdev = dev->dev_private;
184 struct virtio_gpu_framebuffer *vgfb;
185 struct virtio_gpu_object *bo;
186
187 vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
188 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
189 if (vgfb->fence) {
190 struct virtio_gpu_object_array *objs;
191
192 objs = virtio_gpu_array_alloc(1);
193 if (!objs)
194 return;
195 virtio_gpu_array_add_obj(objs, vgfb->base.obj[0]);
196 virtio_gpu_array_lock_resv(objs);
197 virtio_gpu_cmd_resource_flush(vgdev, bo->hw_res_handle, x, y,
198 width, height, objs, vgfb->fence);
199 virtio_gpu_notify(vgdev);
200
201 dma_fence_wait_timeout(&vgfb->fence->f, true,
202 msecs_to_jiffies(50));
203 dma_fence_put(&vgfb->fence->f);
204 vgfb->fence = NULL;
205 } else {
206 virtio_gpu_cmd_resource_flush(vgdev, bo->hw_res_handle, x, y,
207 width, height, NULL, NULL);
208 virtio_gpu_notify(vgdev);
209 }
210 }
211
virtio_gpu_primary_plane_update(struct drm_plane * plane,struct drm_atomic_state * state)212 static void virtio_gpu_primary_plane_update(struct drm_plane *plane,
213 struct drm_atomic_state *state)
214 {
215 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
216 plane);
217 struct drm_device *dev = plane->dev;
218 struct virtio_gpu_device *vgdev = dev->dev_private;
219 struct virtio_gpu_output *output = NULL;
220 struct virtio_gpu_object *bo;
221 struct drm_rect rect;
222
223 if (plane->state->crtc)
224 output = drm_crtc_to_virtio_gpu_output(plane->state->crtc);
225 if (old_state->crtc)
226 output = drm_crtc_to_virtio_gpu_output(old_state->crtc);
227 if (WARN_ON(!output))
228 return;
229
230 if (!plane->state->fb || !output->crtc.state->active) {
231 DRM_DEBUG("nofb\n");
232 virtio_gpu_cmd_set_scanout(vgdev, output->index, 0,
233 plane->state->src_w >> 16,
234 plane->state->src_h >> 16,
235 0, 0);
236 virtio_gpu_notify(vgdev);
237 return;
238 }
239
240 if (!drm_atomic_helper_damage_merged(old_state, plane->state, &rect))
241 return;
242
243 bo = gem_to_virtio_gpu_obj(plane->state->fb->obj[0]);
244 if (bo->dumb)
245 virtio_gpu_update_dumb_bo(vgdev, plane->state, &rect);
246
247 if (plane->state->fb != old_state->fb ||
248 plane->state->src_w != old_state->src_w ||
249 plane->state->src_h != old_state->src_h ||
250 plane->state->src_x != old_state->src_x ||
251 plane->state->src_y != old_state->src_y ||
252 output->needs_modeset) {
253 output->needs_modeset = false;
254 DRM_DEBUG("handle 0x%x, crtc %dx%d+%d+%d, src %dx%d+%d+%d\n",
255 bo->hw_res_handle,
256 plane->state->crtc_w, plane->state->crtc_h,
257 plane->state->crtc_x, plane->state->crtc_y,
258 plane->state->src_w >> 16,
259 plane->state->src_h >> 16,
260 plane->state->src_x >> 16,
261 plane->state->src_y >> 16);
262
263 if (bo->host3d_blob || bo->guest_blob) {
264 virtio_gpu_cmd_set_scanout_blob
265 (vgdev, output->index, bo,
266 plane->state->fb,
267 plane->state->src_w >> 16,
268 plane->state->src_h >> 16,
269 plane->state->src_x >> 16,
270 plane->state->src_y >> 16);
271 } else {
272 virtio_gpu_cmd_set_scanout(vgdev, output->index,
273 bo->hw_res_handle,
274 plane->state->src_w >> 16,
275 plane->state->src_h >> 16,
276 plane->state->src_x >> 16,
277 plane->state->src_y >> 16);
278 }
279 }
280
281 virtio_gpu_resource_flush(plane,
282 rect.x1,
283 rect.y1,
284 rect.x2 - rect.x1,
285 rect.y2 - rect.y1);
286 }
287
virtio_gpu_plane_prepare_fb(struct drm_plane * plane,struct drm_plane_state * new_state)288 static int virtio_gpu_plane_prepare_fb(struct drm_plane *plane,
289 struct drm_plane_state *new_state)
290 {
291 struct drm_device *dev = plane->dev;
292 struct virtio_gpu_device *vgdev = dev->dev_private;
293 struct virtio_gpu_framebuffer *vgfb;
294 struct virtio_gpu_object *bo;
295
296 if (!new_state->fb)
297 return 0;
298
299 vgfb = to_virtio_gpu_framebuffer(new_state->fb);
300 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
301 if (!bo || (plane->type == DRM_PLANE_TYPE_PRIMARY && !bo->guest_blob))
302 return 0;
303
304 if (bo->dumb && (plane->state->fb != new_state->fb)) {
305 vgfb->fence = virtio_gpu_fence_alloc(vgdev);
306 if (!vgfb->fence)
307 return -ENOMEM;
308 }
309
310 return 0;
311 }
312
virtio_gpu_plane_cleanup_fb(struct drm_plane * plane,struct drm_plane_state * state)313 static void virtio_gpu_plane_cleanup_fb(struct drm_plane *plane,
314 struct drm_plane_state *state)
315 {
316 struct virtio_gpu_framebuffer *vgfb;
317
318 if (!state->fb)
319 return;
320
321 vgfb = to_virtio_gpu_framebuffer(state->fb);
322 if (vgfb->fence) {
323 dma_fence_put(&vgfb->fence->f);
324 vgfb->fence = NULL;
325 }
326 }
327
virtio_gpu_cursor_plane_update(struct drm_plane * plane,struct drm_atomic_state * state)328 static void virtio_gpu_cursor_plane_update(struct drm_plane *plane,
329 struct drm_atomic_state *state)
330 {
331 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
332 plane);
333 struct drm_device *dev = plane->dev;
334 struct virtio_gpu_device *vgdev = dev->dev_private;
335 struct virtio_gpu_output *output = NULL;
336 struct virtio_gpu_framebuffer *vgfb;
337 struct virtio_gpu_object *bo = NULL;
338 uint32_t handle;
339
340 if (plane->state->crtc)
341 output = drm_crtc_to_virtio_gpu_output(plane->state->crtc);
342 if (old_state->crtc)
343 output = drm_crtc_to_virtio_gpu_output(old_state->crtc);
344 if (WARN_ON(!output))
345 return;
346
347 if (plane->state->fb) {
348 vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
349 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]);
350 handle = bo->hw_res_handle;
351 } else {
352 handle = 0;
353 }
354
355 if (bo && bo->dumb && (plane->state->fb != old_state->fb)) {
356 /* new cursor -- update & wait */
357 struct virtio_gpu_object_array *objs;
358
359 objs = virtio_gpu_array_alloc(1);
360 if (!objs)
361 return;
362 virtio_gpu_array_add_obj(objs, vgfb->base.obj[0]);
363 virtio_gpu_array_lock_resv(objs);
364 virtio_gpu_cmd_transfer_to_host_2d
365 (vgdev, 0,
366 plane->state->crtc_w,
367 plane->state->crtc_h,
368 0, 0, objs, vgfb->fence);
369 virtio_gpu_notify(vgdev);
370 dma_fence_wait(&vgfb->fence->f, true);
371 dma_fence_put(&vgfb->fence->f);
372 vgfb->fence = NULL;
373 }
374
375 if (plane->state->fb != old_state->fb) {
376 DRM_DEBUG("update, handle %d, pos +%d+%d, hot %d,%d\n", handle,
377 plane->state->crtc_x,
378 plane->state->crtc_y,
379 plane->state->fb ? plane->state->fb->hot_x : 0,
380 plane->state->fb ? plane->state->fb->hot_y : 0);
381 output->cursor.hdr.type =
382 cpu_to_le32(VIRTIO_GPU_CMD_UPDATE_CURSOR);
383 output->cursor.resource_id = cpu_to_le32(handle);
384 if (plane->state->fb) {
385 output->cursor.hot_x =
386 cpu_to_le32(plane->state->fb->hot_x);
387 output->cursor.hot_y =
388 cpu_to_le32(plane->state->fb->hot_y);
389 } else {
390 output->cursor.hot_x = cpu_to_le32(0);
391 output->cursor.hot_y = cpu_to_le32(0);
392 }
393 } else {
394 DRM_DEBUG("move +%d+%d\n",
395 plane->state->crtc_x,
396 plane->state->crtc_y);
397 output->cursor.hdr.type =
398 cpu_to_le32(VIRTIO_GPU_CMD_MOVE_CURSOR);
399 }
400 output->cursor.pos.x = cpu_to_le32(plane->state->crtc_x);
401 output->cursor.pos.y = cpu_to_le32(plane->state->crtc_y);
402 virtio_gpu_cursor_ping(vgdev, output);
403 }
404
405 static const struct drm_plane_helper_funcs virtio_gpu_primary_helper_funcs = {
406 .prepare_fb = virtio_gpu_plane_prepare_fb,
407 .cleanup_fb = virtio_gpu_plane_cleanup_fb,
408 .atomic_check = virtio_gpu_plane_atomic_check,
409 .atomic_update = virtio_gpu_primary_plane_update,
410 };
411
412 static const struct drm_plane_helper_funcs virtio_gpu_cursor_helper_funcs = {
413 .prepare_fb = virtio_gpu_plane_prepare_fb,
414 .cleanup_fb = virtio_gpu_plane_cleanup_fb,
415 .atomic_check = virtio_gpu_plane_atomic_check,
416 .atomic_update = virtio_gpu_cursor_plane_update,
417 };
418
virtio_gpu_plane_init(struct virtio_gpu_device * vgdev,enum drm_plane_type type,int index)419 struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,
420 enum drm_plane_type type,
421 int index)
422 {
423 struct drm_device *dev = vgdev->ddev;
424 const struct drm_plane_helper_funcs *funcs;
425 struct drm_plane *plane;
426 const uint32_t *formats;
427 int ret, nformats;
428
429 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
430 if (!plane)
431 return ERR_PTR(-ENOMEM);
432
433 if (type == DRM_PLANE_TYPE_CURSOR) {
434 formats = virtio_gpu_cursor_formats;
435 nformats = ARRAY_SIZE(virtio_gpu_cursor_formats);
436 funcs = &virtio_gpu_cursor_helper_funcs;
437 } else {
438 formats = virtio_gpu_formats;
439 nformats = ARRAY_SIZE(virtio_gpu_formats);
440 funcs = &virtio_gpu_primary_helper_funcs;
441 }
442 ret = drm_universal_plane_init(dev, plane, 1 << index,
443 &virtio_gpu_plane_funcs,
444 formats, nformats,
445 NULL, type, NULL);
446 if (ret)
447 goto err_plane_init;
448
449 drm_plane_helper_add(plane, funcs);
450 return plane;
451
452 err_plane_init:
453 kfree(plane);
454 return ERR_PTR(ret);
455 }
456