1 /*
2 * Linux driver for VMware's vmxnet3 ethernet NIC.
3 *
4 * Copyright (C) 2008-2021, VMware, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 *
23 * Maintained by: pv-drivers@vmware.com
24 *
25 */
26
27 #include <linux/module.h>
28 #include <net/ip6_checksum.h>
29
30 #include "vmxnet3_int.h"
31
32 char vmxnet3_driver_name[] = "vmxnet3";
33 #define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
34
35 /*
36 * PCI Device ID Table
37 * Last entry must be all 0s
38 */
39 static const struct pci_device_id vmxnet3_pciid_table[] = {
40 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
41 {0}
42 };
43
44 MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
45
46 static int enable_mq = 1;
47
48 static void
49 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac);
50
51 /*
52 * Enable/Disable the given intr
53 */
54 static void
vmxnet3_enable_intr(struct vmxnet3_adapter * adapter,unsigned intr_idx)55 vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
56 {
57 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0);
58 }
59
60
61 static void
vmxnet3_disable_intr(struct vmxnet3_adapter * adapter,unsigned intr_idx)62 vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
63 {
64 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1);
65 }
66
67
68 /*
69 * Enable/Disable all intrs used by the device
70 */
71 static void
vmxnet3_enable_all_intrs(struct vmxnet3_adapter * adapter)72 vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter)
73 {
74 int i;
75
76 for (i = 0; i < adapter->intr.num_intrs; i++)
77 vmxnet3_enable_intr(adapter, i);
78 if (!VMXNET3_VERSION_GE_6(adapter) ||
79 !adapter->queuesExtEnabled) {
80 adapter->shared->devRead.intrConf.intrCtrl &=
81 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
82 } else {
83 adapter->shared->devReadExt.intrConfExt.intrCtrl &=
84 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
85 }
86 }
87
88
89 static void
vmxnet3_disable_all_intrs(struct vmxnet3_adapter * adapter)90 vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter)
91 {
92 int i;
93
94 if (!VMXNET3_VERSION_GE_6(adapter) ||
95 !adapter->queuesExtEnabled) {
96 adapter->shared->devRead.intrConf.intrCtrl |=
97 cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
98 } else {
99 adapter->shared->devReadExt.intrConfExt.intrCtrl |=
100 cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
101 }
102 for (i = 0; i < adapter->intr.num_intrs; i++)
103 vmxnet3_disable_intr(adapter, i);
104 }
105
106
107 static void
vmxnet3_ack_events(struct vmxnet3_adapter * adapter,u32 events)108 vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
109 {
110 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events);
111 }
112
113
114 static bool
vmxnet3_tq_stopped(struct vmxnet3_tx_queue * tq,struct vmxnet3_adapter * adapter)115 vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
116 {
117 return tq->stopped;
118 }
119
120
121 static void
vmxnet3_tq_start(struct vmxnet3_tx_queue * tq,struct vmxnet3_adapter * adapter)122 vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
123 {
124 tq->stopped = false;
125 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
126 }
127
128
129 static void
vmxnet3_tq_wake(struct vmxnet3_tx_queue * tq,struct vmxnet3_adapter * adapter)130 vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
131 {
132 tq->stopped = false;
133 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
134 }
135
136
137 static void
vmxnet3_tq_stop(struct vmxnet3_tx_queue * tq,struct vmxnet3_adapter * adapter)138 vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
139 {
140 tq->stopped = true;
141 tq->num_stop++;
142 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
143 }
144
145
146 /*
147 * Check the link state. This may start or stop the tx queue.
148 */
149 static void
vmxnet3_check_link(struct vmxnet3_adapter * adapter,bool affectTxQueue)150 vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
151 {
152 u32 ret;
153 int i;
154 unsigned long flags;
155
156 spin_lock_irqsave(&adapter->cmd_lock, flags);
157 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
158 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
159 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
160
161 adapter->link_speed = ret >> 16;
162 if (ret & 1) { /* Link is up. */
163 netdev_info(adapter->netdev, "NIC Link is Up %d Mbps\n",
164 adapter->link_speed);
165 netif_carrier_on(adapter->netdev);
166
167 if (affectTxQueue) {
168 for (i = 0; i < adapter->num_tx_queues; i++)
169 vmxnet3_tq_start(&adapter->tx_queue[i],
170 adapter);
171 }
172 } else {
173 netdev_info(adapter->netdev, "NIC Link is Down\n");
174 netif_carrier_off(adapter->netdev);
175
176 if (affectTxQueue) {
177 for (i = 0; i < adapter->num_tx_queues; i++)
178 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
179 }
180 }
181 }
182
183 static void
vmxnet3_process_events(struct vmxnet3_adapter * adapter)184 vmxnet3_process_events(struct vmxnet3_adapter *adapter)
185 {
186 int i;
187 unsigned long flags;
188 u32 events = le32_to_cpu(adapter->shared->ecr);
189 if (!events)
190 return;
191
192 vmxnet3_ack_events(adapter, events);
193
194 /* Check if link state has changed */
195 if (events & VMXNET3_ECR_LINK)
196 vmxnet3_check_link(adapter, true);
197
198 /* Check if there is an error on xmit/recv queues */
199 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
200 spin_lock_irqsave(&adapter->cmd_lock, flags);
201 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
202 VMXNET3_CMD_GET_QUEUE_STATUS);
203 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
204
205 for (i = 0; i < adapter->num_tx_queues; i++)
206 if (adapter->tqd_start[i].status.stopped)
207 dev_err(&adapter->netdev->dev,
208 "%s: tq[%d] error 0x%x\n",
209 adapter->netdev->name, i, le32_to_cpu(
210 adapter->tqd_start[i].status.error));
211 for (i = 0; i < adapter->num_rx_queues; i++)
212 if (adapter->rqd_start[i].status.stopped)
213 dev_err(&adapter->netdev->dev,
214 "%s: rq[%d] error 0x%x\n",
215 adapter->netdev->name, i,
216 adapter->rqd_start[i].status.error);
217
218 schedule_work(&adapter->work);
219 }
220 }
221
222 #ifdef __BIG_ENDIAN_BITFIELD
223 /*
224 * The device expects the bitfields in shared structures to be written in
225 * little endian. When CPU is big endian, the following routines are used to
226 * correctly read and write into ABI.
227 * The general technique used here is : double word bitfields are defined in
228 * opposite order for big endian architecture. Then before reading them in
229 * driver the complete double word is translated using le32_to_cpu. Similarly
230 * After the driver writes into bitfields, cpu_to_le32 is used to translate the
231 * double words into required format.
232 * In order to avoid touching bits in shared structure more than once, temporary
233 * descriptors are used. These are passed as srcDesc to following functions.
234 */
vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc * srcDesc,struct Vmxnet3_RxDesc * dstDesc)235 static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
236 struct Vmxnet3_RxDesc *dstDesc)
237 {
238 u32 *src = (u32 *)srcDesc + 2;
239 u32 *dst = (u32 *)dstDesc + 2;
240 dstDesc->addr = le64_to_cpu(srcDesc->addr);
241 *dst = le32_to_cpu(*src);
242 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
243 }
244
vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc * srcDesc,struct Vmxnet3_TxDesc * dstDesc)245 static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
246 struct Vmxnet3_TxDesc *dstDesc)
247 {
248 int i;
249 u32 *src = (u32 *)(srcDesc + 1);
250 u32 *dst = (u32 *)(dstDesc + 1);
251
252 /* Working backwards so that the gen bit is set at the end. */
253 for (i = 2; i > 0; i--) {
254 src--;
255 dst--;
256 *dst = cpu_to_le32(*src);
257 }
258 }
259
260
vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc * srcDesc,struct Vmxnet3_RxCompDesc * dstDesc)261 static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
262 struct Vmxnet3_RxCompDesc *dstDesc)
263 {
264 int i = 0;
265 u32 *src = (u32 *)srcDesc;
266 u32 *dst = (u32 *)dstDesc;
267 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
268 *dst = le32_to_cpu(*src);
269 src++;
270 dst++;
271 }
272 }
273
274
275 /* Used to read bitfield values from double words. */
get_bitfield32(const __le32 * bitfield,u32 pos,u32 size)276 static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
277 {
278 u32 temp = le32_to_cpu(*bitfield);
279 u32 mask = ((1 << size) - 1) << pos;
280 temp &= mask;
281 temp >>= pos;
282 return temp;
283 }
284
285
286
287 #endif /* __BIG_ENDIAN_BITFIELD */
288
289 #ifdef __BIG_ENDIAN_BITFIELD
290
291 # define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
292 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
293 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
294 # define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
295 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
296 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
297 # define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
298 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
299 VMXNET3_TCD_GEN_SIZE)
300 # define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
301 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
302 # define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
303 (dstrcd) = (tmp); \
304 vmxnet3_RxCompToCPU((rcd), (tmp)); \
305 } while (0)
306 # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
307 (dstrxd) = (tmp); \
308 vmxnet3_RxDescToCPU((rxd), (tmp)); \
309 } while (0)
310
311 #else
312
313 # define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
314 # define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
315 # define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
316 # define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
317 # define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
318 # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
319
320 #endif /* __BIG_ENDIAN_BITFIELD */
321
322
323 static void
vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info * tbi,struct pci_dev * pdev)324 vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
325 struct pci_dev *pdev)
326 {
327 if (tbi->map_type == VMXNET3_MAP_SINGLE)
328 dma_unmap_single(&pdev->dev, tbi->dma_addr, tbi->len,
329 DMA_TO_DEVICE);
330 else if (tbi->map_type == VMXNET3_MAP_PAGE)
331 dma_unmap_page(&pdev->dev, tbi->dma_addr, tbi->len,
332 DMA_TO_DEVICE);
333 else
334 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE);
335
336 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */
337 }
338
339
340 static int
vmxnet3_unmap_pkt(u32 eop_idx,struct vmxnet3_tx_queue * tq,struct pci_dev * pdev,struct vmxnet3_adapter * adapter)341 vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
342 struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
343 {
344 struct sk_buff *skb;
345 int entries = 0;
346
347 /* no out of order completion */
348 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
349 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
350
351 skb = tq->buf_info[eop_idx].skb;
352 BUG_ON(skb == NULL);
353 tq->buf_info[eop_idx].skb = NULL;
354
355 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
356
357 while (tq->tx_ring.next2comp != eop_idx) {
358 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp,
359 pdev);
360
361 /* update next2comp w/o tx_lock. Since we are marking more,
362 * instead of less, tx ring entries avail, the worst case is
363 * that the tx routine incorrectly re-queues a pkt due to
364 * insufficient tx ring entries.
365 */
366 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
367 entries++;
368 }
369
370 dev_kfree_skb_any(skb);
371 return entries;
372 }
373
374
375 static int
vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue * tq,struct vmxnet3_adapter * adapter)376 vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
377 struct vmxnet3_adapter *adapter)
378 {
379 int completed = 0;
380 union Vmxnet3_GenericDesc *gdesc;
381
382 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
383 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
384 /* Prevent any &gdesc->tcd field from being (speculatively)
385 * read before (&gdesc->tcd)->gen is read.
386 */
387 dma_rmb();
388
389 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
390 &gdesc->tcd), tq, adapter->pdev,
391 adapter);
392
393 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
394 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
395 }
396
397 if (completed) {
398 spin_lock(&tq->tx_lock);
399 if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&
400 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) >
401 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) &&
402 netif_carrier_ok(adapter->netdev))) {
403 vmxnet3_tq_wake(tq, adapter);
404 }
405 spin_unlock(&tq->tx_lock);
406 }
407 return completed;
408 }
409
410
411 static void
vmxnet3_tq_cleanup(struct vmxnet3_tx_queue * tq,struct vmxnet3_adapter * adapter)412 vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
413 struct vmxnet3_adapter *adapter)
414 {
415 int i;
416
417 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) {
418 struct vmxnet3_tx_buf_info *tbi;
419
420 tbi = tq->buf_info + tq->tx_ring.next2comp;
421
422 vmxnet3_unmap_tx_buf(tbi, adapter->pdev);
423 if (tbi->skb) {
424 dev_kfree_skb_any(tbi->skb);
425 tbi->skb = NULL;
426 }
427 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
428 }
429
430 /* sanity check, verify all buffers are indeed unmapped and freed */
431 for (i = 0; i < tq->tx_ring.size; i++) {
432 BUG_ON(tq->buf_info[i].skb != NULL ||
433 tq->buf_info[i].map_type != VMXNET3_MAP_NONE);
434 }
435
436 tq->tx_ring.gen = VMXNET3_INIT_GEN;
437 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
438
439 tq->comp_ring.gen = VMXNET3_INIT_GEN;
440 tq->comp_ring.next2proc = 0;
441 }
442
443
444 static void
vmxnet3_tq_destroy(struct vmxnet3_tx_queue * tq,struct vmxnet3_adapter * adapter)445 vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
446 struct vmxnet3_adapter *adapter)
447 {
448 if (tq->tx_ring.base) {
449 dma_free_coherent(&adapter->pdev->dev, tq->tx_ring.size *
450 sizeof(struct Vmxnet3_TxDesc),
451 tq->tx_ring.base, tq->tx_ring.basePA);
452 tq->tx_ring.base = NULL;
453 }
454 if (tq->data_ring.base) {
455 dma_free_coherent(&adapter->pdev->dev,
456 tq->data_ring.size * tq->txdata_desc_size,
457 tq->data_ring.base, tq->data_ring.basePA);
458 tq->data_ring.base = NULL;
459 }
460 if (tq->comp_ring.base) {
461 dma_free_coherent(&adapter->pdev->dev, tq->comp_ring.size *
462 sizeof(struct Vmxnet3_TxCompDesc),
463 tq->comp_ring.base, tq->comp_ring.basePA);
464 tq->comp_ring.base = NULL;
465 }
466 kfree(tq->buf_info);
467 tq->buf_info = NULL;
468 }
469
470
471 /* Destroy all tx queues */
472 void
vmxnet3_tq_destroy_all(struct vmxnet3_adapter * adapter)473 vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
474 {
475 int i;
476
477 for (i = 0; i < adapter->num_tx_queues; i++)
478 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
479 }
480
481
482 static void
vmxnet3_tq_init(struct vmxnet3_tx_queue * tq,struct vmxnet3_adapter * adapter)483 vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
484 struct vmxnet3_adapter *adapter)
485 {
486 int i;
487
488 /* reset the tx ring contents to 0 and reset the tx ring states */
489 memset(tq->tx_ring.base, 0, tq->tx_ring.size *
490 sizeof(struct Vmxnet3_TxDesc));
491 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
492 tq->tx_ring.gen = VMXNET3_INIT_GEN;
493
494 memset(tq->data_ring.base, 0,
495 tq->data_ring.size * tq->txdata_desc_size);
496
497 /* reset the tx comp ring contents to 0 and reset comp ring states */
498 memset(tq->comp_ring.base, 0, tq->comp_ring.size *
499 sizeof(struct Vmxnet3_TxCompDesc));
500 tq->comp_ring.next2proc = 0;
501 tq->comp_ring.gen = VMXNET3_INIT_GEN;
502
503 /* reset the bookkeeping data */
504 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size);
505 for (i = 0; i < tq->tx_ring.size; i++)
506 tq->buf_info[i].map_type = VMXNET3_MAP_NONE;
507
508 /* stats are not reset */
509 }
510
511
512 static int
vmxnet3_tq_create(struct vmxnet3_tx_queue * tq,struct vmxnet3_adapter * adapter)513 vmxnet3_tq_create(struct vmxnet3_tx_queue *tq,
514 struct vmxnet3_adapter *adapter)
515 {
516 BUG_ON(tq->tx_ring.base || tq->data_ring.base ||
517 tq->comp_ring.base || tq->buf_info);
518
519 tq->tx_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
520 tq->tx_ring.size * sizeof(struct Vmxnet3_TxDesc),
521 &tq->tx_ring.basePA, GFP_KERNEL);
522 if (!tq->tx_ring.base) {
523 netdev_err(adapter->netdev, "failed to allocate tx ring\n");
524 goto err;
525 }
526
527 tq->data_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
528 tq->data_ring.size * tq->txdata_desc_size,
529 &tq->data_ring.basePA, GFP_KERNEL);
530 if (!tq->data_ring.base) {
531 netdev_err(adapter->netdev, "failed to allocate tx data ring\n");
532 goto err;
533 }
534
535 tq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
536 tq->comp_ring.size * sizeof(struct Vmxnet3_TxCompDesc),
537 &tq->comp_ring.basePA, GFP_KERNEL);
538 if (!tq->comp_ring.base) {
539 netdev_err(adapter->netdev, "failed to allocate tx comp ring\n");
540 goto err;
541 }
542
543 tq->buf_info = kcalloc_node(tq->tx_ring.size, sizeof(tq->buf_info[0]),
544 GFP_KERNEL,
545 dev_to_node(&adapter->pdev->dev));
546 if (!tq->buf_info)
547 goto err;
548
549 return 0;
550
551 err:
552 vmxnet3_tq_destroy(tq, adapter);
553 return -ENOMEM;
554 }
555
556 static void
vmxnet3_tq_cleanup_all(struct vmxnet3_adapter * adapter)557 vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
558 {
559 int i;
560
561 for (i = 0; i < adapter->num_tx_queues; i++)
562 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
563 }
564
565 /*
566 * starting from ring->next2fill, allocate rx buffers for the given ring
567 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers
568 * are allocated or allocation fails
569 */
570
571 static int
vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue * rq,u32 ring_idx,int num_to_alloc,struct vmxnet3_adapter * adapter)572 vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx,
573 int num_to_alloc, struct vmxnet3_adapter *adapter)
574 {
575 int num_allocated = 0;
576 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx];
577 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx];
578 u32 val;
579
580 while (num_allocated <= num_to_alloc) {
581 struct vmxnet3_rx_buf_info *rbi;
582 union Vmxnet3_GenericDesc *gd;
583
584 rbi = rbi_base + ring->next2fill;
585 gd = ring->base + ring->next2fill;
586
587 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) {
588 if (rbi->skb == NULL) {
589 rbi->skb = __netdev_alloc_skb_ip_align(adapter->netdev,
590 rbi->len,
591 GFP_KERNEL);
592 if (unlikely(rbi->skb == NULL)) {
593 rq->stats.rx_buf_alloc_failure++;
594 break;
595 }
596
597 rbi->dma_addr = dma_map_single(
598 &adapter->pdev->dev,
599 rbi->skb->data, rbi->len,
600 DMA_FROM_DEVICE);
601 if (dma_mapping_error(&adapter->pdev->dev,
602 rbi->dma_addr)) {
603 dev_kfree_skb_any(rbi->skb);
604 rbi->skb = NULL;
605 rq->stats.rx_buf_alloc_failure++;
606 break;
607 }
608 } else {
609 /* rx buffer skipped by the device */
610 }
611 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
612 } else {
613 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE ||
614 rbi->len != PAGE_SIZE);
615
616 if (rbi->page == NULL) {
617 rbi->page = alloc_page(GFP_ATOMIC);
618 if (unlikely(rbi->page == NULL)) {
619 rq->stats.rx_buf_alloc_failure++;
620 break;
621 }
622 rbi->dma_addr = dma_map_page(
623 &adapter->pdev->dev,
624 rbi->page, 0, PAGE_SIZE,
625 DMA_FROM_DEVICE);
626 if (dma_mapping_error(&adapter->pdev->dev,
627 rbi->dma_addr)) {
628 put_page(rbi->page);
629 rbi->page = NULL;
630 rq->stats.rx_buf_alloc_failure++;
631 break;
632 }
633 } else {
634 /* rx buffers skipped by the device */
635 }
636 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
637 }
638
639 gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
640 gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT)
641 | val | rbi->len);
642
643 /* Fill the last buffer but dont mark it ready, or else the
644 * device will think that the queue is full */
645 if (num_allocated == num_to_alloc)
646 break;
647
648 gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT);
649 num_allocated++;
650 vmxnet3_cmd_ring_adv_next2fill(ring);
651 }
652
653 netdev_dbg(adapter->netdev,
654 "alloc_rx_buf: %d allocated, next2fill %u, next2comp %u\n",
655 num_allocated, ring->next2fill, ring->next2comp);
656
657 /* so that the device can distinguish a full ring and an empty ring */
658 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp);
659
660 return num_allocated;
661 }
662
663
664 static void
vmxnet3_append_frag(struct sk_buff * skb,struct Vmxnet3_RxCompDesc * rcd,struct vmxnet3_rx_buf_info * rbi)665 vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd,
666 struct vmxnet3_rx_buf_info *rbi)
667 {
668 skb_frag_t *frag = skb_shinfo(skb)->frags + skb_shinfo(skb)->nr_frags;
669
670 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS);
671
672 __skb_frag_set_page(frag, rbi->page);
673 skb_frag_off_set(frag, 0);
674 skb_frag_size_set(frag, rcd->len);
675 skb->data_len += rcd->len;
676 skb->truesize += PAGE_SIZE;
677 skb_shinfo(skb)->nr_frags++;
678 }
679
680
681 static int
vmxnet3_map_pkt(struct sk_buff * skb,struct vmxnet3_tx_ctx * ctx,struct vmxnet3_tx_queue * tq,struct pci_dev * pdev,struct vmxnet3_adapter * adapter)682 vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
683 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev,
684 struct vmxnet3_adapter *adapter)
685 {
686 u32 dw2, len;
687 unsigned long buf_offset;
688 int i;
689 union Vmxnet3_GenericDesc *gdesc;
690 struct vmxnet3_tx_buf_info *tbi = NULL;
691
692 BUG_ON(ctx->copy_size > skb_headlen(skb));
693
694 /* use the previous gen bit for the SOP desc */
695 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
696
697 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
698 gdesc = ctx->sop_txd; /* both loops below can be skipped */
699
700 /* no need to map the buffer if headers are copied */
701 if (ctx->copy_size) {
702 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
703 tq->tx_ring.next2fill *
704 tq->txdata_desc_size);
705 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
706 ctx->sop_txd->dword[3] = 0;
707
708 tbi = tq->buf_info + tq->tx_ring.next2fill;
709 tbi->map_type = VMXNET3_MAP_NONE;
710
711 netdev_dbg(adapter->netdev,
712 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
713 tq->tx_ring.next2fill,
714 le64_to_cpu(ctx->sop_txd->txd.addr),
715 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
716 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
717
718 /* use the right gen for non-SOP desc */
719 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
720 }
721
722 /* linear part can use multiple tx desc if it's big */
723 len = skb_headlen(skb) - ctx->copy_size;
724 buf_offset = ctx->copy_size;
725 while (len) {
726 u32 buf_size;
727
728 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
729 buf_size = len;
730 dw2 |= len;
731 } else {
732 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
733 /* spec says that for TxDesc.len, 0 == 2^14 */
734 }
735
736 tbi = tq->buf_info + tq->tx_ring.next2fill;
737 tbi->map_type = VMXNET3_MAP_SINGLE;
738 tbi->dma_addr = dma_map_single(&adapter->pdev->dev,
739 skb->data + buf_offset, buf_size,
740 DMA_TO_DEVICE);
741 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
742 return -EFAULT;
743
744 tbi->len = buf_size;
745
746 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
747 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
748
749 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
750 gdesc->dword[2] = cpu_to_le32(dw2);
751 gdesc->dword[3] = 0;
752
753 netdev_dbg(adapter->netdev,
754 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
755 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
756 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
757 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
758 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
759
760 len -= buf_size;
761 buf_offset += buf_size;
762 }
763
764 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
765 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
766 u32 buf_size;
767
768 buf_offset = 0;
769 len = skb_frag_size(frag);
770 while (len) {
771 tbi = tq->buf_info + tq->tx_ring.next2fill;
772 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
773 buf_size = len;
774 dw2 |= len;
775 } else {
776 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
777 /* spec says that for TxDesc.len, 0 == 2^14 */
778 }
779 tbi->map_type = VMXNET3_MAP_PAGE;
780 tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag,
781 buf_offset, buf_size,
782 DMA_TO_DEVICE);
783 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
784 return -EFAULT;
785
786 tbi->len = buf_size;
787
788 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
789 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
790
791 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
792 gdesc->dword[2] = cpu_to_le32(dw2);
793 gdesc->dword[3] = 0;
794
795 netdev_dbg(adapter->netdev,
796 "txd[%u]: 0x%llx %u %u\n",
797 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
798 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
799 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
800 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
801
802 len -= buf_size;
803 buf_offset += buf_size;
804 }
805 }
806
807 ctx->eop_txd = gdesc;
808
809 /* set the last buf_info for the pkt */
810 tbi->skb = skb;
811 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base;
812
813 return 0;
814 }
815
816
817 /* Init all tx queues */
818 static void
vmxnet3_tq_init_all(struct vmxnet3_adapter * adapter)819 vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
820 {
821 int i;
822
823 for (i = 0; i < adapter->num_tx_queues; i++)
824 vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
825 }
826
827
828 /*
829 * parse relevant protocol headers:
830 * For a tso pkt, relevant headers are L2/3/4 including options
831 * For a pkt requesting csum offloading, they are L2/3 and may include L4
832 * if it's a TCP/UDP pkt
833 *
834 * Returns:
835 * -1: error happens during parsing
836 * 0: protocol headers parsed, but too big to be copied
837 * 1: protocol headers parsed and copied
838 *
839 * Other effects:
840 * 1. related *ctx fields are updated.
841 * 2. ctx->copy_size is # of bytes copied
842 * 3. the portion to be copied is guaranteed to be in the linear part
843 *
844 */
845 static int
vmxnet3_parse_hdr(struct sk_buff * skb,struct vmxnet3_tx_queue * tq,struct vmxnet3_tx_ctx * ctx,struct vmxnet3_adapter * adapter)846 vmxnet3_parse_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
847 struct vmxnet3_tx_ctx *ctx,
848 struct vmxnet3_adapter *adapter)
849 {
850 u8 protocol = 0;
851
852 if (ctx->mss) { /* TSO */
853 if (VMXNET3_VERSION_GE_4(adapter) && skb->encapsulation) {
854 ctx->l4_offset = skb_inner_transport_offset(skb);
855 ctx->l4_hdr_size = inner_tcp_hdrlen(skb);
856 ctx->copy_size = ctx->l4_offset + ctx->l4_hdr_size;
857 } else {
858 ctx->l4_offset = skb_transport_offset(skb);
859 ctx->l4_hdr_size = tcp_hdrlen(skb);
860 ctx->copy_size = ctx->l4_offset + ctx->l4_hdr_size;
861 }
862 } else {
863 if (skb->ip_summed == CHECKSUM_PARTIAL) {
864 /* For encap packets, skb_checksum_start_offset refers
865 * to inner L4 offset. Thus, below works for encap as
866 * well as non-encap case
867 */
868 ctx->l4_offset = skb_checksum_start_offset(skb);
869
870 if (VMXNET3_VERSION_GE_4(adapter) &&
871 skb->encapsulation) {
872 struct iphdr *iph = inner_ip_hdr(skb);
873
874 if (iph->version == 4) {
875 protocol = iph->protocol;
876 } else {
877 const struct ipv6hdr *ipv6h;
878
879 ipv6h = inner_ipv6_hdr(skb);
880 protocol = ipv6h->nexthdr;
881 }
882 } else {
883 if (ctx->ipv4) {
884 const struct iphdr *iph = ip_hdr(skb);
885
886 protocol = iph->protocol;
887 } else if (ctx->ipv6) {
888 const struct ipv6hdr *ipv6h;
889
890 ipv6h = ipv6_hdr(skb);
891 protocol = ipv6h->nexthdr;
892 }
893 }
894
895 switch (protocol) {
896 case IPPROTO_TCP:
897 ctx->l4_hdr_size = skb->encapsulation ? inner_tcp_hdrlen(skb) :
898 tcp_hdrlen(skb);
899 break;
900 case IPPROTO_UDP:
901 ctx->l4_hdr_size = sizeof(struct udphdr);
902 break;
903 default:
904 ctx->l4_hdr_size = 0;
905 break;
906 }
907
908 ctx->copy_size = min(ctx->l4_offset +
909 ctx->l4_hdr_size, skb->len);
910 } else {
911 ctx->l4_offset = 0;
912 ctx->l4_hdr_size = 0;
913 /* copy as much as allowed */
914 ctx->copy_size = min_t(unsigned int,
915 tq->txdata_desc_size,
916 skb_headlen(skb));
917 }
918
919 if (skb->len <= VMXNET3_HDR_COPY_SIZE)
920 ctx->copy_size = skb->len;
921
922 /* make sure headers are accessible directly */
923 if (unlikely(!pskb_may_pull(skb, ctx->copy_size)))
924 goto err;
925 }
926
927 if (unlikely(ctx->copy_size > tq->txdata_desc_size)) {
928 tq->stats.oversized_hdr++;
929 ctx->copy_size = 0;
930 return 0;
931 }
932
933 return 1;
934 err:
935 return -1;
936 }
937
938 /*
939 * copy relevant protocol headers to the transmit ring:
940 * For a tso pkt, relevant headers are L2/3/4 including options
941 * For a pkt requesting csum offloading, they are L2/3 and may include L4
942 * if it's a TCP/UDP pkt
943 *
944 *
945 * Note that this requires that vmxnet3_parse_hdr be called first to set the
946 * appropriate bits in ctx first
947 */
948 static void
vmxnet3_copy_hdr(struct sk_buff * skb,struct vmxnet3_tx_queue * tq,struct vmxnet3_tx_ctx * ctx,struct vmxnet3_adapter * adapter)949 vmxnet3_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
950 struct vmxnet3_tx_ctx *ctx,
951 struct vmxnet3_adapter *adapter)
952 {
953 struct Vmxnet3_TxDataDesc *tdd;
954
955 tdd = (struct Vmxnet3_TxDataDesc *)((u8 *)tq->data_ring.base +
956 tq->tx_ring.next2fill *
957 tq->txdata_desc_size);
958
959 memcpy(tdd->data, skb->data, ctx->copy_size);
960 netdev_dbg(adapter->netdev,
961 "copy %u bytes to dataRing[%u]\n",
962 ctx->copy_size, tq->tx_ring.next2fill);
963 }
964
965
966 static void
vmxnet3_prepare_inner_tso(struct sk_buff * skb,struct vmxnet3_tx_ctx * ctx)967 vmxnet3_prepare_inner_tso(struct sk_buff *skb,
968 struct vmxnet3_tx_ctx *ctx)
969 {
970 struct tcphdr *tcph = inner_tcp_hdr(skb);
971 struct iphdr *iph = inner_ip_hdr(skb);
972
973 if (iph->version == 4) {
974 iph->check = 0;
975 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
976 IPPROTO_TCP, 0);
977 } else {
978 struct ipv6hdr *iph = inner_ipv6_hdr(skb);
979
980 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0,
981 IPPROTO_TCP, 0);
982 }
983 }
984
985 static void
vmxnet3_prepare_tso(struct sk_buff * skb,struct vmxnet3_tx_ctx * ctx)986 vmxnet3_prepare_tso(struct sk_buff *skb,
987 struct vmxnet3_tx_ctx *ctx)
988 {
989 struct tcphdr *tcph = tcp_hdr(skb);
990
991 if (ctx->ipv4) {
992 struct iphdr *iph = ip_hdr(skb);
993
994 iph->check = 0;
995 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
996 IPPROTO_TCP, 0);
997 } else if (ctx->ipv6) {
998 tcp_v6_gso_csum_prep(skb);
999 }
1000 }
1001
txd_estimate(const struct sk_buff * skb)1002 static int txd_estimate(const struct sk_buff *skb)
1003 {
1004 int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
1005 int i;
1006
1007 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1008 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1009
1010 count += VMXNET3_TXD_NEEDED(skb_frag_size(frag));
1011 }
1012 return count;
1013 }
1014
1015 /*
1016 * Transmits a pkt thru a given tq
1017 * Returns:
1018 * NETDEV_TX_OK: descriptors are setup successfully
1019 * NETDEV_TX_OK: error occurred, the pkt is dropped
1020 * NETDEV_TX_BUSY: tx ring is full, queue is stopped
1021 *
1022 * Side-effects:
1023 * 1. tx ring may be changed
1024 * 2. tq stats may be updated accordingly
1025 * 3. shared->txNumDeferred may be updated
1026 */
1027
1028 static int
vmxnet3_tq_xmit(struct sk_buff * skb,struct vmxnet3_tx_queue * tq,struct vmxnet3_adapter * adapter,struct net_device * netdev)1029 vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
1030 struct vmxnet3_adapter *adapter, struct net_device *netdev)
1031 {
1032 int ret;
1033 u32 count;
1034 int num_pkts;
1035 int tx_num_deferred;
1036 unsigned long flags;
1037 struct vmxnet3_tx_ctx ctx;
1038 union Vmxnet3_GenericDesc *gdesc;
1039 #ifdef __BIG_ENDIAN_BITFIELD
1040 /* Use temporary descriptor to avoid touching bits multiple times */
1041 union Vmxnet3_GenericDesc tempTxDesc;
1042 #endif
1043
1044 count = txd_estimate(skb);
1045
1046 ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP));
1047 ctx.ipv6 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IPV6));
1048
1049 ctx.mss = skb_shinfo(skb)->gso_size;
1050 if (ctx.mss) {
1051 if (skb_header_cloned(skb)) {
1052 if (unlikely(pskb_expand_head(skb, 0, 0,
1053 GFP_ATOMIC) != 0)) {
1054 tq->stats.drop_tso++;
1055 goto drop_pkt;
1056 }
1057 tq->stats.copy_skb_header++;
1058 }
1059 if (skb->encapsulation) {
1060 vmxnet3_prepare_inner_tso(skb, &ctx);
1061 } else {
1062 vmxnet3_prepare_tso(skb, &ctx);
1063 }
1064 } else {
1065 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) {
1066
1067 /* non-tso pkts must not use more than
1068 * VMXNET3_MAX_TXD_PER_PKT entries
1069 */
1070 if (skb_linearize(skb) != 0) {
1071 tq->stats.drop_too_many_frags++;
1072 goto drop_pkt;
1073 }
1074 tq->stats.linearized++;
1075
1076 /* recalculate the # of descriptors to use */
1077 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
1078 }
1079 }
1080
1081 ret = vmxnet3_parse_hdr(skb, tq, &ctx, adapter);
1082 if (ret >= 0) {
1083 BUG_ON(ret <= 0 && ctx.copy_size != 0);
1084 /* hdrs parsed, check against other limits */
1085 if (ctx.mss) {
1086 if (unlikely(ctx.l4_offset + ctx.l4_hdr_size >
1087 VMXNET3_MAX_TX_BUF_SIZE)) {
1088 tq->stats.drop_oversized_hdr++;
1089 goto drop_pkt;
1090 }
1091 } else {
1092 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1093 if (unlikely(ctx.l4_offset +
1094 skb->csum_offset >
1095 VMXNET3_MAX_CSUM_OFFSET)) {
1096 tq->stats.drop_oversized_hdr++;
1097 goto drop_pkt;
1098 }
1099 }
1100 }
1101 } else {
1102 tq->stats.drop_hdr_inspect_err++;
1103 goto drop_pkt;
1104 }
1105
1106 spin_lock_irqsave(&tq->tx_lock, flags);
1107
1108 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
1109 tq->stats.tx_ring_full++;
1110 netdev_dbg(adapter->netdev,
1111 "tx queue stopped on %s, next2comp %u"
1112 " next2fill %u\n", adapter->netdev->name,
1113 tq->tx_ring.next2comp, tq->tx_ring.next2fill);
1114
1115 vmxnet3_tq_stop(tq, adapter);
1116 spin_unlock_irqrestore(&tq->tx_lock, flags);
1117 return NETDEV_TX_BUSY;
1118 }
1119
1120
1121 vmxnet3_copy_hdr(skb, tq, &ctx, adapter);
1122
1123 /* fill tx descs related to addr & len */
1124 if (vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter))
1125 goto unlock_drop_pkt;
1126
1127 /* setup the EOP desc */
1128 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
1129
1130 /* setup the SOP desc */
1131 #ifdef __BIG_ENDIAN_BITFIELD
1132 gdesc = &tempTxDesc;
1133 gdesc->dword[2] = ctx.sop_txd->dword[2];
1134 gdesc->dword[3] = ctx.sop_txd->dword[3];
1135 #else
1136 gdesc = ctx.sop_txd;
1137 #endif
1138 tx_num_deferred = le32_to_cpu(tq->shared->txNumDeferred);
1139 if (ctx.mss) {
1140 if (VMXNET3_VERSION_GE_4(adapter) && skb->encapsulation) {
1141 gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size;
1142 gdesc->txd.om = VMXNET3_OM_ENCAP;
1143 gdesc->txd.msscof = ctx.mss;
1144
1145 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)
1146 gdesc->txd.oco = 1;
1147 } else {
1148 gdesc->txd.hlen = ctx.l4_offset + ctx.l4_hdr_size;
1149 gdesc->txd.om = VMXNET3_OM_TSO;
1150 gdesc->txd.msscof = ctx.mss;
1151 }
1152 num_pkts = (skb->len - gdesc->txd.hlen + ctx.mss - 1) / ctx.mss;
1153 } else {
1154 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1155 if (VMXNET3_VERSION_GE_4(adapter) &&
1156 skb->encapsulation) {
1157 gdesc->txd.hlen = ctx.l4_offset +
1158 ctx.l4_hdr_size;
1159 gdesc->txd.om = VMXNET3_OM_ENCAP;
1160 gdesc->txd.msscof = 0; /* Reserved */
1161 } else {
1162 gdesc->txd.hlen = ctx.l4_offset;
1163 gdesc->txd.om = VMXNET3_OM_CSUM;
1164 gdesc->txd.msscof = ctx.l4_offset +
1165 skb->csum_offset;
1166 }
1167 } else {
1168 gdesc->txd.om = 0;
1169 gdesc->txd.msscof = 0;
1170 }
1171 num_pkts = 1;
1172 }
1173 le32_add_cpu(&tq->shared->txNumDeferred, num_pkts);
1174 tx_num_deferred += num_pkts;
1175
1176 if (skb_vlan_tag_present(skb)) {
1177 gdesc->txd.ti = 1;
1178 gdesc->txd.tci = skb_vlan_tag_get(skb);
1179 }
1180
1181 /* Ensure that the write to (&gdesc->txd)->gen will be observed after
1182 * all other writes to &gdesc->txd.
1183 */
1184 dma_wmb();
1185
1186 /* finally flips the GEN bit of the SOP desc. */
1187 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
1188 VMXNET3_TXD_GEN);
1189 #ifdef __BIG_ENDIAN_BITFIELD
1190 /* Finished updating in bitfields of Tx Desc, so write them in original
1191 * place.
1192 */
1193 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
1194 (struct Vmxnet3_TxDesc *)ctx.sop_txd);
1195 gdesc = ctx.sop_txd;
1196 #endif
1197 netdev_dbg(adapter->netdev,
1198 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
1199 (u32)(ctx.sop_txd -
1200 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
1201 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
1202
1203 spin_unlock_irqrestore(&tq->tx_lock, flags);
1204
1205 if (tx_num_deferred >= le32_to_cpu(tq->shared->txThreshold)) {
1206 tq->shared->txNumDeferred = 0;
1207 VMXNET3_WRITE_BAR0_REG(adapter,
1208 VMXNET3_REG_TXPROD + tq->qid * 8,
1209 tq->tx_ring.next2fill);
1210 }
1211
1212 return NETDEV_TX_OK;
1213
1214 unlock_drop_pkt:
1215 spin_unlock_irqrestore(&tq->tx_lock, flags);
1216 drop_pkt:
1217 tq->stats.drop_total++;
1218 dev_kfree_skb_any(skb);
1219 return NETDEV_TX_OK;
1220 }
1221
1222
1223 static netdev_tx_t
vmxnet3_xmit_frame(struct sk_buff * skb,struct net_device * netdev)1224 vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1225 {
1226 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
1227
1228 BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
1229 return vmxnet3_tq_xmit(skb,
1230 &adapter->tx_queue[skb->queue_mapping],
1231 adapter, netdev);
1232 }
1233
1234
1235 static void
vmxnet3_rx_csum(struct vmxnet3_adapter * adapter,struct sk_buff * skb,union Vmxnet3_GenericDesc * gdesc)1236 vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
1237 struct sk_buff *skb,
1238 union Vmxnet3_GenericDesc *gdesc)
1239 {
1240 if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) {
1241 if (gdesc->rcd.v4 &&
1242 (le32_to_cpu(gdesc->dword[3]) &
1243 VMXNET3_RCD_CSUM_OK) == VMXNET3_RCD_CSUM_OK) {
1244 skb->ip_summed = CHECKSUM_UNNECESSARY;
1245 if ((le32_to_cpu(gdesc->dword[0]) &
1246 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT))) {
1247 skb->csum_level = 1;
1248 }
1249 WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) &&
1250 !(le32_to_cpu(gdesc->dword[0]) &
1251 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1252 WARN_ON_ONCE(gdesc->rcd.frg &&
1253 !(le32_to_cpu(gdesc->dword[0]) &
1254 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1255 } else if (gdesc->rcd.v6 && (le32_to_cpu(gdesc->dword[3]) &
1256 (1 << VMXNET3_RCD_TUC_SHIFT))) {
1257 skb->ip_summed = CHECKSUM_UNNECESSARY;
1258 if ((le32_to_cpu(gdesc->dword[0]) &
1259 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT))) {
1260 skb->csum_level = 1;
1261 }
1262 WARN_ON_ONCE(!(gdesc->rcd.tcp || gdesc->rcd.udp) &&
1263 !(le32_to_cpu(gdesc->dword[0]) &
1264 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1265 WARN_ON_ONCE(gdesc->rcd.frg &&
1266 !(le32_to_cpu(gdesc->dword[0]) &
1267 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT)));
1268 } else {
1269 if (gdesc->rcd.csum) {
1270 skb->csum = htons(gdesc->rcd.csum);
1271 skb->ip_summed = CHECKSUM_PARTIAL;
1272 } else {
1273 skb_checksum_none_assert(skb);
1274 }
1275 }
1276 } else {
1277 skb_checksum_none_assert(skb);
1278 }
1279 }
1280
1281
1282 static void
vmxnet3_rx_error(struct vmxnet3_rx_queue * rq,struct Vmxnet3_RxCompDesc * rcd,struct vmxnet3_rx_ctx * ctx,struct vmxnet3_adapter * adapter)1283 vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd,
1284 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter)
1285 {
1286 rq->stats.drop_err++;
1287 if (!rcd->fcs)
1288 rq->stats.drop_fcs++;
1289
1290 rq->stats.drop_total++;
1291
1292 /*
1293 * We do not unmap and chain the rx buffer to the skb.
1294 * We basically pretend this buffer is not used and will be recycled
1295 * by vmxnet3_rq_alloc_rx_buf()
1296 */
1297
1298 /*
1299 * ctx->skb may be NULL if this is the first and the only one
1300 * desc for the pkt
1301 */
1302 if (ctx->skb)
1303 dev_kfree_skb_irq(ctx->skb);
1304
1305 ctx->skb = NULL;
1306 }
1307
1308
1309 static u32
vmxnet3_get_hdr_len(struct vmxnet3_adapter * adapter,struct sk_buff * skb,union Vmxnet3_GenericDesc * gdesc)1310 vmxnet3_get_hdr_len(struct vmxnet3_adapter *adapter, struct sk_buff *skb,
1311 union Vmxnet3_GenericDesc *gdesc)
1312 {
1313 u32 hlen, maplen;
1314 union {
1315 void *ptr;
1316 struct ethhdr *eth;
1317 struct vlan_ethhdr *veth;
1318 struct iphdr *ipv4;
1319 struct ipv6hdr *ipv6;
1320 struct tcphdr *tcp;
1321 } hdr;
1322 BUG_ON(gdesc->rcd.tcp == 0);
1323
1324 maplen = skb_headlen(skb);
1325 if (unlikely(sizeof(struct iphdr) + sizeof(struct tcphdr) > maplen))
1326 return 0;
1327
1328 if (skb->protocol == cpu_to_be16(ETH_P_8021Q) ||
1329 skb->protocol == cpu_to_be16(ETH_P_8021AD))
1330 hlen = sizeof(struct vlan_ethhdr);
1331 else
1332 hlen = sizeof(struct ethhdr);
1333
1334 hdr.eth = eth_hdr(skb);
1335 if (gdesc->rcd.v4) {
1336 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IP) &&
1337 hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IP));
1338 hdr.ptr += hlen;
1339 BUG_ON(hdr.ipv4->protocol != IPPROTO_TCP);
1340 hlen = hdr.ipv4->ihl << 2;
1341 hdr.ptr += hdr.ipv4->ihl << 2;
1342 } else if (gdesc->rcd.v6) {
1343 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IPV6) &&
1344 hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IPV6));
1345 hdr.ptr += hlen;
1346 /* Use an estimated value, since we also need to handle
1347 * TSO case.
1348 */
1349 if (hdr.ipv6->nexthdr != IPPROTO_TCP)
1350 return sizeof(struct ipv6hdr) + sizeof(struct tcphdr);
1351 hlen = sizeof(struct ipv6hdr);
1352 hdr.ptr += sizeof(struct ipv6hdr);
1353 } else {
1354 /* Non-IP pkt, dont estimate header length */
1355 return 0;
1356 }
1357
1358 if (hlen + sizeof(struct tcphdr) > maplen)
1359 return 0;
1360
1361 return (hlen + (hdr.tcp->doff << 2));
1362 }
1363
1364 static int
vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue * rq,struct vmxnet3_adapter * adapter,int quota)1365 vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
1366 struct vmxnet3_adapter *adapter, int quota)
1367 {
1368 static const u32 rxprod_reg[2] = {
1369 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2
1370 };
1371 u32 num_pkts = 0;
1372 bool skip_page_frags = false;
1373 bool encap_lro = false;
1374 struct Vmxnet3_RxCompDesc *rcd;
1375 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
1376 u16 segCnt = 0, mss = 0;
1377 #ifdef __BIG_ENDIAN_BITFIELD
1378 struct Vmxnet3_RxDesc rxCmdDesc;
1379 struct Vmxnet3_RxCompDesc rxComp;
1380 #endif
1381 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
1382 &rxComp);
1383 while (rcd->gen == rq->comp_ring.gen) {
1384 struct vmxnet3_rx_buf_info *rbi;
1385 struct sk_buff *skb, *new_skb = NULL;
1386 struct page *new_page = NULL;
1387 dma_addr_t new_dma_addr;
1388 int num_to_alloc;
1389 struct Vmxnet3_RxDesc *rxd;
1390 u32 idx, ring_idx;
1391 struct vmxnet3_cmd_ring *ring = NULL;
1392 if (num_pkts >= quota) {
1393 /* we may stop even before we see the EOP desc of
1394 * the current pkt
1395 */
1396 break;
1397 }
1398
1399 /* Prevent any rcd field from being (speculatively) read before
1400 * rcd->gen is read.
1401 */
1402 dma_rmb();
1403
1404 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2 &&
1405 rcd->rqID != rq->dataRingQid);
1406 idx = rcd->rxdIdx;
1407 ring_idx = VMXNET3_GET_RING_IDX(adapter, rcd->rqID);
1408 ring = rq->rx_ring + ring_idx;
1409 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
1410 &rxCmdDesc);
1411 rbi = rq->buf_info[ring_idx] + idx;
1412
1413 BUG_ON(rxd->addr != rbi->dma_addr ||
1414 rxd->len != rbi->len);
1415
1416 if (unlikely(rcd->eop && rcd->err)) {
1417 vmxnet3_rx_error(rq, rcd, ctx, adapter);
1418 goto rcd_done;
1419 }
1420
1421 if (rcd->sop) { /* first buf of the pkt */
1422 bool rxDataRingUsed;
1423 u16 len;
1424
1425 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||
1426 (rcd->rqID != rq->qid &&
1427 rcd->rqID != rq->dataRingQid));
1428
1429 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB);
1430 BUG_ON(ctx->skb != NULL || rbi->skb == NULL);
1431
1432 if (unlikely(rcd->len == 0)) {
1433 /* Pretend the rx buffer is skipped. */
1434 BUG_ON(!(rcd->sop && rcd->eop));
1435 netdev_dbg(adapter->netdev,
1436 "rxRing[%u][%u] 0 length\n",
1437 ring_idx, idx);
1438 goto rcd_done;
1439 }
1440
1441 skip_page_frags = false;
1442 ctx->skb = rbi->skb;
1443
1444 rxDataRingUsed =
1445 VMXNET3_RX_DATA_RING(adapter, rcd->rqID);
1446 len = rxDataRingUsed ? rcd->len : rbi->len;
1447 new_skb = netdev_alloc_skb_ip_align(adapter->netdev,
1448 len);
1449 if (new_skb == NULL) {
1450 /* Skb allocation failed, do not handover this
1451 * skb to stack. Reuse it. Drop the existing pkt
1452 */
1453 rq->stats.rx_buf_alloc_failure++;
1454 ctx->skb = NULL;
1455 rq->stats.drop_total++;
1456 skip_page_frags = true;
1457 goto rcd_done;
1458 }
1459
1460 if (rxDataRingUsed) {
1461 size_t sz;
1462
1463 BUG_ON(rcd->len > rq->data_ring.desc_size);
1464
1465 ctx->skb = new_skb;
1466 sz = rcd->rxdIdx * rq->data_ring.desc_size;
1467 memcpy(new_skb->data,
1468 &rq->data_ring.base[sz], rcd->len);
1469 } else {
1470 ctx->skb = rbi->skb;
1471
1472 new_dma_addr =
1473 dma_map_single(&adapter->pdev->dev,
1474 new_skb->data, rbi->len,
1475 DMA_FROM_DEVICE);
1476 if (dma_mapping_error(&adapter->pdev->dev,
1477 new_dma_addr)) {
1478 dev_kfree_skb(new_skb);
1479 /* Skb allocation failed, do not
1480 * handover this skb to stack. Reuse
1481 * it. Drop the existing pkt.
1482 */
1483 rq->stats.rx_buf_alloc_failure++;
1484 ctx->skb = NULL;
1485 rq->stats.drop_total++;
1486 skip_page_frags = true;
1487 goto rcd_done;
1488 }
1489
1490 dma_unmap_single(&adapter->pdev->dev,
1491 rbi->dma_addr,
1492 rbi->len,
1493 DMA_FROM_DEVICE);
1494
1495 /* Immediate refill */
1496 rbi->skb = new_skb;
1497 rbi->dma_addr = new_dma_addr;
1498 rxd->addr = cpu_to_le64(rbi->dma_addr);
1499 rxd->len = rbi->len;
1500 }
1501
1502 #ifdef VMXNET3_RSS
1503 if (rcd->rssType != VMXNET3_RCD_RSS_TYPE_NONE &&
1504 (adapter->netdev->features & NETIF_F_RXHASH)) {
1505 enum pkt_hash_types hash_type;
1506
1507 switch (rcd->rssType) {
1508 case VMXNET3_RCD_RSS_TYPE_IPV4:
1509 case VMXNET3_RCD_RSS_TYPE_IPV6:
1510 hash_type = PKT_HASH_TYPE_L3;
1511 break;
1512 case VMXNET3_RCD_RSS_TYPE_TCPIPV4:
1513 case VMXNET3_RCD_RSS_TYPE_TCPIPV6:
1514 case VMXNET3_RCD_RSS_TYPE_UDPIPV4:
1515 case VMXNET3_RCD_RSS_TYPE_UDPIPV6:
1516 hash_type = PKT_HASH_TYPE_L4;
1517 break;
1518 default:
1519 hash_type = PKT_HASH_TYPE_L3;
1520 break;
1521 }
1522 skb_set_hash(ctx->skb,
1523 le32_to_cpu(rcd->rssHash),
1524 hash_type);
1525 }
1526 #endif
1527 skb_put(ctx->skb, rcd->len);
1528
1529 if (VMXNET3_VERSION_GE_2(adapter) &&
1530 rcd->type == VMXNET3_CDTYPE_RXCOMP_LRO) {
1531 struct Vmxnet3_RxCompDescExt *rcdlro;
1532 union Vmxnet3_GenericDesc *gdesc;
1533
1534 rcdlro = (struct Vmxnet3_RxCompDescExt *)rcd;
1535 gdesc = (union Vmxnet3_GenericDesc *)rcd;
1536
1537 segCnt = rcdlro->segCnt;
1538 WARN_ON_ONCE(segCnt == 0);
1539 mss = rcdlro->mss;
1540 if (unlikely(segCnt <= 1))
1541 segCnt = 0;
1542 encap_lro = (le32_to_cpu(gdesc->dword[0]) &
1543 (1UL << VMXNET3_RCD_HDR_INNER_SHIFT));
1544 } else {
1545 segCnt = 0;
1546 }
1547 } else {
1548 BUG_ON(ctx->skb == NULL && !skip_page_frags);
1549
1550 /* non SOP buffer must be type 1 in most cases */
1551 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE);
1552 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY);
1553
1554 /* If an sop buffer was dropped, skip all
1555 * following non-sop fragments. They will be reused.
1556 */
1557 if (skip_page_frags)
1558 goto rcd_done;
1559
1560 if (rcd->len) {
1561 new_page = alloc_page(GFP_ATOMIC);
1562 /* Replacement page frag could not be allocated.
1563 * Reuse this page. Drop the pkt and free the
1564 * skb which contained this page as a frag. Skip
1565 * processing all the following non-sop frags.
1566 */
1567 if (unlikely(!new_page)) {
1568 rq->stats.rx_buf_alloc_failure++;
1569 dev_kfree_skb(ctx->skb);
1570 ctx->skb = NULL;
1571 skip_page_frags = true;
1572 goto rcd_done;
1573 }
1574 new_dma_addr = dma_map_page(&adapter->pdev->dev,
1575 new_page,
1576 0, PAGE_SIZE,
1577 DMA_FROM_DEVICE);
1578 if (dma_mapping_error(&adapter->pdev->dev,
1579 new_dma_addr)) {
1580 put_page(new_page);
1581 rq->stats.rx_buf_alloc_failure++;
1582 dev_kfree_skb(ctx->skb);
1583 ctx->skb = NULL;
1584 skip_page_frags = true;
1585 goto rcd_done;
1586 }
1587
1588 dma_unmap_page(&adapter->pdev->dev,
1589 rbi->dma_addr, rbi->len,
1590 DMA_FROM_DEVICE);
1591
1592 vmxnet3_append_frag(ctx->skb, rcd, rbi);
1593
1594 /* Immediate refill */
1595 rbi->page = new_page;
1596 rbi->dma_addr = new_dma_addr;
1597 rxd->addr = cpu_to_le64(rbi->dma_addr);
1598 rxd->len = rbi->len;
1599 }
1600 }
1601
1602
1603 skb = ctx->skb;
1604 if (rcd->eop) {
1605 u32 mtu = adapter->netdev->mtu;
1606 skb->len += skb->data_len;
1607
1608 vmxnet3_rx_csum(adapter, skb,
1609 (union Vmxnet3_GenericDesc *)rcd);
1610 skb->protocol = eth_type_trans(skb, adapter->netdev);
1611 if ((!rcd->tcp && !encap_lro) ||
1612 !(adapter->netdev->features & NETIF_F_LRO))
1613 goto not_lro;
1614
1615 if (segCnt != 0 && mss != 0) {
1616 skb_shinfo(skb)->gso_type = rcd->v4 ?
1617 SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
1618 skb_shinfo(skb)->gso_size = mss;
1619 skb_shinfo(skb)->gso_segs = segCnt;
1620 } else if ((segCnt != 0 || skb->len > mtu) && !encap_lro) {
1621 u32 hlen;
1622
1623 hlen = vmxnet3_get_hdr_len(adapter, skb,
1624 (union Vmxnet3_GenericDesc *)rcd);
1625 if (hlen == 0)
1626 goto not_lro;
1627
1628 skb_shinfo(skb)->gso_type =
1629 rcd->v4 ? SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
1630 if (segCnt != 0) {
1631 skb_shinfo(skb)->gso_segs = segCnt;
1632 skb_shinfo(skb)->gso_size =
1633 DIV_ROUND_UP(skb->len -
1634 hlen, segCnt);
1635 } else {
1636 skb_shinfo(skb)->gso_size = mtu - hlen;
1637 }
1638 }
1639 not_lro:
1640 if (unlikely(rcd->ts))
1641 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rcd->tci);
1642
1643 if (adapter->netdev->features & NETIF_F_LRO)
1644 netif_receive_skb(skb);
1645 else
1646 napi_gro_receive(&rq->napi, skb);
1647
1648 ctx->skb = NULL;
1649 encap_lro = false;
1650 num_pkts++;
1651 }
1652
1653 rcd_done:
1654 /* device may have skipped some rx descs */
1655 ring->next2comp = idx;
1656 num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring);
1657 ring = rq->rx_ring + ring_idx;
1658
1659 /* Ensure that the writes to rxd->gen bits will be observed
1660 * after all other writes to rxd objects.
1661 */
1662 dma_wmb();
1663
1664 while (num_to_alloc) {
1665 vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd,
1666 &rxCmdDesc);
1667 BUG_ON(!rxd->addr);
1668
1669 /* Recv desc is ready to be used by the device */
1670 rxd->gen = ring->gen;
1671 vmxnet3_cmd_ring_adv_next2fill(ring);
1672 num_to_alloc--;
1673 }
1674
1675 /* if needed, update the register */
1676 if (unlikely(rq->shared->updateRxProd)) {
1677 VMXNET3_WRITE_BAR0_REG(adapter,
1678 rxprod_reg[ring_idx] + rq->qid * 8,
1679 ring->next2fill);
1680 }
1681
1682 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
1683 vmxnet3_getRxComp(rcd,
1684 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
1685 }
1686
1687 return num_pkts;
1688 }
1689
1690
1691 static void
vmxnet3_rq_cleanup(struct vmxnet3_rx_queue * rq,struct vmxnet3_adapter * adapter)1692 vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
1693 struct vmxnet3_adapter *adapter)
1694 {
1695 u32 i, ring_idx;
1696 struct Vmxnet3_RxDesc *rxd;
1697
1698 /* ring has already been cleaned up */
1699 if (!rq->rx_ring[0].base)
1700 return;
1701
1702 for (ring_idx = 0; ring_idx < 2; ring_idx++) {
1703 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
1704 #ifdef __BIG_ENDIAN_BITFIELD
1705 struct Vmxnet3_RxDesc rxDesc;
1706 #endif
1707 vmxnet3_getRxDesc(rxd,
1708 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
1709
1710 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
1711 rq->buf_info[ring_idx][i].skb) {
1712 dma_unmap_single(&adapter->pdev->dev, rxd->addr,
1713 rxd->len, DMA_FROM_DEVICE);
1714 dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
1715 rq->buf_info[ring_idx][i].skb = NULL;
1716 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&
1717 rq->buf_info[ring_idx][i].page) {
1718 dma_unmap_page(&adapter->pdev->dev, rxd->addr,
1719 rxd->len, DMA_FROM_DEVICE);
1720 put_page(rq->buf_info[ring_idx][i].page);
1721 rq->buf_info[ring_idx][i].page = NULL;
1722 }
1723 }
1724
1725 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN;
1726 rq->rx_ring[ring_idx].next2fill =
1727 rq->rx_ring[ring_idx].next2comp = 0;
1728 }
1729
1730 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1731 rq->comp_ring.next2proc = 0;
1732 }
1733
1734
1735 static void
vmxnet3_rq_cleanup_all(struct vmxnet3_adapter * adapter)1736 vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
1737 {
1738 int i;
1739
1740 for (i = 0; i < adapter->num_rx_queues; i++)
1741 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
1742 }
1743
1744
vmxnet3_rq_destroy(struct vmxnet3_rx_queue * rq,struct vmxnet3_adapter * adapter)1745 static void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
1746 struct vmxnet3_adapter *adapter)
1747 {
1748 int i;
1749 int j;
1750
1751 /* all rx buffers must have already been freed */
1752 for (i = 0; i < 2; i++) {
1753 if (rq->buf_info[i]) {
1754 for (j = 0; j < rq->rx_ring[i].size; j++)
1755 BUG_ON(rq->buf_info[i][j].page != NULL);
1756 }
1757 }
1758
1759
1760 for (i = 0; i < 2; i++) {
1761 if (rq->rx_ring[i].base) {
1762 dma_free_coherent(&adapter->pdev->dev,
1763 rq->rx_ring[i].size
1764 * sizeof(struct Vmxnet3_RxDesc),
1765 rq->rx_ring[i].base,
1766 rq->rx_ring[i].basePA);
1767 rq->rx_ring[i].base = NULL;
1768 }
1769 }
1770
1771 if (rq->data_ring.base) {
1772 dma_free_coherent(&adapter->pdev->dev,
1773 rq->rx_ring[0].size * rq->data_ring.desc_size,
1774 rq->data_ring.base, rq->data_ring.basePA);
1775 rq->data_ring.base = NULL;
1776 }
1777
1778 if (rq->comp_ring.base) {
1779 dma_free_coherent(&adapter->pdev->dev, rq->comp_ring.size
1780 * sizeof(struct Vmxnet3_RxCompDesc),
1781 rq->comp_ring.base, rq->comp_ring.basePA);
1782 rq->comp_ring.base = NULL;
1783 }
1784
1785 kfree(rq->buf_info[0]);
1786 rq->buf_info[0] = NULL;
1787 rq->buf_info[1] = NULL;
1788 }
1789
1790 static void
vmxnet3_rq_destroy_all_rxdataring(struct vmxnet3_adapter * adapter)1791 vmxnet3_rq_destroy_all_rxdataring(struct vmxnet3_adapter *adapter)
1792 {
1793 int i;
1794
1795 for (i = 0; i < adapter->num_rx_queues; i++) {
1796 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
1797
1798 if (rq->data_ring.base) {
1799 dma_free_coherent(&adapter->pdev->dev,
1800 (rq->rx_ring[0].size *
1801 rq->data_ring.desc_size),
1802 rq->data_ring.base,
1803 rq->data_ring.basePA);
1804 rq->data_ring.base = NULL;
1805 rq->data_ring.desc_size = 0;
1806 }
1807 }
1808 }
1809
1810 static int
vmxnet3_rq_init(struct vmxnet3_rx_queue * rq,struct vmxnet3_adapter * adapter)1811 vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
1812 struct vmxnet3_adapter *adapter)
1813 {
1814 int i;
1815
1816 /* initialize buf_info */
1817 for (i = 0; i < rq->rx_ring[0].size; i++) {
1818
1819 /* 1st buf for a pkt is skbuff */
1820 if (i % adapter->rx_buf_per_pkt == 0) {
1821 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB;
1822 rq->buf_info[0][i].len = adapter->skb_buf_size;
1823 } else { /* subsequent bufs for a pkt is frag */
1824 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE;
1825 rq->buf_info[0][i].len = PAGE_SIZE;
1826 }
1827 }
1828 for (i = 0; i < rq->rx_ring[1].size; i++) {
1829 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE;
1830 rq->buf_info[1][i].len = PAGE_SIZE;
1831 }
1832
1833 /* reset internal state and allocate buffers for both rings */
1834 for (i = 0; i < 2; i++) {
1835 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0;
1836
1837 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size *
1838 sizeof(struct Vmxnet3_RxDesc));
1839 rq->rx_ring[i].gen = VMXNET3_INIT_GEN;
1840 }
1841 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1,
1842 adapter) == 0) {
1843 /* at least has 1 rx buffer for the 1st ring */
1844 return -ENOMEM;
1845 }
1846 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter);
1847
1848 /* reset the comp ring */
1849 rq->comp_ring.next2proc = 0;
1850 memset(rq->comp_ring.base, 0, rq->comp_ring.size *
1851 sizeof(struct Vmxnet3_RxCompDesc));
1852 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1853
1854 /* reset rxctx */
1855 rq->rx_ctx.skb = NULL;
1856
1857 /* stats are not reset */
1858 return 0;
1859 }
1860
1861
1862 static int
vmxnet3_rq_init_all(struct vmxnet3_adapter * adapter)1863 vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
1864 {
1865 int i, err = 0;
1866
1867 for (i = 0; i < adapter->num_rx_queues; i++) {
1868 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
1869 if (unlikely(err)) {
1870 dev_err(&adapter->netdev->dev, "%s: failed to "
1871 "initialize rx queue%i\n",
1872 adapter->netdev->name, i);
1873 break;
1874 }
1875 }
1876 return err;
1877
1878 }
1879
1880
1881 static int
vmxnet3_rq_create(struct vmxnet3_rx_queue * rq,struct vmxnet3_adapter * adapter)1882 vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
1883 {
1884 int i;
1885 size_t sz;
1886 struct vmxnet3_rx_buf_info *bi;
1887
1888 for (i = 0; i < 2; i++) {
1889
1890 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc);
1891 rq->rx_ring[i].base = dma_alloc_coherent(
1892 &adapter->pdev->dev, sz,
1893 &rq->rx_ring[i].basePA,
1894 GFP_KERNEL);
1895 if (!rq->rx_ring[i].base) {
1896 netdev_err(adapter->netdev,
1897 "failed to allocate rx ring %d\n", i);
1898 goto err;
1899 }
1900 }
1901
1902 if ((adapter->rxdataring_enabled) && (rq->data_ring.desc_size != 0)) {
1903 sz = rq->rx_ring[0].size * rq->data_ring.desc_size;
1904 rq->data_ring.base =
1905 dma_alloc_coherent(&adapter->pdev->dev, sz,
1906 &rq->data_ring.basePA,
1907 GFP_KERNEL);
1908 if (!rq->data_ring.base) {
1909 netdev_err(adapter->netdev,
1910 "rx data ring will be disabled\n");
1911 adapter->rxdataring_enabled = false;
1912 }
1913 } else {
1914 rq->data_ring.base = NULL;
1915 rq->data_ring.desc_size = 0;
1916 }
1917
1918 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc);
1919 rq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, sz,
1920 &rq->comp_ring.basePA,
1921 GFP_KERNEL);
1922 if (!rq->comp_ring.base) {
1923 netdev_err(adapter->netdev, "failed to allocate rx comp ring\n");
1924 goto err;
1925 }
1926
1927 bi = kcalloc_node(rq->rx_ring[0].size + rq->rx_ring[1].size,
1928 sizeof(rq->buf_info[0][0]), GFP_KERNEL,
1929 dev_to_node(&adapter->pdev->dev));
1930 if (!bi)
1931 goto err;
1932
1933 rq->buf_info[0] = bi;
1934 rq->buf_info[1] = bi + rq->rx_ring[0].size;
1935
1936 return 0;
1937
1938 err:
1939 vmxnet3_rq_destroy(rq, adapter);
1940 return -ENOMEM;
1941 }
1942
1943
1944 static int
vmxnet3_rq_create_all(struct vmxnet3_adapter * adapter)1945 vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
1946 {
1947 int i, err = 0;
1948
1949 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter);
1950
1951 for (i = 0; i < adapter->num_rx_queues; i++) {
1952 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
1953 if (unlikely(err)) {
1954 dev_err(&adapter->netdev->dev,
1955 "%s: failed to create rx queue%i\n",
1956 adapter->netdev->name, i);
1957 goto err_out;
1958 }
1959 }
1960
1961 if (!adapter->rxdataring_enabled)
1962 vmxnet3_rq_destroy_all_rxdataring(adapter);
1963
1964 return err;
1965 err_out:
1966 vmxnet3_rq_destroy_all(adapter);
1967 return err;
1968
1969 }
1970
1971 /* Multiple queue aware polling function for tx and rx */
1972
1973 static int
vmxnet3_do_poll(struct vmxnet3_adapter * adapter,int budget)1974 vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
1975 {
1976 int rcd_done = 0, i;
1977 if (unlikely(adapter->shared->ecr))
1978 vmxnet3_process_events(adapter);
1979 for (i = 0; i < adapter->num_tx_queues; i++)
1980 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
1981
1982 for (i = 0; i < adapter->num_rx_queues; i++)
1983 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
1984 adapter, budget);
1985 return rcd_done;
1986 }
1987
1988
1989 static int
vmxnet3_poll(struct napi_struct * napi,int budget)1990 vmxnet3_poll(struct napi_struct *napi, int budget)
1991 {
1992 struct vmxnet3_rx_queue *rx_queue = container_of(napi,
1993 struct vmxnet3_rx_queue, napi);
1994 int rxd_done;
1995
1996 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
1997
1998 if (rxd_done < budget) {
1999 napi_complete_done(napi, rxd_done);
2000 vmxnet3_enable_all_intrs(rx_queue->adapter);
2001 }
2002 return rxd_done;
2003 }
2004
2005 /*
2006 * NAPI polling function for MSI-X mode with multiple Rx queues
2007 * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
2008 */
2009
2010 static int
vmxnet3_poll_rx_only(struct napi_struct * napi,int budget)2011 vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
2012 {
2013 struct vmxnet3_rx_queue *rq = container_of(napi,
2014 struct vmxnet3_rx_queue, napi);
2015 struct vmxnet3_adapter *adapter = rq->adapter;
2016 int rxd_done;
2017
2018 /* When sharing interrupt with corresponding tx queue, process
2019 * tx completions in that queue as well
2020 */
2021 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
2022 struct vmxnet3_tx_queue *tq =
2023 &adapter->tx_queue[rq - adapter->rx_queue];
2024 vmxnet3_tq_tx_complete(tq, adapter);
2025 }
2026
2027 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
2028
2029 if (rxd_done < budget) {
2030 napi_complete_done(napi, rxd_done);
2031 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
2032 }
2033 return rxd_done;
2034 }
2035
2036
2037 #ifdef CONFIG_PCI_MSI
2038
2039 /*
2040 * Handle completion interrupts on tx queues
2041 * Returns whether or not the intr is handled
2042 */
2043
2044 static irqreturn_t
vmxnet3_msix_tx(int irq,void * data)2045 vmxnet3_msix_tx(int irq, void *data)
2046 {
2047 struct vmxnet3_tx_queue *tq = data;
2048 struct vmxnet3_adapter *adapter = tq->adapter;
2049
2050 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2051 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
2052
2053 /* Handle the case where only one irq is allocate for all tx queues */
2054 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
2055 int i;
2056 for (i = 0; i < adapter->num_tx_queues; i++) {
2057 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
2058 vmxnet3_tq_tx_complete(txq, adapter);
2059 }
2060 } else {
2061 vmxnet3_tq_tx_complete(tq, adapter);
2062 }
2063 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
2064
2065 return IRQ_HANDLED;
2066 }
2067
2068
2069 /*
2070 * Handle completion interrupts on rx queues. Returns whether or not the
2071 * intr is handled
2072 */
2073
2074 static irqreturn_t
vmxnet3_msix_rx(int irq,void * data)2075 vmxnet3_msix_rx(int irq, void *data)
2076 {
2077 struct vmxnet3_rx_queue *rq = data;
2078 struct vmxnet3_adapter *adapter = rq->adapter;
2079
2080 /* disable intr if needed */
2081 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2082 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
2083 napi_schedule(&rq->napi);
2084
2085 return IRQ_HANDLED;
2086 }
2087
2088 /*
2089 *----------------------------------------------------------------------------
2090 *
2091 * vmxnet3_msix_event --
2092 *
2093 * vmxnet3 msix event intr handler
2094 *
2095 * Result:
2096 * whether or not the intr is handled
2097 *
2098 *----------------------------------------------------------------------------
2099 */
2100
2101 static irqreturn_t
vmxnet3_msix_event(int irq,void * data)2102 vmxnet3_msix_event(int irq, void *data)
2103 {
2104 struct net_device *dev = data;
2105 struct vmxnet3_adapter *adapter = netdev_priv(dev);
2106
2107 /* disable intr if needed */
2108 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2109 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
2110
2111 if (adapter->shared->ecr)
2112 vmxnet3_process_events(adapter);
2113
2114 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
2115
2116 return IRQ_HANDLED;
2117 }
2118
2119 #endif /* CONFIG_PCI_MSI */
2120
2121
2122 /* Interrupt handler for vmxnet3 */
2123 static irqreturn_t
vmxnet3_intr(int irq,void * dev_id)2124 vmxnet3_intr(int irq, void *dev_id)
2125 {
2126 struct net_device *dev = dev_id;
2127 struct vmxnet3_adapter *adapter = netdev_priv(dev);
2128
2129 if (adapter->intr.type == VMXNET3_IT_INTX) {
2130 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
2131 if (unlikely(icr == 0))
2132 /* not ours */
2133 return IRQ_NONE;
2134 }
2135
2136
2137 /* disable intr if needed */
2138 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
2139 vmxnet3_disable_all_intrs(adapter);
2140
2141 napi_schedule(&adapter->rx_queue[0].napi);
2142
2143 return IRQ_HANDLED;
2144 }
2145
2146 #ifdef CONFIG_NET_POLL_CONTROLLER
2147
2148 /* netpoll callback. */
2149 static void
vmxnet3_netpoll(struct net_device * netdev)2150 vmxnet3_netpoll(struct net_device *netdev)
2151 {
2152 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2153
2154 switch (adapter->intr.type) {
2155 #ifdef CONFIG_PCI_MSI
2156 case VMXNET3_IT_MSIX: {
2157 int i;
2158 for (i = 0; i < adapter->num_rx_queues; i++)
2159 vmxnet3_msix_rx(0, &adapter->rx_queue[i]);
2160 break;
2161 }
2162 #endif
2163 case VMXNET3_IT_MSI:
2164 default:
2165 vmxnet3_intr(0, adapter->netdev);
2166 break;
2167 }
2168
2169 }
2170 #endif /* CONFIG_NET_POLL_CONTROLLER */
2171
2172 static int
vmxnet3_request_irqs(struct vmxnet3_adapter * adapter)2173 vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
2174 {
2175 struct vmxnet3_intr *intr = &adapter->intr;
2176 int err = 0, i;
2177 int vector = 0;
2178
2179 #ifdef CONFIG_PCI_MSI
2180 if (adapter->intr.type == VMXNET3_IT_MSIX) {
2181 for (i = 0; i < adapter->num_tx_queues; i++) {
2182 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
2183 sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
2184 adapter->netdev->name, vector);
2185 err = request_irq(
2186 intr->msix_entries[vector].vector,
2187 vmxnet3_msix_tx, 0,
2188 adapter->tx_queue[i].name,
2189 &adapter->tx_queue[i]);
2190 } else {
2191 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
2192 adapter->netdev->name, vector);
2193 }
2194 if (err) {
2195 dev_err(&adapter->netdev->dev,
2196 "Failed to request irq for MSIX, %s, "
2197 "error %d\n",
2198 adapter->tx_queue[i].name, err);
2199 return err;
2200 }
2201
2202 /* Handle the case where only 1 MSIx was allocated for
2203 * all tx queues */
2204 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
2205 for (; i < adapter->num_tx_queues; i++)
2206 adapter->tx_queue[i].comp_ring.intr_idx
2207 = vector;
2208 vector++;
2209 break;
2210 } else {
2211 adapter->tx_queue[i].comp_ring.intr_idx
2212 = vector++;
2213 }
2214 }
2215 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
2216 vector = 0;
2217
2218 for (i = 0; i < adapter->num_rx_queues; i++) {
2219 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
2220 sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
2221 adapter->netdev->name, vector);
2222 else
2223 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
2224 adapter->netdev->name, vector);
2225 err = request_irq(intr->msix_entries[vector].vector,
2226 vmxnet3_msix_rx, 0,
2227 adapter->rx_queue[i].name,
2228 &(adapter->rx_queue[i]));
2229 if (err) {
2230 netdev_err(adapter->netdev,
2231 "Failed to request irq for MSIX, "
2232 "%s, error %d\n",
2233 adapter->rx_queue[i].name, err);
2234 return err;
2235 }
2236
2237 adapter->rx_queue[i].comp_ring.intr_idx = vector++;
2238 }
2239
2240 sprintf(intr->event_msi_vector_name, "%s-event-%d",
2241 adapter->netdev->name, vector);
2242 err = request_irq(intr->msix_entries[vector].vector,
2243 vmxnet3_msix_event, 0,
2244 intr->event_msi_vector_name, adapter->netdev);
2245 intr->event_intr_idx = vector;
2246
2247 } else if (intr->type == VMXNET3_IT_MSI) {
2248 adapter->num_rx_queues = 1;
2249 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
2250 adapter->netdev->name, adapter->netdev);
2251 } else {
2252 #endif
2253 adapter->num_rx_queues = 1;
2254 err = request_irq(adapter->pdev->irq, vmxnet3_intr,
2255 IRQF_SHARED, adapter->netdev->name,
2256 adapter->netdev);
2257 #ifdef CONFIG_PCI_MSI
2258 }
2259 #endif
2260 intr->num_intrs = vector + 1;
2261 if (err) {
2262 netdev_err(adapter->netdev,
2263 "Failed to request irq (intr type:%d), error %d\n",
2264 intr->type, err);
2265 } else {
2266 /* Number of rx queues will not change after this */
2267 for (i = 0; i < adapter->num_rx_queues; i++) {
2268 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2269 rq->qid = i;
2270 rq->qid2 = i + adapter->num_rx_queues;
2271 rq->dataRingQid = i + 2 * adapter->num_rx_queues;
2272 }
2273
2274 /* init our intr settings */
2275 for (i = 0; i < intr->num_intrs; i++)
2276 intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
2277 if (adapter->intr.type != VMXNET3_IT_MSIX) {
2278 adapter->intr.event_intr_idx = 0;
2279 for (i = 0; i < adapter->num_tx_queues; i++)
2280 adapter->tx_queue[i].comp_ring.intr_idx = 0;
2281 adapter->rx_queue[0].comp_ring.intr_idx = 0;
2282 }
2283
2284 netdev_info(adapter->netdev,
2285 "intr type %u, mode %u, %u vectors allocated\n",
2286 intr->type, intr->mask_mode, intr->num_intrs);
2287 }
2288
2289 return err;
2290 }
2291
2292
2293 static void
vmxnet3_free_irqs(struct vmxnet3_adapter * adapter)2294 vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
2295 {
2296 struct vmxnet3_intr *intr = &adapter->intr;
2297 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
2298
2299 switch (intr->type) {
2300 #ifdef CONFIG_PCI_MSI
2301 case VMXNET3_IT_MSIX:
2302 {
2303 int i, vector = 0;
2304
2305 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
2306 for (i = 0; i < adapter->num_tx_queues; i++) {
2307 free_irq(intr->msix_entries[vector++].vector,
2308 &(adapter->tx_queue[i]));
2309 if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
2310 break;
2311 }
2312 }
2313
2314 for (i = 0; i < adapter->num_rx_queues; i++) {
2315 free_irq(intr->msix_entries[vector++].vector,
2316 &(adapter->rx_queue[i]));
2317 }
2318
2319 free_irq(intr->msix_entries[vector].vector,
2320 adapter->netdev);
2321 BUG_ON(vector >= intr->num_intrs);
2322 break;
2323 }
2324 #endif
2325 case VMXNET3_IT_MSI:
2326 free_irq(adapter->pdev->irq, adapter->netdev);
2327 break;
2328 case VMXNET3_IT_INTX:
2329 free_irq(adapter->pdev->irq, adapter->netdev);
2330 break;
2331 default:
2332 BUG();
2333 }
2334 }
2335
2336
2337 static void
vmxnet3_restore_vlan(struct vmxnet3_adapter * adapter)2338 vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter)
2339 {
2340 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2341 u16 vid;
2342
2343 /* allow untagged pkts */
2344 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
2345
2346 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2347 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
2348 }
2349
2350
2351 static int
vmxnet3_vlan_rx_add_vid(struct net_device * netdev,__be16 proto,u16 vid)2352 vmxnet3_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid)
2353 {
2354 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2355
2356 if (!(netdev->flags & IFF_PROMISC)) {
2357 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2358 unsigned long flags;
2359
2360 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
2361 spin_lock_irqsave(&adapter->cmd_lock, flags);
2362 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2363 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2364 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2365 }
2366
2367 set_bit(vid, adapter->active_vlans);
2368
2369 return 0;
2370 }
2371
2372
2373 static int
vmxnet3_vlan_rx_kill_vid(struct net_device * netdev,__be16 proto,u16 vid)2374 vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)
2375 {
2376 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2377
2378 if (!(netdev->flags & IFF_PROMISC)) {
2379 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2380 unsigned long flags;
2381
2382 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid);
2383 spin_lock_irqsave(&adapter->cmd_lock, flags);
2384 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2385 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2386 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2387 }
2388
2389 clear_bit(vid, adapter->active_vlans);
2390
2391 return 0;
2392 }
2393
2394
2395 static u8 *
vmxnet3_copy_mc(struct net_device * netdev)2396 vmxnet3_copy_mc(struct net_device *netdev)
2397 {
2398 u8 *buf = NULL;
2399 u32 sz = netdev_mc_count(netdev) * ETH_ALEN;
2400
2401 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */
2402 if (sz <= 0xffff) {
2403 /* We may be called with BH disabled */
2404 buf = kmalloc(sz, GFP_ATOMIC);
2405 if (buf) {
2406 struct netdev_hw_addr *ha;
2407 int i = 0;
2408
2409 netdev_for_each_mc_addr(ha, netdev)
2410 memcpy(buf + i++ * ETH_ALEN, ha->addr,
2411 ETH_ALEN);
2412 }
2413 }
2414 return buf;
2415 }
2416
2417
2418 static void
vmxnet3_set_mc(struct net_device * netdev)2419 vmxnet3_set_mc(struct net_device *netdev)
2420 {
2421 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2422 unsigned long flags;
2423 struct Vmxnet3_RxFilterConf *rxConf =
2424 &adapter->shared->devRead.rxFilterConf;
2425 u8 *new_table = NULL;
2426 dma_addr_t new_table_pa = 0;
2427 bool new_table_pa_valid = false;
2428 u32 new_mode = VMXNET3_RXM_UCAST;
2429
2430 if (netdev->flags & IFF_PROMISC) {
2431 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2432 memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable));
2433
2434 new_mode |= VMXNET3_RXM_PROMISC;
2435 } else {
2436 vmxnet3_restore_vlan(adapter);
2437 }
2438
2439 if (netdev->flags & IFF_BROADCAST)
2440 new_mode |= VMXNET3_RXM_BCAST;
2441
2442 if (netdev->flags & IFF_ALLMULTI)
2443 new_mode |= VMXNET3_RXM_ALL_MULTI;
2444 else
2445 if (!netdev_mc_empty(netdev)) {
2446 new_table = vmxnet3_copy_mc(netdev);
2447 if (new_table) {
2448 size_t sz = netdev_mc_count(netdev) * ETH_ALEN;
2449
2450 rxConf->mfTableLen = cpu_to_le16(sz);
2451 new_table_pa = dma_map_single(
2452 &adapter->pdev->dev,
2453 new_table,
2454 sz,
2455 DMA_TO_DEVICE);
2456 if (!dma_mapping_error(&adapter->pdev->dev,
2457 new_table_pa)) {
2458 new_mode |= VMXNET3_RXM_MCAST;
2459 new_table_pa_valid = true;
2460 rxConf->mfTablePA = cpu_to_le64(
2461 new_table_pa);
2462 }
2463 }
2464 if (!new_table_pa_valid) {
2465 netdev_info(netdev,
2466 "failed to copy mcast list, setting ALL_MULTI\n");
2467 new_mode |= VMXNET3_RXM_ALL_MULTI;
2468 }
2469 }
2470
2471 if (!(new_mode & VMXNET3_RXM_MCAST)) {
2472 rxConf->mfTableLen = 0;
2473 rxConf->mfTablePA = 0;
2474 }
2475
2476 spin_lock_irqsave(&adapter->cmd_lock, flags);
2477 if (new_mode != rxConf->rxMode) {
2478 rxConf->rxMode = cpu_to_le32(new_mode);
2479 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2480 VMXNET3_CMD_UPDATE_RX_MODE);
2481 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2482 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2483 }
2484
2485 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2486 VMXNET3_CMD_UPDATE_MAC_FILTERS);
2487 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2488
2489 if (new_table_pa_valid)
2490 dma_unmap_single(&adapter->pdev->dev, new_table_pa,
2491 rxConf->mfTableLen, DMA_TO_DEVICE);
2492 kfree(new_table);
2493 }
2494
2495 void
vmxnet3_rq_destroy_all(struct vmxnet3_adapter * adapter)2496 vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
2497 {
2498 int i;
2499
2500 for (i = 0; i < adapter->num_rx_queues; i++)
2501 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
2502 }
2503
2504
2505 /*
2506 * Set up driver_shared based on settings in adapter.
2507 */
2508
2509 static void
vmxnet3_setup_driver_shared(struct vmxnet3_adapter * adapter)2510 vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
2511 {
2512 struct Vmxnet3_DriverShared *shared = adapter->shared;
2513 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
2514 struct Vmxnet3_DSDevReadExt *devReadExt = &shared->devReadExt;
2515 struct Vmxnet3_TxQueueConf *tqc;
2516 struct Vmxnet3_RxQueueConf *rqc;
2517 int i;
2518
2519 memset(shared, 0, sizeof(*shared));
2520
2521 /* driver settings */
2522 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
2523 devRead->misc.driverInfo.version = cpu_to_le32(
2524 VMXNET3_DRIVER_VERSION_NUM);
2525 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
2526 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
2527 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
2528 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
2529 *((u32 *)&devRead->misc.driverInfo.gos));
2530 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
2531 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
2532
2533 devRead->misc.ddPA = cpu_to_le64(adapter->adapter_pa);
2534 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
2535
2536 /* set up feature flags */
2537 if (adapter->netdev->features & NETIF_F_RXCSUM)
2538 devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
2539
2540 if (adapter->netdev->features & NETIF_F_LRO) {
2541 devRead->misc.uptFeatures |= UPT1_F_LRO;
2542 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
2543 }
2544 if (adapter->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
2545 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
2546
2547 if (adapter->netdev->features & (NETIF_F_GSO_UDP_TUNNEL |
2548 NETIF_F_GSO_UDP_TUNNEL_CSUM))
2549 devRead->misc.uptFeatures |= UPT1_F_RXINNEROFLD;
2550
2551 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
2552 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
2553 devRead->misc.queueDescLen = cpu_to_le32(
2554 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
2555 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
2556
2557 /* tx queue settings */
2558 devRead->misc.numTxQueues = adapter->num_tx_queues;
2559 for (i = 0; i < adapter->num_tx_queues; i++) {
2560 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2561 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
2562 tqc = &adapter->tqd_start[i].conf;
2563 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA);
2564 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
2565 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
2566 tqc->ddPA = cpu_to_le64(~0ULL);
2567 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size);
2568 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size);
2569 tqc->txDataRingDescSize = cpu_to_le32(tq->txdata_desc_size);
2570 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size);
2571 tqc->ddLen = cpu_to_le32(0);
2572 tqc->intrIdx = tq->comp_ring.intr_idx;
2573 }
2574
2575 /* rx queue settings */
2576 devRead->misc.numRxQueues = adapter->num_rx_queues;
2577 for (i = 0; i < adapter->num_rx_queues; i++) {
2578 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2579 rqc = &adapter->rqd_start[i].conf;
2580 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
2581 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
2582 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA);
2583 rqc->ddPA = cpu_to_le64(~0ULL);
2584 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size);
2585 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size);
2586 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size);
2587 rqc->ddLen = cpu_to_le32(0);
2588 rqc->intrIdx = rq->comp_ring.intr_idx;
2589 if (VMXNET3_VERSION_GE_3(adapter)) {
2590 rqc->rxDataRingBasePA =
2591 cpu_to_le64(rq->data_ring.basePA);
2592 rqc->rxDataRingDescSize =
2593 cpu_to_le16(rq->data_ring.desc_size);
2594 }
2595 }
2596
2597 #ifdef VMXNET3_RSS
2598 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
2599
2600 if (adapter->rss) {
2601 struct UPT1_RSSConf *rssConf = adapter->rss_conf;
2602
2603 devRead->misc.uptFeatures |= UPT1_F_RSS;
2604 devRead->misc.numRxQueues = adapter->num_rx_queues;
2605 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
2606 UPT1_RSS_HASH_TYPE_IPV4 |
2607 UPT1_RSS_HASH_TYPE_TCP_IPV6 |
2608 UPT1_RSS_HASH_TYPE_IPV6;
2609 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
2610 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
2611 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
2612 netdev_rss_key_fill(rssConf->hashKey, sizeof(rssConf->hashKey));
2613
2614 for (i = 0; i < rssConf->indTableSize; i++)
2615 rssConf->indTable[i] = ethtool_rxfh_indir_default(
2616 i, adapter->num_rx_queues);
2617
2618 devRead->rssConfDesc.confVer = 1;
2619 devRead->rssConfDesc.confLen = cpu_to_le32(sizeof(*rssConf));
2620 devRead->rssConfDesc.confPA =
2621 cpu_to_le64(adapter->rss_conf_pa);
2622 }
2623
2624 #endif /* VMXNET3_RSS */
2625
2626 /* intr settings */
2627 if (!VMXNET3_VERSION_GE_6(adapter) ||
2628 !adapter->queuesExtEnabled) {
2629 devRead->intrConf.autoMask = adapter->intr.mask_mode ==
2630 VMXNET3_IMM_AUTO;
2631 devRead->intrConf.numIntrs = adapter->intr.num_intrs;
2632 for (i = 0; i < adapter->intr.num_intrs; i++)
2633 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];
2634
2635 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx;
2636 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
2637 } else {
2638 devReadExt->intrConfExt.autoMask = adapter->intr.mask_mode ==
2639 VMXNET3_IMM_AUTO;
2640 devReadExt->intrConfExt.numIntrs = adapter->intr.num_intrs;
2641 for (i = 0; i < adapter->intr.num_intrs; i++)
2642 devReadExt->intrConfExt.modLevels[i] = adapter->intr.mod_levels[i];
2643
2644 devReadExt->intrConfExt.eventIntrIdx = adapter->intr.event_intr_idx;
2645 devReadExt->intrConfExt.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
2646 }
2647
2648 /* rx filter settings */
2649 devRead->rxFilterConf.rxMode = 0;
2650 vmxnet3_restore_vlan(adapter);
2651 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr);
2652
2653 /* the rest are already zeroed */
2654 }
2655
2656 static void
vmxnet3_init_coalesce(struct vmxnet3_adapter * adapter)2657 vmxnet3_init_coalesce(struct vmxnet3_adapter *adapter)
2658 {
2659 struct Vmxnet3_DriverShared *shared = adapter->shared;
2660 union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo;
2661 unsigned long flags;
2662
2663 if (!VMXNET3_VERSION_GE_3(adapter))
2664 return;
2665
2666 spin_lock_irqsave(&adapter->cmd_lock, flags);
2667 cmdInfo->varConf.confVer = 1;
2668 cmdInfo->varConf.confLen =
2669 cpu_to_le32(sizeof(*adapter->coal_conf));
2670 cmdInfo->varConf.confPA = cpu_to_le64(adapter->coal_conf_pa);
2671
2672 if (adapter->default_coal_mode) {
2673 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2674 VMXNET3_CMD_GET_COALESCE);
2675 } else {
2676 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2677 VMXNET3_CMD_SET_COALESCE);
2678 }
2679
2680 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2681 }
2682
2683 static void
vmxnet3_init_rssfields(struct vmxnet3_adapter * adapter)2684 vmxnet3_init_rssfields(struct vmxnet3_adapter *adapter)
2685 {
2686 struct Vmxnet3_DriverShared *shared = adapter->shared;
2687 union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo;
2688 unsigned long flags;
2689
2690 if (!VMXNET3_VERSION_GE_4(adapter))
2691 return;
2692
2693 spin_lock_irqsave(&adapter->cmd_lock, flags);
2694
2695 if (adapter->default_rss_fields) {
2696 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2697 VMXNET3_CMD_GET_RSS_FIELDS);
2698 adapter->rss_fields =
2699 VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2700 } else {
2701 cmdInfo->setRssFields = adapter->rss_fields;
2702 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2703 VMXNET3_CMD_SET_RSS_FIELDS);
2704 /* Not all requested RSS may get applied, so get and
2705 * cache what was actually applied.
2706 */
2707 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2708 VMXNET3_CMD_GET_RSS_FIELDS);
2709 adapter->rss_fields =
2710 VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2711 }
2712
2713 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2714 }
2715
2716 int
vmxnet3_activate_dev(struct vmxnet3_adapter * adapter)2717 vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
2718 {
2719 int err, i;
2720 u32 ret;
2721 unsigned long flags;
2722
2723 netdev_dbg(adapter->netdev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
2724 " ring sizes %u %u %u\n", adapter->netdev->name,
2725 adapter->skb_buf_size, adapter->rx_buf_per_pkt,
2726 adapter->tx_queue[0].tx_ring.size,
2727 adapter->rx_queue[0].rx_ring[0].size,
2728 adapter->rx_queue[0].rx_ring[1].size);
2729
2730 vmxnet3_tq_init_all(adapter);
2731 err = vmxnet3_rq_init_all(adapter);
2732 if (err) {
2733 netdev_err(adapter->netdev,
2734 "Failed to init rx queue error %d\n", err);
2735 goto rq_err;
2736 }
2737
2738 err = vmxnet3_request_irqs(adapter);
2739 if (err) {
2740 netdev_err(adapter->netdev,
2741 "Failed to setup irq for error %d\n", err);
2742 goto irq_err;
2743 }
2744
2745 vmxnet3_setup_driver_shared(adapter);
2746
2747 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
2748 adapter->shared_pa));
2749 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
2750 adapter->shared_pa));
2751 spin_lock_irqsave(&adapter->cmd_lock, flags);
2752 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2753 VMXNET3_CMD_ACTIVATE_DEV);
2754 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
2755 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2756
2757 if (ret != 0) {
2758 netdev_err(adapter->netdev,
2759 "Failed to activate dev: error %u\n", ret);
2760 err = -EINVAL;
2761 goto activate_err;
2762 }
2763
2764 vmxnet3_init_coalesce(adapter);
2765 vmxnet3_init_rssfields(adapter);
2766
2767 for (i = 0; i < adapter->num_rx_queues; i++) {
2768 VMXNET3_WRITE_BAR0_REG(adapter,
2769 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN,
2770 adapter->rx_queue[i].rx_ring[0].next2fill);
2771 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 +
2772 (i * VMXNET3_REG_ALIGN)),
2773 adapter->rx_queue[i].rx_ring[1].next2fill);
2774 }
2775
2776 /* Apply the rx filter settins last. */
2777 vmxnet3_set_mc(adapter->netdev);
2778
2779 /*
2780 * Check link state when first activating device. It will start the
2781 * tx queue if the link is up.
2782 */
2783 vmxnet3_check_link(adapter, true);
2784 netif_tx_wake_all_queues(adapter->netdev);
2785 for (i = 0; i < adapter->num_rx_queues; i++)
2786 napi_enable(&adapter->rx_queue[i].napi);
2787 vmxnet3_enable_all_intrs(adapter);
2788 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
2789 return 0;
2790
2791 activate_err:
2792 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0);
2793 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0);
2794 vmxnet3_free_irqs(adapter);
2795 irq_err:
2796 rq_err:
2797 /* free up buffers we allocated */
2798 vmxnet3_rq_cleanup_all(adapter);
2799 return err;
2800 }
2801
2802
2803 void
vmxnet3_reset_dev(struct vmxnet3_adapter * adapter)2804 vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
2805 {
2806 unsigned long flags;
2807 spin_lock_irqsave(&adapter->cmd_lock, flags);
2808 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
2809 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2810 }
2811
2812
2813 int
vmxnet3_quiesce_dev(struct vmxnet3_adapter * adapter)2814 vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
2815 {
2816 int i;
2817 unsigned long flags;
2818 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
2819 return 0;
2820
2821
2822 spin_lock_irqsave(&adapter->cmd_lock, flags);
2823 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2824 VMXNET3_CMD_QUIESCE_DEV);
2825 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2826 vmxnet3_disable_all_intrs(adapter);
2827
2828 for (i = 0; i < adapter->num_rx_queues; i++)
2829 napi_disable(&adapter->rx_queue[i].napi);
2830 netif_tx_disable(adapter->netdev);
2831 adapter->link_speed = 0;
2832 netif_carrier_off(adapter->netdev);
2833
2834 vmxnet3_tq_cleanup_all(adapter);
2835 vmxnet3_rq_cleanup_all(adapter);
2836 vmxnet3_free_irqs(adapter);
2837 return 0;
2838 }
2839
2840
2841 static void
vmxnet3_write_mac_addr(struct vmxnet3_adapter * adapter,u8 * mac)2842 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2843 {
2844 u32 tmp;
2845
2846 tmp = *(u32 *)mac;
2847 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp);
2848
2849 tmp = (mac[5] << 8) | mac[4];
2850 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp);
2851 }
2852
2853
2854 static int
vmxnet3_set_mac_addr(struct net_device * netdev,void * p)2855 vmxnet3_set_mac_addr(struct net_device *netdev, void *p)
2856 {
2857 struct sockaddr *addr = p;
2858 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2859
2860 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2861 vmxnet3_write_mac_addr(adapter, addr->sa_data);
2862
2863 return 0;
2864 }
2865
2866
2867 /* ==================== initialization and cleanup routines ============ */
2868
2869 static int
vmxnet3_alloc_pci_resources(struct vmxnet3_adapter * adapter)2870 vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter)
2871 {
2872 int err;
2873 unsigned long mmio_start, mmio_len;
2874 struct pci_dev *pdev = adapter->pdev;
2875
2876 err = pci_enable_device(pdev);
2877 if (err) {
2878 dev_err(&pdev->dev, "Failed to enable adapter: error %d\n", err);
2879 return err;
2880 }
2881
2882 err = pci_request_selected_regions(pdev, (1 << 2) - 1,
2883 vmxnet3_driver_name);
2884 if (err) {
2885 dev_err(&pdev->dev,
2886 "Failed to request region for adapter: error %d\n", err);
2887 goto err_enable_device;
2888 }
2889
2890 pci_set_master(pdev);
2891
2892 mmio_start = pci_resource_start(pdev, 0);
2893 mmio_len = pci_resource_len(pdev, 0);
2894 adapter->hw_addr0 = ioremap(mmio_start, mmio_len);
2895 if (!adapter->hw_addr0) {
2896 dev_err(&pdev->dev, "Failed to map bar0\n");
2897 err = -EIO;
2898 goto err_ioremap;
2899 }
2900
2901 mmio_start = pci_resource_start(pdev, 1);
2902 mmio_len = pci_resource_len(pdev, 1);
2903 adapter->hw_addr1 = ioremap(mmio_start, mmio_len);
2904 if (!adapter->hw_addr1) {
2905 dev_err(&pdev->dev, "Failed to map bar1\n");
2906 err = -EIO;
2907 goto err_bar1;
2908 }
2909 return 0;
2910
2911 err_bar1:
2912 iounmap(adapter->hw_addr0);
2913 err_ioremap:
2914 pci_release_selected_regions(pdev, (1 << 2) - 1);
2915 err_enable_device:
2916 pci_disable_device(pdev);
2917 return err;
2918 }
2919
2920
2921 static void
vmxnet3_free_pci_resources(struct vmxnet3_adapter * adapter)2922 vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
2923 {
2924 BUG_ON(!adapter->pdev);
2925
2926 iounmap(adapter->hw_addr0);
2927 iounmap(adapter->hw_addr1);
2928 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1);
2929 pci_disable_device(adapter->pdev);
2930 }
2931
2932
2933 static void
vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter * adapter)2934 vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
2935 {
2936 size_t sz, i, ring0_size, ring1_size, comp_size;
2937 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
2938 VMXNET3_MAX_ETH_HDR_SIZE) {
2939 adapter->skb_buf_size = adapter->netdev->mtu +
2940 VMXNET3_MAX_ETH_HDR_SIZE;
2941 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE)
2942 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE;
2943
2944 adapter->rx_buf_per_pkt = 1;
2945 } else {
2946 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE;
2947 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE +
2948 VMXNET3_MAX_ETH_HDR_SIZE;
2949 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE;
2950 }
2951
2952 /*
2953 * for simplicity, force the ring0 size to be a multiple of
2954 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
2955 */
2956 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
2957 ring0_size = adapter->rx_queue[0].rx_ring[0].size;
2958 ring0_size = (ring0_size + sz - 1) / sz * sz;
2959 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE /
2960 sz * sz);
2961 ring1_size = adapter->rx_queue[0].rx_ring[1].size;
2962 ring1_size = (ring1_size + sz - 1) / sz * sz;
2963 ring1_size = min_t(u32, ring1_size, VMXNET3_RX_RING2_MAX_SIZE /
2964 sz * sz);
2965 comp_size = ring0_size + ring1_size;
2966
2967 for (i = 0; i < adapter->num_rx_queues; i++) {
2968 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2969
2970 rq->rx_ring[0].size = ring0_size;
2971 rq->rx_ring[1].size = ring1_size;
2972 rq->comp_ring.size = comp_size;
2973 }
2974 }
2975
2976
2977 int
vmxnet3_create_queues(struct vmxnet3_adapter * adapter,u32 tx_ring_size,u32 rx_ring_size,u32 rx_ring2_size,u16 txdata_desc_size,u16 rxdata_desc_size)2978 vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
2979 u32 rx_ring_size, u32 rx_ring2_size,
2980 u16 txdata_desc_size, u16 rxdata_desc_size)
2981 {
2982 int err = 0, i;
2983
2984 for (i = 0; i < adapter->num_tx_queues; i++) {
2985 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2986 tq->tx_ring.size = tx_ring_size;
2987 tq->data_ring.size = tx_ring_size;
2988 tq->comp_ring.size = tx_ring_size;
2989 tq->txdata_desc_size = txdata_desc_size;
2990 tq->shared = &adapter->tqd_start[i].ctrl;
2991 tq->stopped = true;
2992 tq->adapter = adapter;
2993 tq->qid = i;
2994 err = vmxnet3_tq_create(tq, adapter);
2995 /*
2996 * Too late to change num_tx_queues. We cannot do away with
2997 * lesser number of queues than what we asked for
2998 */
2999 if (err)
3000 goto queue_err;
3001 }
3002
3003 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
3004 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
3005 vmxnet3_adjust_rx_ring_size(adapter);
3006
3007 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter);
3008 for (i = 0; i < adapter->num_rx_queues; i++) {
3009 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
3010 /* qid and qid2 for rx queues will be assigned later when num
3011 * of rx queues is finalized after allocating intrs */
3012 rq->shared = &adapter->rqd_start[i].ctrl;
3013 rq->adapter = adapter;
3014 rq->data_ring.desc_size = rxdata_desc_size;
3015 err = vmxnet3_rq_create(rq, adapter);
3016 if (err) {
3017 if (i == 0) {
3018 netdev_err(adapter->netdev,
3019 "Could not allocate any rx queues. "
3020 "Aborting.\n");
3021 goto queue_err;
3022 } else {
3023 netdev_info(adapter->netdev,
3024 "Number of rx queues changed "
3025 "to : %d.\n", i);
3026 adapter->num_rx_queues = i;
3027 err = 0;
3028 break;
3029 }
3030 }
3031 }
3032
3033 if (!adapter->rxdataring_enabled)
3034 vmxnet3_rq_destroy_all_rxdataring(adapter);
3035
3036 return err;
3037 queue_err:
3038 vmxnet3_tq_destroy_all(adapter);
3039 return err;
3040 }
3041
3042 static int
vmxnet3_open(struct net_device * netdev)3043 vmxnet3_open(struct net_device *netdev)
3044 {
3045 struct vmxnet3_adapter *adapter;
3046 int err, i;
3047
3048 adapter = netdev_priv(netdev);
3049
3050 for (i = 0; i < adapter->num_tx_queues; i++)
3051 spin_lock_init(&adapter->tx_queue[i].tx_lock);
3052
3053 if (VMXNET3_VERSION_GE_3(adapter)) {
3054 unsigned long flags;
3055 u16 txdata_desc_size;
3056
3057 spin_lock_irqsave(&adapter->cmd_lock, flags);
3058 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3059 VMXNET3_CMD_GET_TXDATA_DESC_SIZE);
3060 txdata_desc_size = VMXNET3_READ_BAR1_REG(adapter,
3061 VMXNET3_REG_CMD);
3062 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3063
3064 if ((txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE) ||
3065 (txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE) ||
3066 (txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK)) {
3067 adapter->txdata_desc_size =
3068 sizeof(struct Vmxnet3_TxDataDesc);
3069 } else {
3070 adapter->txdata_desc_size = txdata_desc_size;
3071 }
3072 } else {
3073 adapter->txdata_desc_size = sizeof(struct Vmxnet3_TxDataDesc);
3074 }
3075
3076 err = vmxnet3_create_queues(adapter,
3077 adapter->tx_ring_size,
3078 adapter->rx_ring_size,
3079 adapter->rx_ring2_size,
3080 adapter->txdata_desc_size,
3081 adapter->rxdata_desc_size);
3082 if (err)
3083 goto queue_err;
3084
3085 err = vmxnet3_activate_dev(adapter);
3086 if (err)
3087 goto activate_err;
3088
3089 return 0;
3090
3091 activate_err:
3092 vmxnet3_rq_destroy_all(adapter);
3093 vmxnet3_tq_destroy_all(adapter);
3094 queue_err:
3095 return err;
3096 }
3097
3098
3099 static int
vmxnet3_close(struct net_device * netdev)3100 vmxnet3_close(struct net_device *netdev)
3101 {
3102 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3103
3104 /*
3105 * Reset_work may be in the middle of resetting the device, wait for its
3106 * completion.
3107 */
3108 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3109 usleep_range(1000, 2000);
3110
3111 vmxnet3_quiesce_dev(adapter);
3112
3113 vmxnet3_rq_destroy_all(adapter);
3114 vmxnet3_tq_destroy_all(adapter);
3115
3116 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3117
3118
3119 return 0;
3120 }
3121
3122
3123 void
vmxnet3_force_close(struct vmxnet3_adapter * adapter)3124 vmxnet3_force_close(struct vmxnet3_adapter *adapter)
3125 {
3126 int i;
3127
3128 /*
3129 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
3130 * vmxnet3_close() will deadlock.
3131 */
3132 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
3133
3134 /* we need to enable NAPI, otherwise dev_close will deadlock */
3135 for (i = 0; i < adapter->num_rx_queues; i++)
3136 napi_enable(&adapter->rx_queue[i].napi);
3137 /*
3138 * Need to clear the quiesce bit to ensure that vmxnet3_close
3139 * can quiesce the device properly
3140 */
3141 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
3142 dev_close(adapter->netdev);
3143 }
3144
3145
3146 static int
vmxnet3_change_mtu(struct net_device * netdev,int new_mtu)3147 vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
3148 {
3149 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3150 int err = 0;
3151
3152 netdev->mtu = new_mtu;
3153
3154 /*
3155 * Reset_work may be in the middle of resetting the device, wait for its
3156 * completion.
3157 */
3158 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3159 usleep_range(1000, 2000);
3160
3161 if (netif_running(netdev)) {
3162 vmxnet3_quiesce_dev(adapter);
3163 vmxnet3_reset_dev(adapter);
3164
3165 /* we need to re-create the rx queue based on the new mtu */
3166 vmxnet3_rq_destroy_all(adapter);
3167 vmxnet3_adjust_rx_ring_size(adapter);
3168 err = vmxnet3_rq_create_all(adapter);
3169 if (err) {
3170 netdev_err(netdev,
3171 "failed to re-create rx queues, "
3172 " error %d. Closing it.\n", err);
3173 goto out;
3174 }
3175
3176 err = vmxnet3_activate_dev(adapter);
3177 if (err) {
3178 netdev_err(netdev,
3179 "failed to re-activate, error %d. "
3180 "Closing it\n", err);
3181 goto out;
3182 }
3183 }
3184
3185 out:
3186 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3187 if (err)
3188 vmxnet3_force_close(adapter);
3189
3190 return err;
3191 }
3192
3193
3194 static void
vmxnet3_declare_features(struct vmxnet3_adapter * adapter,bool dma64)3195 vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64)
3196 {
3197 struct net_device *netdev = adapter->netdev;
3198
3199 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
3200 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX |
3201 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 |
3202 NETIF_F_LRO;
3203
3204 if (VMXNET3_VERSION_GE_4(adapter)) {
3205 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3206 NETIF_F_GSO_UDP_TUNNEL_CSUM;
3207
3208 netdev->hw_enc_features = NETIF_F_SG | NETIF_F_RXCSUM |
3209 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX |
3210 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 |
3211 NETIF_F_LRO | NETIF_F_GSO_UDP_TUNNEL |
3212 NETIF_F_GSO_UDP_TUNNEL_CSUM;
3213 }
3214
3215 if (dma64)
3216 netdev->hw_features |= NETIF_F_HIGHDMA;
3217 netdev->vlan_features = netdev->hw_features &
3218 ~(NETIF_F_HW_VLAN_CTAG_TX |
3219 NETIF_F_HW_VLAN_CTAG_RX);
3220 netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
3221 }
3222
3223
3224 static void
vmxnet3_read_mac_addr(struct vmxnet3_adapter * adapter,u8 * mac)3225 vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
3226 {
3227 u32 tmp;
3228
3229 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL);
3230 *(u32 *)mac = tmp;
3231
3232 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH);
3233 mac[4] = tmp & 0xff;
3234 mac[5] = (tmp >> 8) & 0xff;
3235 }
3236
3237 #ifdef CONFIG_PCI_MSI
3238
3239 /*
3240 * Enable MSIx vectors.
3241 * Returns :
3242 * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required
3243 * were enabled.
3244 * number of vectors which were enabled otherwise (this number is greater
3245 * than VMXNET3_LINUX_MIN_MSIX_VECT)
3246 */
3247
3248 static int
vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter * adapter,int nvec)3249 vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter, int nvec)
3250 {
3251 int ret = pci_enable_msix_range(adapter->pdev,
3252 adapter->intr.msix_entries, nvec, nvec);
3253
3254 if (ret == -ENOSPC && nvec > VMXNET3_LINUX_MIN_MSIX_VECT) {
3255 dev_err(&adapter->netdev->dev,
3256 "Failed to enable %d MSI-X, trying %d\n",
3257 nvec, VMXNET3_LINUX_MIN_MSIX_VECT);
3258
3259 ret = pci_enable_msix_range(adapter->pdev,
3260 adapter->intr.msix_entries,
3261 VMXNET3_LINUX_MIN_MSIX_VECT,
3262 VMXNET3_LINUX_MIN_MSIX_VECT);
3263 }
3264
3265 if (ret < 0) {
3266 dev_err(&adapter->netdev->dev,
3267 "Failed to enable MSI-X, error: %d\n", ret);
3268 }
3269
3270 return ret;
3271 }
3272
3273
3274 #endif /* CONFIG_PCI_MSI */
3275
3276 static void
vmxnet3_alloc_intr_resources(struct vmxnet3_adapter * adapter)3277 vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
3278 {
3279 u32 cfg;
3280 unsigned long flags;
3281
3282 /* intr settings */
3283 spin_lock_irqsave(&adapter->cmd_lock, flags);
3284 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3285 VMXNET3_CMD_GET_CONF_INTR);
3286 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
3287 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3288 adapter->intr.type = cfg & 0x3;
3289 adapter->intr.mask_mode = (cfg >> 2) & 0x3;
3290
3291 if (adapter->intr.type == VMXNET3_IT_AUTO) {
3292 adapter->intr.type = VMXNET3_IT_MSIX;
3293 }
3294
3295 #ifdef CONFIG_PCI_MSI
3296 if (adapter->intr.type == VMXNET3_IT_MSIX) {
3297 int i, nvec, nvec_allocated;
3298
3299 nvec = adapter->share_intr == VMXNET3_INTR_TXSHARE ?
3300 1 : adapter->num_tx_queues;
3301 nvec += adapter->share_intr == VMXNET3_INTR_BUDDYSHARE ?
3302 0 : adapter->num_rx_queues;
3303 nvec += 1; /* for link event */
3304 nvec = nvec > VMXNET3_LINUX_MIN_MSIX_VECT ?
3305 nvec : VMXNET3_LINUX_MIN_MSIX_VECT;
3306
3307 for (i = 0; i < nvec; i++)
3308 adapter->intr.msix_entries[i].entry = i;
3309
3310 nvec_allocated = vmxnet3_acquire_msix_vectors(adapter, nvec);
3311 if (nvec_allocated < 0)
3312 goto msix_err;
3313
3314 /* If we cannot allocate one MSIx vector per queue
3315 * then limit the number of rx queues to 1
3316 */
3317 if (nvec_allocated == VMXNET3_LINUX_MIN_MSIX_VECT &&
3318 nvec != VMXNET3_LINUX_MIN_MSIX_VECT) {
3319 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
3320 || adapter->num_rx_queues != 1) {
3321 adapter->share_intr = VMXNET3_INTR_TXSHARE;
3322 netdev_err(adapter->netdev,
3323 "Number of rx queues : 1\n");
3324 adapter->num_rx_queues = 1;
3325 }
3326 }
3327
3328 adapter->intr.num_intrs = nvec_allocated;
3329 return;
3330
3331 msix_err:
3332 /* If we cannot allocate MSIx vectors use only one rx queue */
3333 dev_info(&adapter->pdev->dev,
3334 "Failed to enable MSI-X, error %d. "
3335 "Limiting #rx queues to 1, try MSI.\n", nvec_allocated);
3336
3337 adapter->intr.type = VMXNET3_IT_MSI;
3338 }
3339
3340 if (adapter->intr.type == VMXNET3_IT_MSI) {
3341 if (!pci_enable_msi(adapter->pdev)) {
3342 adapter->num_rx_queues = 1;
3343 adapter->intr.num_intrs = 1;
3344 return;
3345 }
3346 }
3347 #endif /* CONFIG_PCI_MSI */
3348
3349 adapter->num_rx_queues = 1;
3350 dev_info(&adapter->netdev->dev,
3351 "Using INTx interrupt, #Rx queues: 1.\n");
3352 adapter->intr.type = VMXNET3_IT_INTX;
3353
3354 /* INT-X related setting */
3355 adapter->intr.num_intrs = 1;
3356 }
3357
3358
3359 static void
vmxnet3_free_intr_resources(struct vmxnet3_adapter * adapter)3360 vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter)
3361 {
3362 if (adapter->intr.type == VMXNET3_IT_MSIX)
3363 pci_disable_msix(adapter->pdev);
3364 else if (adapter->intr.type == VMXNET3_IT_MSI)
3365 pci_disable_msi(adapter->pdev);
3366 else
3367 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX);
3368 }
3369
3370
3371 static void
vmxnet3_tx_timeout(struct net_device * netdev,unsigned int txqueue)3372 vmxnet3_tx_timeout(struct net_device *netdev, unsigned int txqueue)
3373 {
3374 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3375 adapter->tx_timeout_count++;
3376
3377 netdev_err(adapter->netdev, "tx hang\n");
3378 schedule_work(&adapter->work);
3379 }
3380
3381
3382 static void
vmxnet3_reset_work(struct work_struct * data)3383 vmxnet3_reset_work(struct work_struct *data)
3384 {
3385 struct vmxnet3_adapter *adapter;
3386
3387 adapter = container_of(data, struct vmxnet3_adapter, work);
3388
3389 /* if another thread is resetting the device, no need to proceed */
3390 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3391 return;
3392
3393 /* if the device is closed, we must leave it alone */
3394 rtnl_lock();
3395 if (netif_running(adapter->netdev)) {
3396 netdev_notice(adapter->netdev, "resetting\n");
3397 vmxnet3_quiesce_dev(adapter);
3398 vmxnet3_reset_dev(adapter);
3399 vmxnet3_activate_dev(adapter);
3400 } else {
3401 netdev_info(adapter->netdev, "already closed\n");
3402 }
3403 rtnl_unlock();
3404
3405 netif_wake_queue(adapter->netdev);
3406 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3407 }
3408
3409
3410 static int
vmxnet3_probe_device(struct pci_dev * pdev,const struct pci_device_id * id)3411 vmxnet3_probe_device(struct pci_dev *pdev,
3412 const struct pci_device_id *id)
3413 {
3414 static const struct net_device_ops vmxnet3_netdev_ops = {
3415 .ndo_open = vmxnet3_open,
3416 .ndo_stop = vmxnet3_close,
3417 .ndo_start_xmit = vmxnet3_xmit_frame,
3418 .ndo_set_mac_address = vmxnet3_set_mac_addr,
3419 .ndo_change_mtu = vmxnet3_change_mtu,
3420 .ndo_fix_features = vmxnet3_fix_features,
3421 .ndo_set_features = vmxnet3_set_features,
3422 .ndo_features_check = vmxnet3_features_check,
3423 .ndo_get_stats64 = vmxnet3_get_stats64,
3424 .ndo_tx_timeout = vmxnet3_tx_timeout,
3425 .ndo_set_rx_mode = vmxnet3_set_mc,
3426 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid,
3427 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid,
3428 #ifdef CONFIG_NET_POLL_CONTROLLER
3429 .ndo_poll_controller = vmxnet3_netpoll,
3430 #endif
3431 };
3432 int err;
3433 bool dma64;
3434 u32 ver;
3435 struct net_device *netdev;
3436 struct vmxnet3_adapter *adapter;
3437 u8 mac[ETH_ALEN];
3438 int size;
3439 int num_tx_queues;
3440 int num_rx_queues;
3441 int queues;
3442 unsigned long flags;
3443
3444 if (!pci_msi_enabled())
3445 enable_mq = 0;
3446
3447 #ifdef VMXNET3_RSS
3448 if (enable_mq)
3449 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3450 (int)num_online_cpus());
3451 else
3452 #endif
3453 num_rx_queues = 1;
3454
3455 if (enable_mq)
3456 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
3457 (int)num_online_cpus());
3458 else
3459 num_tx_queues = 1;
3460
3461 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
3462 max(num_tx_queues, num_rx_queues));
3463 if (!netdev)
3464 return -ENOMEM;
3465
3466 pci_set_drvdata(pdev, netdev);
3467 adapter = netdev_priv(netdev);
3468 adapter->netdev = netdev;
3469 adapter->pdev = pdev;
3470
3471 adapter->tx_ring_size = VMXNET3_DEF_TX_RING_SIZE;
3472 adapter->rx_ring_size = VMXNET3_DEF_RX_RING_SIZE;
3473 adapter->rx_ring2_size = VMXNET3_DEF_RX_RING2_SIZE;
3474
3475 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) == 0) {
3476 dma64 = true;
3477 } else {
3478 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
3479 if (err) {
3480 dev_err(&pdev->dev, "dma_set_mask failed\n");
3481 goto err_set_mask;
3482 }
3483 dma64 = false;
3484 }
3485
3486 spin_lock_init(&adapter->cmd_lock);
3487 adapter->adapter_pa = dma_map_single(&adapter->pdev->dev, adapter,
3488 sizeof(struct vmxnet3_adapter),
3489 DMA_TO_DEVICE);
3490 if (dma_mapping_error(&adapter->pdev->dev, adapter->adapter_pa)) {
3491 dev_err(&pdev->dev, "Failed to map dma\n");
3492 err = -EFAULT;
3493 goto err_set_mask;
3494 }
3495 adapter->shared = dma_alloc_coherent(
3496 &adapter->pdev->dev,
3497 sizeof(struct Vmxnet3_DriverShared),
3498 &adapter->shared_pa, GFP_KERNEL);
3499 if (!adapter->shared) {
3500 dev_err(&pdev->dev, "Failed to allocate memory\n");
3501 err = -ENOMEM;
3502 goto err_alloc_shared;
3503 }
3504
3505 err = vmxnet3_alloc_pci_resources(adapter);
3506 if (err < 0)
3507 goto err_alloc_pci;
3508
3509 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS);
3510 if (ver & (1 << VMXNET3_REV_6)) {
3511 VMXNET3_WRITE_BAR1_REG(adapter,
3512 VMXNET3_REG_VRRS,
3513 1 << VMXNET3_REV_6);
3514 adapter->version = VMXNET3_REV_6 + 1;
3515 } else if (ver & (1 << VMXNET3_REV_5)) {
3516 VMXNET3_WRITE_BAR1_REG(adapter,
3517 VMXNET3_REG_VRRS,
3518 1 << VMXNET3_REV_5);
3519 adapter->version = VMXNET3_REV_5 + 1;
3520 } else if (ver & (1 << VMXNET3_REV_4)) {
3521 VMXNET3_WRITE_BAR1_REG(adapter,
3522 VMXNET3_REG_VRRS,
3523 1 << VMXNET3_REV_4);
3524 adapter->version = VMXNET3_REV_4 + 1;
3525 } else if (ver & (1 << VMXNET3_REV_3)) {
3526 VMXNET3_WRITE_BAR1_REG(adapter,
3527 VMXNET3_REG_VRRS,
3528 1 << VMXNET3_REV_3);
3529 adapter->version = VMXNET3_REV_3 + 1;
3530 } else if (ver & (1 << VMXNET3_REV_2)) {
3531 VMXNET3_WRITE_BAR1_REG(adapter,
3532 VMXNET3_REG_VRRS,
3533 1 << VMXNET3_REV_2);
3534 adapter->version = VMXNET3_REV_2 + 1;
3535 } else if (ver & (1 << VMXNET3_REV_1)) {
3536 VMXNET3_WRITE_BAR1_REG(adapter,
3537 VMXNET3_REG_VRRS,
3538 1 << VMXNET3_REV_1);
3539 adapter->version = VMXNET3_REV_1 + 1;
3540 } else {
3541 dev_err(&pdev->dev,
3542 "Incompatible h/w version (0x%x) for adapter\n", ver);
3543 err = -EBUSY;
3544 goto err_ver;
3545 }
3546 dev_dbg(&pdev->dev, "Using device version %d\n", adapter->version);
3547
3548 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS);
3549 if (ver & 1) {
3550 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1);
3551 } else {
3552 dev_err(&pdev->dev,
3553 "Incompatible upt version (0x%x) for adapter\n", ver);
3554 err = -EBUSY;
3555 goto err_ver;
3556 }
3557
3558 if (VMXNET3_VERSION_GE_6(adapter)) {
3559 spin_lock_irqsave(&adapter->cmd_lock, flags);
3560 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3561 VMXNET3_CMD_GET_MAX_QUEUES_CONF);
3562 queues = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
3563 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3564 if (queues > 0) {
3565 adapter->num_rx_queues = min(num_rx_queues, ((queues >> 8) & 0xff));
3566 adapter->num_tx_queues = min(num_tx_queues, (queues & 0xff));
3567 } else {
3568 adapter->num_rx_queues = min(num_rx_queues,
3569 VMXNET3_DEVICE_DEFAULT_RX_QUEUES);
3570 adapter->num_tx_queues = min(num_tx_queues,
3571 VMXNET3_DEVICE_DEFAULT_TX_QUEUES);
3572 }
3573 if (adapter->num_rx_queues > VMXNET3_MAX_RX_QUEUES ||
3574 adapter->num_tx_queues > VMXNET3_MAX_TX_QUEUES) {
3575 adapter->queuesExtEnabled = true;
3576 } else {
3577 adapter->queuesExtEnabled = false;
3578 }
3579 } else {
3580 adapter->queuesExtEnabled = false;
3581 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
3582 num_tx_queues = rounddown_pow_of_two(num_tx_queues);
3583 adapter->num_rx_queues = min(num_rx_queues,
3584 VMXNET3_DEVICE_DEFAULT_RX_QUEUES);
3585 adapter->num_tx_queues = min(num_tx_queues,
3586 VMXNET3_DEVICE_DEFAULT_TX_QUEUES);
3587 }
3588 dev_info(&pdev->dev,
3589 "# of Tx queues : %d, # of Rx queues : %d\n",
3590 adapter->num_tx_queues, adapter->num_rx_queues);
3591
3592 adapter->rx_buf_per_pkt = 1;
3593
3594 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3595 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
3596 adapter->tqd_start = dma_alloc_coherent(&adapter->pdev->dev, size,
3597 &adapter->queue_desc_pa,
3598 GFP_KERNEL);
3599
3600 if (!adapter->tqd_start) {
3601 dev_err(&pdev->dev, "Failed to allocate memory\n");
3602 err = -ENOMEM;
3603 goto err_ver;
3604 }
3605 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
3606 adapter->num_tx_queues);
3607
3608 adapter->pm_conf = dma_alloc_coherent(&adapter->pdev->dev,
3609 sizeof(struct Vmxnet3_PMConf),
3610 &adapter->pm_conf_pa,
3611 GFP_KERNEL);
3612 if (adapter->pm_conf == NULL) {
3613 err = -ENOMEM;
3614 goto err_alloc_pm;
3615 }
3616
3617 #ifdef VMXNET3_RSS
3618
3619 adapter->rss_conf = dma_alloc_coherent(&adapter->pdev->dev,
3620 sizeof(struct UPT1_RSSConf),
3621 &adapter->rss_conf_pa,
3622 GFP_KERNEL);
3623 if (adapter->rss_conf == NULL) {
3624 err = -ENOMEM;
3625 goto err_alloc_rss;
3626 }
3627 #endif /* VMXNET3_RSS */
3628
3629 if (VMXNET3_VERSION_GE_3(adapter)) {
3630 adapter->coal_conf =
3631 dma_alloc_coherent(&adapter->pdev->dev,
3632 sizeof(struct Vmxnet3_CoalesceScheme)
3633 ,
3634 &adapter->coal_conf_pa,
3635 GFP_KERNEL);
3636 if (!adapter->coal_conf) {
3637 err = -ENOMEM;
3638 goto err_coal_conf;
3639 }
3640 adapter->coal_conf->coalMode = VMXNET3_COALESCE_DISABLED;
3641 adapter->default_coal_mode = true;
3642 }
3643
3644 if (VMXNET3_VERSION_GE_4(adapter)) {
3645 adapter->default_rss_fields = true;
3646 adapter->rss_fields = VMXNET3_RSS_FIELDS_DEFAULT;
3647 }
3648
3649 SET_NETDEV_DEV(netdev, &pdev->dev);
3650 vmxnet3_declare_features(adapter, dma64);
3651
3652 adapter->rxdata_desc_size = VMXNET3_VERSION_GE_3(adapter) ?
3653 VMXNET3_DEF_RXDATA_DESC_SIZE : 0;
3654
3655 if (adapter->num_tx_queues == adapter->num_rx_queues)
3656 adapter->share_intr = VMXNET3_INTR_BUDDYSHARE;
3657 else
3658 adapter->share_intr = VMXNET3_INTR_DONTSHARE;
3659
3660 vmxnet3_alloc_intr_resources(adapter);
3661
3662 #ifdef VMXNET3_RSS
3663 if (adapter->num_rx_queues > 1 &&
3664 adapter->intr.type == VMXNET3_IT_MSIX) {
3665 adapter->rss = true;
3666 netdev->hw_features |= NETIF_F_RXHASH;
3667 netdev->features |= NETIF_F_RXHASH;
3668 dev_dbg(&pdev->dev, "RSS is enabled.\n");
3669 } else {
3670 adapter->rss = false;
3671 }
3672 #endif
3673
3674 vmxnet3_read_mac_addr(adapter, mac);
3675 memcpy(netdev->dev_addr, mac, netdev->addr_len);
3676
3677 netdev->netdev_ops = &vmxnet3_netdev_ops;
3678 vmxnet3_set_ethtool_ops(netdev);
3679 netdev->watchdog_timeo = 5 * HZ;
3680
3681 /* MTU range: 60 - 9190 */
3682 netdev->min_mtu = VMXNET3_MIN_MTU;
3683 if (VMXNET3_VERSION_GE_6(adapter))
3684 netdev->max_mtu = VMXNET3_V6_MAX_MTU;
3685 else
3686 netdev->max_mtu = VMXNET3_MAX_MTU;
3687
3688 INIT_WORK(&adapter->work, vmxnet3_reset_work);
3689 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
3690
3691 if (adapter->intr.type == VMXNET3_IT_MSIX) {
3692 int i;
3693 for (i = 0; i < adapter->num_rx_queues; i++) {
3694 netif_napi_add(adapter->netdev,
3695 &adapter->rx_queue[i].napi,
3696 vmxnet3_poll_rx_only, 64);
3697 }
3698 } else {
3699 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
3700 vmxnet3_poll, 64);
3701 }
3702
3703 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
3704 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
3705
3706 netif_carrier_off(netdev);
3707 err = register_netdev(netdev);
3708
3709 if (err) {
3710 dev_err(&pdev->dev, "Failed to register adapter\n");
3711 goto err_register;
3712 }
3713
3714 vmxnet3_check_link(adapter, false);
3715 return 0;
3716
3717 err_register:
3718 if (VMXNET3_VERSION_GE_3(adapter)) {
3719 dma_free_coherent(&adapter->pdev->dev,
3720 sizeof(struct Vmxnet3_CoalesceScheme),
3721 adapter->coal_conf, adapter->coal_conf_pa);
3722 }
3723 vmxnet3_free_intr_resources(adapter);
3724 err_coal_conf:
3725 #ifdef VMXNET3_RSS
3726 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
3727 adapter->rss_conf, adapter->rss_conf_pa);
3728 err_alloc_rss:
3729 #endif
3730 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
3731 adapter->pm_conf, adapter->pm_conf_pa);
3732 err_alloc_pm:
3733 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
3734 adapter->queue_desc_pa);
3735 err_ver:
3736 vmxnet3_free_pci_resources(adapter);
3737 err_alloc_pci:
3738 dma_free_coherent(&adapter->pdev->dev,
3739 sizeof(struct Vmxnet3_DriverShared),
3740 adapter->shared, adapter->shared_pa);
3741 err_alloc_shared:
3742 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
3743 sizeof(struct vmxnet3_adapter), DMA_TO_DEVICE);
3744 err_set_mask:
3745 free_netdev(netdev);
3746 return err;
3747 }
3748
3749
3750 static void
vmxnet3_remove_device(struct pci_dev * pdev)3751 vmxnet3_remove_device(struct pci_dev *pdev)
3752 {
3753 struct net_device *netdev = pci_get_drvdata(pdev);
3754 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3755 int size = 0;
3756 int num_rx_queues, rx_queues;
3757 unsigned long flags;
3758
3759 #ifdef VMXNET3_RSS
3760 if (enable_mq)
3761 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3762 (int)num_online_cpus());
3763 else
3764 #endif
3765 num_rx_queues = 1;
3766 if (!VMXNET3_VERSION_GE_6(adapter)) {
3767 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
3768 }
3769 if (VMXNET3_VERSION_GE_6(adapter)) {
3770 spin_lock_irqsave(&adapter->cmd_lock, flags);
3771 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3772 VMXNET3_CMD_GET_MAX_QUEUES_CONF);
3773 rx_queues = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
3774 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3775 if (rx_queues > 0)
3776 rx_queues = (rx_queues >> 8) & 0xff;
3777 else
3778 rx_queues = min(num_rx_queues, VMXNET3_DEVICE_DEFAULT_RX_QUEUES);
3779 num_rx_queues = min(num_rx_queues, rx_queues);
3780 } else {
3781 num_rx_queues = min(num_rx_queues,
3782 VMXNET3_DEVICE_DEFAULT_RX_QUEUES);
3783 }
3784
3785 cancel_work_sync(&adapter->work);
3786
3787 unregister_netdev(netdev);
3788
3789 vmxnet3_free_intr_resources(adapter);
3790 vmxnet3_free_pci_resources(adapter);
3791 if (VMXNET3_VERSION_GE_3(adapter)) {
3792 dma_free_coherent(&adapter->pdev->dev,
3793 sizeof(struct Vmxnet3_CoalesceScheme),
3794 adapter->coal_conf, adapter->coal_conf_pa);
3795 }
3796 #ifdef VMXNET3_RSS
3797 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
3798 adapter->rss_conf, adapter->rss_conf_pa);
3799 #endif
3800 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
3801 adapter->pm_conf, adapter->pm_conf_pa);
3802
3803 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3804 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
3805 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
3806 adapter->queue_desc_pa);
3807 dma_free_coherent(&adapter->pdev->dev,
3808 sizeof(struct Vmxnet3_DriverShared),
3809 adapter->shared, adapter->shared_pa);
3810 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
3811 sizeof(struct vmxnet3_adapter), DMA_TO_DEVICE);
3812 free_netdev(netdev);
3813 }
3814
vmxnet3_shutdown_device(struct pci_dev * pdev)3815 static void vmxnet3_shutdown_device(struct pci_dev *pdev)
3816 {
3817 struct net_device *netdev = pci_get_drvdata(pdev);
3818 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3819 unsigned long flags;
3820
3821 /* Reset_work may be in the middle of resetting the device, wait for its
3822 * completion.
3823 */
3824 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3825 usleep_range(1000, 2000);
3826
3827 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED,
3828 &adapter->state)) {
3829 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3830 return;
3831 }
3832 spin_lock_irqsave(&adapter->cmd_lock, flags);
3833 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3834 VMXNET3_CMD_QUIESCE_DEV);
3835 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3836 vmxnet3_disable_all_intrs(adapter);
3837
3838 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3839 }
3840
3841
3842 #ifdef CONFIG_PM
3843
3844 static int
vmxnet3_suspend(struct device * device)3845 vmxnet3_suspend(struct device *device)
3846 {
3847 struct pci_dev *pdev = to_pci_dev(device);
3848 struct net_device *netdev = pci_get_drvdata(pdev);
3849 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3850 struct Vmxnet3_PMConf *pmConf;
3851 struct ethhdr *ehdr;
3852 struct arphdr *ahdr;
3853 u8 *arpreq;
3854 struct in_device *in_dev;
3855 struct in_ifaddr *ifa;
3856 unsigned long flags;
3857 int i = 0;
3858
3859 if (!netif_running(netdev))
3860 return 0;
3861
3862 for (i = 0; i < adapter->num_rx_queues; i++)
3863 napi_disable(&adapter->rx_queue[i].napi);
3864
3865 vmxnet3_disable_all_intrs(adapter);
3866 vmxnet3_free_irqs(adapter);
3867 vmxnet3_free_intr_resources(adapter);
3868
3869 netif_device_detach(netdev);
3870
3871 /* Create wake-up filters. */
3872 pmConf = adapter->pm_conf;
3873 memset(pmConf, 0, sizeof(*pmConf));
3874
3875 if (adapter->wol & WAKE_UCAST) {
3876 pmConf->filters[i].patternSize = ETH_ALEN;
3877 pmConf->filters[i].maskSize = 1;
3878 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
3879 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
3880
3881 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
3882 i++;
3883 }
3884
3885 if (adapter->wol & WAKE_ARP) {
3886 rcu_read_lock();
3887
3888 in_dev = __in_dev_get_rcu(netdev);
3889 if (!in_dev) {
3890 rcu_read_unlock();
3891 goto skip_arp;
3892 }
3893
3894 ifa = rcu_dereference(in_dev->ifa_list);
3895 if (!ifa) {
3896 rcu_read_unlock();
3897 goto skip_arp;
3898 }
3899
3900 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/
3901 sizeof(struct arphdr) + /* ARP header */
3902 2 * ETH_ALEN + /* 2 Ethernet addresses*/
3903 2 * sizeof(u32); /*2 IPv4 addresses */
3904 pmConf->filters[i].maskSize =
3905 (pmConf->filters[i].patternSize - 1) / 8 + 1;
3906
3907 /* ETH_P_ARP in Ethernet header. */
3908 ehdr = (struct ethhdr *)pmConf->filters[i].pattern;
3909 ehdr->h_proto = htons(ETH_P_ARP);
3910
3911 /* ARPOP_REQUEST in ARP header. */
3912 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN];
3913 ahdr->ar_op = htons(ARPOP_REQUEST);
3914 arpreq = (u8 *)(ahdr + 1);
3915
3916 /* The Unicast IPv4 address in 'tip' field. */
3917 arpreq += 2 * ETH_ALEN + sizeof(u32);
3918 *(__be32 *)arpreq = ifa->ifa_address;
3919
3920 rcu_read_unlock();
3921
3922 /* The mask for the relevant bits. */
3923 pmConf->filters[i].mask[0] = 0x00;
3924 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
3925 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
3926 pmConf->filters[i].mask[3] = 0x00;
3927 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
3928 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
3929
3930 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
3931 i++;
3932 }
3933
3934 skip_arp:
3935 if (adapter->wol & WAKE_MAGIC)
3936 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
3937
3938 pmConf->numFilters = i;
3939
3940 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3941 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3942 *pmConf));
3943 adapter->shared->devRead.pmConfDesc.confPA =
3944 cpu_to_le64(adapter->pm_conf_pa);
3945
3946 spin_lock_irqsave(&adapter->cmd_lock, flags);
3947 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3948 VMXNET3_CMD_UPDATE_PMCFG);
3949 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3950
3951 pci_save_state(pdev);
3952 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
3953 adapter->wol);
3954 pci_disable_device(pdev);
3955 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND));
3956
3957 return 0;
3958 }
3959
3960
3961 static int
vmxnet3_resume(struct device * device)3962 vmxnet3_resume(struct device *device)
3963 {
3964 int err;
3965 unsigned long flags;
3966 struct pci_dev *pdev = to_pci_dev(device);
3967 struct net_device *netdev = pci_get_drvdata(pdev);
3968 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3969
3970 if (!netif_running(netdev))
3971 return 0;
3972
3973 pci_set_power_state(pdev, PCI_D0);
3974 pci_restore_state(pdev);
3975 err = pci_enable_device_mem(pdev);
3976 if (err != 0)
3977 return err;
3978
3979 pci_enable_wake(pdev, PCI_D0, 0);
3980
3981 vmxnet3_alloc_intr_resources(adapter);
3982
3983 /* During hibernate and suspend, device has to be reinitialized as the
3984 * device state need not be preserved.
3985 */
3986
3987 /* Need not check adapter state as other reset tasks cannot run during
3988 * device resume.
3989 */
3990 spin_lock_irqsave(&adapter->cmd_lock, flags);
3991 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3992 VMXNET3_CMD_QUIESCE_DEV);
3993 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3994 vmxnet3_tq_cleanup_all(adapter);
3995 vmxnet3_rq_cleanup_all(adapter);
3996
3997 vmxnet3_reset_dev(adapter);
3998 err = vmxnet3_activate_dev(adapter);
3999 if (err != 0) {
4000 netdev_err(netdev,
4001 "failed to re-activate on resume, error: %d", err);
4002 vmxnet3_force_close(adapter);
4003 return err;
4004 }
4005 netif_device_attach(netdev);
4006
4007 return 0;
4008 }
4009
4010 static const struct dev_pm_ops vmxnet3_pm_ops = {
4011 .suspend = vmxnet3_suspend,
4012 .resume = vmxnet3_resume,
4013 .freeze = vmxnet3_suspend,
4014 .restore = vmxnet3_resume,
4015 };
4016 #endif
4017
4018 static struct pci_driver vmxnet3_driver = {
4019 .name = vmxnet3_driver_name,
4020 .id_table = vmxnet3_pciid_table,
4021 .probe = vmxnet3_probe_device,
4022 .remove = vmxnet3_remove_device,
4023 .shutdown = vmxnet3_shutdown_device,
4024 #ifdef CONFIG_PM
4025 .driver.pm = &vmxnet3_pm_ops,
4026 #endif
4027 };
4028
4029
4030 static int __init
vmxnet3_init_module(void)4031 vmxnet3_init_module(void)
4032 {
4033 pr_info("%s - version %s\n", VMXNET3_DRIVER_DESC,
4034 VMXNET3_DRIVER_VERSION_REPORT);
4035 return pci_register_driver(&vmxnet3_driver);
4036 }
4037
4038 module_init(vmxnet3_init_module);
4039
4040
4041 static void
vmxnet3_exit_module(void)4042 vmxnet3_exit_module(void)
4043 {
4044 pci_unregister_driver(&vmxnet3_driver);
4045 }
4046
4047 module_exit(vmxnet3_exit_module);
4048
4049 MODULE_AUTHOR("VMware, Inc.");
4050 MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC);
4051 MODULE_LICENSE("GPL v2");
4052 MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING);
4053