1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Driver for Microsemi VSC85xx PHYs
4 *
5 * Author: Nagaraju Lakkaraju
6 * License: Dual MIT/GPL
7 * Copyright (c) 2016 Microsemi Corporation
8 */
9
10 #include <linux/firmware.h>
11 #include <linux/jiffies.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/mdio.h>
15 #include <linux/mii.h>
16 #include <linux/phy.h>
17 #include <linux/of.h>
18 #include <linux/netdevice.h>
19 #include <dt-bindings/net/mscc-phy-vsc8531.h>
20 #include "mscc_serdes.h"
21 #include "mscc.h"
22
23 static const struct vsc85xx_hw_stat vsc85xx_hw_stats[] = {
24 {
25 .string = "phy_receive_errors",
26 .reg = MSCC_PHY_ERR_RX_CNT,
27 .page = MSCC_PHY_PAGE_STANDARD,
28 .mask = ERR_CNT_MASK,
29 }, {
30 .string = "phy_false_carrier",
31 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT,
32 .page = MSCC_PHY_PAGE_STANDARD,
33 .mask = ERR_CNT_MASK,
34 }, {
35 .string = "phy_cu_media_link_disconnect",
36 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
37 .page = MSCC_PHY_PAGE_STANDARD,
38 .mask = ERR_CNT_MASK,
39 }, {
40 .string = "phy_cu_media_crc_good_count",
41 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
42 .page = MSCC_PHY_PAGE_EXTENDED,
43 .mask = VALID_CRC_CNT_CRC_MASK,
44 }, {
45 .string = "phy_cu_media_crc_error_count",
46 .reg = MSCC_PHY_EXT_PHY_CNTL_4,
47 .page = MSCC_PHY_PAGE_EXTENDED,
48 .mask = ERR_CNT_MASK,
49 },
50 };
51
52 static const struct vsc85xx_hw_stat vsc8584_hw_stats[] = {
53 {
54 .string = "phy_receive_errors",
55 .reg = MSCC_PHY_ERR_RX_CNT,
56 .page = MSCC_PHY_PAGE_STANDARD,
57 .mask = ERR_CNT_MASK,
58 }, {
59 .string = "phy_false_carrier",
60 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT,
61 .page = MSCC_PHY_PAGE_STANDARD,
62 .mask = ERR_CNT_MASK,
63 }, {
64 .string = "phy_cu_media_link_disconnect",
65 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT,
66 .page = MSCC_PHY_PAGE_STANDARD,
67 .mask = ERR_CNT_MASK,
68 }, {
69 .string = "phy_cu_media_crc_good_count",
70 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT,
71 .page = MSCC_PHY_PAGE_EXTENDED,
72 .mask = VALID_CRC_CNT_CRC_MASK,
73 }, {
74 .string = "phy_cu_media_crc_error_count",
75 .reg = MSCC_PHY_EXT_PHY_CNTL_4,
76 .page = MSCC_PHY_PAGE_EXTENDED,
77 .mask = ERR_CNT_MASK,
78 }, {
79 .string = "phy_serdes_tx_good_pkt_count",
80 .reg = MSCC_PHY_SERDES_TX_VALID_CNT,
81 .page = MSCC_PHY_PAGE_EXTENDED_3,
82 .mask = VALID_CRC_CNT_CRC_MASK,
83 }, {
84 .string = "phy_serdes_tx_bad_crc_count",
85 .reg = MSCC_PHY_SERDES_TX_CRC_ERR_CNT,
86 .page = MSCC_PHY_PAGE_EXTENDED_3,
87 .mask = ERR_CNT_MASK,
88 }, {
89 .string = "phy_serdes_rx_good_pkt_count",
90 .reg = MSCC_PHY_SERDES_RX_VALID_CNT,
91 .page = MSCC_PHY_PAGE_EXTENDED_3,
92 .mask = VALID_CRC_CNT_CRC_MASK,
93 }, {
94 .string = "phy_serdes_rx_bad_crc_count",
95 .reg = MSCC_PHY_SERDES_RX_CRC_ERR_CNT,
96 .page = MSCC_PHY_PAGE_EXTENDED_3,
97 .mask = ERR_CNT_MASK,
98 },
99 };
100
101 #if IS_ENABLED(CONFIG_OF_MDIO)
102 static const struct vsc8531_edge_rate_table edge_table[] = {
103 {MSCC_VDDMAC_3300, { 0, 2, 4, 7, 10, 17, 29, 53} },
104 {MSCC_VDDMAC_2500, { 0, 3, 6, 10, 14, 23, 37, 63} },
105 {MSCC_VDDMAC_1800, { 0, 5, 9, 16, 23, 35, 52, 76} },
106 {MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} },
107 };
108 #endif
109
vsc85xx_phy_read_page(struct phy_device * phydev)110 static int vsc85xx_phy_read_page(struct phy_device *phydev)
111 {
112 return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS);
113 }
114
vsc85xx_phy_write_page(struct phy_device * phydev,int page)115 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page)
116 {
117 return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page);
118 }
119
vsc85xx_get_sset_count(struct phy_device * phydev)120 static int vsc85xx_get_sset_count(struct phy_device *phydev)
121 {
122 struct vsc8531_private *priv = phydev->priv;
123
124 if (!priv)
125 return 0;
126
127 return priv->nstats;
128 }
129
vsc85xx_get_strings(struct phy_device * phydev,u8 * data)130 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data)
131 {
132 struct vsc8531_private *priv = phydev->priv;
133 int i;
134
135 if (!priv)
136 return;
137
138 for (i = 0; i < priv->nstats; i++)
139 strlcpy(data + i * ETH_GSTRING_LEN, priv->hw_stats[i].string,
140 ETH_GSTRING_LEN);
141 }
142
vsc85xx_get_stat(struct phy_device * phydev,int i)143 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i)
144 {
145 struct vsc8531_private *priv = phydev->priv;
146 int val;
147
148 val = phy_read_paged(phydev, priv->hw_stats[i].page,
149 priv->hw_stats[i].reg);
150 if (val < 0)
151 return U64_MAX;
152
153 val = val & priv->hw_stats[i].mask;
154 priv->stats[i] += val;
155
156 return priv->stats[i];
157 }
158
vsc85xx_get_stats(struct phy_device * phydev,struct ethtool_stats * stats,u64 * data)159 static void vsc85xx_get_stats(struct phy_device *phydev,
160 struct ethtool_stats *stats, u64 *data)
161 {
162 struct vsc8531_private *priv = phydev->priv;
163 int i;
164
165 if (!priv)
166 return;
167
168 for (i = 0; i < priv->nstats; i++)
169 data[i] = vsc85xx_get_stat(phydev, i);
170 }
171
vsc85xx_led_cntl_set(struct phy_device * phydev,u8 led_num,u8 mode)172 static int vsc85xx_led_cntl_set(struct phy_device *phydev,
173 u8 led_num,
174 u8 mode)
175 {
176 int rc;
177 u16 reg_val;
178
179 mutex_lock(&phydev->lock);
180 reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL);
181 reg_val &= ~LED_MODE_SEL_MASK(led_num);
182 reg_val |= LED_MODE_SEL(led_num, (u16)mode);
183 rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val);
184 mutex_unlock(&phydev->lock);
185
186 return rc;
187 }
188
vsc85xx_mdix_get(struct phy_device * phydev,u8 * mdix)189 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix)
190 {
191 u16 reg_val;
192
193 reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL);
194 if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK)
195 *mdix = ETH_TP_MDI_X;
196 else
197 *mdix = ETH_TP_MDI;
198
199 return 0;
200 }
201
vsc85xx_mdix_set(struct phy_device * phydev,u8 mdix)202 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix)
203 {
204 int rc;
205 u16 reg_val;
206
207 reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL);
208 if (mdix == ETH_TP_MDI || mdix == ETH_TP_MDI_X) {
209 reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK |
210 DISABLE_POLARITY_CORR_MASK |
211 DISABLE_HP_AUTO_MDIX_MASK);
212 } else {
213 reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK |
214 DISABLE_POLARITY_CORR_MASK |
215 DISABLE_HP_AUTO_MDIX_MASK);
216 }
217 rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val);
218 if (rc)
219 return rc;
220
221 reg_val = 0;
222
223 if (mdix == ETH_TP_MDI)
224 reg_val = FORCE_MDI_CROSSOVER_MDI;
225 else if (mdix == ETH_TP_MDI_X)
226 reg_val = FORCE_MDI_CROSSOVER_MDIX;
227
228 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
229 MSCC_PHY_EXT_MODE_CNTL, FORCE_MDI_CROSSOVER_MASK,
230 reg_val);
231 if (rc < 0)
232 return rc;
233
234 return genphy_restart_aneg(phydev);
235 }
236
vsc85xx_downshift_get(struct phy_device * phydev,u8 * count)237 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count)
238 {
239 int reg_val;
240
241 reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
242 MSCC_PHY_ACTIPHY_CNTL);
243 if (reg_val < 0)
244 return reg_val;
245
246 reg_val &= DOWNSHIFT_CNTL_MASK;
247 if (!(reg_val & DOWNSHIFT_EN))
248 *count = DOWNSHIFT_DEV_DISABLE;
249 else
250 *count = ((reg_val & ~DOWNSHIFT_EN) >> DOWNSHIFT_CNTL_POS) + 2;
251
252 return 0;
253 }
254
vsc85xx_downshift_set(struct phy_device * phydev,u8 count)255 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count)
256 {
257 if (count == DOWNSHIFT_DEV_DEFAULT_COUNT) {
258 /* Default downshift count 3 (i.e. Bit3:2 = 0b01) */
259 count = ((1 << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
260 } else if (count > DOWNSHIFT_COUNT_MAX || count == 1) {
261 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n");
262 return -ERANGE;
263 } else if (count) {
264 /* Downshift count is either 2,3,4 or 5 */
265 count = (((count - 2) << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN);
266 }
267
268 return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED,
269 MSCC_PHY_ACTIPHY_CNTL, DOWNSHIFT_CNTL_MASK,
270 count);
271 }
272
vsc85xx_wol_set(struct phy_device * phydev,struct ethtool_wolinfo * wol)273 static int vsc85xx_wol_set(struct phy_device *phydev,
274 struct ethtool_wolinfo *wol)
275 {
276 const u8 *mac_addr = phydev->attached_dev->dev_addr;
277 int rc;
278 u16 reg_val;
279 u8 i;
280 u16 pwd[3] = {0, 0, 0};
281 struct ethtool_wolinfo *wol_conf = wol;
282
283 mutex_lock(&phydev->lock);
284 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
285 if (rc < 0) {
286 rc = phy_restore_page(phydev, rc, rc);
287 goto out_unlock;
288 }
289
290 if (wol->wolopts & WAKE_MAGIC) {
291 /* Store the device address for the magic packet */
292 for (i = 0; i < ARRAY_SIZE(pwd); i++)
293 pwd[i] = mac_addr[5 - (i * 2 + 1)] << 8 |
294 mac_addr[5 - i * 2];
295 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]);
296 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]);
297 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]);
298 } else {
299 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0);
300 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0);
301 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0);
302 }
303
304 if (wol_conf->wolopts & WAKE_MAGICSECURE) {
305 for (i = 0; i < ARRAY_SIZE(pwd); i++)
306 pwd[i] = wol_conf->sopass[5 - (i * 2 + 1)] << 8 |
307 wol_conf->sopass[5 - i * 2];
308 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]);
309 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]);
310 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]);
311 } else {
312 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0);
313 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0);
314 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0);
315 }
316
317 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
318 if (wol_conf->wolopts & WAKE_MAGICSECURE)
319 reg_val |= SECURE_ON_ENABLE;
320 else
321 reg_val &= ~SECURE_ON_ENABLE;
322 __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val);
323
324 rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
325 if (rc < 0)
326 goto out_unlock;
327
328 if (wol->wolopts & WAKE_MAGIC) {
329 /* Enable the WOL interrupt */
330 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
331 reg_val |= MII_VSC85XX_INT_MASK_WOL;
332 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
333 if (rc)
334 goto out_unlock;
335 } else {
336 /* Disable the WOL interrupt */
337 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK);
338 reg_val &= (~MII_VSC85XX_INT_MASK_WOL);
339 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val);
340 if (rc)
341 goto out_unlock;
342 }
343 /* Clear WOL iterrupt status */
344 reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS);
345
346 out_unlock:
347 mutex_unlock(&phydev->lock);
348
349 return rc;
350 }
351
vsc85xx_wol_get(struct phy_device * phydev,struct ethtool_wolinfo * wol)352 static void vsc85xx_wol_get(struct phy_device *phydev,
353 struct ethtool_wolinfo *wol)
354 {
355 int rc;
356 u16 reg_val;
357 u8 i;
358 u16 pwd[3] = {0, 0, 0};
359 struct ethtool_wolinfo *wol_conf = wol;
360
361 mutex_lock(&phydev->lock);
362 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2);
363 if (rc < 0)
364 goto out_unlock;
365
366 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL);
367 if (reg_val & SECURE_ON_ENABLE)
368 wol_conf->wolopts |= WAKE_MAGICSECURE;
369 if (wol_conf->wolopts & WAKE_MAGICSECURE) {
370 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD);
371 pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD);
372 pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD);
373 for (i = 0; i < ARRAY_SIZE(pwd); i++) {
374 wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff;
375 wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00)
376 >> 8;
377 }
378 }
379
380 out_unlock:
381 phy_restore_page(phydev, rc, rc > 0 ? 0 : rc);
382 mutex_unlock(&phydev->lock);
383 }
384
385 #if IS_ENABLED(CONFIG_OF_MDIO)
vsc85xx_edge_rate_magic_get(struct phy_device * phydev)386 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
387 {
388 u32 vdd, sd;
389 int i, j;
390 struct device *dev = &phydev->mdio.dev;
391 struct device_node *of_node = dev->of_node;
392 u8 sd_array_size = ARRAY_SIZE(edge_table[0].slowdown);
393
394 if (!of_node)
395 return -ENODEV;
396
397 if (of_property_read_u32(of_node, "vsc8531,vddmac", &vdd))
398 vdd = MSCC_VDDMAC_3300;
399
400 if (of_property_read_u32(of_node, "vsc8531,edge-slowdown", &sd))
401 sd = 0;
402
403 for (i = 0; i < ARRAY_SIZE(edge_table); i++)
404 if (edge_table[i].vddmac == vdd)
405 for (j = 0; j < sd_array_size; j++)
406 if (edge_table[i].slowdown[j] == sd)
407 return (sd_array_size - j - 1);
408
409 return -EINVAL;
410 }
411
vsc85xx_dt_led_mode_get(struct phy_device * phydev,char * led,u32 default_mode)412 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
413 char *led,
414 u32 default_mode)
415 {
416 struct vsc8531_private *priv = phydev->priv;
417 struct device *dev = &phydev->mdio.dev;
418 struct device_node *of_node = dev->of_node;
419 u32 led_mode;
420 int err;
421
422 if (!of_node)
423 return -ENODEV;
424
425 led_mode = default_mode;
426 err = of_property_read_u32(of_node, led, &led_mode);
427 if (!err && !(BIT(led_mode) & priv->supp_led_modes)) {
428 phydev_err(phydev, "DT %s invalid\n", led);
429 return -EINVAL;
430 }
431
432 return led_mode;
433 }
434
435 #else
vsc85xx_edge_rate_magic_get(struct phy_device * phydev)436 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev)
437 {
438 return 0;
439 }
440
vsc85xx_dt_led_mode_get(struct phy_device * phydev,char * led,u8 default_mode)441 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev,
442 char *led,
443 u8 default_mode)
444 {
445 return default_mode;
446 }
447 #endif /* CONFIG_OF_MDIO */
448
vsc85xx_dt_led_modes_get(struct phy_device * phydev,u32 * default_mode)449 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev,
450 u32 *default_mode)
451 {
452 struct vsc8531_private *priv = phydev->priv;
453 char led_dt_prop[28];
454 int i, ret;
455
456 for (i = 0; i < priv->nleds; i++) {
457 ret = sprintf(led_dt_prop, "vsc8531,led-%d-mode", i);
458 if (ret < 0)
459 return ret;
460
461 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop,
462 default_mode[i]);
463 if (ret < 0)
464 return ret;
465 priv->leds_mode[i] = ret;
466 }
467
468 return 0;
469 }
470
vsc85xx_edge_rate_cntl_set(struct phy_device * phydev,u8 edge_rate)471 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate)
472 {
473 int rc;
474
475 mutex_lock(&phydev->lock);
476 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
477 MSCC_PHY_WOL_MAC_CONTROL, EDGE_RATE_CNTL_MASK,
478 edge_rate << EDGE_RATE_CNTL_POS);
479 mutex_unlock(&phydev->lock);
480
481 return rc;
482 }
483
vsc85xx_mac_if_set(struct phy_device * phydev,phy_interface_t interface)484 static int vsc85xx_mac_if_set(struct phy_device *phydev,
485 phy_interface_t interface)
486 {
487 int rc;
488 u16 reg_val;
489
490 mutex_lock(&phydev->lock);
491 reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
492 reg_val &= ~(MAC_IF_SELECTION_MASK);
493 switch (interface) {
494 case PHY_INTERFACE_MODE_RGMII_TXID:
495 case PHY_INTERFACE_MODE_RGMII_RXID:
496 case PHY_INTERFACE_MODE_RGMII_ID:
497 case PHY_INTERFACE_MODE_RGMII:
498 reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);
499 break;
500 case PHY_INTERFACE_MODE_RMII:
501 reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS);
502 break;
503 case PHY_INTERFACE_MODE_MII:
504 case PHY_INTERFACE_MODE_GMII:
505 reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS);
506 break;
507 default:
508 rc = -EINVAL;
509 goto out_unlock;
510 }
511 rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val);
512 if (rc)
513 goto out_unlock;
514
515 rc = genphy_soft_reset(phydev);
516
517 out_unlock:
518 mutex_unlock(&phydev->lock);
519
520 return rc;
521 }
522
523 /* Set the RGMII RX and TX clock skews individually, according to the PHY
524 * interface type, to:
525 * * 0.2 ns (their default, and lowest, hardware value) if delays should
526 * not be enabled
527 * * 2.0 ns (which causes the data to be sampled at exactly half way between
528 * clock transitions at 1000 Mbps) if delays should be enabled
529 */
vsc85xx_update_rgmii_cntl(struct phy_device * phydev,u32 rgmii_cntl,u16 rgmii_rx_delay_mask,u16 rgmii_tx_delay_mask)530 static int vsc85xx_update_rgmii_cntl(struct phy_device *phydev, u32 rgmii_cntl,
531 u16 rgmii_rx_delay_mask,
532 u16 rgmii_tx_delay_mask)
533 {
534 u16 rgmii_rx_delay_pos = ffs(rgmii_rx_delay_mask) - 1;
535 u16 rgmii_tx_delay_pos = ffs(rgmii_tx_delay_mask) - 1;
536 u16 reg_val = 0;
537 u16 mask = 0;
538 int rc = 0;
539
540 /* For traffic to pass, the VSC8502 family needs the RX_CLK disable bit
541 * to be unset for all PHY modes, so do that as part of the paged
542 * register modification.
543 * For some family members (like VSC8530/31/40/41) this bit is reserved
544 * and read-only, and the RX clock is enabled by default.
545 */
546 if (rgmii_cntl == VSC8502_RGMII_CNTL)
547 mask |= VSC8502_RGMII_RX_CLK_DISABLE;
548
549 if (phy_interface_is_rgmii(phydev))
550 mask |= rgmii_rx_delay_mask | rgmii_tx_delay_mask;
551
552 mutex_lock(&phydev->lock);
553
554 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
555 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
556 reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_rx_delay_pos;
557 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
558 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
559 reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_tx_delay_pos;
560
561 if (mask)
562 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
563 rgmii_cntl, mask, reg_val);
564
565 mutex_unlock(&phydev->lock);
566
567 return rc;
568 }
569
vsc85xx_default_config(struct phy_device * phydev)570 static int vsc85xx_default_config(struct phy_device *phydev)
571 {
572 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
573
574 return vsc85xx_update_rgmii_cntl(phydev, VSC8502_RGMII_CNTL,
575 VSC8502_RGMII_RX_DELAY_MASK,
576 VSC8502_RGMII_TX_DELAY_MASK);
577 }
578
vsc85xx_get_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,void * data)579 static int vsc85xx_get_tunable(struct phy_device *phydev,
580 struct ethtool_tunable *tuna, void *data)
581 {
582 switch (tuna->id) {
583 case ETHTOOL_PHY_DOWNSHIFT:
584 return vsc85xx_downshift_get(phydev, (u8 *)data);
585 default:
586 return -EINVAL;
587 }
588 }
589
vsc85xx_set_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,const void * data)590 static int vsc85xx_set_tunable(struct phy_device *phydev,
591 struct ethtool_tunable *tuna,
592 const void *data)
593 {
594 switch (tuna->id) {
595 case ETHTOOL_PHY_DOWNSHIFT:
596 return vsc85xx_downshift_set(phydev, *(u8 *)data);
597 default:
598 return -EINVAL;
599 }
600 }
601
602 /* mdiobus lock should be locked when using this function */
vsc85xx_tr_write(struct phy_device * phydev,u16 addr,u32 val)603 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val)
604 {
605 __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
606 __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
607 __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
608 }
609
vsc8531_pre_init_seq_set(struct phy_device * phydev)610 static int vsc8531_pre_init_seq_set(struct phy_device *phydev)
611 {
612 int rc;
613 static const struct reg_val init_seq[] = {
614 {0x0f90, 0x00688980},
615 {0x0696, 0x00000003},
616 {0x07fa, 0x0050100f},
617 {0x1686, 0x00000004},
618 };
619 unsigned int i;
620 int oldpage;
621
622 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD,
623 MSCC_PHY_EXT_CNTL_STATUS, SMI_BROADCAST_WR_EN,
624 SMI_BROADCAST_WR_EN);
625 if (rc < 0)
626 return rc;
627 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
628 MSCC_PHY_TEST_PAGE_24, 0, 0x0400);
629 if (rc < 0)
630 return rc;
631 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
632 MSCC_PHY_TEST_PAGE_5, 0x0a00, 0x0e00);
633 if (rc < 0)
634 return rc;
635 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST,
636 MSCC_PHY_TEST_PAGE_8, TR_CLK_DISABLE, TR_CLK_DISABLE);
637 if (rc < 0)
638 return rc;
639
640 mutex_lock(&phydev->lock);
641 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
642 if (oldpage < 0)
643 goto out_unlock;
644
645 for (i = 0; i < ARRAY_SIZE(init_seq); i++)
646 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val);
647
648 out_unlock:
649 oldpage = phy_restore_page(phydev, oldpage, oldpage);
650 mutex_unlock(&phydev->lock);
651
652 return oldpage;
653 }
654
vsc85xx_eee_init_seq_set(struct phy_device * phydev)655 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev)
656 {
657 static const struct reg_val init_eee[] = {
658 {0x0f82, 0x0012b00a},
659 {0x1686, 0x00000004},
660 {0x168c, 0x00d2c46f},
661 {0x17a2, 0x00000620},
662 {0x16a0, 0x00eeffdd},
663 {0x16a6, 0x00071448},
664 {0x16a4, 0x0013132f},
665 {0x16a8, 0x00000000},
666 {0x0ffc, 0x00c0a028},
667 {0x0fe8, 0x0091b06c},
668 {0x0fea, 0x00041600},
669 {0x0f80, 0x00000af4},
670 {0x0fec, 0x00901809},
671 {0x0fee, 0x0000a6a1},
672 {0x0ffe, 0x00b01007},
673 {0x16b0, 0x00eeff00},
674 {0x16b2, 0x00007000},
675 {0x16b4, 0x00000814},
676 };
677 unsigned int i;
678 int oldpage;
679
680 mutex_lock(&phydev->lock);
681 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR);
682 if (oldpage < 0)
683 goto out_unlock;
684
685 for (i = 0; i < ARRAY_SIZE(init_eee); i++)
686 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val);
687
688 out_unlock:
689 oldpage = phy_restore_page(phydev, oldpage, oldpage);
690 mutex_unlock(&phydev->lock);
691
692 return oldpage;
693 }
694
695 /* phydev->bus->mdio_lock should be locked when using this function */
phy_base_write(struct phy_device * phydev,u32 regnum,u16 val)696 int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val)
697 {
698 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
699 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
700 dump_stack();
701 }
702
703 return __phy_package_write(phydev, regnum, val);
704 }
705
706 /* phydev->bus->mdio_lock should be locked when using this function */
phy_base_read(struct phy_device * phydev,u32 regnum)707 int phy_base_read(struct phy_device *phydev, u32 regnum)
708 {
709 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) {
710 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n");
711 dump_stack();
712 }
713
714 return __phy_package_read(phydev, regnum);
715 }
716
vsc85xx_csr_read(struct phy_device * phydev,enum csr_target target,u32 reg)717 u32 vsc85xx_csr_read(struct phy_device *phydev,
718 enum csr_target target, u32 reg)
719 {
720 unsigned long deadline;
721 u32 val, val_l, val_h;
722
723 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
724
725 /* CSR registers are grouped under different Target IDs.
726 * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and
727 * MSCC_EXT_PAGE_CSR_CNTL_19 registers.
728 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20
729 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19.
730 */
731
732 /* Setup the Target ID */
733 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
734 MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2));
735
736 if ((target >> 2 == 0x1) || (target >> 2 == 0x3))
737 /* non-MACsec access */
738 target &= 0x3;
739 else
740 target = 0;
741
742 /* Trigger CSR Action - Read into the CSR's */
743 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
744 MSCC_PHY_CSR_CNTL_19_CMD | MSCC_PHY_CSR_CNTL_19_READ |
745 MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) |
746 MSCC_PHY_CSR_CNTL_19_TARGET(target));
747
748 /* Wait for register access*/
749 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
750 do {
751 usleep_range(500, 1000);
752 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
753 } while (time_before(jiffies, deadline) &&
754 !(val & MSCC_PHY_CSR_CNTL_19_CMD));
755
756 if (!(val & MSCC_PHY_CSR_CNTL_19_CMD))
757 return 0xffffffff;
758
759 /* Read the Least Significant Word (LSW) (17) */
760 val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17);
761
762 /* Read the Most Significant Word (MSW) (18) */
763 val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18);
764
765 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
766 MSCC_PHY_PAGE_STANDARD);
767
768 return (val_h << 16) | val_l;
769 }
770
vsc85xx_csr_write(struct phy_device * phydev,enum csr_target target,u32 reg,u32 val)771 int vsc85xx_csr_write(struct phy_device *phydev,
772 enum csr_target target, u32 reg, u32 val)
773 {
774 unsigned long deadline;
775
776 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL);
777
778 /* CSR registers are grouped under different Target IDs.
779 * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and
780 * MSCC_EXT_PAGE_CSR_CNTL_19 registers.
781 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20
782 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19.
783 */
784
785 /* Setup the Target ID */
786 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20,
787 MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2));
788
789 /* Write the Least Significant Word (LSW) (17) */
790 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val);
791
792 /* Write the Most Significant Word (MSW) (18) */
793 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16));
794
795 if ((target >> 2 == 0x1) || (target >> 2 == 0x3))
796 /* non-MACsec access */
797 target &= 0x3;
798 else
799 target = 0;
800
801 /* Trigger CSR Action - Write into the CSR's */
802 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19,
803 MSCC_PHY_CSR_CNTL_19_CMD |
804 MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) |
805 MSCC_PHY_CSR_CNTL_19_TARGET(target));
806
807 /* Wait for register access */
808 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
809 do {
810 usleep_range(500, 1000);
811 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19);
812 } while (time_before(jiffies, deadline) &&
813 !(val & MSCC_PHY_CSR_CNTL_19_CMD));
814
815 if (!(val & MSCC_PHY_CSR_CNTL_19_CMD))
816 return -ETIMEDOUT;
817
818 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
819 MSCC_PHY_PAGE_STANDARD);
820
821 return 0;
822 }
823
824 /* bus->mdio_lock should be locked when using this function */
vsc8584_csr_write(struct phy_device * phydev,u16 addr,u32 val)825 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val)
826 {
827 phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16);
828 phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0));
829 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr));
830 }
831
832 /* bus->mdio_lock should be locked when using this function */
vsc8584_cmd(struct phy_device * phydev,u16 val)833 int vsc8584_cmd(struct phy_device *phydev, u16 val)
834 {
835 unsigned long deadline;
836 u16 reg_val;
837
838 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
839 MSCC_PHY_PAGE_EXTENDED_GPIO);
840
841 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val);
842
843 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
844 do {
845 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD);
846 } while (time_before(jiffies, deadline) &&
847 (reg_val & PROC_CMD_NCOMPLETED) &&
848 !(reg_val & PROC_CMD_FAILED));
849
850 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
851
852 if (reg_val & PROC_CMD_FAILED)
853 return -EIO;
854
855 if (reg_val & PROC_CMD_NCOMPLETED)
856 return -ETIMEDOUT;
857
858 return 0;
859 }
860
861 /* bus->mdio_lock should be locked when using this function */
vsc8584_micro_deassert_reset(struct phy_device * phydev,bool patch_en)862 static int vsc8584_micro_deassert_reset(struct phy_device *phydev,
863 bool patch_en)
864 {
865 u32 enable, release;
866
867 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
868 MSCC_PHY_PAGE_EXTENDED_GPIO);
869
870 enable = RUN_FROM_INT_ROM | MICRO_CLK_EN | DW8051_CLK_EN;
871 release = MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN |
872 MICRO_CLK_EN;
873
874 if (patch_en) {
875 enable |= MICRO_PATCH_EN;
876 release |= MICRO_PATCH_EN;
877
878 /* Clear all patches */
879 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
880 }
881
882 /* Enable 8051 Micro clock; CLEAR/SET patch present; disable PRAM clock
883 * override and addr. auto-incr; operate at 125 MHz
884 */
885 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable);
886 /* Release 8051 Micro SW reset */
887 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release);
888
889 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
890
891 return 0;
892 }
893
894 /* bus->mdio_lock should be locked when using this function */
vsc8584_micro_assert_reset(struct phy_device * phydev)895 static int vsc8584_micro_assert_reset(struct phy_device *phydev)
896 {
897 int ret;
898 u16 reg;
899
900 ret = vsc8584_cmd(phydev, PROC_CMD_NOP);
901 if (ret)
902 return ret;
903
904 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
905 MSCC_PHY_PAGE_EXTENDED_GPIO);
906
907 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
908 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
909 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
910
911 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b);
912 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b);
913
914 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
915 reg |= EN_PATCH_RAM_TRAP_ADDR(4);
916 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
917
918 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP);
919
920 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
921 reg &= ~MICRO_NSOFT_RESET;
922 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg);
923
924 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF |
925 PROC_CMD_SGMII_PORT(0) | PROC_CMD_NO_MAC_CONF |
926 PROC_CMD_READ);
927
928 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
929 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4);
930 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
931
932 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
933
934 return 0;
935 }
936
937 /* bus->mdio_lock should be locked when using this function */
vsc8584_get_fw_crc(struct phy_device * phydev,u16 start,u16 size,u16 * crc)938 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size,
939 u16 *crc)
940 {
941 int ret;
942
943 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
944
945 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start);
946 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size);
947
948 /* Start Micro command */
949 ret = vsc8584_cmd(phydev, PROC_CMD_CRC16);
950 if (ret)
951 goto out;
952
953 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
954
955 *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2);
956
957 out:
958 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
959
960 return ret;
961 }
962
963 /* bus->mdio_lock should be locked when using this function */
vsc8584_patch_fw(struct phy_device * phydev,const struct firmware * fw)964 static int vsc8584_patch_fw(struct phy_device *phydev,
965 const struct firmware *fw)
966 {
967 int i, ret;
968
969 ret = vsc8584_micro_assert_reset(phydev);
970 if (ret) {
971 dev_err(&phydev->mdio.dev,
972 "%s: failed to assert reset of micro\n", __func__);
973 return ret;
974 }
975
976 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
977 MSCC_PHY_PAGE_EXTENDED_GPIO);
978
979 /* Hold 8051 Micro in SW Reset, Enable auto incr address and patch clock
980 * Disable the 8051 Micro clock
981 */
982 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM |
983 AUTOINC_ADDR | PATCH_RAM_CLK | MICRO_CLK_EN |
984 MICRO_CLK_DIVIDE(2));
985 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN |
986 INT_MEM_DATA(2));
987 phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000);
988
989 for (i = 0; i < fw->size; i++)
990 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM |
991 INT_MEM_WRITE_EN | fw->data[i]);
992
993 /* Clear internal memory access */
994 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM);
995
996 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
997
998 return 0;
999 }
1000
1001 /* bus->mdio_lock should be locked when using this function */
vsc8574_is_serdes_init(struct phy_device * phydev)1002 static bool vsc8574_is_serdes_init(struct phy_device *phydev)
1003 {
1004 u16 reg;
1005 bool ret;
1006
1007 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1008 MSCC_PHY_PAGE_EXTENDED_GPIO);
1009
1010 reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1));
1011 if (reg != 0x3eb7) {
1012 ret = false;
1013 goto out;
1014 }
1015
1016 reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1));
1017 if (reg != 0x4012) {
1018 ret = false;
1019 goto out;
1020 }
1021
1022 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1023 if (reg != EN_PATCH_RAM_TRAP_ADDR(1)) {
1024 ret = false;
1025 goto out;
1026 }
1027
1028 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS);
1029 if ((MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN |
1030 MICRO_CLK_EN) != (reg & MSCC_DW8051_VLD_MASK)) {
1031 ret = false;
1032 goto out;
1033 }
1034
1035 ret = true;
1036 out:
1037 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1038
1039 return ret;
1040 }
1041
1042 /* bus->mdio_lock should be locked when using this function */
vsc8574_config_pre_init(struct phy_device * phydev)1043 static int vsc8574_config_pre_init(struct phy_device *phydev)
1044 {
1045 static const struct reg_val pre_init1[] = {
1046 {0x0fae, 0x000401bd},
1047 {0x0fac, 0x000f000f},
1048 {0x17a0, 0x00a0f147},
1049 {0x0fe4, 0x00052f54},
1050 {0x1792, 0x0027303d},
1051 {0x07fe, 0x00000704},
1052 {0x0fe0, 0x00060150},
1053 {0x0f82, 0x0012b00a},
1054 {0x0f80, 0x00000d74},
1055 {0x02e0, 0x00000012},
1056 {0x03a2, 0x00050208},
1057 {0x03b2, 0x00009186},
1058 {0x0fb0, 0x000e3700},
1059 {0x1688, 0x00049f81},
1060 {0x0fd2, 0x0000ffff},
1061 {0x168a, 0x00039fa2},
1062 {0x1690, 0x0020640b},
1063 {0x0258, 0x00002220},
1064 {0x025a, 0x00002a20},
1065 {0x025c, 0x00003060},
1066 {0x025e, 0x00003fa0},
1067 {0x03a6, 0x0000e0f0},
1068 {0x0f92, 0x00001489},
1069 {0x16a2, 0x00007000},
1070 {0x16a6, 0x00071448},
1071 {0x16a0, 0x00eeffdd},
1072 {0x0fe8, 0x0091b06c},
1073 {0x0fea, 0x00041600},
1074 {0x16b0, 0x00eeff00},
1075 {0x16b2, 0x00007000},
1076 {0x16b4, 0x00000814},
1077 {0x0f90, 0x00688980},
1078 {0x03a4, 0x0000d8f0},
1079 {0x0fc0, 0x00000400},
1080 {0x07fa, 0x0050100f},
1081 {0x0796, 0x00000003},
1082 {0x07f8, 0x00c3ff98},
1083 {0x0fa4, 0x0018292a},
1084 {0x168c, 0x00d2c46f},
1085 {0x17a2, 0x00000620},
1086 {0x16a4, 0x0013132f},
1087 {0x16a8, 0x00000000},
1088 {0x0ffc, 0x00c0a028},
1089 {0x0fec, 0x00901c09},
1090 {0x0fee, 0x0004a6a1},
1091 {0x0ffe, 0x00b01807},
1092 };
1093 static const struct reg_val pre_init2[] = {
1094 {0x0486, 0x0008a518},
1095 {0x0488, 0x006dc696},
1096 {0x048a, 0x00000912},
1097 {0x048e, 0x00000db6},
1098 {0x049c, 0x00596596},
1099 {0x049e, 0x00000514},
1100 {0x04a2, 0x00410280},
1101 {0x04a4, 0x00000000},
1102 {0x04a6, 0x00000000},
1103 {0x04a8, 0x00000000},
1104 {0x04aa, 0x00000000},
1105 {0x04ae, 0x007df7dd},
1106 {0x04b0, 0x006d95d4},
1107 {0x04b2, 0x00492410},
1108 };
1109 struct device *dev = &phydev->mdio.dev;
1110 const struct firmware *fw;
1111 unsigned int i;
1112 u16 crc, reg;
1113 bool serdes_init;
1114 int ret;
1115
1116 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1117
1118 /* all writes below are broadcasted to all PHYs in the same package */
1119 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1120 reg |= SMI_BROADCAST_WR_EN;
1121 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1122
1123 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1124
1125 /* The below register writes are tweaking analog and electrical
1126 * configuration that were determined through characterization by PHY
1127 * engineers. These don't mean anything more than "these are the best
1128 * values".
1129 */
1130 phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040);
1131
1132 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1133
1134 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320);
1135 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00);
1136 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca);
1137 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20);
1138
1139 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1140 reg |= TR_CLK_DISABLE;
1141 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1142
1143 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1144
1145 for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1146 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1147
1148 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1149
1150 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1151
1152 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1153
1154 for (i = 0; i < ARRAY_SIZE(pre_init2); i++)
1155 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1156
1157 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1158
1159 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1160 reg &= ~TR_CLK_DISABLE;
1161 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1162
1163 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1164
1165 /* end of write broadcasting */
1166 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1167 reg &= ~SMI_BROADCAST_WR_EN;
1168 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1169
1170 ret = request_firmware(&fw, MSCC_VSC8574_REVB_INT8051_FW, dev);
1171 if (ret) {
1172 dev_err(dev, "failed to load firmware %s, ret: %d\n",
1173 MSCC_VSC8574_REVB_INT8051_FW, ret);
1174 return ret;
1175 }
1176
1177 /* Add one byte to size for the one added by the patch_fw function */
1178 ret = vsc8584_get_fw_crc(phydev,
1179 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR,
1180 fw->size + 1, &crc);
1181 if (ret)
1182 goto out;
1183
1184 if (crc == MSCC_VSC8574_REVB_INT8051_FW_CRC) {
1185 serdes_init = vsc8574_is_serdes_init(phydev);
1186
1187 if (!serdes_init) {
1188 ret = vsc8584_micro_assert_reset(phydev);
1189 if (ret) {
1190 dev_err(dev,
1191 "%s: failed to assert reset of micro\n",
1192 __func__);
1193 goto out;
1194 }
1195 }
1196 } else {
1197 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n");
1198
1199 serdes_init = false;
1200
1201 if (vsc8584_patch_fw(phydev, fw))
1202 dev_warn(dev,
1203 "failed to patch FW, expect non-optimal device\n");
1204 }
1205
1206 if (!serdes_init) {
1207 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1208 MSCC_PHY_PAGE_EXTENDED_GPIO);
1209
1210 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7);
1211 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012);
1212 phy_base_write(phydev, MSCC_INT_MEM_CNTL,
1213 EN_PATCH_RAM_TRAP_ADDR(1));
1214
1215 vsc8584_micro_deassert_reset(phydev, false);
1216
1217 /* Add one byte to size for the one added by the patch_fw
1218 * function
1219 */
1220 ret = vsc8584_get_fw_crc(phydev,
1221 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR,
1222 fw->size + 1, &crc);
1223 if (ret)
1224 goto out;
1225
1226 if (crc != MSCC_VSC8574_REVB_INT8051_FW_CRC)
1227 dev_warn(dev,
1228 "FW CRC after patching is not the expected one, expect non-optimal device\n");
1229 }
1230
1231 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1232 MSCC_PHY_PAGE_EXTENDED_GPIO);
1233
1234 ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT |
1235 PROC_CMD_PHY_INIT);
1236
1237 out:
1238 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1239
1240 release_firmware(fw);
1241
1242 return ret;
1243 }
1244
1245 /* Access LCPLL Cfg_2 */
vsc8584_pll5g_cfg2_wr(struct phy_device * phydev,bool disable_fsm)1246 static void vsc8584_pll5g_cfg2_wr(struct phy_device *phydev,
1247 bool disable_fsm)
1248 {
1249 u32 rd_dat;
1250
1251 rd_dat = vsc85xx_csr_read(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2);
1252 rd_dat &= ~BIT(PHY_S6G_CFG2_FSM_DIS);
1253 rd_dat |= (disable_fsm << PHY_S6G_CFG2_FSM_DIS);
1254 vsc85xx_csr_write(phydev, MACRO_CTRL, PHY_S6G_PLL5G_CFG2, rd_dat);
1255 }
1256
1257 /* trigger a read to the spcified MCB */
vsc8584_mcb_rd_trig(struct phy_device * phydev,u32 mcb_reg_addr,u8 mcb_slave_num)1258 static int vsc8584_mcb_rd_trig(struct phy_device *phydev,
1259 u32 mcb_reg_addr, u8 mcb_slave_num)
1260 {
1261 u32 rd_dat = 0;
1262
1263 /* read MCB */
1264 vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr,
1265 (0x40000000 | (1L << mcb_slave_num)));
1266
1267 return read_poll_timeout(vsc85xx_csr_read, rd_dat,
1268 !(rd_dat & 0x40000000),
1269 4000, 200000, 0,
1270 phydev, MACRO_CTRL, mcb_reg_addr);
1271 }
1272
1273 /* trigger a write to the spcified MCB */
vsc8584_mcb_wr_trig(struct phy_device * phydev,u32 mcb_reg_addr,u8 mcb_slave_num)1274 static int vsc8584_mcb_wr_trig(struct phy_device *phydev,
1275 u32 mcb_reg_addr,
1276 u8 mcb_slave_num)
1277 {
1278 u32 rd_dat = 0;
1279
1280 /* write back MCB */
1281 vsc85xx_csr_write(phydev, MACRO_CTRL, mcb_reg_addr,
1282 (0x80000000 | (1L << mcb_slave_num)));
1283
1284 return read_poll_timeout(vsc85xx_csr_read, rd_dat,
1285 !(rd_dat & 0x80000000),
1286 4000, 200000, 0,
1287 phydev, MACRO_CTRL, mcb_reg_addr);
1288 }
1289
1290 /* Sequence to Reset LCPLL for the VIPER and ELISE PHY */
vsc8584_pll5g_reset(struct phy_device * phydev)1291 static int vsc8584_pll5g_reset(struct phy_device *phydev)
1292 {
1293 bool dis_fsm;
1294 int ret = 0;
1295
1296 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0);
1297 if (ret < 0)
1298 goto done;
1299 dis_fsm = 1;
1300
1301 /* Reset LCPLL */
1302 vsc8584_pll5g_cfg2_wr(phydev, dis_fsm);
1303
1304 /* write back LCPLL MCB */
1305 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0);
1306 if (ret < 0)
1307 goto done;
1308
1309 /* 10 mSec sleep while LCPLL is hold in reset */
1310 usleep_range(10000, 20000);
1311
1312 /* read LCPLL MCB into CSRs */
1313 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0);
1314 if (ret < 0)
1315 goto done;
1316 dis_fsm = 0;
1317
1318 /* Release the Reset of LCPLL */
1319 vsc8584_pll5g_cfg2_wr(phydev, dis_fsm);
1320
1321 /* write back LCPLL MCB */
1322 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0);
1323 if (ret < 0)
1324 goto done;
1325
1326 usleep_range(110000, 200000);
1327 done:
1328 return ret;
1329 }
1330
1331 /* bus->mdio_lock should be locked when using this function */
vsc8584_config_pre_init(struct phy_device * phydev)1332 static int vsc8584_config_pre_init(struct phy_device *phydev)
1333 {
1334 static const struct reg_val pre_init1[] = {
1335 {0x07fa, 0x0050100f},
1336 {0x1688, 0x00049f81},
1337 {0x0f90, 0x00688980},
1338 {0x03a4, 0x0000d8f0},
1339 {0x0fc0, 0x00000400},
1340 {0x0f82, 0x0012b002},
1341 {0x1686, 0x00000004},
1342 {0x168c, 0x00d2c46f},
1343 {0x17a2, 0x00000620},
1344 {0x16a0, 0x00eeffdd},
1345 {0x16a6, 0x00071448},
1346 {0x16a4, 0x0013132f},
1347 {0x16a8, 0x00000000},
1348 {0x0ffc, 0x00c0a028},
1349 {0x0fe8, 0x0091b06c},
1350 {0x0fea, 0x00041600},
1351 {0x0f80, 0x00fffaff},
1352 {0x0fec, 0x00901809},
1353 {0x0ffe, 0x00b01007},
1354 {0x16b0, 0x00eeff00},
1355 {0x16b2, 0x00007000},
1356 {0x16b4, 0x00000814},
1357 };
1358 static const struct reg_val pre_init2[] = {
1359 {0x0486, 0x0008a518},
1360 {0x0488, 0x006dc696},
1361 {0x048a, 0x00000912},
1362 };
1363 const struct firmware *fw;
1364 struct device *dev = &phydev->mdio.dev;
1365 unsigned int i;
1366 u16 crc, reg;
1367 int ret;
1368
1369 ret = vsc8584_pll5g_reset(phydev);
1370 if (ret < 0) {
1371 dev_err(dev, "failed LCPLL reset, ret: %d\n", ret);
1372 return ret;
1373 }
1374
1375 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1376
1377 /* all writes below are broadcasted to all PHYs in the same package */
1378 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1379 reg |= SMI_BROADCAST_WR_EN;
1380 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1381
1382 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0);
1383
1384 reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL);
1385 reg |= PARALLEL_DET_IGNORE_ADVERTISED;
1386 phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg);
1387
1388 /* The below register writes are tweaking analog and electrical
1389 * configuration that were determined through characterization by PHY
1390 * engineers. These don't mean anything more than "these are the best
1391 * values".
1392 */
1393 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3);
1394
1395 phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000);
1396
1397 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1398
1399 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20);
1400
1401 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1402 reg |= TR_CLK_DISABLE;
1403 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1404
1405 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1406
1407 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4));
1408
1409 reg = phy_base_read(phydev, MSCC_PHY_TR_MSB);
1410 reg &= ~0x007f;
1411 reg |= 0x0019;
1412 phy_base_write(phydev, MSCC_PHY_TR_MSB, reg);
1413
1414 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4));
1415
1416 for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
1417 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
1418
1419 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2);
1420
1421 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e);
1422
1423 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
1424
1425 for (i = 0; i < ARRAY_SIZE(pre_init2); i++)
1426 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val);
1427
1428 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
1429
1430 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
1431 reg &= ~TR_CLK_DISABLE;
1432 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
1433
1434 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1435
1436 /* end of write broadcasting */
1437 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1438 reg &= ~SMI_BROADCAST_WR_EN;
1439 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1440
1441 ret = request_firmware(&fw, MSCC_VSC8584_REVB_INT8051_FW, dev);
1442 if (ret) {
1443 dev_err(dev, "failed to load firmware %s, ret: %d\n",
1444 MSCC_VSC8584_REVB_INT8051_FW, ret);
1445 return ret;
1446 }
1447
1448 /* Add one byte to size for the one added by the patch_fw function */
1449 ret = vsc8584_get_fw_crc(phydev,
1450 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR,
1451 fw->size + 1, &crc);
1452 if (ret)
1453 goto out;
1454
1455 if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) {
1456 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n");
1457 if (vsc8584_patch_fw(phydev, fw))
1458 dev_warn(dev,
1459 "failed to patch FW, expect non-optimal device\n");
1460 }
1461
1462 vsc8584_micro_deassert_reset(phydev, false);
1463
1464 /* Add one byte to size for the one added by the patch_fw function */
1465 ret = vsc8584_get_fw_crc(phydev,
1466 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR,
1467 fw->size + 1, &crc);
1468 if (ret)
1469 goto out;
1470
1471 if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC)
1472 dev_warn(dev,
1473 "FW CRC after patching is not the expected one, expect non-optimal device\n");
1474
1475 ret = vsc8584_micro_assert_reset(phydev);
1476 if (ret)
1477 goto out;
1478
1479 /* Write patch vector 0, to skip IB cal polling */
1480 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_GPIO);
1481 reg = MSCC_ROM_TRAP_SERDES_6G_CFG; /* ROM address to trap, for patch vector 0 */
1482 ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg);
1483 if (ret)
1484 goto out;
1485
1486 reg = MSCC_RAM_TRAP_SERDES_6G_CFG; /* RAM address to jump to, when patch vector 0 enabled */
1487 ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg);
1488 if (ret)
1489 goto out;
1490
1491 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1492 reg |= PATCH_VEC_ZERO_EN; /* bit 8, enable patch vector 0 */
1493 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
1494 if (ret)
1495 goto out;
1496
1497 vsc8584_micro_deassert_reset(phydev, true);
1498
1499 out:
1500 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1501
1502 release_firmware(fw);
1503
1504 return ret;
1505 }
1506
vsc8584_get_base_addr(struct phy_device * phydev)1507 static void vsc8584_get_base_addr(struct phy_device *phydev)
1508 {
1509 struct vsc8531_private *vsc8531 = phydev->priv;
1510 u16 val, addr;
1511
1512 phy_lock_mdio_bus(phydev);
1513 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED);
1514
1515 addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4);
1516 addr >>= PHY_CNTL_4_ADDR_POS;
1517
1518 val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL);
1519
1520 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1521 phy_unlock_mdio_bus(phydev);
1522
1523 /* In the package, there are two pairs of PHYs (PHY0 + PHY2 and
1524 * PHY1 + PHY3). The first PHY of each pair (PHY0 and PHY1) is
1525 * the base PHY for timestamping operations.
1526 */
1527 vsc8531->ts_base_addr = phydev->mdio.addr;
1528 vsc8531->ts_base_phy = addr;
1529
1530 if (val & PHY_ADDR_REVERSED) {
1531 vsc8531->base_addr = phydev->mdio.addr + addr;
1532 if (addr > 1) {
1533 vsc8531->ts_base_addr += 2;
1534 vsc8531->ts_base_phy += 2;
1535 }
1536 } else {
1537 vsc8531->base_addr = phydev->mdio.addr - addr;
1538 if (addr > 1) {
1539 vsc8531->ts_base_addr -= 2;
1540 vsc8531->ts_base_phy -= 2;
1541 }
1542 }
1543
1544 vsc8531->addr = addr;
1545 }
1546
vsc85xx_coma_mode_release(struct phy_device * phydev)1547 static void vsc85xx_coma_mode_release(struct phy_device *phydev)
1548 {
1549 /* The coma mode (pin or reg) provides an optional feature that
1550 * may be used to control when the PHYs become active.
1551 * Alternatively the COMA_MODE pin may be connected low
1552 * so that the PHYs are fully active once out of reset.
1553 */
1554
1555 /* Enable output (mode=0) and write zero to it */
1556 vsc85xx_phy_write_page(phydev, MSCC_PHY_PAGE_EXTENDED_GPIO);
1557 __phy_modify(phydev, MSCC_PHY_GPIO_CONTROL_2,
1558 MSCC_PHY_COMA_MODE | MSCC_PHY_COMA_OUTPUT, 0);
1559 vsc85xx_phy_write_page(phydev, MSCC_PHY_PAGE_STANDARD);
1560 }
1561
vsc8584_config_host_serdes(struct phy_device * phydev)1562 static int vsc8584_config_host_serdes(struct phy_device *phydev)
1563 {
1564 struct vsc8531_private *vsc8531 = phydev->priv;
1565 int ret;
1566 u16 val;
1567
1568 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1569 MSCC_PHY_PAGE_EXTENDED_GPIO);
1570 if (ret)
1571 return ret;
1572
1573 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1574 val &= ~MAC_CFG_MASK;
1575 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
1576 val |= MAC_CFG_QSGMII;
1577 } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1578 val |= MAC_CFG_SGMII;
1579 } else {
1580 ret = -EINVAL;
1581 return ret;
1582 }
1583
1584 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1585 if (ret)
1586 return ret;
1587
1588 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1589 MSCC_PHY_PAGE_STANDARD);
1590 if (ret)
1591 return ret;
1592
1593 val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT |
1594 PROC_CMD_READ_MOD_WRITE_PORT;
1595 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII)
1596 val |= PROC_CMD_QSGMII_MAC;
1597 else
1598 val |= PROC_CMD_SGMII_MAC;
1599
1600 ret = vsc8584_cmd(phydev, val);
1601 if (ret)
1602 return ret;
1603
1604 usleep_range(10000, 20000);
1605
1606 /* Disable SerDes for 100Base-FX */
1607 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1608 PROC_CMD_FIBER_PORT(vsc8531->addr) |
1609 PROC_CMD_FIBER_DISABLE |
1610 PROC_CMD_READ_MOD_WRITE_PORT |
1611 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_100BASE_FX);
1612 if (ret)
1613 return ret;
1614
1615 /* Disable SerDes for 1000Base-X */
1616 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1617 PROC_CMD_FIBER_PORT(vsc8531->addr) |
1618 PROC_CMD_FIBER_DISABLE |
1619 PROC_CMD_READ_MOD_WRITE_PORT |
1620 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_1000BASE_X);
1621 if (ret)
1622 return ret;
1623
1624 return vsc85xx_sd6g_config_v2(phydev);
1625 }
1626
vsc8574_config_host_serdes(struct phy_device * phydev)1627 static int vsc8574_config_host_serdes(struct phy_device *phydev)
1628 {
1629 struct vsc8531_private *vsc8531 = phydev->priv;
1630 int ret;
1631 u16 val;
1632
1633 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1634 MSCC_PHY_PAGE_EXTENDED_GPIO);
1635 if (ret)
1636 return ret;
1637
1638 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1639 val &= ~MAC_CFG_MASK;
1640 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) {
1641 val |= MAC_CFG_QSGMII;
1642 } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1643 val |= MAC_CFG_SGMII;
1644 } else if (phy_interface_is_rgmii(phydev)) {
1645 val |= MAC_CFG_RGMII;
1646 } else {
1647 ret = -EINVAL;
1648 return ret;
1649 }
1650
1651 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1652 if (ret)
1653 return ret;
1654
1655 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1656 MSCC_PHY_PAGE_STANDARD);
1657 if (ret)
1658 return ret;
1659
1660 if (!phy_interface_is_rgmii(phydev)) {
1661 val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT |
1662 PROC_CMD_READ_MOD_WRITE_PORT;
1663 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII)
1664 val |= PROC_CMD_QSGMII_MAC;
1665 else
1666 val |= PROC_CMD_SGMII_MAC;
1667
1668 ret = vsc8584_cmd(phydev, val);
1669 if (ret)
1670 return ret;
1671
1672 usleep_range(10000, 20000);
1673 }
1674
1675 /* Disable SerDes for 100Base-FX */
1676 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1677 PROC_CMD_FIBER_PORT(vsc8531->addr) |
1678 PROC_CMD_FIBER_DISABLE |
1679 PROC_CMD_READ_MOD_WRITE_PORT |
1680 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_100BASE_FX);
1681 if (ret)
1682 return ret;
1683
1684 /* Disable SerDes for 1000Base-X */
1685 return vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF |
1686 PROC_CMD_FIBER_PORT(vsc8531->addr) |
1687 PROC_CMD_FIBER_DISABLE |
1688 PROC_CMD_READ_MOD_WRITE_PORT |
1689 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_1000BASE_X);
1690 }
1691
vsc8584_config_init(struct phy_device * phydev)1692 static int vsc8584_config_init(struct phy_device *phydev)
1693 {
1694 struct vsc8531_private *vsc8531 = phydev->priv;
1695 int ret, i;
1696 u16 val;
1697
1698 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1699
1700 phy_lock_mdio_bus(phydev);
1701
1702 /* Some parts of the init sequence are identical for every PHY in the
1703 * package. Some parts are modifying the GPIO register bank which is a
1704 * set of registers that are affecting all PHYs, a few resetting the
1705 * microprocessor common to all PHYs. The CRC check responsible of the
1706 * checking the firmware within the 8051 microprocessor can only be
1707 * accessed via the PHY whose internal address in the package is 0.
1708 * All PHYs' interrupts mask register has to be zeroed before enabling
1709 * any PHY's interrupt in this register.
1710 * For all these reasons, we need to do the init sequence once and only
1711 * once whatever is the first PHY in the package that is initialized and
1712 * do the correct init sequence for all PHYs that are package-critical
1713 * in this pre-init function.
1714 */
1715 if (phy_package_init_once(phydev)) {
1716 /* The following switch statement assumes that the lowest
1717 * nibble of the phy_id_mask is always 0. This works because
1718 * the lowest nibble of the PHY_ID's below are also 0.
1719 */
1720 WARN_ON(phydev->drv->phy_id_mask & 0xf);
1721
1722 switch (phydev->phy_id & phydev->drv->phy_id_mask) {
1723 case PHY_ID_VSC8504:
1724 case PHY_ID_VSC8552:
1725 case PHY_ID_VSC8572:
1726 case PHY_ID_VSC8574:
1727 ret = vsc8574_config_pre_init(phydev);
1728 if (ret)
1729 goto err;
1730 ret = vsc8574_config_host_serdes(phydev);
1731 if (ret)
1732 goto err;
1733 break;
1734 case PHY_ID_VSC856X:
1735 case PHY_ID_VSC8575:
1736 case PHY_ID_VSC8582:
1737 case PHY_ID_VSC8584:
1738 ret = vsc8584_config_pre_init(phydev);
1739 if (ret)
1740 goto err;
1741 ret = vsc8584_config_host_serdes(phydev);
1742 if (ret)
1743 goto err;
1744 vsc85xx_coma_mode_release(phydev);
1745 break;
1746 default:
1747 ret = -EINVAL;
1748 break;
1749 }
1750
1751 if (ret)
1752 goto err;
1753 }
1754
1755 phy_unlock_mdio_bus(phydev);
1756
1757 ret = vsc8584_macsec_init(phydev);
1758 if (ret)
1759 return ret;
1760
1761 ret = vsc8584_ptp_init(phydev);
1762 if (ret)
1763 return ret;
1764
1765 val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
1766 val &= ~(MEDIA_OP_MODE_MASK | VSC8584_MAC_IF_SELECTION_MASK);
1767 val |= (MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS) |
1768 (VSC8584_MAC_IF_SELECTION_SGMII << VSC8584_MAC_IF_SELECTION_POS);
1769 ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val);
1770 if (ret)
1771 return ret;
1772
1773 ret = vsc85xx_update_rgmii_cntl(phydev, VSC8572_RGMII_CNTL,
1774 VSC8572_RGMII_RX_DELAY_MASK,
1775 VSC8572_RGMII_TX_DELAY_MASK);
1776 if (ret)
1777 return ret;
1778
1779 ret = genphy_soft_reset(phydev);
1780 if (ret)
1781 return ret;
1782
1783 for (i = 0; i < vsc8531->nleds; i++) {
1784 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1785 if (ret)
1786 return ret;
1787 }
1788
1789 return 0;
1790
1791 err:
1792 phy_unlock_mdio_bus(phydev);
1793 return ret;
1794 }
1795
vsc8584_handle_interrupt(struct phy_device * phydev)1796 static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev)
1797 {
1798 irqreturn_t ret;
1799 int irq_status;
1800
1801 irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS);
1802 if (irq_status < 0)
1803 return IRQ_NONE;
1804
1805 /* Timestamping IRQ does not set a bit in the global INT_STATUS, so
1806 * irq_status would be 0.
1807 */
1808 ret = vsc8584_handle_ts_interrupt(phydev);
1809 if (!(irq_status & MII_VSC85XX_INT_MASK_MASK))
1810 return ret;
1811
1812 if (irq_status & MII_VSC85XX_INT_MASK_EXT)
1813 vsc8584_handle_macsec_interrupt(phydev);
1814
1815 if (irq_status & MII_VSC85XX_INT_MASK_LINK_CHG)
1816 phy_trigger_machine(phydev);
1817
1818 return IRQ_HANDLED;
1819 }
1820
vsc85xx_config_init(struct phy_device * phydev)1821 static int vsc85xx_config_init(struct phy_device *phydev)
1822 {
1823 int rc, i, phy_id;
1824 struct vsc8531_private *vsc8531 = phydev->priv;
1825
1826 rc = vsc85xx_default_config(phydev);
1827 if (rc)
1828 return rc;
1829
1830 rc = vsc85xx_mac_if_set(phydev, phydev->interface);
1831 if (rc)
1832 return rc;
1833
1834 rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic);
1835 if (rc)
1836 return rc;
1837
1838 phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask;
1839 if (PHY_ID_VSC8531 == phy_id || PHY_ID_VSC8541 == phy_id ||
1840 PHY_ID_VSC8530 == phy_id || PHY_ID_VSC8540 == phy_id) {
1841 rc = vsc8531_pre_init_seq_set(phydev);
1842 if (rc)
1843 return rc;
1844 }
1845
1846 rc = vsc85xx_eee_init_seq_set(phydev);
1847 if (rc)
1848 return rc;
1849
1850 for (i = 0; i < vsc8531->nleds; i++) {
1851 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
1852 if (rc)
1853 return rc;
1854 }
1855
1856 return 0;
1857 }
1858
__phy_write_mcb_s6g(struct phy_device * phydev,u32 reg,u8 mcb,u32 op)1859 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb,
1860 u32 op)
1861 {
1862 unsigned long deadline;
1863 u32 val;
1864 int ret;
1865
1866 ret = vsc85xx_csr_write(phydev, PHY_MCB_TARGET, reg,
1867 op | (1 << mcb));
1868 if (ret)
1869 return -EINVAL;
1870
1871 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS);
1872 do {
1873 usleep_range(500, 1000);
1874 val = vsc85xx_csr_read(phydev, PHY_MCB_TARGET, reg);
1875
1876 if (val == 0xffffffff)
1877 return -EIO;
1878
1879 } while (time_before(jiffies, deadline) && (val & op));
1880
1881 if (val & op)
1882 return -ETIMEDOUT;
1883
1884 return 0;
1885 }
1886
1887 /* Trigger a read to the specified MCB */
phy_update_mcb_s6g(struct phy_device * phydev,u32 reg,u8 mcb)1888 int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1889 {
1890 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ);
1891 }
1892
1893 /* Trigger a write to the specified MCB */
phy_commit_mcb_s6g(struct phy_device * phydev,u32 reg,u8 mcb)1894 int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb)
1895 {
1896 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE);
1897 }
1898
vsc8514_config_host_serdes(struct phy_device * phydev)1899 static int vsc8514_config_host_serdes(struct phy_device *phydev)
1900 {
1901 int ret;
1902 u16 val;
1903
1904 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1905 MSCC_PHY_PAGE_EXTENDED_GPIO);
1906 if (ret)
1907 return ret;
1908
1909 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK);
1910 val &= ~MAC_CFG_MASK;
1911 val |= MAC_CFG_QSGMII;
1912 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val);
1913 if (ret)
1914 return ret;
1915
1916 ret = phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
1917 MSCC_PHY_PAGE_STANDARD);
1918 if (ret)
1919 return ret;
1920
1921 ret = vsc8584_cmd(phydev, PROC_CMD_NOP);
1922 if (ret)
1923 return ret;
1924
1925 ret = vsc8584_cmd(phydev,
1926 PROC_CMD_MCB_ACCESS_MAC_CONF |
1927 PROC_CMD_RST_CONF_PORT |
1928 PROC_CMD_READ_MOD_WRITE_PORT | PROC_CMD_QSGMII_MAC);
1929 if (ret) {
1930 dev_err(&phydev->mdio.dev, "%s: QSGMII error: %d\n",
1931 __func__, ret);
1932 return ret;
1933 }
1934
1935 /* Apply 6G SerDes FOJI Algorithm
1936 * Initial condition requirement:
1937 * 1. hold 8051 in reset
1938 * 2. disable patch vector 0, in order to allow IB cal poll during FoJi
1939 * 3. deassert 8051 reset after change patch vector status
1940 * 4. proceed with FoJi (vsc85xx_sd6g_config_v2)
1941 */
1942 vsc8584_micro_assert_reset(phydev);
1943 val = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
1944 /* clear bit 8, to disable patch vector 0 */
1945 val &= ~PATCH_VEC_ZERO_EN;
1946 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, val);
1947 /* Enable 8051 clock, don't set patch present, disable PRAM clock override */
1948 vsc8584_micro_deassert_reset(phydev, false);
1949
1950 return vsc85xx_sd6g_config_v2(phydev);
1951 }
1952
vsc8514_config_pre_init(struct phy_device * phydev)1953 static int vsc8514_config_pre_init(struct phy_device *phydev)
1954 {
1955 /* These are the settings to override the silicon default
1956 * values to handle hardware performance of PHY. They
1957 * are set at Power-On state and remain until PHY Reset.
1958 */
1959 static const struct reg_val pre_init1[] = {
1960 {0x0f90, 0x00688980},
1961 {0x0786, 0x00000003},
1962 {0x07fa, 0x0050100f},
1963 {0x0f82, 0x0012b002},
1964 {0x1686, 0x00000004},
1965 {0x168c, 0x00d2c46f},
1966 {0x17a2, 0x00000620},
1967 {0x16a0, 0x00eeffdd},
1968 {0x16a6, 0x00071448},
1969 {0x16a4, 0x0013132f},
1970 {0x16a8, 0x00000000},
1971 {0x0ffc, 0x00c0a028},
1972 {0x0fe8, 0x0091b06c},
1973 {0x0fea, 0x00041600},
1974 {0x0f80, 0x00fffaff},
1975 {0x0fec, 0x00901809},
1976 {0x0ffe, 0x00b01007},
1977 {0x16b0, 0x00eeff00},
1978 {0x16b2, 0x00007000},
1979 {0x16b4, 0x00000814},
1980 };
1981 struct device *dev = &phydev->mdio.dev;
1982 unsigned int i;
1983 u16 reg;
1984 int ret;
1985
1986 ret = vsc8584_pll5g_reset(phydev);
1987 if (ret < 0) {
1988 dev_err(dev, "failed LCPLL reset, ret: %d\n", ret);
1989 return ret;
1990 }
1991
1992 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
1993
1994 /* all writes below are broadcasted to all PHYs in the same package */
1995 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
1996 reg |= SMI_BROADCAST_WR_EN;
1997 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
1998
1999 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
2000
2001 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
2002 reg |= BIT(15);
2003 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
2004
2005 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR);
2006
2007 for (i = 0; i < ARRAY_SIZE(pre_init1); i++)
2008 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val);
2009
2010 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST);
2011
2012 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8);
2013 reg &= ~BIT(15);
2014 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg);
2015
2016 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD);
2017
2018 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS);
2019 reg &= ~SMI_BROADCAST_WR_EN;
2020 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg);
2021
2022 /* Add pre-patching commands to:
2023 * 1. enable 8051 clock, operate 8051 clock at 125 MHz
2024 * instead of HW default 62.5MHz
2025 * 2. write patch vector 0, to skip IB cal polling executed
2026 * as part of the 0x80E0 ROM command
2027 */
2028 vsc8584_micro_deassert_reset(phydev, false);
2029
2030 vsc8584_micro_assert_reset(phydev);
2031 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS,
2032 MSCC_PHY_PAGE_EXTENDED_GPIO);
2033 /* ROM address to trap, for patch vector 0 */
2034 reg = MSCC_ROM_TRAP_SERDES_6G_CFG;
2035 ret = phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), reg);
2036 if (ret)
2037 goto err;
2038 /* RAM address to jump to, when patch vector 0 enabled */
2039 reg = MSCC_RAM_TRAP_SERDES_6G_CFG;
2040 ret = phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), reg);
2041 if (ret)
2042 goto err;
2043 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL);
2044 reg |= PATCH_VEC_ZERO_EN; /* bit 8, enable patch vector 0 */
2045 ret = phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg);
2046 if (ret)
2047 goto err;
2048
2049 /* Enable 8051 clock, don't set patch present
2050 * yet, disable PRAM clock override
2051 */
2052 vsc8584_micro_deassert_reset(phydev, false);
2053 return ret;
2054 err:
2055 /* restore 8051 and bail w error */
2056 vsc8584_micro_deassert_reset(phydev, false);
2057 return ret;
2058 }
2059
vsc8514_config_init(struct phy_device * phydev)2060 static int vsc8514_config_init(struct phy_device *phydev)
2061 {
2062 struct vsc8531_private *vsc8531 = phydev->priv;
2063 int ret, i;
2064
2065 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
2066
2067 phy_lock_mdio_bus(phydev);
2068
2069 /* Some parts of the init sequence are identical for every PHY in the
2070 * package. Some parts are modifying the GPIO register bank which is a
2071 * set of registers that are affecting all PHYs, a few resetting the
2072 * microprocessor common to all PHYs.
2073 * All PHYs' interrupts mask register has to be zeroed before enabling
2074 * any PHY's interrupt in this register.
2075 * For all these reasons, we need to do the init sequence once and only
2076 * once whatever is the first PHY in the package that is initialized and
2077 * do the correct init sequence for all PHYs that are package-critical
2078 * in this pre-init function.
2079 */
2080 if (phy_package_init_once(phydev)) {
2081 ret = vsc8514_config_pre_init(phydev);
2082 if (ret)
2083 goto err;
2084 ret = vsc8514_config_host_serdes(phydev);
2085 if (ret)
2086 goto err;
2087 vsc85xx_coma_mode_release(phydev);
2088 }
2089
2090 phy_unlock_mdio_bus(phydev);
2091
2092 ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK,
2093 MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS);
2094
2095 if (ret)
2096 return ret;
2097
2098 ret = genphy_soft_reset(phydev);
2099
2100 if (ret)
2101 return ret;
2102
2103 for (i = 0; i < vsc8531->nleds; i++) {
2104 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]);
2105 if (ret)
2106 return ret;
2107 }
2108
2109 return ret;
2110
2111 err:
2112 phy_unlock_mdio_bus(phydev);
2113 return ret;
2114 }
2115
vsc85xx_ack_interrupt(struct phy_device * phydev)2116 static int vsc85xx_ack_interrupt(struct phy_device *phydev)
2117 {
2118 int rc = 0;
2119
2120 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
2121 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
2122
2123 return (rc < 0) ? rc : 0;
2124 }
2125
vsc85xx_config_intr(struct phy_device * phydev)2126 static int vsc85xx_config_intr(struct phy_device *phydev)
2127 {
2128 int rc;
2129
2130 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
2131 rc = vsc85xx_ack_interrupt(phydev);
2132 if (rc)
2133 return rc;
2134
2135 vsc8584_config_macsec_intr(phydev);
2136 vsc8584_config_ts_intr(phydev);
2137
2138 rc = phy_write(phydev, MII_VSC85XX_INT_MASK,
2139 MII_VSC85XX_INT_MASK_MASK);
2140 } else {
2141 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0);
2142 if (rc < 0)
2143 return rc;
2144 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS);
2145 if (rc < 0)
2146 return rc;
2147
2148 rc = vsc85xx_ack_interrupt(phydev);
2149 }
2150
2151 return rc;
2152 }
2153
vsc85xx_handle_interrupt(struct phy_device * phydev)2154 static irqreturn_t vsc85xx_handle_interrupt(struct phy_device *phydev)
2155 {
2156 int irq_status;
2157
2158 irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS);
2159 if (irq_status < 0) {
2160 phy_error(phydev);
2161 return IRQ_NONE;
2162 }
2163
2164 if (!(irq_status & MII_VSC85XX_INT_MASK_MASK))
2165 return IRQ_NONE;
2166
2167 phy_trigger_machine(phydev);
2168
2169 return IRQ_HANDLED;
2170 }
2171
vsc85xx_config_aneg(struct phy_device * phydev)2172 static int vsc85xx_config_aneg(struct phy_device *phydev)
2173 {
2174 int rc;
2175
2176 rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl);
2177 if (rc < 0)
2178 return rc;
2179
2180 return genphy_config_aneg(phydev);
2181 }
2182
vsc85xx_read_status(struct phy_device * phydev)2183 static int vsc85xx_read_status(struct phy_device *phydev)
2184 {
2185 int rc;
2186
2187 rc = vsc85xx_mdix_get(phydev, &phydev->mdix);
2188 if (rc < 0)
2189 return rc;
2190
2191 return genphy_read_status(phydev);
2192 }
2193
vsc8514_probe(struct phy_device * phydev)2194 static int vsc8514_probe(struct phy_device *phydev)
2195 {
2196 struct vsc8531_private *vsc8531;
2197 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
2198 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
2199 VSC8531_DUPLEX_COLLISION};
2200
2201 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2202 if (!vsc8531)
2203 return -ENOMEM;
2204
2205 phydev->priv = vsc8531;
2206
2207 vsc8584_get_base_addr(phydev);
2208 devm_phy_package_join(&phydev->mdio.dev, phydev,
2209 vsc8531->base_addr, 0);
2210
2211 vsc8531->nleds = 4;
2212 vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES;
2213 vsc8531->hw_stats = vsc85xx_hw_stats;
2214 vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats);
2215 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2216 sizeof(u64), GFP_KERNEL);
2217 if (!vsc8531->stats)
2218 return -ENOMEM;
2219
2220 return vsc85xx_dt_led_modes_get(phydev, default_mode);
2221 }
2222
vsc8574_probe(struct phy_device * phydev)2223 static int vsc8574_probe(struct phy_device *phydev)
2224 {
2225 struct vsc8531_private *vsc8531;
2226 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
2227 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
2228 VSC8531_DUPLEX_COLLISION};
2229
2230 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2231 if (!vsc8531)
2232 return -ENOMEM;
2233
2234 phydev->priv = vsc8531;
2235
2236 vsc8584_get_base_addr(phydev);
2237 devm_phy_package_join(&phydev->mdio.dev, phydev,
2238 vsc8531->base_addr, 0);
2239
2240 vsc8531->nleds = 4;
2241 vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
2242 vsc8531->hw_stats = vsc8584_hw_stats;
2243 vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats);
2244 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2245 sizeof(u64), GFP_KERNEL);
2246 if (!vsc8531->stats)
2247 return -ENOMEM;
2248
2249 return vsc85xx_dt_led_modes_get(phydev, default_mode);
2250 }
2251
vsc8584_probe(struct phy_device * phydev)2252 static int vsc8584_probe(struct phy_device *phydev)
2253 {
2254 struct vsc8531_private *vsc8531;
2255 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY,
2256 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY,
2257 VSC8531_DUPLEX_COLLISION};
2258 int ret;
2259
2260 if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) {
2261 dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n");
2262 return -ENOTSUPP;
2263 }
2264
2265 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2266 if (!vsc8531)
2267 return -ENOMEM;
2268
2269 phydev->priv = vsc8531;
2270
2271 vsc8584_get_base_addr(phydev);
2272 devm_phy_package_join(&phydev->mdio.dev, phydev, vsc8531->base_addr,
2273 sizeof(struct vsc85xx_shared_private));
2274
2275 vsc8531->nleds = 4;
2276 vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES;
2277 vsc8531->hw_stats = vsc8584_hw_stats;
2278 vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats);
2279 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2280 sizeof(u64), GFP_KERNEL);
2281 if (!vsc8531->stats)
2282 return -ENOMEM;
2283
2284 if (phy_package_probe_once(phydev)) {
2285 ret = vsc8584_ptp_probe_once(phydev);
2286 if (ret)
2287 return ret;
2288 }
2289
2290 ret = vsc8584_ptp_probe(phydev);
2291 if (ret)
2292 return ret;
2293
2294 return vsc85xx_dt_led_modes_get(phydev, default_mode);
2295 }
2296
vsc85xx_probe(struct phy_device * phydev)2297 static int vsc85xx_probe(struct phy_device *phydev)
2298 {
2299 struct vsc8531_private *vsc8531;
2300 int rate_magic;
2301 u32 default_mode[2] = {VSC8531_LINK_1000_ACTIVITY,
2302 VSC8531_LINK_100_ACTIVITY};
2303
2304 rate_magic = vsc85xx_edge_rate_magic_get(phydev);
2305 if (rate_magic < 0)
2306 return rate_magic;
2307
2308 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL);
2309 if (!vsc8531)
2310 return -ENOMEM;
2311
2312 phydev->priv = vsc8531;
2313
2314 vsc8531->rate_magic = rate_magic;
2315 vsc8531->nleds = 2;
2316 vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES;
2317 vsc8531->hw_stats = vsc85xx_hw_stats;
2318 vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats);
2319 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats,
2320 sizeof(u64), GFP_KERNEL);
2321 if (!vsc8531->stats)
2322 return -ENOMEM;
2323
2324 return vsc85xx_dt_led_modes_get(phydev, default_mode);
2325 }
2326
2327 /* Microsemi VSC85xx PHYs */
2328 static struct phy_driver vsc85xx_driver[] = {
2329 {
2330 .phy_id = PHY_ID_VSC8502,
2331 .name = "Microsemi GE VSC8502 SyncE",
2332 .phy_id_mask = 0xfffffff0,
2333 /* PHY_BASIC_FEATURES */
2334 .soft_reset = &genphy_soft_reset,
2335 .config_init = &vsc85xx_config_init,
2336 .config_aneg = &vsc85xx_config_aneg,
2337 .read_status = &vsc85xx_read_status,
2338 .handle_interrupt = vsc85xx_handle_interrupt,
2339 .config_intr = &vsc85xx_config_intr,
2340 .suspend = &genphy_suspend,
2341 .resume = &genphy_resume,
2342 .probe = &vsc85xx_probe,
2343 .set_wol = &vsc85xx_wol_set,
2344 .get_wol = &vsc85xx_wol_get,
2345 .get_tunable = &vsc85xx_get_tunable,
2346 .set_tunable = &vsc85xx_set_tunable,
2347 .read_page = &vsc85xx_phy_read_page,
2348 .write_page = &vsc85xx_phy_write_page,
2349 .get_sset_count = &vsc85xx_get_sset_count,
2350 .get_strings = &vsc85xx_get_strings,
2351 .get_stats = &vsc85xx_get_stats,
2352 },
2353 {
2354 .phy_id = PHY_ID_VSC8504,
2355 .name = "Microsemi GE VSC8504 SyncE",
2356 .phy_id_mask = 0xfffffff0,
2357 /* PHY_GBIT_FEATURES */
2358 .soft_reset = &genphy_soft_reset,
2359 .config_init = &vsc8584_config_init,
2360 .config_aneg = &vsc85xx_config_aneg,
2361 .aneg_done = &genphy_aneg_done,
2362 .read_status = &vsc85xx_read_status,
2363 .handle_interrupt = vsc85xx_handle_interrupt,
2364 .config_intr = &vsc85xx_config_intr,
2365 .suspend = &genphy_suspend,
2366 .resume = &genphy_resume,
2367 .probe = &vsc8574_probe,
2368 .set_wol = &vsc85xx_wol_set,
2369 .get_wol = &vsc85xx_wol_get,
2370 .get_tunable = &vsc85xx_get_tunable,
2371 .set_tunable = &vsc85xx_set_tunable,
2372 .read_page = &vsc85xx_phy_read_page,
2373 .write_page = &vsc85xx_phy_write_page,
2374 .get_sset_count = &vsc85xx_get_sset_count,
2375 .get_strings = &vsc85xx_get_strings,
2376 .get_stats = &vsc85xx_get_stats,
2377 },
2378 {
2379 .phy_id = PHY_ID_VSC8514,
2380 .name = "Microsemi GE VSC8514 SyncE",
2381 .phy_id_mask = 0xfffffff0,
2382 .soft_reset = &genphy_soft_reset,
2383 .config_init = &vsc8514_config_init,
2384 .config_aneg = &vsc85xx_config_aneg,
2385 .read_status = &vsc85xx_read_status,
2386 .handle_interrupt = vsc85xx_handle_interrupt,
2387 .config_intr = &vsc85xx_config_intr,
2388 .suspend = &genphy_suspend,
2389 .resume = &genphy_resume,
2390 .probe = &vsc8514_probe,
2391 .set_wol = &vsc85xx_wol_set,
2392 .get_wol = &vsc85xx_wol_get,
2393 .get_tunable = &vsc85xx_get_tunable,
2394 .set_tunable = &vsc85xx_set_tunable,
2395 .read_page = &vsc85xx_phy_read_page,
2396 .write_page = &vsc85xx_phy_write_page,
2397 .get_sset_count = &vsc85xx_get_sset_count,
2398 .get_strings = &vsc85xx_get_strings,
2399 .get_stats = &vsc85xx_get_stats,
2400 },
2401 {
2402 .phy_id = PHY_ID_VSC8530,
2403 .name = "Microsemi FE VSC8530",
2404 .phy_id_mask = 0xfffffff0,
2405 /* PHY_BASIC_FEATURES */
2406 .soft_reset = &genphy_soft_reset,
2407 .config_init = &vsc85xx_config_init,
2408 .config_aneg = &vsc85xx_config_aneg,
2409 .read_status = &vsc85xx_read_status,
2410 .handle_interrupt = vsc85xx_handle_interrupt,
2411 .config_intr = &vsc85xx_config_intr,
2412 .suspend = &genphy_suspend,
2413 .resume = &genphy_resume,
2414 .probe = &vsc85xx_probe,
2415 .set_wol = &vsc85xx_wol_set,
2416 .get_wol = &vsc85xx_wol_get,
2417 .get_tunable = &vsc85xx_get_tunable,
2418 .set_tunable = &vsc85xx_set_tunable,
2419 .read_page = &vsc85xx_phy_read_page,
2420 .write_page = &vsc85xx_phy_write_page,
2421 .get_sset_count = &vsc85xx_get_sset_count,
2422 .get_strings = &vsc85xx_get_strings,
2423 .get_stats = &vsc85xx_get_stats,
2424 },
2425 {
2426 .phy_id = PHY_ID_VSC8531,
2427 .name = "Microsemi VSC8531",
2428 .phy_id_mask = 0xfffffff0,
2429 /* PHY_GBIT_FEATURES */
2430 .soft_reset = &genphy_soft_reset,
2431 .config_init = &vsc85xx_config_init,
2432 .config_aneg = &vsc85xx_config_aneg,
2433 .read_status = &vsc85xx_read_status,
2434 .handle_interrupt = vsc85xx_handle_interrupt,
2435 .config_intr = &vsc85xx_config_intr,
2436 .suspend = &genphy_suspend,
2437 .resume = &genphy_resume,
2438 .probe = &vsc85xx_probe,
2439 .set_wol = &vsc85xx_wol_set,
2440 .get_wol = &vsc85xx_wol_get,
2441 .get_tunable = &vsc85xx_get_tunable,
2442 .set_tunable = &vsc85xx_set_tunable,
2443 .read_page = &vsc85xx_phy_read_page,
2444 .write_page = &vsc85xx_phy_write_page,
2445 .get_sset_count = &vsc85xx_get_sset_count,
2446 .get_strings = &vsc85xx_get_strings,
2447 .get_stats = &vsc85xx_get_stats,
2448 },
2449 {
2450 .phy_id = PHY_ID_VSC8540,
2451 .name = "Microsemi FE VSC8540 SyncE",
2452 .phy_id_mask = 0xfffffff0,
2453 /* PHY_BASIC_FEATURES */
2454 .soft_reset = &genphy_soft_reset,
2455 .config_init = &vsc85xx_config_init,
2456 .config_aneg = &vsc85xx_config_aneg,
2457 .read_status = &vsc85xx_read_status,
2458 .handle_interrupt = vsc85xx_handle_interrupt,
2459 .config_intr = &vsc85xx_config_intr,
2460 .suspend = &genphy_suspend,
2461 .resume = &genphy_resume,
2462 .probe = &vsc85xx_probe,
2463 .set_wol = &vsc85xx_wol_set,
2464 .get_wol = &vsc85xx_wol_get,
2465 .get_tunable = &vsc85xx_get_tunable,
2466 .set_tunable = &vsc85xx_set_tunable,
2467 .read_page = &vsc85xx_phy_read_page,
2468 .write_page = &vsc85xx_phy_write_page,
2469 .get_sset_count = &vsc85xx_get_sset_count,
2470 .get_strings = &vsc85xx_get_strings,
2471 .get_stats = &vsc85xx_get_stats,
2472 },
2473 {
2474 .phy_id = PHY_ID_VSC8541,
2475 .name = "Microsemi VSC8541 SyncE",
2476 .phy_id_mask = 0xfffffff0,
2477 /* PHY_GBIT_FEATURES */
2478 .soft_reset = &genphy_soft_reset,
2479 .config_init = &vsc85xx_config_init,
2480 .config_aneg = &vsc85xx_config_aneg,
2481 .read_status = &vsc85xx_read_status,
2482 .handle_interrupt = vsc85xx_handle_interrupt,
2483 .config_intr = &vsc85xx_config_intr,
2484 .suspend = &genphy_suspend,
2485 .resume = &genphy_resume,
2486 .probe = &vsc85xx_probe,
2487 .set_wol = &vsc85xx_wol_set,
2488 .get_wol = &vsc85xx_wol_get,
2489 .get_tunable = &vsc85xx_get_tunable,
2490 .set_tunable = &vsc85xx_set_tunable,
2491 .read_page = &vsc85xx_phy_read_page,
2492 .write_page = &vsc85xx_phy_write_page,
2493 .get_sset_count = &vsc85xx_get_sset_count,
2494 .get_strings = &vsc85xx_get_strings,
2495 .get_stats = &vsc85xx_get_stats,
2496 },
2497 {
2498 .phy_id = PHY_ID_VSC8552,
2499 .name = "Microsemi GE VSC8552 SyncE",
2500 .phy_id_mask = 0xfffffff0,
2501 /* PHY_GBIT_FEATURES */
2502 .soft_reset = &genphy_soft_reset,
2503 .config_init = &vsc8584_config_init,
2504 .config_aneg = &vsc85xx_config_aneg,
2505 .read_status = &vsc85xx_read_status,
2506 .handle_interrupt = vsc85xx_handle_interrupt,
2507 .config_intr = &vsc85xx_config_intr,
2508 .suspend = &genphy_suspend,
2509 .resume = &genphy_resume,
2510 .probe = &vsc8574_probe,
2511 .set_wol = &vsc85xx_wol_set,
2512 .get_wol = &vsc85xx_wol_get,
2513 .get_tunable = &vsc85xx_get_tunable,
2514 .set_tunable = &vsc85xx_set_tunable,
2515 .read_page = &vsc85xx_phy_read_page,
2516 .write_page = &vsc85xx_phy_write_page,
2517 .get_sset_count = &vsc85xx_get_sset_count,
2518 .get_strings = &vsc85xx_get_strings,
2519 .get_stats = &vsc85xx_get_stats,
2520 },
2521 {
2522 .phy_id = PHY_ID_VSC856X,
2523 .name = "Microsemi GE VSC856X SyncE",
2524 .phy_id_mask = 0xfffffff0,
2525 /* PHY_GBIT_FEATURES */
2526 .soft_reset = &genphy_soft_reset,
2527 .config_init = &vsc8584_config_init,
2528 .config_aneg = &vsc85xx_config_aneg,
2529 .read_status = &vsc85xx_read_status,
2530 .handle_interrupt = vsc85xx_handle_interrupt,
2531 .config_intr = &vsc85xx_config_intr,
2532 .suspend = &genphy_suspend,
2533 .resume = &genphy_resume,
2534 .probe = &vsc8584_probe,
2535 .get_tunable = &vsc85xx_get_tunable,
2536 .set_tunable = &vsc85xx_set_tunable,
2537 .read_page = &vsc85xx_phy_read_page,
2538 .write_page = &vsc85xx_phy_write_page,
2539 .get_sset_count = &vsc85xx_get_sset_count,
2540 .get_strings = &vsc85xx_get_strings,
2541 .get_stats = &vsc85xx_get_stats,
2542 },
2543 {
2544 .phy_id = PHY_ID_VSC8572,
2545 .name = "Microsemi GE VSC8572 SyncE",
2546 .phy_id_mask = 0xfffffff0,
2547 /* PHY_GBIT_FEATURES */
2548 .soft_reset = &genphy_soft_reset,
2549 .config_init = &vsc8584_config_init,
2550 .config_aneg = &vsc85xx_config_aneg,
2551 .aneg_done = &genphy_aneg_done,
2552 .read_status = &vsc85xx_read_status,
2553 .handle_interrupt = &vsc8584_handle_interrupt,
2554 .config_intr = &vsc85xx_config_intr,
2555 .suspend = &genphy_suspend,
2556 .resume = &genphy_resume,
2557 .probe = &vsc8574_probe,
2558 .set_wol = &vsc85xx_wol_set,
2559 .get_wol = &vsc85xx_wol_get,
2560 .get_tunable = &vsc85xx_get_tunable,
2561 .set_tunable = &vsc85xx_set_tunable,
2562 .read_page = &vsc85xx_phy_read_page,
2563 .write_page = &vsc85xx_phy_write_page,
2564 .get_sset_count = &vsc85xx_get_sset_count,
2565 .get_strings = &vsc85xx_get_strings,
2566 .get_stats = &vsc85xx_get_stats,
2567 },
2568 {
2569 .phy_id = PHY_ID_VSC8574,
2570 .name = "Microsemi GE VSC8574 SyncE",
2571 .phy_id_mask = 0xfffffff0,
2572 /* PHY_GBIT_FEATURES */
2573 .soft_reset = &genphy_soft_reset,
2574 .config_init = &vsc8584_config_init,
2575 .config_aneg = &vsc85xx_config_aneg,
2576 .aneg_done = &genphy_aneg_done,
2577 .read_status = &vsc85xx_read_status,
2578 .handle_interrupt = vsc85xx_handle_interrupt,
2579 .config_intr = &vsc85xx_config_intr,
2580 .suspend = &genphy_suspend,
2581 .resume = &genphy_resume,
2582 .probe = &vsc8574_probe,
2583 .set_wol = &vsc85xx_wol_set,
2584 .get_wol = &vsc85xx_wol_get,
2585 .get_tunable = &vsc85xx_get_tunable,
2586 .set_tunable = &vsc85xx_set_tunable,
2587 .read_page = &vsc85xx_phy_read_page,
2588 .write_page = &vsc85xx_phy_write_page,
2589 .get_sset_count = &vsc85xx_get_sset_count,
2590 .get_strings = &vsc85xx_get_strings,
2591 .get_stats = &vsc85xx_get_stats,
2592 },
2593 {
2594 .phy_id = PHY_ID_VSC8575,
2595 .name = "Microsemi GE VSC8575 SyncE",
2596 .phy_id_mask = 0xfffffff0,
2597 /* PHY_GBIT_FEATURES */
2598 .soft_reset = &genphy_soft_reset,
2599 .config_init = &vsc8584_config_init,
2600 .config_aneg = &vsc85xx_config_aneg,
2601 .aneg_done = &genphy_aneg_done,
2602 .read_status = &vsc85xx_read_status,
2603 .handle_interrupt = &vsc8584_handle_interrupt,
2604 .config_intr = &vsc85xx_config_intr,
2605 .suspend = &genphy_suspend,
2606 .resume = &genphy_resume,
2607 .probe = &vsc8584_probe,
2608 .get_tunable = &vsc85xx_get_tunable,
2609 .set_tunable = &vsc85xx_set_tunable,
2610 .read_page = &vsc85xx_phy_read_page,
2611 .write_page = &vsc85xx_phy_write_page,
2612 .get_sset_count = &vsc85xx_get_sset_count,
2613 .get_strings = &vsc85xx_get_strings,
2614 .get_stats = &vsc85xx_get_stats,
2615 },
2616 {
2617 .phy_id = PHY_ID_VSC8582,
2618 .name = "Microsemi GE VSC8582 SyncE",
2619 .phy_id_mask = 0xfffffff0,
2620 /* PHY_GBIT_FEATURES */
2621 .soft_reset = &genphy_soft_reset,
2622 .config_init = &vsc8584_config_init,
2623 .config_aneg = &vsc85xx_config_aneg,
2624 .aneg_done = &genphy_aneg_done,
2625 .read_status = &vsc85xx_read_status,
2626 .handle_interrupt = &vsc8584_handle_interrupt,
2627 .config_intr = &vsc85xx_config_intr,
2628 .suspend = &genphy_suspend,
2629 .resume = &genphy_resume,
2630 .probe = &vsc8584_probe,
2631 .get_tunable = &vsc85xx_get_tunable,
2632 .set_tunable = &vsc85xx_set_tunable,
2633 .read_page = &vsc85xx_phy_read_page,
2634 .write_page = &vsc85xx_phy_write_page,
2635 .get_sset_count = &vsc85xx_get_sset_count,
2636 .get_strings = &vsc85xx_get_strings,
2637 .get_stats = &vsc85xx_get_stats,
2638 },
2639 {
2640 .phy_id = PHY_ID_VSC8584,
2641 .name = "Microsemi GE VSC8584 SyncE",
2642 .phy_id_mask = 0xfffffff0,
2643 /* PHY_GBIT_FEATURES */
2644 .soft_reset = &genphy_soft_reset,
2645 .config_init = &vsc8584_config_init,
2646 .config_aneg = &vsc85xx_config_aneg,
2647 .aneg_done = &genphy_aneg_done,
2648 .read_status = &vsc85xx_read_status,
2649 .handle_interrupt = &vsc8584_handle_interrupt,
2650 .config_intr = &vsc85xx_config_intr,
2651 .suspend = &genphy_suspend,
2652 .resume = &genphy_resume,
2653 .probe = &vsc8584_probe,
2654 .get_tunable = &vsc85xx_get_tunable,
2655 .set_tunable = &vsc85xx_set_tunable,
2656 .read_page = &vsc85xx_phy_read_page,
2657 .write_page = &vsc85xx_phy_write_page,
2658 .get_sset_count = &vsc85xx_get_sset_count,
2659 .get_strings = &vsc85xx_get_strings,
2660 .get_stats = &vsc85xx_get_stats,
2661 .link_change_notify = &vsc85xx_link_change_notify,
2662 }
2663
2664 };
2665
2666 module_phy_driver(vsc85xx_driver);
2667
2668 static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = {
2669 { PHY_ID_VSC8502, 0xfffffff0, },
2670 { PHY_ID_VSC8504, 0xfffffff0, },
2671 { PHY_ID_VSC8514, 0xfffffff0, },
2672 { PHY_ID_VSC8530, 0xfffffff0, },
2673 { PHY_ID_VSC8531, 0xfffffff0, },
2674 { PHY_ID_VSC8540, 0xfffffff0, },
2675 { PHY_ID_VSC8541, 0xfffffff0, },
2676 { PHY_ID_VSC8552, 0xfffffff0, },
2677 { PHY_ID_VSC856X, 0xfffffff0, },
2678 { PHY_ID_VSC8572, 0xfffffff0, },
2679 { PHY_ID_VSC8574, 0xfffffff0, },
2680 { PHY_ID_VSC8575, 0xfffffff0, },
2681 { PHY_ID_VSC8582, 0xfffffff0, },
2682 { PHY_ID_VSC8584, 0xfffffff0, },
2683 { }
2684 };
2685
2686 MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl);
2687
2688 MODULE_DESCRIPTION("Microsemi VSC85xx PHY driver");
2689 MODULE_AUTHOR("Nagaraju Lakkaraju");
2690 MODULE_LICENSE("Dual MIT/GPL");
2691
2692 MODULE_FIRMWARE(MSCC_VSC8584_REVB_INT8051_FW);
2693 MODULE_FIRMWARE(MSCC_VSC8574_REVB_INT8051_FW);
2694