1// SPDX-License-Identifier: GPL-2.0 2#include "bcm283x.dtsi" 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/soc/bcm2835-pm.h> 6 7/ { 8 compatible = "brcm,bcm2711"; 9 10 #address-cells = <2>; 11 #size-cells = <1>; 12 13 interrupt-parent = <&gicv2>; 14 15 vc4: gpu { 16 compatible = "brcm,bcm2711-vc5"; 17 status = "disabled"; 18 }; 19 20 clk_27MHz: clk-27M { 21 #clock-cells = <0>; 22 compatible = "fixed-clock"; 23 clock-frequency = <27000000>; 24 clock-output-names = "27MHz-clock"; 25 }; 26 27 clk_108MHz: clk-108M { 28 #clock-cells = <0>; 29 compatible = "fixed-clock"; 30 clock-frequency = <108000000>; 31 clock-output-names = "108MHz-clock"; 32 }; 33 34 soc { 35 /* 36 * Defined ranges: 37 * Common BCM283x peripherals 38 * BCM2711-specific peripherals 39 * ARM-local peripherals 40 */ 41 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>, 42 <0x7c000000 0x0 0xfc000000 0x02000000>, 43 <0x40000000 0x0 0xff800000 0x00800000>; 44 /* Emulate a contiguous 30-bit address range for DMA */ 45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>; 46 47 /* 48 * This node is the provider for the enable-method for 49 * bringing up secondary cores. 50 */ 51 local_intc: local_intc@40000000 { 52 compatible = "brcm,bcm2836-l1-intc"; 53 reg = <0x40000000 0x100>; 54 }; 55 56 gicv2: interrupt-controller@40041000 { 57 interrupt-controller; 58 #interrupt-cells = <3>; 59 compatible = "arm,gic-400"; 60 reg = <0x40041000 0x1000>, 61 <0x40042000 0x2000>, 62 <0x40044000 0x2000>, 63 <0x40046000 0x2000>; 64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 65 IRQ_TYPE_LEVEL_HIGH)>; 66 }; 67 68 avs_monitor: avs-monitor@7d5d2000 { 69 compatible = "brcm,bcm2711-avs-monitor", 70 "syscon", "simple-mfd"; 71 reg = <0x7d5d2000 0xf00>; 72 73 thermal: thermal { 74 compatible = "brcm,bcm2711-thermal"; 75 #thermal-sensor-cells = <0>; 76 }; 77 }; 78 79 dma: dma@7e007000 { 80 compatible = "brcm,bcm2835-dma"; 81 reg = <0x7e007000 0xb00>; 82 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 89 /* DMA lite 7 - 10 */ 90 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 94 interrupt-names = "dma0", 95 "dma1", 96 "dma2", 97 "dma3", 98 "dma4", 99 "dma5", 100 "dma6", 101 "dma7", 102 "dma8", 103 "dma9", 104 "dma10"; 105 #dma-cells = <1>; 106 brcm,dma-channel-mask = <0x07f5>; 107 }; 108 109 pm: watchdog@7e100000 { 110 compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; 111 #power-domain-cells = <1>; 112 #reset-cells = <1>; 113 reg = <0x7e100000 0x114>, 114 <0x7e00a000 0x24>, 115 <0x7ec11000 0x20>; 116 clocks = <&clocks BCM2835_CLOCK_V3D>, 117 <&clocks BCM2835_CLOCK_PERI_IMAGE>, 118 <&clocks BCM2835_CLOCK_H264>, 119 <&clocks BCM2835_CLOCK_ISP>; 120 clock-names = "v3d", "peri_image", "h264", "isp"; 121 system-power-controller; 122 }; 123 124 rng@7e104000 { 125 compatible = "brcm,bcm2711-rng200"; 126 reg = <0x7e104000 0x28>; 127 }; 128 129 uart2: serial@7e201400 { 130 compatible = "arm,pl011", "arm,primecell"; 131 reg = <0x7e201400 0x200>; 132 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 133 clocks = <&clocks BCM2835_CLOCK_UART>, 134 <&clocks BCM2835_CLOCK_VPU>; 135 clock-names = "uartclk", "apb_pclk"; 136 arm,primecell-periphid = <0x00241011>; 137 status = "disabled"; 138 }; 139 140 uart3: serial@7e201600 { 141 compatible = "arm,pl011", "arm,primecell"; 142 reg = <0x7e201600 0x200>; 143 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 144 clocks = <&clocks BCM2835_CLOCK_UART>, 145 <&clocks BCM2835_CLOCK_VPU>; 146 clock-names = "uartclk", "apb_pclk"; 147 arm,primecell-periphid = <0x00241011>; 148 status = "disabled"; 149 }; 150 151 uart4: serial@7e201800 { 152 compatible = "arm,pl011", "arm,primecell"; 153 reg = <0x7e201800 0x200>; 154 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&clocks BCM2835_CLOCK_UART>, 156 <&clocks BCM2835_CLOCK_VPU>; 157 clock-names = "uartclk", "apb_pclk"; 158 arm,primecell-periphid = <0x00241011>; 159 status = "disabled"; 160 }; 161 162 uart5: serial@7e201a00 { 163 compatible = "arm,pl011", "arm,primecell"; 164 reg = <0x7e201a00 0x200>; 165 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&clocks BCM2835_CLOCK_UART>, 167 <&clocks BCM2835_CLOCK_VPU>; 168 clock-names = "uartclk", "apb_pclk"; 169 arm,primecell-periphid = <0x00241011>; 170 status = "disabled"; 171 }; 172 173 spi3: spi@7e204600 { 174 compatible = "brcm,bcm2835-spi"; 175 reg = <0x7e204600 0x0200>; 176 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 177 clocks = <&clocks BCM2835_CLOCK_VPU>; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 status = "disabled"; 181 }; 182 183 spi4: spi@7e204800 { 184 compatible = "brcm,bcm2835-spi"; 185 reg = <0x7e204800 0x0200>; 186 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&clocks BCM2835_CLOCK_VPU>; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 status = "disabled"; 191 }; 192 193 spi5: spi@7e204a00 { 194 compatible = "brcm,bcm2835-spi"; 195 reg = <0x7e204a00 0x0200>; 196 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&clocks BCM2835_CLOCK_VPU>; 198 #address-cells = <1>; 199 #size-cells = <0>; 200 status = "disabled"; 201 }; 202 203 spi6: spi@7e204c00 { 204 compatible = "brcm,bcm2835-spi"; 205 reg = <0x7e204c00 0x0200>; 206 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&clocks BCM2835_CLOCK_VPU>; 208 #address-cells = <1>; 209 #size-cells = <0>; 210 status = "disabled"; 211 }; 212 213 i2c3: i2c@7e205600 { 214 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 215 reg = <0x7e205600 0x200>; 216 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&clocks BCM2835_CLOCK_VPU>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 status = "disabled"; 221 }; 222 223 i2c4: i2c@7e205800 { 224 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 225 reg = <0x7e205800 0x200>; 226 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&clocks BCM2835_CLOCK_VPU>; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 status = "disabled"; 231 }; 232 233 i2c5: i2c@7e205a00 { 234 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 235 reg = <0x7e205a00 0x200>; 236 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&clocks BCM2835_CLOCK_VPU>; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 status = "disabled"; 241 }; 242 243 i2c6: i2c@7e205c00 { 244 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 245 reg = <0x7e205c00 0x200>; 246 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&clocks BCM2835_CLOCK_VPU>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 status = "disabled"; 251 }; 252 253 pixelvalve0: pixelvalve@7e206000 { 254 compatible = "brcm,bcm2711-pixelvalve0"; 255 reg = <0x7e206000 0x100>; 256 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 257 status = "disabled"; 258 }; 259 260 pixelvalve1: pixelvalve@7e207000 { 261 compatible = "brcm,bcm2711-pixelvalve1"; 262 reg = <0x7e207000 0x100>; 263 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 264 status = "disabled"; 265 }; 266 267 pixelvalve2: pixelvalve@7e20a000 { 268 compatible = "brcm,bcm2711-pixelvalve2"; 269 reg = <0x7e20a000 0x100>; 270 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 271 status = "disabled"; 272 }; 273 274 pwm1: pwm@7e20c800 { 275 compatible = "brcm,bcm2835-pwm"; 276 reg = <0x7e20c800 0x28>; 277 clocks = <&clocks BCM2835_CLOCK_PWM>; 278 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; 279 assigned-clock-rates = <10000000>; 280 #pwm-cells = <2>; 281 status = "disabled"; 282 }; 283 284 pixelvalve4: pixelvalve@7e216000 { 285 compatible = "brcm,bcm2711-pixelvalve4"; 286 reg = <0x7e216000 0x100>; 287 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 288 status = "disabled"; 289 }; 290 291 hvs: hvs@7e400000 { 292 compatible = "brcm,bcm2711-hvs"; 293 reg = <0x7e400000 0x8000>; 294 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 295 }; 296 297 pixelvalve3: pixelvalve@7ec12000 { 298 compatible = "brcm,bcm2711-pixelvalve3"; 299 reg = <0x7ec12000 0x100>; 300 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 301 status = "disabled"; 302 }; 303 304 vec: vec@7ec13000 { 305 compatible = "brcm,bcm2711-vec"; 306 reg = <0x7ec13000 0x1000>; 307 clocks = <&clocks BCM2835_CLOCK_VEC>; 308 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 309 status = "disabled"; 310 }; 311 312 dvp: clock@7ef00000 { 313 compatible = "brcm,brcm2711-dvp"; 314 reg = <0x7ef00000 0x10>; 315 clocks = <&clk_108MHz>; 316 #clock-cells = <1>; 317 #reset-cells = <1>; 318 }; 319 320 aon_intr: interrupt-controller@7ef00100 { 321 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; 322 reg = <0x7ef00100 0x30>; 323 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 324 interrupt-controller; 325 #interrupt-cells = <1>; 326 }; 327 328 hdmi0: hdmi@7ef00700 { 329 compatible = "brcm,bcm2711-hdmi0"; 330 reg = <0x7ef00700 0x300>, 331 <0x7ef00300 0x200>, 332 <0x7ef00f00 0x80>, 333 <0x7ef00f80 0x80>, 334 <0x7ef01b00 0x200>, 335 <0x7ef01f00 0x400>, 336 <0x7ef00200 0x80>, 337 <0x7ef04300 0x100>, 338 <0x7ef20000 0x100>; 339 reg-names = "hdmi", 340 "dvp", 341 "phy", 342 "rm", 343 "packet", 344 "metadata", 345 "csc", 346 "cec", 347 "hd"; 348 clock-names = "hdmi", "bvb", "audio", "cec"; 349 resets = <&dvp 0>; 350 interrupt-parent = <&aon_intr>; 351 interrupts = <0>, <1>, <2>, 352 <3>, <4>, <5>; 353 interrupt-names = "cec-tx", "cec-rx", "cec-low", 354 "wakeup", "hpd-connected", "hpd-removed"; 355 ddc = <&ddc0>; 356 dmas = <&dma 10>; 357 dma-names = "audio-rx"; 358 status = "disabled"; 359 }; 360 361 ddc0: i2c@7ef04500 { 362 compatible = "brcm,bcm2711-hdmi-i2c"; 363 reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>; 364 reg-names = "bsc", "auto-i2c"; 365 clock-frequency = <97500>; 366 status = "disabled"; 367 }; 368 369 hdmi1: hdmi@7ef05700 { 370 compatible = "brcm,bcm2711-hdmi1"; 371 reg = <0x7ef05700 0x300>, 372 <0x7ef05300 0x200>, 373 <0x7ef05f00 0x80>, 374 <0x7ef05f80 0x80>, 375 <0x7ef06b00 0x200>, 376 <0x7ef06f00 0x400>, 377 <0x7ef00280 0x80>, 378 <0x7ef09300 0x100>, 379 <0x7ef20000 0x100>; 380 reg-names = "hdmi", 381 "dvp", 382 "phy", 383 "rm", 384 "packet", 385 "metadata", 386 "csc", 387 "cec", 388 "hd"; 389 ddc = <&ddc1>; 390 clock-names = "hdmi", "bvb", "audio", "cec"; 391 resets = <&dvp 1>; 392 interrupt-parent = <&aon_intr>; 393 interrupts = <8>, <7>, <6>, 394 <9>, <10>, <11>; 395 interrupt-names = "cec-tx", "cec-rx", "cec-low", 396 "wakeup", "hpd-connected", "hpd-removed"; 397 dmas = <&dma 17>; 398 dma-names = "audio-rx"; 399 status = "disabled"; 400 }; 401 402 ddc1: i2c@7ef09500 { 403 compatible = "brcm,bcm2711-hdmi-i2c"; 404 reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>; 405 reg-names = "bsc", "auto-i2c"; 406 clock-frequency = <97500>; 407 status = "disabled"; 408 }; 409 }; 410 411 /* 412 * emmc2 has different DMA constraints based on SoC revisions. It was 413 * moved into its own bus, so as for RPi4's firmware to update them. 414 * The firmware will find whether the emmc2bus alias is defined, and if 415 * so, it'll edit the dma-ranges property below accordingly. 416 */ 417 emmc2bus: emmc2bus { 418 compatible = "simple-bus"; 419 #address-cells = <2>; 420 #size-cells = <1>; 421 422 ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>; 423 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>; 424 425 emmc2: mmc@7e340000 { 426 compatible = "brcm,bcm2711-emmc2"; 427 reg = <0x0 0x7e340000 0x100>; 428 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&clocks BCM2711_CLOCK_EMMC2>; 430 status = "disabled"; 431 }; 432 }; 433 434 arm-pmu { 435 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3"; 436 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 440 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 441 }; 442 443 timer { 444 compatible = "arm,armv8-timer"; 445 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 446 IRQ_TYPE_LEVEL_LOW)>, 447 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 448 IRQ_TYPE_LEVEL_LOW)>, 449 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 450 IRQ_TYPE_LEVEL_LOW)>, 451 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 452 IRQ_TYPE_LEVEL_LOW)>; 453 /* This only applies to the ARMv7 stub */ 454 arm,cpu-registers-not-fw-configured; 455 }; 456 457 cpus: cpus { 458 #address-cells = <1>; 459 #size-cells = <0>; 460 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit 461 462 /* Source for d/i-cache-line-size and d/i-cache-sets 463 * https://developer.arm.com/documentation/100095/0003 464 * /Level-1-Memory-System/About-the-L1-memory-system?lang=en 465 * Source for d/i-cache-size 466 * https://www.raspberrypi.com/documentation/computers 467 * /processors.html#bcm2711 468 */ 469 cpu0: cpu@0 { 470 device_type = "cpu"; 471 compatible = "arm,cortex-a72"; 472 reg = <0>; 473 enable-method = "spin-table"; 474 cpu-release-addr = <0x0 0x000000d8>; 475 d-cache-size = <0x8000>; 476 d-cache-line-size = <64>; 477 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 478 i-cache-size = <0xc000>; 479 i-cache-line-size = <64>; 480 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 481 next-level-cache = <&l2>; 482 }; 483 484 cpu1: cpu@1 { 485 device_type = "cpu"; 486 compatible = "arm,cortex-a72"; 487 reg = <1>; 488 enable-method = "spin-table"; 489 cpu-release-addr = <0x0 0x000000e0>; 490 d-cache-size = <0x8000>; 491 d-cache-line-size = <64>; 492 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 493 i-cache-size = <0xc000>; 494 i-cache-line-size = <64>; 495 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 496 next-level-cache = <&l2>; 497 }; 498 499 cpu2: cpu@2 { 500 device_type = "cpu"; 501 compatible = "arm,cortex-a72"; 502 reg = <2>; 503 enable-method = "spin-table"; 504 cpu-release-addr = <0x0 0x000000e8>; 505 d-cache-size = <0x8000>; 506 d-cache-line-size = <64>; 507 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 508 i-cache-size = <0xc000>; 509 i-cache-line-size = <64>; 510 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 511 next-level-cache = <&l2>; 512 }; 513 514 cpu3: cpu@3 { 515 device_type = "cpu"; 516 compatible = "arm,cortex-a72"; 517 reg = <3>; 518 enable-method = "spin-table"; 519 cpu-release-addr = <0x0 0x000000f0>; 520 d-cache-size = <0x8000>; 521 d-cache-line-size = <64>; 522 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 523 i-cache-size = <0xc000>; 524 i-cache-line-size = <64>; 525 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set 526 next-level-cache = <&l2>; 527 }; 528 529 /* Source for d/i-cache-line-size and d/i-cache-sets 530 * https://developer.arm.com/documentation/100095/0003 531 * /Level-2-Memory-System/About-the-L2-memory-system?lang=en 532 * Source for d/i-cache-size 533 * https://www.raspberrypi.com/documentation/computers 534 * /processors.html#bcm2711 535 */ 536 l2: l2-cache0 { 537 compatible = "cache"; 538 cache-size = <0x100000>; 539 cache-line-size = <64>; 540 cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set 541 cache-level = <2>; 542 }; 543 }; 544 545 scb { 546 compatible = "simple-bus"; 547 #address-cells = <2>; 548 #size-cells = <1>; 549 550 ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, 551 <0x6 0x00000000 0x6 0x00000000 0x40000000>; 552 553 pcie0: pcie@7d500000 { 554 compatible = "brcm,bcm2711-pcie"; 555 reg = <0x0 0x7d500000 0x9310>; 556 device_type = "pci"; 557 #address-cells = <3>; 558 #interrupt-cells = <1>; 559 #size-cells = <2>; 560 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 562 interrupt-names = "pcie", "msi"; 563 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 564 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 565 IRQ_TYPE_LEVEL_HIGH>, 566 <0 0 0 2 &gicv2 GIC_SPI 144 567 IRQ_TYPE_LEVEL_HIGH>, 568 <0 0 0 3 &gicv2 GIC_SPI 145 569 IRQ_TYPE_LEVEL_HIGH>, 570 <0 0 0 4 &gicv2 GIC_SPI 146 571 IRQ_TYPE_LEVEL_HIGH>; 572 msi-controller; 573 msi-parent = <&pcie0>; 574 575 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 576 0x0 0x04000000>; 577 /* 578 * The wrapper around the PCIe block has a bug 579 * preventing it from accessing beyond the first 3GB of 580 * memory. 581 */ 582 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 583 0x0 0xc0000000>; 584 brcm,enable-ssc; 585 }; 586 587 genet: ethernet@7d580000 { 588 compatible = "brcm,bcm2711-genet-v5"; 589 reg = <0x0 0x7d580000 0x10000>; 590 #address-cells = <0x1>; 591 #size-cells = <0x1>; 592 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 594 status = "disabled"; 595 596 genet_mdio: mdio@e14 { 597 compatible = "brcm,genet-mdio-v5"; 598 reg = <0xe14 0x8>; 599 reg-names = "mdio"; 600 #address-cells = <0x1>; 601 #size-cells = <0x0>; 602 }; 603 }; 604 }; 605}; 606 607&clk_osc { 608 clock-frequency = <54000000>; 609}; 610 611&clocks { 612 compatible = "brcm,bcm2711-cprman"; 613}; 614 615&cpu_thermal { 616 coefficients = <(-487) 410040>; 617 thermal-sensors = <&thermal>; 618}; 619 620&dsi0 { 621 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 622}; 623 624&dsi1 { 625 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 626 compatible = "brcm,bcm2711-dsi1"; 627}; 628 629&gpio { 630 compatible = "brcm,bcm2711-gpio"; 631 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 635 636 gpio-ranges = <&gpio 0 0 58>; 637 638 gpclk0_gpio49: gpclk0_gpio49 { 639 pin-gpclk { 640 pins = "gpio49"; 641 function = "alt1"; 642 bias-disable; 643 }; 644 }; 645 gpclk1_gpio50: gpclk1_gpio50 { 646 pin-gpclk { 647 pins = "gpio50"; 648 function = "alt1"; 649 bias-disable; 650 }; 651 }; 652 gpclk2_gpio51: gpclk2_gpio51 { 653 pin-gpclk { 654 pins = "gpio51"; 655 function = "alt1"; 656 bias-disable; 657 }; 658 }; 659 660 i2c0_gpio46: i2c0_gpio46 { 661 pin-sda { 662 function = "alt0"; 663 pins = "gpio46"; 664 bias-pull-up; 665 }; 666 pin-scl { 667 function = "alt0"; 668 pins = "gpio47"; 669 bias-disable; 670 }; 671 }; 672 i2c1_gpio46: i2c1_gpio46 { 673 pin-sda { 674 function = "alt1"; 675 pins = "gpio46"; 676 bias-pull-up; 677 }; 678 pin-scl { 679 function = "alt1"; 680 pins = "gpio47"; 681 bias-disable; 682 }; 683 }; 684 i2c3_gpio2: i2c3_gpio2 { 685 pin-sda { 686 function = "alt5"; 687 pins = "gpio2"; 688 bias-pull-up; 689 }; 690 pin-scl { 691 function = "alt5"; 692 pins = "gpio3"; 693 bias-disable; 694 }; 695 }; 696 i2c3_gpio4: i2c3_gpio4 { 697 pin-sda { 698 function = "alt5"; 699 pins = "gpio4"; 700 bias-pull-up; 701 }; 702 pin-scl { 703 function = "alt5"; 704 pins = "gpio5"; 705 bias-disable; 706 }; 707 }; 708 i2c4_gpio6: i2c4_gpio6 { 709 pin-sda { 710 function = "alt5"; 711 pins = "gpio6"; 712 bias-pull-up; 713 }; 714 pin-scl { 715 function = "alt5"; 716 pins = "gpio7"; 717 bias-disable; 718 }; 719 }; 720 i2c4_gpio8: i2c4_gpio8 { 721 pin-sda { 722 function = "alt5"; 723 pins = "gpio8"; 724 bias-pull-up; 725 }; 726 pin-scl { 727 function = "alt5"; 728 pins = "gpio9"; 729 bias-disable; 730 }; 731 }; 732 i2c5_gpio10: i2c5_gpio10 { 733 pin-sda { 734 function = "alt5"; 735 pins = "gpio10"; 736 bias-pull-up; 737 }; 738 pin-scl { 739 function = "alt5"; 740 pins = "gpio11"; 741 bias-disable; 742 }; 743 }; 744 i2c5_gpio12: i2c5_gpio12 { 745 pin-sda { 746 function = "alt5"; 747 pins = "gpio12"; 748 bias-pull-up; 749 }; 750 pin-scl { 751 function = "alt5"; 752 pins = "gpio13"; 753 bias-disable; 754 }; 755 }; 756 i2c6_gpio0: i2c6_gpio0 { 757 pin-sda { 758 function = "alt5"; 759 pins = "gpio0"; 760 bias-pull-up; 761 }; 762 pin-scl { 763 function = "alt5"; 764 pins = "gpio1"; 765 bias-disable; 766 }; 767 }; 768 i2c6_gpio22: i2c6_gpio22 { 769 pin-sda { 770 function = "alt5"; 771 pins = "gpio22"; 772 bias-pull-up; 773 }; 774 pin-scl { 775 function = "alt5"; 776 pins = "gpio23"; 777 bias-disable; 778 }; 779 }; 780 i2c_slave_gpio8: i2c_slave_gpio8 { 781 pins-i2c-slave { 782 pins = "gpio8", 783 "gpio9", 784 "gpio10", 785 "gpio11"; 786 function = "alt3"; 787 }; 788 }; 789 790 jtag_gpio48: jtag_gpio48 { 791 pins-jtag { 792 pins = "gpio48", 793 "gpio49", 794 "gpio50", 795 "gpio51", 796 "gpio52", 797 "gpio53"; 798 function = "alt4"; 799 }; 800 }; 801 802 mii_gpio28: mii_gpio28 { 803 pins-mii { 804 pins = "gpio28", 805 "gpio29", 806 "gpio30", 807 "gpio31"; 808 function = "alt4"; 809 }; 810 }; 811 mii_gpio36: mii_gpio36 { 812 pins-mii { 813 pins = "gpio36", 814 "gpio37", 815 "gpio38", 816 "gpio39"; 817 function = "alt5"; 818 }; 819 }; 820 821 pcm_gpio50: pcm_gpio50 { 822 pins-pcm { 823 pins = "gpio50", 824 "gpio51", 825 "gpio52", 826 "gpio53"; 827 function = "alt2"; 828 }; 829 }; 830 831 pwm0_0_gpio12: pwm0_0_gpio12 { 832 pin-pwm { 833 pins = "gpio12"; 834 function = "alt0"; 835 bias-disable; 836 }; 837 }; 838 pwm0_0_gpio18: pwm0_0_gpio18 { 839 pin-pwm { 840 pins = "gpio18"; 841 function = "alt5"; 842 bias-disable; 843 }; 844 }; 845 pwm1_0_gpio40: pwm1_0_gpio40 { 846 pin-pwm { 847 pins = "gpio40"; 848 function = "alt0"; 849 bias-disable; 850 }; 851 }; 852 pwm0_1_gpio13: pwm0_1_gpio13 { 853 pin-pwm { 854 pins = "gpio13"; 855 function = "alt0"; 856 bias-disable; 857 }; 858 }; 859 pwm0_1_gpio19: pwm0_1_gpio19 { 860 pin-pwm { 861 pins = "gpio19"; 862 function = "alt5"; 863 bias-disable; 864 }; 865 }; 866 pwm1_1_gpio41: pwm1_1_gpio41 { 867 pin-pwm { 868 pins = "gpio41"; 869 function = "alt0"; 870 bias-disable; 871 }; 872 }; 873 pwm0_1_gpio45: pwm0_1_gpio45 { 874 pin-pwm { 875 pins = "gpio45"; 876 function = "alt0"; 877 bias-disable; 878 }; 879 }; 880 pwm0_0_gpio52: pwm0_0_gpio52 { 881 pin-pwm { 882 pins = "gpio52"; 883 function = "alt1"; 884 bias-disable; 885 }; 886 }; 887 pwm0_1_gpio53: pwm0_1_gpio53 { 888 pin-pwm { 889 pins = "gpio53"; 890 function = "alt1"; 891 bias-disable; 892 }; 893 }; 894 895 rgmii_gpio35: rgmii_gpio35 { 896 pin-start-stop { 897 pins = "gpio35"; 898 function = "alt4"; 899 }; 900 pin-rx-ok { 901 pins = "gpio36"; 902 function = "alt4"; 903 }; 904 }; 905 rgmii_irq_gpio34: rgmii_irq_gpio34 { 906 pin-irq { 907 pins = "gpio34"; 908 function = "alt5"; 909 }; 910 }; 911 rgmii_irq_gpio39: rgmii_irq_gpio39 { 912 pin-irq { 913 pins = "gpio39"; 914 function = "alt4"; 915 }; 916 }; 917 rgmii_mdio_gpio28: rgmii_mdio_gpio28 { 918 pins-mdio { 919 pins = "gpio28", 920 "gpio29"; 921 function = "alt5"; 922 }; 923 }; 924 rgmii_mdio_gpio37: rgmii_mdio_gpio37 { 925 pins-mdio { 926 pins = "gpio37", 927 "gpio38"; 928 function = "alt4"; 929 }; 930 }; 931 932 spi0_gpio46: spi0_gpio46 { 933 pins-spi { 934 pins = "gpio46", 935 "gpio47", 936 "gpio48", 937 "gpio49"; 938 function = "alt2"; 939 }; 940 }; 941 spi2_gpio46: spi2_gpio46 { 942 pins-spi { 943 pins = "gpio46", 944 "gpio47", 945 "gpio48", 946 "gpio49", 947 "gpio50"; 948 function = "alt5"; 949 }; 950 }; 951 spi3_gpio0: spi3_gpio0 { 952 pins-spi { 953 pins = "gpio0", 954 "gpio1", 955 "gpio2", 956 "gpio3"; 957 function = "alt3"; 958 }; 959 }; 960 spi4_gpio4: spi4_gpio4 { 961 pins-spi { 962 pins = "gpio4", 963 "gpio5", 964 "gpio6", 965 "gpio7"; 966 function = "alt3"; 967 }; 968 }; 969 spi5_gpio12: spi5_gpio12 { 970 pins-spi { 971 pins = "gpio12", 972 "gpio13", 973 "gpio14", 974 "gpio15"; 975 function = "alt3"; 976 }; 977 }; 978 spi6_gpio18: spi6_gpio18 { 979 pins-spi { 980 pins = "gpio18", 981 "gpio19", 982 "gpio20", 983 "gpio21"; 984 function = "alt3"; 985 }; 986 }; 987 988 uart2_gpio0: uart2_gpio0 { 989 pin-tx { 990 pins = "gpio0"; 991 function = "alt4"; 992 bias-disable; 993 }; 994 pin-rx { 995 pins = "gpio1"; 996 function = "alt4"; 997 bias-pull-up; 998 }; 999 }; 1000 uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 { 1001 pin-cts { 1002 pins = "gpio2"; 1003 function = "alt4"; 1004 bias-pull-up; 1005 }; 1006 pin-rts { 1007 pins = "gpio3"; 1008 function = "alt4"; 1009 bias-disable; 1010 }; 1011 }; 1012 uart3_gpio4: uart3_gpio4 { 1013 pin-tx { 1014 pins = "gpio4"; 1015 function = "alt4"; 1016 bias-disable; 1017 }; 1018 pin-rx { 1019 pins = "gpio5"; 1020 function = "alt4"; 1021 bias-pull-up; 1022 }; 1023 }; 1024 uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 { 1025 pin-cts { 1026 pins = "gpio6"; 1027 function = "alt4"; 1028 bias-pull-up; 1029 }; 1030 pin-rts { 1031 pins = "gpio7"; 1032 function = "alt4"; 1033 bias-disable; 1034 }; 1035 }; 1036 uart4_gpio8: uart4_gpio8 { 1037 pin-tx { 1038 pins = "gpio8"; 1039 function = "alt4"; 1040 bias-disable; 1041 }; 1042 pin-rx { 1043 pins = "gpio9"; 1044 function = "alt4"; 1045 bias-pull-up; 1046 }; 1047 }; 1048 uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 { 1049 pin-cts { 1050 pins = "gpio10"; 1051 function = "alt4"; 1052 bias-pull-up; 1053 }; 1054 pin-rts { 1055 pins = "gpio11"; 1056 function = "alt4"; 1057 bias-disable; 1058 }; 1059 }; 1060 uart5_gpio12: uart5_gpio12 { 1061 pin-tx { 1062 pins = "gpio12"; 1063 function = "alt4"; 1064 bias-disable; 1065 }; 1066 pin-rx { 1067 pins = "gpio13"; 1068 function = "alt4"; 1069 bias-pull-up; 1070 }; 1071 }; 1072 uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 { 1073 pin-cts { 1074 pins = "gpio14"; 1075 function = "alt4"; 1076 bias-pull-up; 1077 }; 1078 pin-rts { 1079 pins = "gpio15"; 1080 function = "alt4"; 1081 bias-disable; 1082 }; 1083 }; 1084}; 1085 1086&rmem { 1087 #address-cells = <2>; 1088}; 1089 1090&cma { 1091 /* 1092 * arm64 reserves the CMA by default somewhere in ZONE_DMA32, 1093 * that's not good enough for the BCM2711 as some devices can 1094 * only address the lower 1G of memory (ZONE_DMA). 1095 */ 1096 alloc-ranges = <0x0 0x00000000 0x40000000>; 1097}; 1098 1099&i2c0 { 1100 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 1101 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1102}; 1103 1104&i2c1 { 1105 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; 1106 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1107}; 1108 1109&mailbox { 1110 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1111}; 1112 1113&sdhci { 1114 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1115}; 1116 1117&sdhost { 1118 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1119}; 1120 1121&spi { 1122 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1123}; 1124 1125&spi1 { 1126 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1127}; 1128 1129&spi2 { 1130 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1131}; 1132 1133&system_timer { 1134 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1138}; 1139 1140&txp { 1141 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1142}; 1143 1144&uart0 { 1145 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1146}; 1147 1148&uart1 { 1149 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1150}; 1151 1152&usb { 1153 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1154}; 1155 1156&vec { 1157 compatible = "brcm,bcm2711-vec"; 1158 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1159}; 1160