1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on OF_IRQ 7 8config ARM_GIC 9 bool 10 select IRQ_DOMAIN_HIERARCHY 11 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 12 13config ARM_GIC_PM 14 bool 15 depends on PM 16 select ARM_GIC 17 18config ARM_GIC_MAX_NR 19 int 20 depends on ARM_GIC 21 default 2 if ARCH_REALVIEW 22 default 1 23 24config ARM_GIC_V2M 25 bool 26 depends on PCI 27 select ARM_GIC 28 select PCI_MSI 29 30config GIC_NON_BANKED 31 bool 32 33config ARM_GIC_V3 34 bool 35 select IRQ_DOMAIN_HIERARCHY 36 select PARTITION_PERCPU 37 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 38 39config ARM_GIC_V3_ITS 40 bool 41 select GENERIC_MSI_IRQ_DOMAIN 42 default ARM_GIC_V3 43 44config ARM_GIC_V3_ITS_PCI 45 bool 46 depends on ARM_GIC_V3_ITS 47 depends on PCI 48 depends on PCI_MSI 49 default ARM_GIC_V3_ITS 50 51config ARM_GIC_V3_ITS_FSL_MC 52 bool 53 depends on ARM_GIC_V3_ITS 54 depends on FSL_MC_BUS 55 default ARM_GIC_V3_ITS 56 57config ARM_NVIC 58 bool 59 select IRQ_DOMAIN_HIERARCHY 60 select GENERIC_IRQ_CHIP 61 62config ARM_VIC 63 bool 64 select IRQ_DOMAIN 65 66config ARM_VIC_NR 67 int 68 default 4 if ARCH_S5PV210 69 default 2 70 depends on ARM_VIC 71 help 72 The maximum number of VICs available in the system, for 73 power management. 74 75config ARMADA_370_XP_IRQ 76 bool 77 select GENERIC_IRQ_CHIP 78 select PCI_MSI if PCI 79 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 80 81config ALPINE_MSI 82 bool 83 depends on PCI 84 select PCI_MSI 85 select GENERIC_IRQ_CHIP 86 87config AL_FIC 88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 89 depends on OF || COMPILE_TEST 90 select GENERIC_IRQ_CHIP 91 select IRQ_DOMAIN 92 help 93 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 94 95config ATMEL_AIC_IRQ 96 bool 97 select GENERIC_IRQ_CHIP 98 select IRQ_DOMAIN 99 select SPARSE_IRQ 100 101config ATMEL_AIC5_IRQ 102 bool 103 select GENERIC_IRQ_CHIP 104 select IRQ_DOMAIN 105 select SPARSE_IRQ 106 107config I8259 108 bool 109 select IRQ_DOMAIN 110 111config BCM6345_L1_IRQ 112 bool 113 select GENERIC_IRQ_CHIP 114 select IRQ_DOMAIN 115 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 116 117config BCM7038_L1_IRQ 118 bool 119 select GENERIC_IRQ_CHIP 120 select IRQ_DOMAIN 121 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 122 123config BCM7120_L2_IRQ 124 bool 125 select GENERIC_IRQ_CHIP 126 select IRQ_DOMAIN 127 128config BRCMSTB_L2_IRQ 129 bool 130 select GENERIC_IRQ_CHIP 131 select IRQ_DOMAIN 132 133config DAVINCI_AINTC 134 bool 135 select GENERIC_IRQ_CHIP 136 select IRQ_DOMAIN 137 138config DAVINCI_CP_INTC 139 bool 140 select GENERIC_IRQ_CHIP 141 select IRQ_DOMAIN 142 143config DW_APB_ICTL 144 bool 145 select GENERIC_IRQ_CHIP 146 select IRQ_DOMAIN_HIERARCHY 147 148config FARADAY_FTINTC010 149 bool 150 select IRQ_DOMAIN 151 select SPARSE_IRQ 152 153config HISILICON_IRQ_MBIGEN 154 bool 155 select ARM_GIC_V3 156 select ARM_GIC_V3_ITS 157 158config IMGPDC_IRQ 159 bool 160 select GENERIC_IRQ_CHIP 161 select IRQ_DOMAIN 162 163config IXP4XX_IRQ 164 bool 165 select IRQ_DOMAIN 166 select SPARSE_IRQ 167 168config MADERA_IRQ 169 tristate 170 171config IRQ_MIPS_CPU 172 bool 173 select GENERIC_IRQ_CHIP 174 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 175 select IRQ_DOMAIN 176 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 177 178config CLPS711X_IRQCHIP 179 bool 180 depends on ARCH_CLPS711X 181 select IRQ_DOMAIN 182 select SPARSE_IRQ 183 default y 184 185config OMPIC 186 bool 187 188config OR1K_PIC 189 bool 190 select IRQ_DOMAIN 191 192config OMAP_IRQCHIP 193 bool 194 select GENERIC_IRQ_CHIP 195 select IRQ_DOMAIN 196 197config ORION_IRQCHIP 198 bool 199 select IRQ_DOMAIN 200 201config PIC32_EVIC 202 bool 203 select GENERIC_IRQ_CHIP 204 select IRQ_DOMAIN 205 206config JCORE_AIC 207 bool "J-Core integrated AIC" if COMPILE_TEST 208 depends on OF 209 select IRQ_DOMAIN 210 help 211 Support for the J-Core integrated AIC. 212 213config RDA_INTC 214 bool 215 select IRQ_DOMAIN 216 217config RENESAS_INTC_IRQPIN 218 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 219 select IRQ_DOMAIN 220 help 221 Enable support for the Renesas Interrupt Controller for external 222 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 223 224config RENESAS_IRQC 225 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 226 select GENERIC_IRQ_CHIP 227 select IRQ_DOMAIN 228 help 229 Enable support for the Renesas Interrupt Controller for external 230 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 231 232config RENESAS_RZA1_IRQC 233 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 234 select IRQ_DOMAIN_HIERARCHY 235 help 236 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 237 to 8 external interrupts with configurable sense select. 238 239config SL28CPLD_INTC 240 bool "Kontron sl28cpld IRQ controller" 241 depends on MFD_SL28CPLD=y || COMPILE_TEST 242 select REGMAP_IRQ 243 help 244 Interrupt controller driver for the board management controller 245 found on the Kontron sl28 CPLD. 246 247config ST_IRQCHIP 248 bool 249 select REGMAP 250 select MFD_SYSCON 251 help 252 Enables SysCfg Controlled IRQs on STi based platforms. 253 254config TB10X_IRQC 255 bool 256 select IRQ_DOMAIN 257 select GENERIC_IRQ_CHIP 258 259config TS4800_IRQ 260 tristate "TS-4800 IRQ controller" 261 select IRQ_DOMAIN 262 depends on HAS_IOMEM 263 depends on SOC_IMX51 || COMPILE_TEST 264 help 265 Support for the TS-4800 FPGA IRQ controller 266 267config VERSATILE_FPGA_IRQ 268 bool 269 select IRQ_DOMAIN 270 271config VERSATILE_FPGA_IRQ_NR 272 int 273 default 4 274 depends on VERSATILE_FPGA_IRQ 275 276config XTENSA_MX 277 bool 278 select IRQ_DOMAIN 279 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 280 281config XILINX_INTC 282 bool "Xilinx Interrupt Controller IP" 283 depends on MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP 284 select IRQ_DOMAIN 285 help 286 Support for the Xilinx Interrupt Controller IP core. 287 This is used as a primary controller with MicroBlaze and can also 288 be used as a secondary chained controller on other platforms. 289 290config IRQ_CROSSBAR 291 bool 292 help 293 Support for a CROSSBAR ip that precedes the main interrupt controller. 294 The primary irqchip invokes the crossbar's callback which inturn allocates 295 a free irq and configures the IP. Thus the peripheral interrupts are 296 routed to one of the free irqchip interrupt lines. 297 298config KEYSTONE_IRQ 299 tristate "Keystone 2 IRQ controller IP" 300 depends on ARCH_KEYSTONE 301 help 302 Support for Texas Instruments Keystone 2 IRQ controller IP which 303 is part of the Keystone 2 IPC mechanism 304 305config MIPS_GIC 306 bool 307 select GENERIC_IRQ_IPI if SMP 308 select IRQ_DOMAIN_HIERARCHY 309 select MIPS_CM 310 311config INGENIC_IRQ 312 bool 313 depends on MACH_INGENIC 314 default y 315 316config INGENIC_TCU_IRQ 317 bool "Ingenic JZ47xx TCU interrupt controller" 318 default MACH_INGENIC 319 depends on MIPS || COMPILE_TEST 320 select MFD_SYSCON 321 select GENERIC_IRQ_CHIP 322 help 323 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 324 JZ47xx SoCs. 325 326 If unsure, say N. 327 328config RENESAS_H8300H_INTC 329 bool 330 select IRQ_DOMAIN 331 332config RENESAS_H8S_INTC 333 bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST 334 select IRQ_DOMAIN 335 help 336 Enable support for the Renesas H8/300 Interrupt Controller, as found 337 on Renesas H8S SoCs. 338 339config IMX_GPCV2 340 bool 341 select IRQ_DOMAIN 342 help 343 Enables the wakeup IRQs for IMX platforms with GPCv2 block 344 345config IRQ_MXS 346 def_bool y if MACH_ASM9260 || ARCH_MXS 347 select IRQ_DOMAIN 348 select STMP_DEVICE 349 350config MSCC_OCELOT_IRQ 351 bool 352 select IRQ_DOMAIN 353 select GENERIC_IRQ_CHIP 354 355config MVEBU_GICP 356 bool 357 358config MVEBU_ICU 359 bool 360 361config MVEBU_ODMI 362 bool 363 select GENERIC_MSI_IRQ_DOMAIN 364 365config MVEBU_PIC 366 bool 367 368config MVEBU_SEI 369 bool 370 371config LS_EXTIRQ 372 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 373 select MFD_SYSCON 374 375config LS_SCFG_MSI 376 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 377 depends on PCI && PCI_MSI 378 379config PARTITION_PERCPU 380 bool 381 382config STM32_EXTI 383 bool 384 select IRQ_DOMAIN 385 select GENERIC_IRQ_CHIP 386 387config QCOM_IRQ_COMBINER 388 bool "QCOM IRQ combiner support" 389 depends on ARCH_QCOM && ACPI 390 select IRQ_DOMAIN_HIERARCHY 391 help 392 Say yes here to add support for the IRQ combiner devices embedded 393 in Qualcomm Technologies chips. 394 395config IRQ_UNIPHIER_AIDET 396 bool "UniPhier AIDET support" if COMPILE_TEST 397 depends on ARCH_UNIPHIER || COMPILE_TEST 398 default ARCH_UNIPHIER 399 select IRQ_DOMAIN_HIERARCHY 400 help 401 Support for the UniPhier AIDET (ARM Interrupt Detector). 402 403config MESON_IRQ_GPIO 404 tristate "Meson GPIO Interrupt Multiplexer" 405 depends on ARCH_MESON || COMPILE_TEST 406 default ARCH_MESON 407 select IRQ_DOMAIN_HIERARCHY 408 help 409 Support Meson SoC Family GPIO Interrupt Multiplexer 410 411config GOLDFISH_PIC 412 bool "Goldfish programmable interrupt controller" 413 depends on MIPS && (GOLDFISH || COMPILE_TEST) 414 select GENERIC_IRQ_CHIP 415 select IRQ_DOMAIN 416 help 417 Say yes here to enable Goldfish interrupt controller driver used 418 for Goldfish based virtual platforms. 419 420config QCOM_PDC 421 tristate "QCOM PDC" 422 depends on ARCH_QCOM 423 select IRQ_DOMAIN_HIERARCHY 424 help 425 Power Domain Controller driver to manage and configure wakeup 426 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 427 428config CSKY_MPINTC 429 bool 430 depends on CSKY 431 help 432 Say yes here to enable C-SKY SMP interrupt controller driver used 433 for C-SKY SMP system. 434 In fact it's not mmio map in hardware and it uses ld/st to visit the 435 controller's register inside CPU. 436 437config CSKY_APB_INTC 438 bool "C-SKY APB Interrupt Controller" 439 depends on CSKY 440 help 441 Say yes here to enable C-SKY APB interrupt controller driver used 442 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 443 the controller's register. 444 445config IMX_IRQSTEER 446 bool "i.MX IRQSTEER support" 447 depends on ARCH_MXC || COMPILE_TEST 448 default ARCH_MXC 449 select IRQ_DOMAIN 450 help 451 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 452 453config IMX_INTMUX 454 bool "i.MX INTMUX support" if COMPILE_TEST 455 default y if ARCH_MXC 456 select IRQ_DOMAIN 457 help 458 Support for the i.MX INTMUX interrupt multiplexer. 459 460config LS1X_IRQ 461 bool "Loongson-1 Interrupt Controller" 462 depends on MACH_LOONGSON32 463 default y 464 select IRQ_DOMAIN 465 select GENERIC_IRQ_CHIP 466 help 467 Support for the Loongson-1 platform Interrupt Controller. 468 469config TI_SCI_INTR_IRQCHIP 470 bool 471 depends on TI_SCI_PROTOCOL 472 select IRQ_DOMAIN_HIERARCHY 473 help 474 This enables the irqchip driver support for K3 Interrupt router 475 over TI System Control Interface available on some new TI's SoCs. 476 If you wish to use interrupt router irq resources managed by the 477 TI System Controller, say Y here. Otherwise, say N. 478 479config TI_SCI_INTA_IRQCHIP 480 bool 481 depends on TI_SCI_PROTOCOL 482 select IRQ_DOMAIN_HIERARCHY 483 select TI_SCI_INTA_MSI_DOMAIN 484 help 485 This enables the irqchip driver support for K3 Interrupt aggregator 486 over TI System Control Interface available on some new TI's SoCs. 487 If you wish to use interrupt aggregator irq resources managed by the 488 TI System Controller, say Y here. Otherwise, say N. 489 490config TI_PRUSS_INTC 491 tristate 492 depends on TI_PRUSS 493 default TI_PRUSS 494 select IRQ_DOMAIN 495 help 496 This enables support for the PRU-ICSS Local Interrupt Controller 497 present within a PRU-ICSS subsystem present on various TI SoCs. 498 The PRUSS INTC enables various interrupts to be routed to multiple 499 different processors within the SoC. 500 501config RISCV_INTC 502 bool "RISC-V Local Interrupt Controller" 503 depends on RISCV 504 default y 505 help 506 This enables support for the per-HART local interrupt controller 507 found in standard RISC-V systems. The per-HART local interrupt 508 controller handles timer interrupts, software interrupts, and 509 hardware interrupts. Without a per-HART local interrupt controller, 510 a RISC-V system will be unable to handle any interrupts. 511 512 If you don't know what to do here, say Y. 513 514config SIFIVE_PLIC 515 bool "SiFive Platform-Level Interrupt Controller" 516 depends on RISCV 517 select IRQ_DOMAIN_HIERARCHY 518 help 519 This enables support for the PLIC chip found in SiFive (and 520 potentially other) RISC-V systems. The PLIC controls devices 521 interrupts and connects them to each core's local interrupt 522 controller. Aside from timer and software interrupts, all other 523 interrupt sources are subordinate to the PLIC. 524 525 If you don't know what to do here, say Y. 526 527config EXYNOS_IRQ_COMBINER 528 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 529 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 530 help 531 Say yes here to add support for the IRQ combiner devices embedded 532 in Samsung Exynos chips. 533 534config LOONGSON_LIOINTC 535 bool "Loongson Local I/O Interrupt Controller" 536 depends on MACH_LOONGSON64 537 default y 538 select IRQ_DOMAIN 539 select GENERIC_IRQ_CHIP 540 help 541 Support for the Loongson Local I/O Interrupt Controller. 542 543config LOONGSON_HTPIC 544 bool "Loongson3 HyperTransport PIC Controller" 545 depends on MACH_LOONGSON64 546 default y 547 select IRQ_DOMAIN 548 select GENERIC_IRQ_CHIP 549 help 550 Support for the Loongson-3 HyperTransport PIC Controller. 551 552config LOONGSON_HTVEC 553 bool "Loongson3 HyperTransport Interrupt Vector Controller" 554 depends on MACH_LOONGSON64 555 default MACH_LOONGSON64 556 select IRQ_DOMAIN_HIERARCHY 557 help 558 Support for the Loongson3 HyperTransport Interrupt Vector Controller. 559 560config LOONGSON_PCH_PIC 561 bool "Loongson PCH PIC Controller" 562 depends on MACH_LOONGSON64 || COMPILE_TEST 563 default MACH_LOONGSON64 564 select IRQ_DOMAIN_HIERARCHY 565 select IRQ_FASTEOI_HIERARCHY_HANDLERS 566 help 567 Support for the Loongson PCH PIC Controller. 568 569config LOONGSON_PCH_MSI 570 bool "Loongson PCH MSI Controller" 571 depends on MACH_LOONGSON64 || COMPILE_TEST 572 depends on PCI 573 default MACH_LOONGSON64 574 select IRQ_DOMAIN_HIERARCHY 575 select PCI_MSI 576 help 577 Support for the Loongson PCH MSI Controller. 578 579config MST_IRQ 580 bool "MStar Interrupt Controller" 581 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 582 default ARCH_MEDIATEK 583 select IRQ_DOMAIN 584 select IRQ_DOMAIN_HIERARCHY 585 help 586 Support MStar Interrupt Controller. 587 588config WPCM450_AIC 589 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 590 depends on ARCH_WPCM450 591 help 592 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 593 594config IRQ_IDT3243X 595 bool 596 select GENERIC_IRQ_CHIP 597 select IRQ_DOMAIN 598 599config APPLE_AIC 600 bool "Apple Interrupt Controller (AIC)" 601 depends on ARM64 602 depends on ARCH_APPLE || COMPILE_TEST 603 help 604 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 605 such as the M1. 606 607endmenu 608