1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Copyright 2015 Freescale Semiconductor, Inc. 4// Copyright 2016 Toradex AG 5 6#include <dt-bindings/clock/imx7d-clock.h> 7#include <dt-bindings/power/imx7-power.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/reset/imx7-reset.h> 12#include "imx7d-pinfunc.h" 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 /* 18 * The decompressor and also some bootloaders rely on a 19 * pre-existing /chosen node to be available to insert the 20 * command line and merge other ATAGS info. 21 */ 22 chosen {}; 23 24 aliases { 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 gpio5 = &gpio6; 31 gpio6 = &gpio7; 32 i2c0 = &i2c1; 33 i2c1 = &i2c2; 34 i2c2 = &i2c3; 35 i2c3 = &i2c4; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 serial4 = &uart5; 44 serial5 = &uart6; 45 serial6 = &uart7; 46 spi0 = &ecspi1; 47 spi1 = &ecspi2; 48 spi2 = &ecspi3; 49 spi3 = &ecspi4; 50 usb0 = &usbotg1; 51 usb1 = &usbh; 52 }; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 idle-states { 59 entry-method = "psci"; 60 61 cpu_sleep_wait: cpu-sleep-wait { 62 compatible = "arm,idle-state"; 63 arm,psci-suspend-param = <0x0010000>; 64 local-timer-stop; 65 entry-latency-us = <100>; 66 exit-latency-us = <50>; 67 min-residency-us = <1000>; 68 }; 69 }; 70 71 cpu0: cpu@0 { 72 compatible = "arm,cortex-a7"; 73 device_type = "cpu"; 74 reg = <0>; 75 clock-frequency = <792000000>; 76 clock-latency = <61036>; /* two CLK32 periods */ 77 clocks = <&clks IMX7D_CLK_ARM>; 78 cpu-idle-states = <&cpu_sleep_wait>; 79 }; 80 }; 81 82 ckil: clock-cki { 83 compatible = "fixed-clock"; 84 #clock-cells = <0>; 85 clock-frequency = <32768>; 86 clock-output-names = "ckil"; 87 }; 88 89 osc: clock-osc { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <24000000>; 93 clock-output-names = "osc"; 94 }; 95 96 usbphynop1: usbphynop1 { 97 compatible = "usb-nop-xceiv"; 98 clocks = <&clks IMX7D_USB_PHY1_CLK>; 99 clock-names = "main_clk"; 100 #phy-cells = <0>; 101 }; 102 103 usbphynop3: usbphynop3 { 104 compatible = "usb-nop-xceiv"; 105 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; 106 clock-names = "main_clk"; 107 power-domains = <&pgc_hsic_phy>; 108 #phy-cells = <0>; 109 }; 110 111 pmu { 112 compatible = "arm,cortex-a7-pmu"; 113 interrupt-parent = <&gpc>; 114 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 115 interrupt-affinity = <&cpu0>; 116 }; 117 118 replicator { 119 /* 120 * non-configurable replicators don't show up on the 121 * AMBA bus. As such no need to add "arm,primecell" 122 */ 123 compatible = "arm,coresight-static-replicator"; 124 125 out-ports { 126 #address-cells = <1>; 127 #size-cells = <0>; 128 /* replicator output ports */ 129 port@0 { 130 reg = <0>; 131 replicator_out_port0: endpoint { 132 remote-endpoint = <&tpiu_in_port>; 133 }; 134 }; 135 136 port@1 { 137 reg = <1>; 138 replicator_out_port1: endpoint { 139 remote-endpoint = <&etr_in_port>; 140 }; 141 }; 142 }; 143 144 in-ports { 145 port { 146 replicator_in_port0: endpoint { 147 remote-endpoint = <&etf_out_port>; 148 }; 149 }; 150 }; 151 }; 152 153 timer { 154 compatible = "arm,armv7-timer"; 155 arm,cpu-registers-not-fw-configured; 156 interrupt-parent = <&intc>; 157 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 158 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 159 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 160 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 161 }; 162 163 soc { 164 #address-cells = <1>; 165 #size-cells = <1>; 166 compatible = "simple-bus"; 167 interrupt-parent = <&gpc>; 168 ranges; 169 170 funnel@30041000 { 171 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 172 reg = <0x30041000 0x1000>; 173 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 174 clock-names = "apb_pclk"; 175 176 ca_funnel_in_ports: in-ports { 177 #address-cells = <1>; 178 #size-cells = <0>; 179 180 port@0 { 181 reg = <0>; 182 ca_funnel_in_port0: endpoint { 183 remote-endpoint = <&etm0_out_port>; 184 }; 185 }; 186 187 /* the other input ports are not connect to anything */ 188 }; 189 190 out-ports { 191 port { 192 ca_funnel_out_port0: endpoint { 193 remote-endpoint = <&hugo_funnel_in_port0>; 194 }; 195 }; 196 197 }; 198 }; 199 200 etm@3007c000 { 201 compatible = "arm,coresight-etm3x", "arm,primecell"; 202 reg = <0x3007c000 0x1000>; 203 cpu = <&cpu0>; 204 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 205 clock-names = "apb_pclk"; 206 207 out-ports { 208 port { 209 etm0_out_port: endpoint { 210 remote-endpoint = <&ca_funnel_in_port0>; 211 }; 212 }; 213 }; 214 }; 215 216 funnel@30083000 { 217 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 218 reg = <0x30083000 0x1000>; 219 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 220 clock-names = "apb_pclk"; 221 222 in-ports { 223 #address-cells = <1>; 224 #size-cells = <0>; 225 226 port@0 { 227 reg = <0>; 228 hugo_funnel_in_port0: endpoint { 229 remote-endpoint = <&ca_funnel_out_port0>; 230 }; 231 }; 232 233 port@1 { 234 reg = <1>; 235 hugo_funnel_in_port1: endpoint { 236 /* M4 input */ 237 }; 238 }; 239 /* the other input ports are not connect to anything */ 240 }; 241 242 out-ports { 243 port { 244 hugo_funnel_out_port0: endpoint { 245 remote-endpoint = <&etf_in_port>; 246 }; 247 }; 248 }; 249 }; 250 251 etf@30084000 { 252 compatible = "arm,coresight-tmc", "arm,primecell"; 253 reg = <0x30084000 0x1000>; 254 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 255 clock-names = "apb_pclk"; 256 257 in-ports { 258 port { 259 etf_in_port: endpoint { 260 remote-endpoint = <&hugo_funnel_out_port0>; 261 }; 262 }; 263 }; 264 265 out-ports { 266 port { 267 etf_out_port: endpoint { 268 remote-endpoint = <&replicator_in_port0>; 269 }; 270 }; 271 }; 272 }; 273 274 etr@30086000 { 275 compatible = "arm,coresight-tmc", "arm,primecell"; 276 reg = <0x30086000 0x1000>; 277 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 278 clock-names = "apb_pclk"; 279 280 in-ports { 281 port { 282 etr_in_port: endpoint { 283 remote-endpoint = <&replicator_out_port1>; 284 }; 285 }; 286 }; 287 }; 288 289 tpiu@30087000 { 290 compatible = "arm,coresight-tpiu", "arm,primecell"; 291 reg = <0x30087000 0x1000>; 292 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 293 clock-names = "apb_pclk"; 294 295 in-ports { 296 port { 297 tpiu_in_port: endpoint { 298 remote-endpoint = <&replicator_out_port0>; 299 }; 300 }; 301 }; 302 }; 303 304 intc: interrupt-controller@31001000 { 305 compatible = "arm,cortex-a7-gic"; 306 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 307 #interrupt-cells = <3>; 308 interrupt-controller; 309 interrupt-parent = <&intc>; 310 reg = <0x31001000 0x1000>, 311 <0x31002000 0x2000>, 312 <0x31004000 0x2000>, 313 <0x31006000 0x2000>; 314 }; 315 316 aips1: bus@30000000 { 317 compatible = "fsl,aips-bus", "simple-bus"; 318 #address-cells = <1>; 319 #size-cells = <1>; 320 reg = <0x30000000 0x400000>; 321 ranges; 322 323 gpio1: gpio@30200000 { 324 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 325 reg = <0x30200000 0x10000>; 326 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ 327 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ 328 gpio-controller; 329 #gpio-cells = <2>; 330 interrupt-controller; 331 #interrupt-cells = <2>; 332 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; 333 }; 334 335 gpio2: gpio@30210000 { 336 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 337 reg = <0x30210000 0x10000>; 338 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 340 gpio-controller; 341 #gpio-cells = <2>; 342 interrupt-controller; 343 #interrupt-cells = <2>; 344 gpio-ranges = <&iomuxc 0 13 32>; 345 }; 346 347 gpio3: gpio@30220000 { 348 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 349 reg = <0x30220000 0x10000>; 350 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 352 gpio-controller; 353 #gpio-cells = <2>; 354 interrupt-controller; 355 #interrupt-cells = <2>; 356 gpio-ranges = <&iomuxc 0 45 29>; 357 }; 358 359 gpio4: gpio@30230000 { 360 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 361 reg = <0x30230000 0x10000>; 362 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 364 gpio-controller; 365 #gpio-cells = <2>; 366 interrupt-controller; 367 #interrupt-cells = <2>; 368 gpio-ranges = <&iomuxc 0 74 24>; 369 }; 370 371 gpio5: gpio@30240000 { 372 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 373 reg = <0x30240000 0x10000>; 374 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 376 gpio-controller; 377 #gpio-cells = <2>; 378 interrupt-controller; 379 #interrupt-cells = <2>; 380 gpio-ranges = <&iomuxc 0 98 18>; 381 }; 382 383 gpio6: gpio@30250000 { 384 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 385 reg = <0x30250000 0x10000>; 386 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 388 gpio-controller; 389 #gpio-cells = <2>; 390 interrupt-controller; 391 #interrupt-cells = <2>; 392 gpio-ranges = <&iomuxc 0 116 23>; 393 }; 394 395 gpio7: gpio@30260000 { 396 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 397 reg = <0x30260000 0x10000>; 398 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 400 gpio-controller; 401 #gpio-cells = <2>; 402 interrupt-controller; 403 #interrupt-cells = <2>; 404 gpio-ranges = <&iomuxc 0 139 16>; 405 }; 406 407 wdog1: watchdog@30280000 { 408 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 409 reg = <0x30280000 0x10000>; 410 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; 412 }; 413 414 wdog2: watchdog@30290000 { 415 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 416 reg = <0x30290000 0x10000>; 417 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; 419 status = "disabled"; 420 }; 421 422 wdog3: watchdog@302a0000 { 423 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 424 reg = <0x302a0000 0x10000>; 425 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; 427 status = "disabled"; 428 }; 429 430 wdog4: watchdog@302b0000 { 431 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 432 reg = <0x302b0000 0x10000>; 433 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 434 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; 435 status = "disabled"; 436 }; 437 438 iomuxc_lpsr: iomuxc-lpsr@302c0000 { 439 compatible = "fsl,imx7d-iomuxc-lpsr"; 440 reg = <0x302c0000 0x10000>; 441 fsl,input-sel = <&iomuxc>; 442 }; 443 444 gpt1: timer@302d0000 { 445 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 446 reg = <0x302d0000 0x10000>; 447 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&clks IMX7D_GPT1_ROOT_CLK>, 449 <&clks IMX7D_GPT1_ROOT_CLK>; 450 clock-names = "ipg", "per"; 451 }; 452 453 gpt2: timer@302e0000 { 454 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 455 reg = <0x302e0000 0x10000>; 456 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&clks IMX7D_GPT2_ROOT_CLK>, 458 <&clks IMX7D_GPT2_ROOT_CLK>; 459 clock-names = "ipg", "per"; 460 status = "disabled"; 461 }; 462 463 gpt3: timer@302f0000 { 464 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 465 reg = <0x302f0000 0x10000>; 466 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&clks IMX7D_GPT3_ROOT_CLK>, 468 <&clks IMX7D_GPT3_ROOT_CLK>; 469 clock-names = "ipg", "per"; 470 status = "disabled"; 471 }; 472 473 gpt4: timer@30300000 { 474 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt"; 475 reg = <0x30300000 0x10000>; 476 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&clks IMX7D_GPT4_ROOT_CLK>, 478 <&clks IMX7D_GPT4_ROOT_CLK>; 479 clock-names = "ipg", "per"; 480 status = "disabled"; 481 }; 482 483 kpp: keypad@30320000 { 484 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; 485 reg = <0x30320000 0x10000>; 486 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&clks IMX7D_KPP_ROOT_CLK>; 488 status = "disabled"; 489 }; 490 491 iomuxc: pinctrl@30330000 { 492 compatible = "fsl,imx7d-iomuxc"; 493 reg = <0x30330000 0x10000>; 494 }; 495 496 gpr: iomuxc-gpr@30340000 { 497 compatible = "fsl,imx7d-iomuxc-gpr", 498 "fsl,imx6q-iomuxc-gpr", "syscon", 499 "simple-mfd"; 500 reg = <0x30340000 0x10000>; 501 502 mux: mux-controller { 503 compatible = "mmio-mux"; 504 #mux-control-cells = <1>; 505 mux-reg-masks = <0x14 0x00000010>; 506 }; 507 508 video_mux: csi-mux { 509 compatible = "video-mux"; 510 mux-controls = <&mux 0>; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 status = "disabled"; 514 515 port@0 { 516 reg = <0>; 517 }; 518 519 port@1 { 520 reg = <1>; 521 522 csi_mux_from_mipi_vc0: endpoint { 523 remote-endpoint = <&mipi_vc0_to_csi_mux>; 524 }; 525 }; 526 527 port@2 { 528 reg = <2>; 529 530 csi_mux_to_csi: endpoint { 531 remote-endpoint = <&csi_from_csi_mux>; 532 }; 533 }; 534 }; 535 }; 536 537 ocotp: efuse@30350000 { 538 #address-cells = <1>; 539 #size-cells = <1>; 540 compatible = "fsl,imx7d-ocotp", "syscon"; 541 reg = <0x30350000 0x10000>; 542 clocks = <&clks IMX7D_OCOTP_CLK>; 543 544 tempmon_calib: calib@3c { 545 reg = <0x3c 0x4>; 546 }; 547 548 fuse_grade: fuse-grade@10 { 549 reg = <0x10 0x4>; 550 }; 551 }; 552 553 anatop: anatop@30360000 { 554 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", 555 "syscon", "simple-mfd"; 556 reg = <0x30360000 0x10000>; 557 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 559 560 reg_1p0d: regulator-vdd1p0d { 561 compatible = "fsl,anatop-regulator"; 562 regulator-name = "vdd1p0d"; 563 regulator-min-microvolt = <800000>; 564 regulator-max-microvolt = <1200000>; 565 anatop-reg-offset = <0x210>; 566 anatop-vol-bit-shift = <8>; 567 anatop-vol-bit-width = <5>; 568 anatop-min-bit-val = <8>; 569 anatop-min-voltage = <800000>; 570 anatop-max-voltage = <1200000>; 571 anatop-enable-bit = <0>; 572 }; 573 574 reg_1p2: regulator-vdd1p2 { 575 compatible = "fsl,anatop-regulator"; 576 regulator-name = "vdd1p2"; 577 regulator-min-microvolt = <1100000>; 578 regulator-max-microvolt = <1300000>; 579 anatop-reg-offset = <0x220>; 580 anatop-vol-bit-shift = <8>; 581 anatop-vol-bit-width = <5>; 582 anatop-min-bit-val = <0x14>; 583 anatop-min-voltage = <1100000>; 584 anatop-max-voltage = <1300000>; 585 anatop-enable-bit = <0>; 586 }; 587 588 tempmon: tempmon { 589 compatible = "fsl,imx7d-tempmon"; 590 interrupt-parent = <&gpc>; 591 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 592 fsl,tempmon = <&anatop>; 593 nvmem-cells = <&tempmon_calib>, <&fuse_grade>; 594 nvmem-cell-names = "calib", "temp_grade"; 595 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; 596 }; 597 }; 598 599 snvs: snvs@30370000 { 600 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 601 reg = <0x30370000 0x10000>; 602 603 snvs_rtc: snvs-rtc-lp { 604 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 605 regmap = <&snvs>; 606 offset = <0x34>; 607 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&clks IMX7D_SNVS_CLK>; 610 clock-names = "snvs-rtc"; 611 }; 612 613 snvs_pwrkey: snvs-powerkey { 614 compatible = "fsl,sec-v4.0-pwrkey"; 615 regmap = <&snvs>; 616 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&clks IMX7D_SNVS_CLK>; 618 clock-names = "snvs-pwrkey"; 619 linux,keycode = <KEY_POWER>; 620 wakeup-source; 621 status = "disabled"; 622 }; 623 }; 624 625 clks: clock-controller@30380000 { 626 compatible = "fsl,imx7d-ccm"; 627 reg = <0x30380000 0x10000>; 628 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 630 #clock-cells = <1>; 631 clocks = <&ckil>, <&osc>; 632 clock-names = "ckil", "osc"; 633 }; 634 635 src: reset-controller@30390000 { 636 compatible = "fsl,imx7d-src", "syscon"; 637 reg = <0x30390000 0x10000>; 638 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 639 #reset-cells = <1>; 640 }; 641 642 gpc: gpc@303a0000 { 643 compatible = "fsl,imx7d-gpc"; 644 reg = <0x303a0000 0x10000>; 645 interrupt-controller; 646 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 647 #interrupt-cells = <3>; 648 interrupt-parent = <&intc>; 649 #power-domain-cells = <1>; 650 651 pgc { 652 #address-cells = <1>; 653 #size-cells = <0>; 654 655 pgc_mipi_phy: power-domain@0 { 656 #power-domain-cells = <0>; 657 reg = <0>; 658 power-supply = <®_1p0d>; 659 }; 660 661 pgc_pcie_phy: power-domain@1 { 662 #power-domain-cells = <0>; 663 reg = <1>; 664 power-supply = <®_1p0d>; 665 }; 666 667 pgc_hsic_phy: power-domain@2 { 668 #power-domain-cells = <0>; 669 reg = <2>; 670 power-supply = <®_1p2>; 671 }; 672 }; 673 }; 674 }; 675 676 aips2: bus@30400000 { 677 compatible = "fsl,aips-bus", "simple-bus"; 678 #address-cells = <1>; 679 #size-cells = <1>; 680 reg = <0x30400000 0x400000>; 681 ranges; 682 683 adc1: adc@30610000 { 684 compatible = "fsl,imx7d-adc"; 685 reg = <0x30610000 0x10000>; 686 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 688 clock-names = "adc"; 689 #io-channel-cells = <1>; 690 status = "disabled"; 691 }; 692 693 adc2: adc@30620000 { 694 compatible = "fsl,imx7d-adc"; 695 reg = <0x30620000 0x10000>; 696 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 698 clock-names = "adc"; 699 #io-channel-cells = <1>; 700 status = "disabled"; 701 }; 702 703 ecspi4: spi@30630000 { 704 #address-cells = <1>; 705 #size-cells = <0>; 706 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 707 reg = <0x30630000 0x10000>; 708 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, 710 <&clks IMX7D_ECSPI4_ROOT_CLK>; 711 clock-names = "ipg", "per"; 712 status = "disabled"; 713 }; 714 715 ftm1: pwm@30640000 { 716 compatible = "fsl,vf610-ftm-pwm"; 717 reg = <0x30640000 0x10000>; 718 #pwm-cells = <3>; 719 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 720 clock-names = "ftm_sys", "ftm_ext", 721 "ftm_fix", "ftm_cnt_clk_en"; 722 clocks = <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, 723 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, 724 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>, 725 <&clks IMX7D_FLEXTIMER1_ROOT_CLK>; 726 status = "disabled"; 727 }; 728 729 ftm2: pwm@30650000 { 730 compatible = "fsl,vf610-ftm-pwm"; 731 reg = <0x30650000 0x10000>; 732 #pwm-cells = <3>; 733 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 734 clock-names = "ftm_sys", "ftm_ext", 735 "ftm_fix", "ftm_cnt_clk_en"; 736 clocks = <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, 737 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, 738 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>, 739 <&clks IMX7D_FLEXTIMER2_ROOT_CLK>; 740 status = "disabled"; 741 }; 742 743 pwm1: pwm@30660000 { 744 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 745 reg = <0x30660000 0x10000>; 746 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&clks IMX7D_PWM1_ROOT_CLK>, 748 <&clks IMX7D_PWM1_ROOT_CLK>; 749 clock-names = "ipg", "per"; 750 #pwm-cells = <3>; 751 status = "disabled"; 752 }; 753 754 pwm2: pwm@30670000 { 755 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 756 reg = <0x30670000 0x10000>; 757 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&clks IMX7D_PWM2_ROOT_CLK>, 759 <&clks IMX7D_PWM2_ROOT_CLK>; 760 clock-names = "ipg", "per"; 761 #pwm-cells = <3>; 762 status = "disabled"; 763 }; 764 765 pwm3: pwm@30680000 { 766 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 767 reg = <0x30680000 0x10000>; 768 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&clks IMX7D_PWM3_ROOT_CLK>, 770 <&clks IMX7D_PWM3_ROOT_CLK>; 771 clock-names = "ipg", "per"; 772 #pwm-cells = <3>; 773 status = "disabled"; 774 }; 775 776 pwm4: pwm@30690000 { 777 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 778 reg = <0x30690000 0x10000>; 779 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&clks IMX7D_PWM4_ROOT_CLK>, 781 <&clks IMX7D_PWM4_ROOT_CLK>; 782 clock-names = "ipg", "per"; 783 #pwm-cells = <3>; 784 status = "disabled"; 785 }; 786 787 csi: csi@30710000 { 788 compatible = "fsl,imx7-csi"; 789 reg = <0x30710000 0x10000>; 790 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&clks IMX7D_CLK_DUMMY>, 792 <&clks IMX7D_CSI_MCLK_ROOT_CLK>, 793 <&clks IMX7D_CLK_DUMMY>; 794 clock-names = "axi", "mclk", "dcic"; 795 status = "disabled"; 796 797 port { 798 csi_from_csi_mux: endpoint { 799 remote-endpoint = <&csi_mux_to_csi>; 800 }; 801 }; 802 }; 803 804 lcdif: lcdif@30730000 { 805 compatible = "fsl,imx7d-lcdif", "fsl,imx6sx-lcdif"; 806 reg = <0x30730000 0x10000>; 807 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 808 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, 809 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; 810 clock-names = "pix", "axi"; 811 status = "disabled"; 812 }; 813 814 mipi_csi: mipi-csi@30750000 { 815 compatible = "fsl,imx7-mipi-csi2"; 816 reg = <0x30750000 0x10000>; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 821 <&clks IMX7D_MIPI_CSI_ROOT_CLK>, 822 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; 823 clock-names = "pclk", "wrap", "phy"; 824 power-domains = <&pgc_mipi_phy>; 825 phy-supply = <®_1p0d>; 826 resets = <&src IMX7_RESET_MIPI_PHY_MRST>; 827 reset-names = "mrst"; 828 status = "disabled"; 829 830 port@0 { 831 reg = <0>; 832 }; 833 834 port@1 { 835 reg = <1>; 836 837 mipi_vc0_to_csi_mux: endpoint { 838 remote-endpoint = <&csi_mux_from_mipi_vc0>; 839 }; 840 }; 841 }; 842 }; 843 844 aips3: bus@30800000 { 845 compatible = "fsl,aips-bus", "simple-bus"; 846 #address-cells = <1>; 847 #size-cells = <1>; 848 reg = <0x30800000 0x400000>; 849 ranges; 850 851 spba-bus@30800000 { 852 compatible = "fsl,spba-bus", "simple-bus"; 853 #address-cells = <1>; 854 #size-cells = <1>; 855 reg = <0x30800000 0x100000>; 856 ranges; 857 858 ecspi1: spi@30820000 { 859 #address-cells = <1>; 860 #size-cells = <0>; 861 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 862 reg = <0x30820000 0x10000>; 863 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, 865 <&clks IMX7D_ECSPI1_ROOT_CLK>; 866 clock-names = "ipg", "per"; 867 status = "disabled"; 868 }; 869 870 ecspi2: spi@30830000 { 871 #address-cells = <1>; 872 #size-cells = <0>; 873 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 874 reg = <0x30830000 0x10000>; 875 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, 877 <&clks IMX7D_ECSPI2_ROOT_CLK>; 878 clock-names = "ipg", "per"; 879 status = "disabled"; 880 }; 881 882 ecspi3: spi@30840000 { 883 #address-cells = <1>; 884 #size-cells = <0>; 885 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 886 reg = <0x30840000 0x10000>; 887 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 888 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, 889 <&clks IMX7D_ECSPI3_ROOT_CLK>; 890 clock-names = "ipg", "per"; 891 status = "disabled"; 892 }; 893 894 uart1: serial@30860000 { 895 compatible = "fsl,imx7d-uart", 896 "fsl,imx6q-uart"; 897 reg = <0x30860000 0x10000>; 898 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 899 clocks = <&clks IMX7D_UART1_ROOT_CLK>, 900 <&clks IMX7D_UART1_ROOT_CLK>; 901 clock-names = "ipg", "per"; 902 status = "disabled"; 903 }; 904 905 uart2: serial@30890000 { 906 compatible = "fsl,imx7d-uart", 907 "fsl,imx6q-uart"; 908 reg = <0x30890000 0x10000>; 909 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 910 clocks = <&clks IMX7D_UART2_ROOT_CLK>, 911 <&clks IMX7D_UART2_ROOT_CLK>; 912 clock-names = "ipg", "per"; 913 status = "disabled"; 914 }; 915 916 uart3: serial@30880000 { 917 compatible = "fsl,imx7d-uart", 918 "fsl,imx6q-uart"; 919 reg = <0x30880000 0x10000>; 920 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 921 clocks = <&clks IMX7D_UART3_ROOT_CLK>, 922 <&clks IMX7D_UART3_ROOT_CLK>; 923 clock-names = "ipg", "per"; 924 status = "disabled"; 925 }; 926 927 sai1: sai@308a0000 { 928 #sound-dai-cells = <0>; 929 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 930 reg = <0x308a0000 0x10000>; 931 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 932 clocks = <&clks IMX7D_SAI1_IPG_CLK>, 933 <&clks IMX7D_SAI1_ROOT_CLK>, 934 <&clks IMX7D_CLK_DUMMY>, 935 <&clks IMX7D_CLK_DUMMY>; 936 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 937 dma-names = "rx", "tx"; 938 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; 939 status = "disabled"; 940 }; 941 942 sai2: sai@308b0000 { 943 #sound-dai-cells = <0>; 944 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 945 reg = <0x308b0000 0x10000>; 946 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 947 clocks = <&clks IMX7D_SAI2_IPG_CLK>, 948 <&clks IMX7D_SAI2_ROOT_CLK>, 949 <&clks IMX7D_CLK_DUMMY>, 950 <&clks IMX7D_CLK_DUMMY>; 951 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 952 dma-names = "rx", "tx"; 953 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; 954 status = "disabled"; 955 }; 956 957 sai3: sai@308c0000 { 958 #sound-dai-cells = <0>; 959 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 960 reg = <0x308c0000 0x10000>; 961 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&clks IMX7D_SAI3_IPG_CLK>, 963 <&clks IMX7D_SAI3_ROOT_CLK>, 964 <&clks IMX7D_CLK_DUMMY>, 965 <&clks IMX7D_CLK_DUMMY>; 966 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 967 dma-names = "rx", "tx"; 968 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; 969 status = "disabled"; 970 }; 971 }; 972 973 crypto: crypto@30900000 { 974 compatible = "fsl,sec-v4.0"; 975 #address-cells = <1>; 976 #size-cells = <1>; 977 reg = <0x30900000 0x40000>; 978 ranges = <0 0x30900000 0x40000>; 979 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&clks IMX7D_CAAM_CLK>, 981 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; 982 clock-names = "ipg", "aclk"; 983 984 sec_jr0: jr@1000 { 985 compatible = "fsl,sec-v4.0-job-ring"; 986 reg = <0x1000 0x1000>; 987 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 988 }; 989 990 sec_jr1: jr@2000 { 991 compatible = "fsl,sec-v4.0-job-ring"; 992 reg = <0x2000 0x1000>; 993 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 994 }; 995 996 sec_jr2: jr@3000 { 997 compatible = "fsl,sec-v4.0-job-ring"; 998 reg = <0x3000 0x1000>; 999 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1000 }; 1001 }; 1002 1003 flexcan1: can@30a00000 { 1004 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 1005 reg = <0x30a00000 0x10000>; 1006 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1007 clocks = <&clks IMX7D_CLK_DUMMY>, 1008 <&clks IMX7D_CAN1_ROOT_CLK>; 1009 clock-names = "ipg", "per"; 1010 fsl,stop-mode = <&gpr 0x10 1>; 1011 status = "disabled"; 1012 }; 1013 1014 flexcan2: can@30a10000 { 1015 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 1016 reg = <0x30a10000 0x10000>; 1017 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1018 clocks = <&clks IMX7D_CLK_DUMMY>, 1019 <&clks IMX7D_CAN2_ROOT_CLK>; 1020 clock-names = "ipg", "per"; 1021 fsl,stop-mode = <&gpr 0x10 2>; 1022 status = "disabled"; 1023 }; 1024 1025 i2c1: i2c@30a20000 { 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1029 reg = <0x30a20000 0x10000>; 1030 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1031 clocks = <&clks IMX7D_I2C1_ROOT_CLK>; 1032 status = "disabled"; 1033 }; 1034 1035 i2c2: i2c@30a30000 { 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1039 reg = <0x30a30000 0x10000>; 1040 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1041 clocks = <&clks IMX7D_I2C2_ROOT_CLK>; 1042 status = "disabled"; 1043 }; 1044 1045 i2c3: i2c@30a40000 { 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1049 reg = <0x30a40000 0x10000>; 1050 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1051 clocks = <&clks IMX7D_I2C3_ROOT_CLK>; 1052 status = "disabled"; 1053 }; 1054 1055 i2c4: i2c@30a50000 { 1056 #address-cells = <1>; 1057 #size-cells = <0>; 1058 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1059 reg = <0x30a50000 0x10000>; 1060 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1061 clocks = <&clks IMX7D_I2C4_ROOT_CLK>; 1062 status = "disabled"; 1063 }; 1064 1065 uart4: serial@30a60000 { 1066 compatible = "fsl,imx7d-uart", 1067 "fsl,imx6q-uart"; 1068 reg = <0x30a60000 0x10000>; 1069 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1070 clocks = <&clks IMX7D_UART4_ROOT_CLK>, 1071 <&clks IMX7D_UART4_ROOT_CLK>; 1072 clock-names = "ipg", "per"; 1073 status = "disabled"; 1074 }; 1075 1076 uart5: serial@30a70000 { 1077 compatible = "fsl,imx7d-uart", 1078 "fsl,imx6q-uart"; 1079 reg = <0x30a70000 0x10000>; 1080 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1081 clocks = <&clks IMX7D_UART5_ROOT_CLK>, 1082 <&clks IMX7D_UART5_ROOT_CLK>; 1083 clock-names = "ipg", "per"; 1084 status = "disabled"; 1085 }; 1086 1087 uart6: serial@30a80000 { 1088 compatible = "fsl,imx7d-uart", 1089 "fsl,imx6q-uart"; 1090 reg = <0x30a80000 0x10000>; 1091 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1092 clocks = <&clks IMX7D_UART6_ROOT_CLK>, 1093 <&clks IMX7D_UART6_ROOT_CLK>; 1094 clock-names = "ipg", "per"; 1095 status = "disabled"; 1096 }; 1097 1098 uart7: serial@30a90000 { 1099 compatible = "fsl,imx7d-uart", 1100 "fsl,imx6q-uart"; 1101 reg = <0x30a90000 0x10000>; 1102 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1103 clocks = <&clks IMX7D_UART7_ROOT_CLK>, 1104 <&clks IMX7D_UART7_ROOT_CLK>; 1105 clock-names = "ipg", "per"; 1106 status = "disabled"; 1107 }; 1108 1109 mu0a: mailbox@30aa0000 { 1110 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1111 reg = <0x30aa0000 0x10000>; 1112 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1113 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1114 #mbox-cells = <2>; 1115 status = "disabled"; 1116 }; 1117 1118 mu0b: mailbox@30ab0000 { 1119 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1120 reg = <0x30ab0000 0x10000>; 1121 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1122 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1123 #mbox-cells = <2>; 1124 fsl,mu-side-b; 1125 status = "disabled"; 1126 }; 1127 1128 usbotg1: usb@30b10000 { 1129 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1130 reg = <0x30b10000 0x200>; 1131 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1132 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1133 fsl,usbphy = <&usbphynop1>; 1134 fsl,usbmisc = <&usbmisc1 0>; 1135 phy-clkgate-delay-us = <400>; 1136 status = "disabled"; 1137 }; 1138 1139 usbh: usb@30b30000 { 1140 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1141 reg = <0x30b30000 0x200>; 1142 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1143 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1144 fsl,usbphy = <&usbphynop3>; 1145 fsl,usbmisc = <&usbmisc3 0>; 1146 phy_type = "hsic"; 1147 dr_mode = "host"; 1148 phy-clkgate-delay-us = <400>; 1149 status = "disabled"; 1150 }; 1151 1152 usbmisc1: usbmisc@30b10200 { 1153 #index-cells = <1>; 1154 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1155 reg = <0x30b10200 0x200>; 1156 }; 1157 1158 usbmisc3: usbmisc@30b30200 { 1159 #index-cells = <1>; 1160 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1161 reg = <0x30b30200 0x200>; 1162 }; 1163 1164 usdhc1: mmc@30b40000 { 1165 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1166 reg = <0x30b40000 0x10000>; 1167 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1168 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1169 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1170 <&clks IMX7D_USDHC1_ROOT_CLK>; 1171 clock-names = "ipg", "ahb", "per"; 1172 bus-width = <4>; 1173 fsl,tuning-step = <2>; 1174 fsl,tuning-start-tap = <20>; 1175 status = "disabled"; 1176 }; 1177 1178 usdhc2: mmc@30b50000 { 1179 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1180 reg = <0x30b50000 0x10000>; 1181 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1182 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1183 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1184 <&clks IMX7D_USDHC2_ROOT_CLK>; 1185 clock-names = "ipg", "ahb", "per"; 1186 bus-width = <4>; 1187 fsl,tuning-step = <2>; 1188 fsl,tuning-start-tap = <20>; 1189 status = "disabled"; 1190 }; 1191 1192 usdhc3: mmc@30b60000 { 1193 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1194 reg = <0x30b60000 0x10000>; 1195 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1196 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1197 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1198 <&clks IMX7D_USDHC3_ROOT_CLK>; 1199 clock-names = "ipg", "ahb", "per"; 1200 bus-width = <4>; 1201 fsl,tuning-step = <2>; 1202 fsl,tuning-start-tap = <20>; 1203 status = "disabled"; 1204 }; 1205 1206 qspi: spi@30bb0000 { 1207 compatible = "fsl,imx7d-qspi"; 1208 reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; 1209 reg-names = "QuadSPI", "QuadSPI-memory"; 1210 #address-cells = <1>; 1211 #size-cells = <0>; 1212 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1213 clocks = <&clks IMX7D_QSPI_ROOT_CLK>, 1214 <&clks IMX7D_QSPI_ROOT_CLK>; 1215 clock-names = "qspi_en", "qspi"; 1216 status = "disabled"; 1217 }; 1218 1219 sdma: dma-controller@30bd0000 { 1220 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; 1221 reg = <0x30bd0000 0x10000>; 1222 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1223 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1224 <&clks IMX7D_SDMA_CORE_CLK>; 1225 clock-names = "ipg", "ahb"; 1226 #dma-cells = <3>; 1227 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1228 }; 1229 1230 fec1: ethernet@30be0000 { 1231 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; 1232 reg = <0x30be0000 0x10000>; 1233 interrupt-names = "int0", "int1", "int2", "pps"; 1234 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1238 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>, 1239 <&clks IMX7D_ENET_AXI_ROOT_CLK>, 1240 <&clks IMX7D_ENET1_TIME_ROOT_CLK>, 1241 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, 1242 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; 1243 clock-names = "ipg", "ahb", "ptp", 1244 "enet_clk_ref", "enet_out"; 1245 fsl,num-tx-queues = <3>; 1246 fsl,num-rx-queues = <3>; 1247 fsl,stop-mode = <&gpr 0x10 3>; 1248 status = "disabled"; 1249 }; 1250 }; 1251 1252 dma_apbh: dma-controller@33000000 { 1253 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1254 reg = <0x33000000 0x2000>; 1255 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1259 #dma-cells = <1>; 1260 dma-channels = <4>; 1261 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1262 }; 1263 1264 gpmi: nand-controller@33002000{ 1265 compatible = "fsl,imx7d-gpmi-nand"; 1266 #address-cells = <1>; 1267 #size-cells = <0>; 1268 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1269 reg-names = "gpmi-nand", "bch"; 1270 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1271 interrupt-names = "bch"; 1272 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, 1273 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1274 clock-names = "gpmi_io", "gpmi_bch_apb"; 1275 dmas = <&dma_apbh 0>; 1276 dma-names = "rx-tx"; 1277 status = "disabled"; 1278 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; 1279 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; 1280 }; 1281 }; 1282}; 1283