1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * CAAM/SEC 4.x driver backend
4 * Private/internal definitions between modules
5 *
6 * Copyright 2008-2011 Freescale Semiconductor, Inc.
7 * Copyright 2019 NXP
8 */
9
10 #ifndef INTERN_H
11 #define INTERN_H
12
13 #include "ctrl.h"
14 #include <crypto/engine.h>
15
16 /* Currently comes from Kconfig param as a ^2 (driver-required) */
17 #define JOBR_DEPTH (1 << CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE)
18
19 /*
20 * Maximum size for crypto-engine software queue based on Job Ring
21 * size (JOBR_DEPTH) and a THRESHOLD (reserved for the non-crypto-API
22 * requests that are not passed through crypto-engine)
23 */
24 #define THRESHOLD 15
25 #define CRYPTO_ENGINE_MAX_QLEN (JOBR_DEPTH - THRESHOLD)
26
27 /* Kconfig params for interrupt coalescing if selected (else zero) */
28 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_INTC
29 #define JOBR_INTC JRCFG_ICEN
30 #define JOBR_INTC_TIME_THLD CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD
31 #define JOBR_INTC_COUNT_THLD CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_COUNT_THLD
32 #else
33 #define JOBR_INTC 0
34 #define JOBR_INTC_TIME_THLD 0
35 #define JOBR_INTC_COUNT_THLD 0
36 #endif
37
38 /*
39 * Storage for tracking each in-process entry moving across a ring
40 * Each entry on an output ring needs one of these
41 */
42 struct caam_jrentry_info {
43 void (*callbk)(struct device *dev, u32 *desc, u32 status, void *arg);
44 void *cbkarg; /* Argument per ring entry */
45 u32 *desc_addr_virt; /* Stored virt addr for postprocessing */
46 dma_addr_t desc_addr_dma; /* Stored bus addr for done matching */
47 u32 desc_size; /* Stored size for postprocessing, header derived */
48 };
49
50 /* Private sub-storage for a single JobR */
51 struct caam_drv_private_jr {
52 struct list_head list_node; /* Job Ring device list */
53 struct device *dev;
54 int ridx;
55 struct caam_job_ring __iomem *rregs; /* JobR's register space */
56 struct tasklet_struct irqtask;
57 int irq; /* One per queue */
58 bool hwrng;
59
60 /* Number of scatterlist crypt transforms active on the JobR */
61 atomic_t tfm_count ____cacheline_aligned;
62
63 /* Job ring info */
64 struct caam_jrentry_info *entinfo; /* Alloc'ed 1 per ring entry */
65 spinlock_t inplock ____cacheline_aligned; /* Input ring index lock */
66 u32 inpring_avail; /* Number of free entries in input ring */
67 int head; /* entinfo (s/w ring) head index */
68 void *inpring; /* Base of input ring, alloc
69 * DMA-safe */
70 int out_ring_read_index; /* Output index "tail" */
71 int tail; /* entinfo (s/w ring) tail index */
72 void *outring; /* Base of output ring, DMA-safe */
73 struct crypto_engine *engine;
74 };
75
76 /*
77 * Driver-private storage for a single CAAM block instance
78 */
79 struct caam_drv_private {
80 /* Physical-presence section */
81 struct caam_ctrl __iomem *ctrl; /* controller region */
82 struct caam_deco __iomem *deco; /* DECO/CCB views */
83 struct caam_assurance __iomem *assure;
84 struct caam_queue_if __iomem *qi; /* QI control region */
85 struct caam_job_ring __iomem *jr[4]; /* JobR's register space */
86
87 struct iommu_domain *domain;
88
89 /*
90 * Detected geometry block. Filled in from device tree if powerpc,
91 * or from register-based version detection code
92 */
93 u8 total_jobrs; /* Total Job Rings in device */
94 u8 qi_present; /* Nonzero if QI present in device */
95 u8 mc_en; /* Nonzero if MC f/w is active */
96 int secvio_irq; /* Security violation interrupt number */
97 int virt_en; /* Virtualization enabled in CAAM */
98 int era; /* CAAM Era (internal HW revision) */
99
100 #define RNG4_MAX_HANDLES 2
101 /* RNG4 block */
102 u32 rng4_sh_init; /* This bitmap shows which of the State
103 Handles of the RNG4 block are initialized
104 by this driver */
105
106 struct clk_bulk_data *clks;
107 int num_clks;
108 /*
109 * debugfs entries for developer view into driver/device
110 * variables at runtime.
111 */
112 #ifdef CONFIG_DEBUG_FS
113 struct dentry *ctl; /* controller dir */
114 struct debugfs_blob_wrapper ctl_kek_wrap, ctl_tkek_wrap, ctl_tdsk_wrap;
115 #endif
116 };
117
118 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API
119
120 int caam_algapi_init(struct device *dev);
121 void caam_algapi_exit(void);
122
123 #else
124
caam_algapi_init(struct device * dev)125 static inline int caam_algapi_init(struct device *dev)
126 {
127 return 0;
128 }
129
caam_algapi_exit(void)130 static inline void caam_algapi_exit(void)
131 {
132 }
133
134 #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API */
135
136 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API
137
138 int caam_algapi_hash_init(struct device *dev);
139 void caam_algapi_hash_exit(void);
140
141 #else
142
caam_algapi_hash_init(struct device * dev)143 static inline int caam_algapi_hash_init(struct device *dev)
144 {
145 return 0;
146 }
147
caam_algapi_hash_exit(void)148 static inline void caam_algapi_hash_exit(void)
149 {
150 }
151
152 #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API */
153
154 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API
155
156 int caam_pkc_init(struct device *dev);
157 void caam_pkc_exit(void);
158
159 #else
160
caam_pkc_init(struct device * dev)161 static inline int caam_pkc_init(struct device *dev)
162 {
163 return 0;
164 }
165
caam_pkc_exit(void)166 static inline void caam_pkc_exit(void)
167 {
168 }
169
170 #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API */
171
172 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API
173
174 int caam_rng_init(struct device *dev);
175 void caam_rng_exit(struct device *dev);
176
177 #else
178
caam_rng_init(struct device * dev)179 static inline int caam_rng_init(struct device *dev)
180 {
181 return 0;
182 }
183
caam_rng_exit(struct device * dev)184 static inline void caam_rng_exit(struct device *dev) {}
185
186 #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API */
187
188 #ifdef CONFIG_CAAM_QI
189
190 int caam_qi_algapi_init(struct device *dev);
191 void caam_qi_algapi_exit(void);
192
193 #else
194
caam_qi_algapi_init(struct device * dev)195 static inline int caam_qi_algapi_init(struct device *dev)
196 {
197 return 0;
198 }
199
caam_qi_algapi_exit(void)200 static inline void caam_qi_algapi_exit(void)
201 {
202 }
203
204 #endif /* CONFIG_CAAM_QI */
205
caam_get_dma_mask(struct device * dev)206 static inline u64 caam_get_dma_mask(struct device *dev)
207 {
208 struct device_node *nprop = dev->of_node;
209
210 if (caam_ptr_sz != sizeof(u64))
211 return DMA_BIT_MASK(32);
212
213 if (caam_dpaa2)
214 return DMA_BIT_MASK(49);
215
216 if (of_device_is_compatible(nprop, "fsl,sec-v5.0-job-ring") ||
217 of_device_is_compatible(nprop, "fsl,sec-v5.0"))
218 return DMA_BIT_MASK(40);
219
220 return DMA_BIT_MASK(36);
221 }
222
223
224 #endif /* INTERN_H */
225