1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/mt8192-pinfunc.h> 11 12/ { 13 compatible = "mediatek,mt8192"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 clk26m: oscillator0 { 19 compatible = "fixed-clock"; 20 #clock-cells = <0>; 21 clock-frequency = <26000000>; 22 clock-output-names = "clk26m"; 23 }; 24 25 clk32k: oscillator1 { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <32768>; 29 clock-output-names = "clk32k"; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 cpu0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a55"; 39 reg = <0x000>; 40 enable-method = "psci"; 41 clock-frequency = <1701000000>; 42 cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 43 next-level-cache = <&l2_0>; 44 performance-domains = <&performance 0>; 45 capacity-dmips-mhz = <427>; 46 }; 47 48 cpu1: cpu@100 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a55"; 51 reg = <0x100>; 52 enable-method = "psci"; 53 clock-frequency = <1701000000>; 54 cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 55 next-level-cache = <&l2_0>; 56 performance-domains = <&performance 0>; 57 capacity-dmips-mhz = <427>; 58 }; 59 60 cpu2: cpu@200 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a55"; 63 reg = <0x200>; 64 enable-method = "psci"; 65 clock-frequency = <1701000000>; 66 cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 67 next-level-cache = <&l2_0>; 68 performance-domains = <&performance 0>; 69 capacity-dmips-mhz = <427>; 70 }; 71 72 cpu3: cpu@300 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a55"; 75 reg = <0x300>; 76 enable-method = "psci"; 77 clock-frequency = <1701000000>; 78 cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 79 next-level-cache = <&l2_0>; 80 performance-domains = <&performance 0>; 81 capacity-dmips-mhz = <427>; 82 }; 83 84 cpu4: cpu@400 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a76"; 87 reg = <0x400>; 88 enable-method = "psci"; 89 clock-frequency = <2171000000>; 90 cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 91 next-level-cache = <&l2_1>; 92 performance-domains = <&performance 1>; 93 capacity-dmips-mhz = <1024>; 94 }; 95 96 cpu5: cpu@500 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a76"; 99 reg = <0x500>; 100 enable-method = "psci"; 101 clock-frequency = <2171000000>; 102 cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 103 next-level-cache = <&l2_1>; 104 performance-domains = <&performance 1>; 105 capacity-dmips-mhz = <1024>; 106 }; 107 108 cpu6: cpu@600 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a76"; 111 reg = <0x600>; 112 enable-method = "psci"; 113 clock-frequency = <2171000000>; 114 cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 115 next-level-cache = <&l2_1>; 116 performance-domains = <&performance 1>; 117 capacity-dmips-mhz = <1024>; 118 }; 119 120 cpu7: cpu@700 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a76"; 123 reg = <0x700>; 124 enable-method = "psci"; 125 clock-frequency = <2171000000>; 126 cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 127 next-level-cache = <&l2_1>; 128 performance-domains = <&performance 1>; 129 capacity-dmips-mhz = <1024>; 130 }; 131 132 cpu-map { 133 cluster0 { 134 core0 { 135 cpu = <&cpu0>; 136 }; 137 core1 { 138 cpu = <&cpu1>; 139 }; 140 core2 { 141 cpu = <&cpu2>; 142 }; 143 core3 { 144 cpu = <&cpu3>; 145 }; 146 core4 { 147 cpu = <&cpu4>; 148 }; 149 core5 { 150 cpu = <&cpu5>; 151 }; 152 core6 { 153 cpu = <&cpu6>; 154 }; 155 core7 { 156 cpu = <&cpu7>; 157 }; 158 }; 159 }; 160 161 l2_0: l2-cache0 { 162 compatible = "cache"; 163 next-level-cache = <&l3_0>; 164 }; 165 166 l2_1: l2-cache1 { 167 compatible = "cache"; 168 next-level-cache = <&l3_0>; 169 }; 170 171 l3_0: l3-cache { 172 compatible = "cache"; 173 }; 174 175 idle-states { 176 entry-method = "psci"; 177 cpu_sleep_l: cpu-sleep-l { 178 compatible = "arm,idle-state"; 179 arm,psci-suspend-param = <0x00010001>; 180 local-timer-stop; 181 entry-latency-us = <55>; 182 exit-latency-us = <140>; 183 min-residency-us = <780>; 184 }; 185 cpu_sleep_b: cpu-sleep-b { 186 compatible = "arm,idle-state"; 187 arm,psci-suspend-param = <0x00010001>; 188 local-timer-stop; 189 entry-latency-us = <35>; 190 exit-latency-us = <145>; 191 min-residency-us = <720>; 192 }; 193 cluster_sleep_l: cluster-sleep-l { 194 compatible = "arm,idle-state"; 195 arm,psci-suspend-param = <0x01010002>; 196 local-timer-stop; 197 entry-latency-us = <60>; 198 exit-latency-us = <155>; 199 min-residency-us = <860>; 200 }; 201 cluster_sleep_b: cluster-sleep-b { 202 compatible = "arm,idle-state"; 203 arm,psci-suspend-param = <0x01010002>; 204 local-timer-stop; 205 entry-latency-us = <40>; 206 exit-latency-us = <155>; 207 min-residency-us = <780>; 208 }; 209 }; 210 }; 211 212 pmu-a55 { 213 compatible = "arm,cortex-a55-pmu"; 214 interrupt-parent = <&gic>; 215 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 216 }; 217 218 pmu-a76 { 219 compatible = "arm,cortex-a76-pmu"; 220 interrupt-parent = <&gic>; 221 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 222 }; 223 224 psci { 225 compatible = "arm,psci-1.0"; 226 method = "smc"; 227 }; 228 229 timer: timer { 230 compatible = "arm,armv8-timer"; 231 interrupt-parent = <&gic>; 232 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 233 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 234 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 235 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 236 clock-frequency = <13000000>; 237 }; 238 239 soc { 240 #address-cells = <2>; 241 #size-cells = <2>; 242 compatible = "simple-bus"; 243 ranges; 244 245 performance: performance-controller@11bc10 { 246 compatible = "mediatek,cpufreq-hw"; 247 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 248 #performance-domain-cells = <1>; 249 }; 250 251 gic: interrupt-controller@c000000 { 252 compatible = "arm,gic-v3"; 253 #interrupt-cells = <4>; 254 #redistributor-regions = <1>; 255 interrupt-parent = <&gic>; 256 interrupt-controller; 257 reg = <0 0x0c000000 0 0x40000>, 258 <0 0x0c040000 0 0x200000>; 259 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 260 261 ppi-partitions { 262 ppi_cluster0: interrupt-partition-0 { 263 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 264 }; 265 ppi_cluster1: interrupt-partition-1 { 266 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 267 }; 268 }; 269 }; 270 271 pio: pinctrl@10005000 { 272 compatible = "mediatek,mt8192-pinctrl"; 273 reg = <0 0x10005000 0 0x1000>, 274 <0 0x11c20000 0 0x1000>, 275 <0 0x11d10000 0 0x1000>, 276 <0 0x11d30000 0 0x1000>, 277 <0 0x11d40000 0 0x1000>, 278 <0 0x11e20000 0 0x1000>, 279 <0 0x11e70000 0 0x1000>, 280 <0 0x11ea0000 0 0x1000>, 281 <0 0x11f20000 0 0x1000>, 282 <0 0x11f30000 0 0x1000>, 283 <0 0x1000b000 0 0x1000>; 284 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 285 "iocfg_bl", "iocfg_br", "iocfg_lm", 286 "iocfg_lb", "iocfg_rt", "iocfg_lt", 287 "iocfg_tl", "eint"; 288 gpio-controller; 289 #gpio-cells = <2>; 290 gpio-ranges = <&pio 0 0 220>; 291 interrupt-controller; 292 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 293 #interrupt-cells = <2>; 294 }; 295 296 systimer: timer@10017000 { 297 compatible = "mediatek,mt8192-timer", 298 "mediatek,mt6765-timer"; 299 reg = <0 0x10017000 0 0x1000>; 300 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 301 clocks = <&clk26m>; 302 clock-names = "clk13m"; 303 }; 304 305 uart0: serial@11002000 { 306 compatible = "mediatek,mt8192-uart", 307 "mediatek,mt6577-uart"; 308 reg = <0 0x11002000 0 0x1000>; 309 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 310 clocks = <&clk26m>, <&clk26m>; 311 clock-names = "baud", "bus"; 312 status = "disabled"; 313 }; 314 315 uart1: serial@11003000 { 316 compatible = "mediatek,mt8192-uart", 317 "mediatek,mt6577-uart"; 318 reg = <0 0x11003000 0 0x1000>; 319 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 320 clocks = <&clk26m>, <&clk26m>; 321 clock-names = "baud", "bus"; 322 status = "disabled"; 323 }; 324 325 spi0: spi@1100a000 { 326 compatible = "mediatek,mt8192-spi", 327 "mediatek,mt6765-spi"; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 reg = <0 0x1100a000 0 0x1000>; 331 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 332 clocks = <&clk26m>, 333 <&clk26m>, 334 <&clk26m>; 335 clock-names = "parent-clk", "sel-clk", "spi-clk"; 336 status = "disabled"; 337 }; 338 339 spi1: spi@11010000 { 340 compatible = "mediatek,mt8192-spi", 341 "mediatek,mt6765-spi"; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 reg = <0 0x11010000 0 0x1000>; 345 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 346 clocks = <&clk26m>, 347 <&clk26m>, 348 <&clk26m>; 349 clock-names = "parent-clk", "sel-clk", "spi-clk"; 350 status = "disabled"; 351 }; 352 353 spi2: spi@11012000 { 354 compatible = "mediatek,mt8192-spi", 355 "mediatek,mt6765-spi"; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 reg = <0 0x11012000 0 0x1000>; 359 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 360 clocks = <&clk26m>, 361 <&clk26m>, 362 <&clk26m>; 363 clock-names = "parent-clk", "sel-clk", "spi-clk"; 364 status = "disabled"; 365 }; 366 367 spi3: spi@11013000 { 368 compatible = "mediatek,mt8192-spi", 369 "mediatek,mt6765-spi"; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 reg = <0 0x11013000 0 0x1000>; 373 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 374 clocks = <&clk26m>, 375 <&clk26m>, 376 <&clk26m>; 377 clock-names = "parent-clk", "sel-clk", "spi-clk"; 378 status = "disabled"; 379 }; 380 381 spi4: spi@11018000 { 382 compatible = "mediatek,mt8192-spi", 383 "mediatek,mt6765-spi"; 384 #address-cells = <1>; 385 #size-cells = <0>; 386 reg = <0 0x11018000 0 0x1000>; 387 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 388 clocks = <&clk26m>, 389 <&clk26m>, 390 <&clk26m>; 391 clock-names = "parent-clk", "sel-clk", "spi-clk"; 392 status = "disabled"; 393 }; 394 395 spi5: spi@11019000 { 396 compatible = "mediatek,mt8192-spi", 397 "mediatek,mt6765-spi"; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 reg = <0 0x11019000 0 0x1000>; 401 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 402 clocks = <&clk26m>, 403 <&clk26m>, 404 <&clk26m>; 405 clock-names = "parent-clk", "sel-clk", "spi-clk"; 406 status = "disabled"; 407 }; 408 409 spi6: spi@1101d000 { 410 compatible = "mediatek,mt8192-spi", 411 "mediatek,mt6765-spi"; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 reg = <0 0x1101d000 0 0x1000>; 415 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 416 clocks = <&clk26m>, 417 <&clk26m>, 418 <&clk26m>; 419 clock-names = "parent-clk", "sel-clk", "spi-clk"; 420 status = "disabled"; 421 }; 422 423 spi7: spi@1101e000 { 424 compatible = "mediatek,mt8192-spi", 425 "mediatek,mt6765-spi"; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 reg = <0 0x1101e000 0 0x1000>; 429 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 430 clocks = <&clk26m>, 431 <&clk26m>, 432 <&clk26m>; 433 clock-names = "parent-clk", "sel-clk", "spi-clk"; 434 status = "disabled"; 435 }; 436 437 nor_flash: spi@11234000 { 438 compatible = "mediatek,mt8192-nor"; 439 reg = <0 0x11234000 0 0xe0>; 440 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 441 clocks = <&clk26m>, 442 <&clk26m>, 443 <&clk26m>; 444 clock-names = "spi", "sf", "axi"; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 status = "disabled"; 448 }; 449 450 i2c3: i2c3@11cb0000 { 451 compatible = "mediatek,mt8192-i2c"; 452 reg = <0 0x11cb0000 0 0x1000>, 453 <0 0x10217300 0 0x80>; 454 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 455 clocks = <&clk26m>, <&clk26m>; 456 clock-names = "main", "dma"; 457 clock-div = <1>; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 status = "disabled"; 461 }; 462 463 i2c7: i2c7@11d00000 { 464 compatible = "mediatek,mt8192-i2c"; 465 reg = <0 0x11d00000 0 0x1000>, 466 <0 0x10217600 0 0x180>; 467 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 468 clocks = <&clk26m>, <&clk26m>; 469 clock-names = "main", "dma"; 470 clock-div = <1>; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 status = "disabled"; 474 }; 475 476 i2c8: i2c8@11d01000 { 477 compatible = "mediatek,mt8192-i2c"; 478 reg = <0 0x11d01000 0 0x1000>, 479 <0 0x10217780 0 0x180>; 480 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 481 clocks = <&clk26m>, <&clk26m>; 482 clock-names = "main", "dma"; 483 clock-div = <1>; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 status = "disabled"; 487 }; 488 489 i2c9: i2c9@11d02000 { 490 compatible = "mediatek,mt8192-i2c"; 491 reg = <0 0x11d02000 0 0x1000>, 492 <0 0x10217900 0 0x180>; 493 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 494 clocks = <&clk26m>, <&clk26m>; 495 clock-names = "main", "dma"; 496 clock-div = <1>; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 status = "disabled"; 500 }; 501 502 i2c1: i2c1@11d20000 { 503 compatible = "mediatek,mt8192-i2c"; 504 reg = <0 0x11d20000 0 0x1000>, 505 <0 0x10217100 0 0x80>; 506 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 507 clocks = <&clk26m>, <&clk26m>; 508 clock-names = "main", "dma"; 509 clock-div = <1>; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 status = "disabled"; 513 }; 514 515 i2c2: i2c2@11d21000 { 516 compatible = "mediatek,mt8192-i2c"; 517 reg = <0 0x11d21000 0 0x1000>, 518 <0 0x10217180 0 0x180>; 519 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 520 clocks = <&clk26m>, <&clk26m>; 521 clock-names = "main", "dma"; 522 clock-div = <1>; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 status = "disabled"; 526 }; 527 528 i2c4: i2c4@11d22000 { 529 compatible = "mediatek,mt8192-i2c"; 530 reg = <0 0x11d22000 0 0x1000>, 531 <0 0x10217380 0 0x180>; 532 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 533 clocks = <&clk26m>, <&clk26m>; 534 clock-names = "main", "dma"; 535 clock-div = <1>; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 status = "disabled"; 539 }; 540 541 i2c5: i2c5@11e00000 { 542 compatible = "mediatek,mt8192-i2c"; 543 reg = <0 0x11e00000 0 0x1000>, 544 <0 0x10217500 0 0x80>; 545 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 546 clocks = <&clk26m>, <&clk26m>; 547 clock-names = "main", "dma"; 548 clock-div = <1>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 status = "disabled"; 552 }; 553 554 i2c0: i2c0@11f00000 { 555 compatible = "mediatek,mt8192-i2c"; 556 reg = <0 0x11f00000 0 0x1000>, 557 <0 0x10217080 0 0x80>; 558 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 559 clocks = <&clk26m>, <&clk26m>; 560 clock-names = "main", "dma"; 561 clock-div = <1>; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 status = "disabled"; 565 }; 566 567 i2c6: i2c6@11f01000 { 568 compatible = "mediatek,mt8192-i2c"; 569 reg = <0 0x11f01000 0 0x1000>, 570 <0 0x10217580 0 0x80>; 571 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 572 clocks = <&clk26m>, <&clk26m>; 573 clock-names = "main", "dma"; 574 clock-div = <1>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 status = "disabled"; 578 }; 579 }; 580}; 581