1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * IOMMU API for MTK architected m4u v1 implementations
4 *
5 * Copyright (c) 2015-2016 MediaTek Inc.
6 * Author: Honghui Zhang <honghui.zhang@mediatek.com>
7 *
8 * Based on driver/iommu/mtk_iommu.c
9 */
10 #include <linux/memblock.h>
11 #include <linux/bug.h>
12 #include <linux/clk.h>
13 #include <linux/component.h>
14 #include <linux/device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/err.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/iommu.h>
20 #include <linux/iopoll.h>
21 #include <linux/list.h>
22 #include <linux/module.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_platform.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <linux/spinlock.h>
29 #include <asm/barrier.h>
30 #include <asm/dma-iommu.h>
31 #include <linux/init.h>
32 #include <dt-bindings/memory/mt2701-larb-port.h>
33 #include <soc/mediatek/smi.h>
34 #include "mtk_iommu.h"
35
36 #define REG_MMU_PT_BASE_ADDR 0x000
37
38 #define F_ALL_INVLD 0x2
39 #define F_MMU_INV_RANGE 0x1
40 #define F_INVLD_EN0 BIT(0)
41 #define F_INVLD_EN1 BIT(1)
42
43 #define F_MMU_FAULT_VA_MSK 0xfffff000
44 #define MTK_PROTECT_PA_ALIGN 128
45
46 #define REG_MMU_CTRL_REG 0x210
47 #define F_MMU_CTRL_COHERENT_EN BIT(8)
48 #define REG_MMU_IVRP_PADDR 0x214
49 #define REG_MMU_INT_CONTROL 0x220
50 #define F_INT_TRANSLATION_FAULT BIT(0)
51 #define F_INT_MAIN_MULTI_HIT_FAULT BIT(1)
52 #define F_INT_INVALID_PA_FAULT BIT(2)
53 #define F_INT_ENTRY_REPLACEMENT_FAULT BIT(3)
54 #define F_INT_TABLE_WALK_FAULT BIT(4)
55 #define F_INT_TLB_MISS_FAULT BIT(5)
56 #define F_INT_PFH_DMA_FIFO_OVERFLOW BIT(6)
57 #define F_INT_MISS_DMA_FIFO_OVERFLOW BIT(7)
58
59 #define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5)
60 #define F_INT_CLR_BIT BIT(12)
61
62 #define REG_MMU_FAULT_ST 0x224
63 #define REG_MMU_FAULT_VA 0x228
64 #define REG_MMU_INVLD_PA 0x22C
65 #define REG_MMU_INT_ID 0x388
66 #define REG_MMU_INVALIDATE 0x5c0
67 #define REG_MMU_INVLD_START_A 0x5c4
68 #define REG_MMU_INVLD_END_A 0x5c8
69
70 #define REG_MMU_INV_SEL 0x5d8
71 #define REG_MMU_STANDARD_AXI_MODE 0x5e8
72
73 #define REG_MMU_DCM 0x5f0
74 #define F_MMU_DCM_ON BIT(1)
75 #define REG_MMU_CPE_DONE 0x60c
76 #define F_DESC_VALID 0x2
77 #define F_DESC_NONSEC BIT(3)
78 #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7))
79 #define MT2701_M4U_TF_PORT(TF) (((TF) >> 8) & 0xF)
80 /* MTK generation one iommu HW only support 4K size mapping */
81 #define MT2701_IOMMU_PAGE_SHIFT 12
82 #define MT2701_IOMMU_PAGE_SIZE (1UL << MT2701_IOMMU_PAGE_SHIFT)
83 #define MT2701_LARB_NR_MAX 3
84
85 /*
86 * MTK m4u support 4GB iova address space, and only support 4K page
87 * mapping. So the pagetable size should be exactly as 4M.
88 */
89 #define M2701_IOMMU_PGT_SIZE SZ_4M
90
91 struct mtk_iommu_domain {
92 spinlock_t pgtlock; /* lock for page table */
93 struct iommu_domain domain;
94 u32 *pgt_va;
95 dma_addr_t pgt_pa;
96 struct mtk_iommu_data *data;
97 };
98
to_mtk_domain(struct iommu_domain * dom)99 static struct mtk_iommu_domain *to_mtk_domain(struct iommu_domain *dom)
100 {
101 return container_of(dom, struct mtk_iommu_domain, domain);
102 }
103
104 static const int mt2701_m4u_in_larb[] = {
105 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
106 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
107 };
108
mt2701_m4u_to_larb(int id)109 static inline int mt2701_m4u_to_larb(int id)
110 {
111 int i;
112
113 for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--)
114 if ((id) >= mt2701_m4u_in_larb[i])
115 return i;
116
117 return 0;
118 }
119
mt2701_m4u_to_port(int id)120 static inline int mt2701_m4u_to_port(int id)
121 {
122 int larb = mt2701_m4u_to_larb(id);
123
124 return id - mt2701_m4u_in_larb[larb];
125 }
126
mtk_iommu_tlb_flush_all(struct mtk_iommu_data * data)127 static void mtk_iommu_tlb_flush_all(struct mtk_iommu_data *data)
128 {
129 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
130 data->base + REG_MMU_INV_SEL);
131 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
132 wmb(); /* Make sure the tlb flush all done */
133 }
134
mtk_iommu_tlb_flush_range(struct mtk_iommu_data * data,unsigned long iova,size_t size)135 static void mtk_iommu_tlb_flush_range(struct mtk_iommu_data *data,
136 unsigned long iova, size_t size)
137 {
138 int ret;
139 u32 tmp;
140
141 writel_relaxed(F_INVLD_EN1 | F_INVLD_EN0,
142 data->base + REG_MMU_INV_SEL);
143 writel_relaxed(iova & F_MMU_FAULT_VA_MSK,
144 data->base + REG_MMU_INVLD_START_A);
145 writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK,
146 data->base + REG_MMU_INVLD_END_A);
147 writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
148
149 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
150 tmp, tmp != 0, 10, 100000);
151 if (ret) {
152 dev_warn(data->dev,
153 "Partial TLB flush timed out, falling back to full flush\n");
154 mtk_iommu_tlb_flush_all(data);
155 }
156 /* Clear the CPE status */
157 writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
158 }
159
mtk_iommu_isr(int irq,void * dev_id)160 static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
161 {
162 struct mtk_iommu_data *data = dev_id;
163 struct mtk_iommu_domain *dom = data->m4u_dom;
164 u32 int_state, regval, fault_iova, fault_pa;
165 unsigned int fault_larb, fault_port;
166
167 /* Read error information from registers */
168 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST);
169 fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
170
171 fault_iova &= F_MMU_FAULT_VA_MSK;
172 fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
173 regval = readl_relaxed(data->base + REG_MMU_INT_ID);
174 fault_larb = MT2701_M4U_TF_LARB(regval);
175 fault_port = MT2701_M4U_TF_PORT(regval);
176
177 /*
178 * MTK v1 iommu HW could not determine whether the fault is read or
179 * write fault, report as read fault.
180 */
181 if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
182 IOMMU_FAULT_READ))
183 dev_err_ratelimited(data->dev,
184 "fault type=0x%x iova=0x%x pa=0x%x larb=%d port=%d\n",
185 int_state, fault_iova, fault_pa,
186 fault_larb, fault_port);
187
188 /* Interrupt clear */
189 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL);
190 regval |= F_INT_CLR_BIT;
191 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
192
193 mtk_iommu_tlb_flush_all(data);
194
195 return IRQ_HANDLED;
196 }
197
mtk_iommu_config(struct mtk_iommu_data * data,struct device * dev,bool enable)198 static void mtk_iommu_config(struct mtk_iommu_data *data,
199 struct device *dev, bool enable)
200 {
201 struct mtk_smi_larb_iommu *larb_mmu;
202 unsigned int larbid, portid;
203 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
204 int i;
205
206 for (i = 0; i < fwspec->num_ids; ++i) {
207 larbid = mt2701_m4u_to_larb(fwspec->ids[i]);
208 portid = mt2701_m4u_to_port(fwspec->ids[i]);
209 larb_mmu = &data->larb_imu[larbid];
210
211 dev_dbg(dev, "%s iommu port: %d\n",
212 enable ? "enable" : "disable", portid);
213
214 if (enable)
215 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid);
216 else
217 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid);
218 }
219 }
220
mtk_iommu_domain_finalise(struct mtk_iommu_data * data)221 static int mtk_iommu_domain_finalise(struct mtk_iommu_data *data)
222 {
223 struct mtk_iommu_domain *dom = data->m4u_dom;
224
225 spin_lock_init(&dom->pgtlock);
226
227 dom->pgt_va = dma_alloc_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
228 &dom->pgt_pa, GFP_KERNEL);
229 if (!dom->pgt_va)
230 return -ENOMEM;
231
232 writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR);
233
234 dom->data = data;
235
236 return 0;
237 }
238
mtk_iommu_domain_alloc(unsigned type)239 static struct iommu_domain *mtk_iommu_domain_alloc(unsigned type)
240 {
241 struct mtk_iommu_domain *dom;
242
243 if (type != IOMMU_DOMAIN_UNMANAGED)
244 return NULL;
245
246 dom = kzalloc(sizeof(*dom), GFP_KERNEL);
247 if (!dom)
248 return NULL;
249
250 return &dom->domain;
251 }
252
mtk_iommu_domain_free(struct iommu_domain * domain)253 static void mtk_iommu_domain_free(struct iommu_domain *domain)
254 {
255 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
256 struct mtk_iommu_data *data = dom->data;
257
258 dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
259 dom->pgt_va, dom->pgt_pa);
260 kfree(to_mtk_domain(domain));
261 }
262
mtk_iommu_attach_device(struct iommu_domain * domain,struct device * dev)263 static int mtk_iommu_attach_device(struct iommu_domain *domain,
264 struct device *dev)
265 {
266 struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
267 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
268 struct dma_iommu_mapping *mtk_mapping;
269 int ret;
270
271 /* Only allow the domain created internally. */
272 mtk_mapping = data->mapping;
273 if (mtk_mapping->domain != domain)
274 return 0;
275
276 if (!data->m4u_dom) {
277 data->m4u_dom = dom;
278 ret = mtk_iommu_domain_finalise(data);
279 if (ret) {
280 data->m4u_dom = NULL;
281 return ret;
282 }
283 }
284
285 mtk_iommu_config(data, dev, true);
286 return 0;
287 }
288
mtk_iommu_detach_device(struct iommu_domain * domain,struct device * dev)289 static void mtk_iommu_detach_device(struct iommu_domain *domain,
290 struct device *dev)
291 {
292 struct mtk_iommu_data *data = dev_iommu_priv_get(dev);
293
294 mtk_iommu_config(data, dev, false);
295 }
296
mtk_iommu_map(struct iommu_domain * domain,unsigned long iova,phys_addr_t paddr,size_t size,int prot,gfp_t gfp)297 static int mtk_iommu_map(struct iommu_domain *domain, unsigned long iova,
298 phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
299 {
300 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
301 unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT;
302 unsigned long flags;
303 unsigned int i;
304 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT);
305 u32 pabase = (u32)paddr;
306 int map_size = 0;
307
308 spin_lock_irqsave(&dom->pgtlock, flags);
309 for (i = 0; i < page_num; i++) {
310 if (pgt_base_iova[i]) {
311 memset(pgt_base_iova, 0, i * sizeof(u32));
312 break;
313 }
314 pgt_base_iova[i] = pabase | F_DESC_VALID | F_DESC_NONSEC;
315 pabase += MT2701_IOMMU_PAGE_SIZE;
316 map_size += MT2701_IOMMU_PAGE_SIZE;
317 }
318
319 spin_unlock_irqrestore(&dom->pgtlock, flags);
320
321 mtk_iommu_tlb_flush_range(dom->data, iova, size);
322
323 return map_size == size ? 0 : -EEXIST;
324 }
325
mtk_iommu_unmap(struct iommu_domain * domain,unsigned long iova,size_t size,struct iommu_iotlb_gather * gather)326 static size_t mtk_iommu_unmap(struct iommu_domain *domain,
327 unsigned long iova, size_t size,
328 struct iommu_iotlb_gather *gather)
329 {
330 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
331 unsigned long flags;
332 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT);
333 unsigned int page_num = size >> MT2701_IOMMU_PAGE_SHIFT;
334
335 spin_lock_irqsave(&dom->pgtlock, flags);
336 memset(pgt_base_iova, 0, page_num * sizeof(u32));
337 spin_unlock_irqrestore(&dom->pgtlock, flags);
338
339 mtk_iommu_tlb_flush_range(dom->data, iova, size);
340
341 return size;
342 }
343
mtk_iommu_iova_to_phys(struct iommu_domain * domain,dma_addr_t iova)344 static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
345 dma_addr_t iova)
346 {
347 struct mtk_iommu_domain *dom = to_mtk_domain(domain);
348 unsigned long flags;
349 phys_addr_t pa;
350
351 spin_lock_irqsave(&dom->pgtlock, flags);
352 pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT));
353 pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1));
354 spin_unlock_irqrestore(&dom->pgtlock, flags);
355
356 return pa;
357 }
358
359 static const struct iommu_ops mtk_iommu_ops;
360
361 /*
362 * MTK generation one iommu HW only support one iommu domain, and all the client
363 * sharing the same iova address space.
364 */
mtk_iommu_create_mapping(struct device * dev,struct of_phandle_args * args)365 static int mtk_iommu_create_mapping(struct device *dev,
366 struct of_phandle_args *args)
367 {
368 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
369 struct mtk_iommu_data *data;
370 struct platform_device *m4updev;
371 struct dma_iommu_mapping *mtk_mapping;
372 int ret;
373
374 if (args->args_count != 1) {
375 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n",
376 args->args_count);
377 return -EINVAL;
378 }
379
380 if (!fwspec) {
381 ret = iommu_fwspec_init(dev, &args->np->fwnode, &mtk_iommu_ops);
382 if (ret)
383 return ret;
384 fwspec = dev_iommu_fwspec_get(dev);
385 } else if (dev_iommu_fwspec_get(dev)->ops != &mtk_iommu_ops) {
386 return -EINVAL;
387 }
388
389 if (!dev_iommu_priv_get(dev)) {
390 /* Get the m4u device */
391 m4updev = of_find_device_by_node(args->np);
392 if (WARN_ON(!m4updev))
393 return -EINVAL;
394
395 dev_iommu_priv_set(dev, platform_get_drvdata(m4updev));
396 }
397
398 ret = iommu_fwspec_add_ids(dev, args->args, 1);
399 if (ret)
400 return ret;
401
402 data = dev_iommu_priv_get(dev);
403 mtk_mapping = data->mapping;
404 if (!mtk_mapping) {
405 /* MTK iommu support 4GB iova address space. */
406 mtk_mapping = arm_iommu_create_mapping(&platform_bus_type,
407 0, 1ULL << 32);
408 if (IS_ERR(mtk_mapping))
409 return PTR_ERR(mtk_mapping);
410
411 data->mapping = mtk_mapping;
412 }
413
414 return 0;
415 }
416
mtk_iommu_def_domain_type(struct device * dev)417 static int mtk_iommu_def_domain_type(struct device *dev)
418 {
419 return IOMMU_DOMAIN_UNMANAGED;
420 }
421
mtk_iommu_probe_device(struct device * dev)422 static struct iommu_device *mtk_iommu_probe_device(struct device *dev)
423 {
424 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
425 struct of_phandle_args iommu_spec;
426 struct mtk_iommu_data *data;
427 int err, idx = 0, larbid, larbidx;
428 struct device_link *link;
429 struct device *larbdev;
430
431 /*
432 * In the deferred case, free the existed fwspec.
433 * Always initialize the fwspec internally.
434 */
435 if (fwspec) {
436 iommu_fwspec_free(dev);
437 fwspec = dev_iommu_fwspec_get(dev);
438 }
439
440 while (!of_parse_phandle_with_args(dev->of_node, "iommus",
441 "#iommu-cells",
442 idx, &iommu_spec)) {
443
444 err = mtk_iommu_create_mapping(dev, &iommu_spec);
445 of_node_put(iommu_spec.np);
446 if (err)
447 return ERR_PTR(err);
448
449 /* dev->iommu_fwspec might have changed */
450 fwspec = dev_iommu_fwspec_get(dev);
451 idx++;
452 }
453
454 if (!fwspec || fwspec->ops != &mtk_iommu_ops)
455 return ERR_PTR(-ENODEV); /* Not a iommu client device */
456
457 data = dev_iommu_priv_get(dev);
458
459 /* Link the consumer device with the smi-larb device(supplier) */
460 larbid = mt2701_m4u_to_larb(fwspec->ids[0]);
461 if (larbid >= MT2701_LARB_NR_MAX)
462 return ERR_PTR(-EINVAL);
463
464 for (idx = 1; idx < fwspec->num_ids; idx++) {
465 larbidx = mt2701_m4u_to_larb(fwspec->ids[idx]);
466 if (larbid != larbidx) {
467 dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n",
468 larbid, larbidx);
469 return ERR_PTR(-EINVAL);
470 }
471 }
472
473 larbdev = data->larb_imu[larbid].dev;
474 if (!larbdev)
475 return ERR_PTR(-EINVAL);
476
477 link = device_link_add(dev, larbdev,
478 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
479 if (!link)
480 dev_err(dev, "Unable to link %s\n", dev_name(larbdev));
481
482 return &data->iommu;
483 }
484
mtk_iommu_probe_finalize(struct device * dev)485 static void mtk_iommu_probe_finalize(struct device *dev)
486 {
487 struct dma_iommu_mapping *mtk_mapping;
488 struct mtk_iommu_data *data;
489 int err;
490
491 data = dev_iommu_priv_get(dev);
492 mtk_mapping = data->mapping;
493
494 err = arm_iommu_attach_device(dev, mtk_mapping);
495 if (err)
496 dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n");
497 }
498
mtk_iommu_release_device(struct device * dev)499 static void mtk_iommu_release_device(struct device *dev)
500 {
501 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
502 struct mtk_iommu_data *data;
503 struct device *larbdev;
504 unsigned int larbid;
505
506 if (!fwspec || fwspec->ops != &mtk_iommu_ops)
507 return;
508
509 data = dev_iommu_priv_get(dev);
510 larbid = mt2701_m4u_to_larb(fwspec->ids[0]);
511 larbdev = data->larb_imu[larbid].dev;
512 device_link_remove(dev, larbdev);
513
514 iommu_fwspec_free(dev);
515 }
516
mtk_iommu_hw_init(const struct mtk_iommu_data * data)517 static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
518 {
519 u32 regval;
520 int ret;
521
522 ret = clk_prepare_enable(data->bclk);
523 if (ret) {
524 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret);
525 return ret;
526 }
527
528 regval = F_MMU_CTRL_COHERENT_EN | F_MMU_TF_PROTECT_SEL(2);
529 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
530
531 regval = F_INT_TRANSLATION_FAULT |
532 F_INT_MAIN_MULTI_HIT_FAULT |
533 F_INT_INVALID_PA_FAULT |
534 F_INT_ENTRY_REPLACEMENT_FAULT |
535 F_INT_TABLE_WALK_FAULT |
536 F_INT_TLB_MISS_FAULT |
537 F_INT_PFH_DMA_FIFO_OVERFLOW |
538 F_INT_MISS_DMA_FIFO_OVERFLOW;
539 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
540
541 /* protect memory,hw will write here while translation fault */
542 writel_relaxed(data->protect_base,
543 data->base + REG_MMU_IVRP_PADDR);
544
545 writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM);
546
547 if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
548 dev_name(data->dev), (void *)data)) {
549 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
550 clk_disable_unprepare(data->bclk);
551 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
552 return -ENODEV;
553 }
554
555 return 0;
556 }
557
558 static const struct iommu_ops mtk_iommu_ops = {
559 .domain_alloc = mtk_iommu_domain_alloc,
560 .domain_free = mtk_iommu_domain_free,
561 .attach_dev = mtk_iommu_attach_device,
562 .detach_dev = mtk_iommu_detach_device,
563 .map = mtk_iommu_map,
564 .unmap = mtk_iommu_unmap,
565 .iova_to_phys = mtk_iommu_iova_to_phys,
566 .probe_device = mtk_iommu_probe_device,
567 .probe_finalize = mtk_iommu_probe_finalize,
568 .release_device = mtk_iommu_release_device,
569 .def_domain_type = mtk_iommu_def_domain_type,
570 .device_group = generic_device_group,
571 .pgsize_bitmap = ~0UL << MT2701_IOMMU_PAGE_SHIFT,
572 .owner = THIS_MODULE,
573 };
574
575 static const struct of_device_id mtk_iommu_of_ids[] = {
576 { .compatible = "mediatek,mt2701-m4u", },
577 {}
578 };
579
580 static const struct component_master_ops mtk_iommu_com_ops = {
581 .bind = mtk_iommu_bind,
582 .unbind = mtk_iommu_unbind,
583 };
584
mtk_iommu_probe(struct platform_device * pdev)585 static int mtk_iommu_probe(struct platform_device *pdev)
586 {
587 struct mtk_iommu_data *data;
588 struct device *dev = &pdev->dev;
589 struct resource *res;
590 struct component_match *match = NULL;
591 void *protect;
592 int larb_nr, ret, i;
593
594 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
595 if (!data)
596 return -ENOMEM;
597
598 data->dev = dev;
599
600 /* Protect memory. HW will access here while translation fault.*/
601 protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2,
602 GFP_KERNEL | GFP_DMA);
603 if (!protect)
604 return -ENOMEM;
605 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
606
607 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
608 data->base = devm_ioremap_resource(dev, res);
609 if (IS_ERR(data->base))
610 return PTR_ERR(data->base);
611
612 data->irq = platform_get_irq(pdev, 0);
613 if (data->irq < 0)
614 return data->irq;
615
616 data->bclk = devm_clk_get(dev, "bclk");
617 if (IS_ERR(data->bclk))
618 return PTR_ERR(data->bclk);
619
620 larb_nr = of_count_phandle_with_args(dev->of_node,
621 "mediatek,larbs", NULL);
622 if (larb_nr < 0)
623 return larb_nr;
624
625 for (i = 0; i < larb_nr; i++) {
626 struct device_node *larbnode;
627 struct platform_device *plarbdev;
628
629 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i);
630 if (!larbnode)
631 return -EINVAL;
632
633 if (!of_device_is_available(larbnode)) {
634 of_node_put(larbnode);
635 continue;
636 }
637
638 plarbdev = of_find_device_by_node(larbnode);
639 if (!plarbdev) {
640 of_node_put(larbnode);
641 return -ENODEV;
642 }
643 data->larb_imu[i].dev = &plarbdev->dev;
644
645 component_match_add_release(dev, &match, release_of,
646 compare_of, larbnode);
647 }
648
649 platform_set_drvdata(pdev, data);
650
651 ret = mtk_iommu_hw_init(data);
652 if (ret)
653 return ret;
654
655 ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL,
656 dev_name(&pdev->dev));
657 if (ret)
658 goto out_clk_unprepare;
659
660 ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev);
661 if (ret)
662 goto out_sysfs_remove;
663
664 if (!iommu_present(&platform_bus_type)) {
665 ret = bus_set_iommu(&platform_bus_type, &mtk_iommu_ops);
666 if (ret)
667 goto out_dev_unreg;
668 }
669
670 ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match);
671 if (ret)
672 goto out_bus_set_null;
673 return ret;
674
675 out_bus_set_null:
676 bus_set_iommu(&platform_bus_type, NULL);
677 out_dev_unreg:
678 iommu_device_unregister(&data->iommu);
679 out_sysfs_remove:
680 iommu_device_sysfs_remove(&data->iommu);
681 out_clk_unprepare:
682 clk_disable_unprepare(data->bclk);
683 return ret;
684 }
685
mtk_iommu_remove(struct platform_device * pdev)686 static int mtk_iommu_remove(struct platform_device *pdev)
687 {
688 struct mtk_iommu_data *data = platform_get_drvdata(pdev);
689
690 iommu_device_sysfs_remove(&data->iommu);
691 iommu_device_unregister(&data->iommu);
692
693 if (iommu_present(&platform_bus_type))
694 bus_set_iommu(&platform_bus_type, NULL);
695
696 clk_disable_unprepare(data->bclk);
697 devm_free_irq(&pdev->dev, data->irq, data);
698 component_master_del(&pdev->dev, &mtk_iommu_com_ops);
699 return 0;
700 }
701
mtk_iommu_suspend(struct device * dev)702 static int __maybe_unused mtk_iommu_suspend(struct device *dev)
703 {
704 struct mtk_iommu_data *data = dev_get_drvdata(dev);
705 struct mtk_iommu_suspend_reg *reg = &data->reg;
706 void __iomem *base = data->base;
707
708 reg->standard_axi_mode = readl_relaxed(base +
709 REG_MMU_STANDARD_AXI_MODE);
710 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM);
711 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG);
712 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL);
713 return 0;
714 }
715
mtk_iommu_resume(struct device * dev)716 static int __maybe_unused mtk_iommu_resume(struct device *dev)
717 {
718 struct mtk_iommu_data *data = dev_get_drvdata(dev);
719 struct mtk_iommu_suspend_reg *reg = &data->reg;
720 void __iomem *base = data->base;
721
722 writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR);
723 writel_relaxed(reg->standard_axi_mode,
724 base + REG_MMU_STANDARD_AXI_MODE);
725 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM);
726 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
727 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL);
728 writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR);
729 return 0;
730 }
731
732 static const struct dev_pm_ops mtk_iommu_pm_ops = {
733 SET_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
734 };
735
736 static struct platform_driver mtk_iommu_driver = {
737 .probe = mtk_iommu_probe,
738 .remove = mtk_iommu_remove,
739 .driver = {
740 .name = "mtk-iommu-v1",
741 .of_match_table = mtk_iommu_of_ids,
742 .pm = &mtk_iommu_pm_ops,
743 }
744 };
745 module_platform_driver(mtk_iommu_driver);
746
747 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U v1 implementations");
748 MODULE_LICENSE("GPL v2");
749