1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/clock/qcom,gcc-ipq4019.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 model = "Qualcomm Technologies, Inc. IPQ4019"; 17 compatible = "qcom,ipq4019"; 18 interrupt-parent = <&intc>; 19 20 reserved-memory { 21 #address-cells = <0x1>; 22 #size-cells = <0x1>; 23 ranges; 24 25 smem_region: smem@87e00000 { 26 reg = <0x87e00000 0x080000>; 27 no-map; 28 }; 29 30 tz@87e80000 { 31 reg = <0x87e80000 0x180000>; 32 no-map; 33 }; 34 }; 35 36 aliases { 37 spi0 = &blsp1_spi1; 38 spi1 = &blsp1_spi2; 39 i2c0 = &blsp1_i2c3; 40 i2c1 = &blsp1_i2c4; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 enable-method = "qcom,kpss-acc-v2"; 50 next-level-cache = <&L2>; 51 qcom,acc = <&acc0>; 52 qcom,saw = <&saw0>; 53 reg = <0x0>; 54 clocks = <&gcc GCC_APPS_CLK_SRC>; 55 clock-frequency = <0>; 56 clock-latency = <256000>; 57 operating-points-v2 = <&cpu0_opp_table>; 58 }; 59 60 cpu@1 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a7"; 63 enable-method = "qcom,kpss-acc-v2"; 64 next-level-cache = <&L2>; 65 qcom,acc = <&acc1>; 66 qcom,saw = <&saw1>; 67 reg = <0x1>; 68 clocks = <&gcc GCC_APPS_CLK_SRC>; 69 clock-frequency = <0>; 70 clock-latency = <256000>; 71 operating-points-v2 = <&cpu0_opp_table>; 72 }; 73 74 cpu@2 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a7"; 77 enable-method = "qcom,kpss-acc-v2"; 78 next-level-cache = <&L2>; 79 qcom,acc = <&acc2>; 80 qcom,saw = <&saw2>; 81 reg = <0x2>; 82 clocks = <&gcc GCC_APPS_CLK_SRC>; 83 clock-frequency = <0>; 84 clock-latency = <256000>; 85 operating-points-v2 = <&cpu0_opp_table>; 86 }; 87 88 cpu@3 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a7"; 91 enable-method = "qcom,kpss-acc-v2"; 92 next-level-cache = <&L2>; 93 qcom,acc = <&acc3>; 94 qcom,saw = <&saw3>; 95 reg = <0x3>; 96 clocks = <&gcc GCC_APPS_CLK_SRC>; 97 clock-frequency = <0>; 98 clock-latency = <256000>; 99 operating-points-v2 = <&cpu0_opp_table>; 100 }; 101 102 L2: l2-cache { 103 compatible = "cache"; 104 cache-level = <2>; 105 qcom,saw = <&saw_l2>; 106 }; 107 }; 108 109 cpu0_opp_table: opp_table0 { 110 compatible = "operating-points-v2"; 111 opp-shared; 112 113 opp-48000000 { 114 opp-hz = /bits/ 64 <48000000>; 115 clock-latency-ns = <256000>; 116 }; 117 opp-200000000 { 118 opp-hz = /bits/ 64 <200000000>; 119 clock-latency-ns = <256000>; 120 }; 121 opp-500000000 { 122 opp-hz = /bits/ 64 <500000000>; 123 clock-latency-ns = <256000>; 124 }; 125 opp-716000000 { 126 opp-hz = /bits/ 64 <716000000>; 127 clock-latency-ns = <256000>; 128 }; 129 }; 130 131 memory { 132 device_type = "memory"; 133 reg = <0x0 0x0>; 134 }; 135 136 pmu { 137 compatible = "arm,cortex-a7-pmu"; 138 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 139 IRQ_TYPE_LEVEL_HIGH)>; 140 }; 141 142 clocks { 143 sleep_clk: sleep_clk { 144 compatible = "fixed-clock"; 145 clock-frequency = <32000>; 146 clock-output-names = "gcc_sleep_clk_src"; 147 #clock-cells = <0>; 148 }; 149 150 xo: xo { 151 compatible = "fixed-clock"; 152 clock-frequency = <48000000>; 153 #clock-cells = <0>; 154 }; 155 }; 156 157 firmware { 158 scm { 159 compatible = "qcom,scm-ipq4019"; 160 }; 161 }; 162 163 timer { 164 compatible = "arm,armv7-timer"; 165 interrupts = <1 2 0xf08>, 166 <1 3 0xf08>, 167 <1 4 0xf08>, 168 <1 1 0xf08>; 169 clock-frequency = <48000000>; 170 always-on; 171 }; 172 173 soc { 174 #address-cells = <1>; 175 #size-cells = <1>; 176 ranges; 177 compatible = "simple-bus"; 178 179 intc: interrupt-controller@b000000 { 180 compatible = "qcom,msm-qgic2"; 181 interrupt-controller; 182 #interrupt-cells = <3>; 183 reg = <0x0b000000 0x1000>, 184 <0x0b002000 0x1000>; 185 }; 186 187 gcc: clock-controller@1800000 { 188 compatible = "qcom,gcc-ipq4019"; 189 #clock-cells = <1>; 190 #reset-cells = <1>; 191 reg = <0x1800000 0x60000>; 192 }; 193 194 prng: rng@22000 { 195 compatible = "qcom,prng"; 196 reg = <0x22000 0x140>; 197 clocks = <&gcc GCC_PRNG_AHB_CLK>; 198 clock-names = "core"; 199 status = "disabled"; 200 }; 201 202 tlmm: pinctrl@1000000 { 203 compatible = "qcom,ipq4019-pinctrl"; 204 reg = <0x01000000 0x300000>; 205 gpio-controller; 206 gpio-ranges = <&tlmm 0 0 100>; 207 #gpio-cells = <2>; 208 interrupt-controller; 209 #interrupt-cells = <2>; 210 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 211 }; 212 213 vqmmc: regulator@1948000 { 214 compatible = "qcom,vqmmc-ipq4019-regulator"; 215 reg = <0x01948000 0x4>; 216 regulator-name = "vqmmc"; 217 regulator-min-microvolt = <1500000>; 218 regulator-max-microvolt = <3000000>; 219 regulator-always-on; 220 status = "disabled"; 221 }; 222 223 sdhci: sdhci@7824900 { 224 compatible = "qcom,sdhci-msm-v4"; 225 reg = <0x7824900 0x11c>, <0x7824000 0x800>; 226 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 227 interrupt-names = "hc_irq", "pwr_irq"; 228 bus-width = <8>; 229 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, 230 <&gcc GCC_DCD_XO_CLK>; 231 clock-names = "core", "iface", "xo"; 232 status = "disabled"; 233 }; 234 235 blsp_dma: dma@7884000 { 236 compatible = "qcom,bam-v1.7.0"; 237 reg = <0x07884000 0x23000>; 238 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 240 clock-names = "bam_clk"; 241 #dma-cells = <1>; 242 qcom,ee = <0>; 243 status = "disabled"; 244 }; 245 246 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */ 247 compatible = "qcom,spi-qup-v2.2.1"; 248 reg = <0x78b5000 0x600>; 249 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 251 <&gcc GCC_BLSP1_AHB_CLK>; 252 clock-names = "core", "iface"; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 dmas = <&blsp_dma 5>, <&blsp_dma 4>; 256 dma-names = "rx", "tx"; 257 status = "disabled"; 258 }; 259 260 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */ 261 compatible = "qcom,spi-qup-v2.2.1"; 262 reg = <0x78b6000 0x600>; 263 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 265 <&gcc GCC_BLSP1_AHB_CLK>; 266 clock-names = "core", "iface"; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 dmas = <&blsp_dma 7>, <&blsp_dma 6>; 270 dma-names = "rx", "tx"; 271 status = "disabled"; 272 }; 273 274 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */ 275 compatible = "qcom,i2c-qup-v2.2.1"; 276 reg = <0x78b7000 0x600>; 277 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 279 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; 280 clock-names = "iface", "core"; 281 #address-cells = <1>; 282 #size-cells = <0>; 283 dmas = <&blsp_dma 9>, <&blsp_dma 8>; 284 dma-names = "rx", "tx"; 285 status = "disabled"; 286 }; 287 288 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */ 289 compatible = "qcom,i2c-qup-v2.2.1"; 290 reg = <0x78b8000 0x600>; 291 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 293 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 294 clock-names = "iface", "core"; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 dmas = <&blsp_dma 11>, <&blsp_dma 10>; 298 dma-names = "rx", "tx"; 299 status = "disabled"; 300 }; 301 302 cryptobam: dma@8e04000 { 303 compatible = "qcom,bam-v1.7.0"; 304 reg = <0x08e04000 0x20000>; 305 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 307 clock-names = "bam_clk"; 308 #dma-cells = <1>; 309 qcom,ee = <1>; 310 qcom,controlled-remotely; 311 status = "disabled"; 312 }; 313 314 crypto: crypto@8e3a000 { 315 compatible = "qcom,crypto-v5.1"; 316 reg = <0x08e3a000 0x6000>; 317 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 318 <&gcc GCC_CRYPTO_AXI_CLK>, 319 <&gcc GCC_CRYPTO_CLK>; 320 clock-names = "iface", "bus", "core"; 321 dmas = <&cryptobam 2>, <&cryptobam 3>; 322 dma-names = "rx", "tx"; 323 status = "disabled"; 324 }; 325 326 acc0: clock-controller@b088000 { 327 compatible = "qcom,kpss-acc-v2"; 328 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; 329 }; 330 331 acc1: clock-controller@b098000 { 332 compatible = "qcom,kpss-acc-v2"; 333 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; 334 }; 335 336 acc2: clock-controller@b0a8000 { 337 compatible = "qcom,kpss-acc-v2"; 338 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; 339 }; 340 341 acc3: clock-controller@b0b8000 { 342 compatible = "qcom,kpss-acc-v2"; 343 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; 344 }; 345 346 saw0: regulator@b089000 { 347 compatible = "qcom,saw2"; 348 reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; 349 regulator; 350 }; 351 352 saw1: regulator@b099000 { 353 compatible = "qcom,saw2"; 354 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; 355 regulator; 356 }; 357 358 saw2: regulator@b0a9000 { 359 compatible = "qcom,saw2"; 360 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; 361 regulator; 362 }; 363 364 saw3: regulator@b0b9000 { 365 compatible = "qcom,saw2"; 366 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; 367 regulator; 368 }; 369 370 saw_l2: regulator@b012000 { 371 compatible = "qcom,saw2"; 372 reg = <0xb012000 0x1000>; 373 regulator; 374 }; 375 376 blsp1_uart1: serial@78af000 { 377 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 378 reg = <0x78af000 0x200>; 379 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 380 status = "disabled"; 381 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 382 <&gcc GCC_BLSP1_AHB_CLK>; 383 clock-names = "core", "iface"; 384 dmas = <&blsp_dma 1>, <&blsp_dma 0>; 385 dma-names = "rx", "tx"; 386 }; 387 388 blsp1_uart2: serial@78b0000 { 389 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 390 reg = <0x78b0000 0x200>; 391 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 392 status = "disabled"; 393 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 394 <&gcc GCC_BLSP1_AHB_CLK>; 395 clock-names = "core", "iface"; 396 dmas = <&blsp_dma 3>, <&blsp_dma 2>; 397 dma-names = "rx", "tx"; 398 }; 399 400 watchdog: watchdog@b017000 { 401 compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019"; 402 reg = <0xb017000 0x40>; 403 clocks = <&sleep_clk>; 404 timeout-sec = <10>; 405 status = "disabled"; 406 }; 407 408 restart@4ab000 { 409 compatible = "qcom,pshold"; 410 reg = <0x4ab000 0x4>; 411 }; 412 413 pcie0: pci@40000000 { 414 compatible = "qcom,pcie-ipq4019", "snps,dw-pcie"; 415 reg = <0x40000000 0xf1d 416 0x40000f20 0xa8 417 0x80000 0x2000 418 0x40100000 0x1000>; 419 reg-names = "dbi", "elbi", "parf", "config"; 420 device_type = "pci"; 421 linux,pci-domain = <0>; 422 bus-range = <0x00 0xff>; 423 num-lanes = <1>; 424 #address-cells = <3>; 425 #size-cells = <2>; 426 427 ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>, 428 <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>; 429 430 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 431 interrupt-names = "msi"; 432 #interrupt-cells = <1>; 433 interrupt-map-mask = <0 0 0 0x7>; 434 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 435 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 436 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 437 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 438 clocks = <&gcc GCC_PCIE_AHB_CLK>, 439 <&gcc GCC_PCIE_AXI_M_CLK>, 440 <&gcc GCC_PCIE_AXI_S_CLK>; 441 clock-names = "aux", 442 "master_bus", 443 "slave_bus"; 444 445 resets = <&gcc PCIE_AXI_M_ARES>, 446 <&gcc PCIE_AXI_S_ARES>, 447 <&gcc PCIE_PIPE_ARES>, 448 <&gcc PCIE_AXI_M_VMIDMT_ARES>, 449 <&gcc PCIE_AXI_S_XPU_ARES>, 450 <&gcc PCIE_PARF_XPU_ARES>, 451 <&gcc PCIE_PHY_ARES>, 452 <&gcc PCIE_AXI_M_STICKY_ARES>, 453 <&gcc PCIE_PIPE_STICKY_ARES>, 454 <&gcc PCIE_PWR_ARES>, 455 <&gcc PCIE_AHB_ARES>, 456 <&gcc PCIE_PHY_AHB_ARES>; 457 reset-names = "axi_m", 458 "axi_s", 459 "pipe", 460 "axi_m_vmid", 461 "axi_s_xpu", 462 "parf", 463 "phy", 464 "axi_m_sticky", 465 "pipe_sticky", 466 "pwr", 467 "ahb", 468 "phy_ahb"; 469 470 status = "disabled"; 471 }; 472 473 qpic_bam: dma@7984000 { 474 compatible = "qcom,bam-v1.7.0"; 475 reg = <0x7984000 0x1a000>; 476 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&gcc GCC_QPIC_CLK>; 478 clock-names = "bam_clk"; 479 #dma-cells = <1>; 480 qcom,ee = <0>; 481 status = "disabled"; 482 }; 483 484 nand: nand-controller@79b0000 { 485 compatible = "qcom,ipq4019-nand"; 486 reg = <0x79b0000 0x1000>; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 clocks = <&gcc GCC_QPIC_CLK>, 490 <&gcc GCC_QPIC_AHB_CLK>; 491 clock-names = "core", "aon"; 492 493 dmas = <&qpic_bam 0>, 494 <&qpic_bam 1>, 495 <&qpic_bam 2>; 496 dma-names = "tx", "rx", "cmd"; 497 status = "disabled"; 498 499 nand@0 { 500 reg = <0>; 501 502 nand-ecc-strength = <4>; 503 nand-ecc-step-size = <512>; 504 nand-bus-width = <8>; 505 }; 506 }; 507 508 wifi0: wifi@a000000 { 509 compatible = "qcom,ipq4019-wifi"; 510 reg = <0xa000000 0x200000>; 511 resets = <&gcc WIFI0_CPU_INIT_RESET>, 512 <&gcc WIFI0_RADIO_SRIF_RESET>, 513 <&gcc WIFI0_RADIO_WARM_RESET>, 514 <&gcc WIFI0_RADIO_COLD_RESET>, 515 <&gcc WIFI0_CORE_WARM_RESET>, 516 <&gcc WIFI0_CORE_COLD_RESET>; 517 reset-names = "wifi_cpu_init", "wifi_radio_srif", 518 "wifi_radio_warm", "wifi_radio_cold", 519 "wifi_core_warm", "wifi_core_cold"; 520 clocks = <&gcc GCC_WCSS2G_CLK>, 521 <&gcc GCC_WCSS2G_REF_CLK>, 522 <&gcc GCC_WCSS2G_RTC_CLK>; 523 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", 524 "wifi_wcss_rtc"; 525 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 526 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 527 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 528 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 529 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 530 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 531 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 532 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 533 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>, 534 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 535 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 536 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 537 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 538 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 539 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 540 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 541 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 542 interrupt-names = "msi0", "msi1", "msi2", "msi3", 543 "msi4", "msi5", "msi6", "msi7", 544 "msi8", "msi9", "msi10", "msi11", 545 "msi12", "msi13", "msi14", "msi15", 546 "legacy"; 547 status = "disabled"; 548 }; 549 550 wifi1: wifi@a800000 { 551 compatible = "qcom,ipq4019-wifi"; 552 reg = <0xa800000 0x200000>; 553 resets = <&gcc WIFI1_CPU_INIT_RESET>, 554 <&gcc WIFI1_RADIO_SRIF_RESET>, 555 <&gcc WIFI1_RADIO_WARM_RESET>, 556 <&gcc WIFI1_RADIO_COLD_RESET>, 557 <&gcc WIFI1_CORE_WARM_RESET>, 558 <&gcc WIFI1_CORE_COLD_RESET>; 559 reset-names = "wifi_cpu_init", "wifi_radio_srif", 560 "wifi_radio_warm", "wifi_radio_cold", 561 "wifi_core_warm", "wifi_core_cold"; 562 clocks = <&gcc GCC_WCSS5G_CLK>, 563 <&gcc GCC_WCSS5G_REF_CLK>, 564 <&gcc GCC_WCSS5G_RTC_CLK>; 565 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref", 566 "wifi_wcss_rtc"; 567 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 568 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 569 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 570 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 571 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 572 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 573 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 574 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 575 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>, 576 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 577 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 578 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 579 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 580 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 581 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 582 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 583 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 584 interrupt-names = "msi0", "msi1", "msi2", "msi3", 585 "msi4", "msi5", "msi6", "msi7", 586 "msi8", "msi9", "msi10", "msi11", 587 "msi12", "msi13", "msi14", "msi15", 588 "legacy"; 589 status = "disabled"; 590 }; 591 592 mdio: mdio@90000 { 593 #address-cells = <1>; 594 #size-cells = <0>; 595 compatible = "qcom,ipq4019-mdio"; 596 reg = <0x90000 0x64>; 597 status = "disabled"; 598 599 ethphy0: ethernet-phy@0 { 600 reg = <0>; 601 }; 602 603 ethphy1: ethernet-phy@1 { 604 reg = <1>; 605 }; 606 607 ethphy2: ethernet-phy@2 { 608 reg = <2>; 609 }; 610 611 ethphy3: ethernet-phy@3 { 612 reg = <3>; 613 }; 614 615 ethphy4: ethernet-phy@4 { 616 reg = <4>; 617 }; 618 }; 619 620 usb3_ss_phy: ssphy@9a000 { 621 compatible = "qcom,usb-ss-ipq4019-phy"; 622 #phy-cells = <0>; 623 reg = <0x9a000 0x800>; 624 reg-names = "phy_base"; 625 resets = <&gcc USB3_UNIPHY_PHY_ARES>; 626 reset-names = "por_rst"; 627 status = "disabled"; 628 }; 629 630 usb3_hs_phy: hsphy@a6000 { 631 compatible = "qcom,usb-hs-ipq4019-phy"; 632 #phy-cells = <0>; 633 reg = <0xa6000 0x40>; 634 reg-names = "phy_base"; 635 resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; 636 reset-names = "por_rst", "srif_rst"; 637 status = "disabled"; 638 }; 639 640 usb3: usb3@8af8800 { 641 compatible = "qcom,dwc3"; 642 reg = <0x8af8800 0x100>; 643 #address-cells = <1>; 644 #size-cells = <1>; 645 clocks = <&gcc GCC_USB3_MASTER_CLK>, 646 <&gcc GCC_USB3_SLEEP_CLK>, 647 <&gcc GCC_USB3_MOCK_UTMI_CLK>; 648 clock-names = "master", "sleep", "mock_utmi"; 649 ranges; 650 status = "disabled"; 651 652 dwc3@8a00000 { 653 compatible = "snps,dwc3"; 654 reg = <0x8a00000 0xf8000>; 655 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 656 phys = <&usb3_hs_phy>, <&usb3_ss_phy>; 657 phy-names = "usb2-phy", "usb3-phy"; 658 dr_mode = "host"; 659 }; 660 }; 661 662 usb2_hs_phy: hsphy@a8000 { 663 compatible = "qcom,usb-hs-ipq4019-phy"; 664 #phy-cells = <0>; 665 reg = <0xa8000 0x40>; 666 reg-names = "phy_base"; 667 resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; 668 reset-names = "por_rst", "srif_rst"; 669 status = "disabled"; 670 }; 671 672 usb2: usb2@60f8800 { 673 compatible = "qcom,dwc3"; 674 reg = <0x60f8800 0x100>; 675 #address-cells = <1>; 676 #size-cells = <1>; 677 clocks = <&gcc GCC_USB2_MASTER_CLK>, 678 <&gcc GCC_USB2_SLEEP_CLK>, 679 <&gcc GCC_USB2_MOCK_UTMI_CLK>; 680 clock-names = "master", "sleep", "mock_utmi"; 681 ranges; 682 status = "disabled"; 683 684 dwc3@6000000 { 685 compatible = "snps,dwc3"; 686 reg = <0x6000000 0xf8000>; 687 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 688 phys = <&usb2_hs_phy>; 689 phy-names = "usb2-phy"; 690 dr_mode = "host"; 691 }; 692 }; 693 }; 694}; 695