| /arch/mips/cavium-octeon/ |
| D | octeon-memcpy.S | 90 #define ADD daddu macro
203 ADD src, src, 16*NBYTES
205 ADD dst, dst, 16*NBYTES
252 ADD src, src, 8*NBYTES
254 ADD dst, dst, 8*NBYTES
271 ADD src, src, 4*NBYTES
273 ADD dst, dst, 4*NBYTES
289 ADD src, src, NBYTES
291 ADD dst, dst, NBYTES
299 ADD src, src, NBYTES
[all …]
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| /arch/mips/lib/ |
| D | memcpy.S | 155 #define ADD daddu macro
192 #define ADD addu macro
336 ADD src, src, 8*NBYTES
337 ADD dst, dst, 8*NBYTES
365 ADD src, src, 4*NBYTES
372 ADD dst, dst, 4*NBYTES
384 ADD src, src, NBYTES
388 ADD dst, dst, NBYTES
406 ADD t1, dst, len # t1 is just past last byte of dst
427 ADD t2, zero, NBYTES
[all …]
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| D | csum_partial.S | 45 #define ADD daddu macro
52 #define ADD addu macro
62 ADD sum, reg; \
64 ADD sum, v1; \
380 #define ADD daddu macro
400 #define ADD addu macro
481 ADD src, src, 8*NBYTES
499 ADD dst, dst, 8*NBYTES
502 ADD len, 8*NBYTES # revert len (see above)
521 ADD src, src, 4*NBYTES
[all …]
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| /arch/arm/kernel/ |
| D | phys2virt.S | 155 @ In the non-LPAE case, all patchable instructions are ADD or SUB
163 @ ADD | cond | 0 0 1 0 1 0 0 0 | Rn | Rd | imm12 |
173 @ instructions based on bits 23:22 of the opcode, and ADD/SUB can be
189 tst ip, #PV_BIT24 @ ADD/SUB have bit 24 clear
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| /arch/sparc/net/ |
| D | bpf_jit_comp_32.c | 73 #define ADD F3(2, 0x00) macro
280 *prog++ = (ADD | RS1(R1) | RS2(R2) | RD(R3))
283 *prog++ = (ADD | IMMED | RS1(R1) | S13(IMM) | RD(R3))
295 *prog++ = (ADD | IMMED | RS1(SP) | S13(SZ) | RD(SP))
400 emit_alu_X(ADD); in bpf_jit_compile()
403 emit_alu_K(ADD, K); in bpf_jit_compile()
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| D | bpf_jit_comp_64.c | 141 #define ADD F3(2, 0x00) macro
826 emit(ADD | IMMED | RS1(FP) | S13(STACK_BIAS) | RD(vfp), ctx); in build_prologue()
873 emit_alu_K(ADD, tmp, 1, ctx); in emit_tail_call()
878 emit_alu(ADD, bpf_array, tmp, ctx); in emit_tail_call()
920 emit_alu(ADD, src, dst, ctx); in build_insn()
1056 emit_alu3_K(ADD, SP, STACK_BIAS + 128, tmp, ctx); in build_insn()
1075 emit_alu_K(ADD, dst, imm, ctx); in build_insn()
1391 emit_alu3(ADD, dst, tmp, tmp, ctx); in build_insn()
1394 emit_alu3(ADD, tmp2, src, tmp3, ctx); in build_insn()
1419 emit_alu3(ADD, dst, tmp, tmp, ctx); in build_insn()
[all …]
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| /arch/arm64/net/ |
| D | bpf_jit.h | 101 #define A64_ADD_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, ADD)
153 #define A64_ADD(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, ADD)
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| /arch/arc/include/asm/ |
| D | entry-arcv2.h | 154 ; ISA requires ADD.nz to have same dest and src reg operands
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| /arch/arc/kernel/ |
| D | entry.S | 368 ##### DONT ADD CODE HERE - .Lrestore_regs actually follows in entry-<isa>.S
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| /arch/m68k/fpsp040/ |
| D | round.S | 191 | ADD SINGLE
209 | ADD EXTENDED
228 | ADD DOUBLE
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| D | slogn.S | 418 faddx KLOG2(%a6),%fp0 | ...FINAL ADD
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| /arch/x86/lib/ |
| D | x86-opcode-map.txt | 41 00: ADD Eb,Gb
42 01: ADD Ev,Gv
43 02: ADD Gb,Eb
44 03: ADD Gv,Ev
45 04: ADD AL,Ib
46 05: ADD rAX,Iz
894 0: ADD
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| /arch/sh/math-emu/ |
| D | math.c | 108 BOTH_PRmn(ARITH_X, ADD); in fadd()
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| /arch/m68k/ifpsp060/src/ |
| D | fplsp.S | 7410 mov.b &FADD_OP,%d1 # last inst is ADD
7641 mov.b &FADD_OP,%d1 # last inst is ADD
7932 mov.b &FADD_OP,%d1 # last inst is ADD
8315 fadd.x KLOG2(%a6),%fp0 # FINAL ADD
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| D | fpsp.S | 14658 # ADD: norms and denorms
|