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Searched refs:AR71XX_RESET_REG_MISC_INT_ENABLE (Results 1 – 2 of 2) sorted by relevance

/arch/mips/ath79/
Dclock.c532 misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); in qca956x_clocks_init()
534 ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc); in qca956x_clocks_init()
/arch/mips/include/asm/mach-ath79/
Dar71xx_regs.h517 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 macro