| /arch/sparc/kernel/ |
| D | cpu.c | 54 #define CPU(ver, _name) \ macro
68 CPU(0, "Fujitsu MB86900/1A or LSI L64831 SparcKIT-40"),
70 CPU(4, "Fujitsu MB86904"),
71 CPU(5, "Fujitsu TurboSparc MB86907"),
72 CPU(-1, NULL)
88 CPU(0, "LSI Logic Corporation - L64811"),
90 CPU(1, "Cypress/ROSS CY7C601"),
92 CPU(3, "Cypress/ROSS CY7C611"),
94 CPU(0xf, "ROSS HyperSparc RT620"),
95 CPU(0xe, "ROSS HyperSparc RT625 or RT626"),
[all …]
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| /arch/mips/bcm63xx/ |
| D | Kconfig | 2 menu "CPU support"
6 bool "support 3368 CPU"
11 bool "support 6328 CPU"
16 bool "support 6338 CPU"
21 bool "support 6345 CPU"
25 bool "support 6348 CPU"
30 bool "support 6358 CPU"
35 bool "support 6362 CPU"
40 bool "support 6368 CPU"
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| /arch/arc/plat-axs10x/ |
| D | Kconfig | 21 typically contain a CPU and memory.
27 bool "AXS101 with AXC001 CPU Card (ARC 770D/EM6/AS221)"
29 This adds support for the 770D/EM6/AS221 CPU Card. Only the ARC
37 bool "AXS103 with AXC003 CPU Card (ARC HS38x)"
40 This adds support for the HS38x CPU Card.
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| /arch/h8300/kernel/ |
| D | setup.c | 38 #define CPU "H8/300H" macro
40 #define CPU "H8S" macro
42 #define CPU "Unknown" macro
100 pr_notice("\r\n\nuClinux " CPU "\n"); in setup_arch()
124 cpu = CPU; in show_cpuinfo()
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| /arch/arm/common/ |
| D | mcpm_head.S | 56 mla r4, r3, r10, r9 @ r4 = canonical CPU index
88 @ Signal that this CPU is coming UP:
95 @ state, because there is at least one active CPU (this CPU).
123 @ Any CPU trying to take the cluster into CLUSTER_GOING_DOWN from this
176 @ If a platform-specific CPU setup hook is needed, it is
180 mov r0, #0 @ first (CPU) affinity level
184 @ Mark the CPU as up:
192 ldr r5, [r6, r4, lsl #2] @ r5 = CPU entry vector
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| /arch/csky/ |
| D | Kconfig | 108 For SMP, CPU needs "ldex&stex" instructions for atomic operations.
170 prompt "CPU MODEL"
174 bool "CSKY CPU ck610"
180 bool "CSKY CPU ck810"
185 bool "CSKY CPU ck807"
189 bool "CSKY CPU ck860"
277 bool "CPU has VDSP coprocessor"
281 bool "CPU has FPU coprocessor"
285 bool "CPU has Icache invalidate instructions"
289 bool "CPU has Trusted Execution Environment"
[all …]
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| /arch/x86/ |
| D | Kconfig.cpu | 2 # Put here option for CPU selection and depending optimization
8 This is the processor type of your CPU. This information is
10 that can run on all supported x86 CPU types (albeit not
39 - "AMD Elan" for the 32-bit AMD Elan embedded CPU.
48 - "Generic-x86-64" for a kernel which runs on any x86-64 CPU.
57 Select this for an 486-class CPU without an FPU such as
64 Select this for an 486-class CPU such as AMD/Cyrix/IBM/Intel
211 stores for this CPU, which can increase performance of some
239 treat this chip as a generic 586. Whilst the CPU is 686 class,
244 incarnations of the CPU.
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| /arch/arm/kernel/ |
| D | hyp-stub.S | 44 cmp \mode, \reg1 @ matches primary CPU boot mode?
71 @ Call this from the primary CPU
100 retne lr @ give up if the CPU is not in HYP mode
|
| D | sleep.S | 65 ldr r4, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
71 sub sp, sp, r4 @ allocate CPU state on stack
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| /arch/arc/boot/dts/ |
| D | axc001.dtsi | 7 * Device tree for AXC001 770D/EM6/AS221 CPU card
8 * Note that this file only supports the 770D CPU
44 * this GPIO block ORs all interrupts on CPU card (creg,..)
84 * which acts as a wire between MB INTC and CPU INTC.
87 * CPU INTC, thus we set "interrupts = <7>" instead of
|
| D | axc003_idu.dtsi | 7 * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
59 * this GPIO block ORs all interrupts on CPU card (creg,..)
128 * which acts as a wire between MB INTC and CPU INTC.
131 * CPU INTC, thus we set "interrupts = <0 1>" instead of
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| /arch/mips/jazz/ |
| D | Kconfig | 7 This is a machine with a R4400 133/150 MHz CPU. To compile a Linux
18 This is a machine with a R4000 100 MHz CPU. To compile a Linux
28 This is a machine with a R4000 100 MHz CPU. To compile a Linux
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| /arch/arm64/boot/dts/hisilicon/ |
| D | hi6220-coresight.dtsi | 378 /* CTI - CPU-0 */
391 /* CTI - CPU-1 */
404 /* CTI - CPU-2 */
417 /* CTI - CPU-3 */
430 /* CTI - CPU-4 */
443 /* CTI - CPU-5 */
456 /* CTI - CPU-6 */
469 /* CTI - CPU-7 */
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| /arch/arm/boot/dts/ |
| D | imx6s-dhcom-drc02.dts | 14 * but the Solo is actually a DualLite with only one CPU. So use
15 * DualLite for the Solo and disable one CPU node.
|
| /arch/sh/ |
| D | Kconfig | 292 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
298 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
305 if you have a 100 Mhz SH-3 HD6417708R CPU.
311 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
318 Select SH7710 if you have a SH3-DSP SH7710 CPU.
325 Select SH7712 if you have a SH3-DSP SH7712 CPU.
335 Select SH7720 if you have a SH3-DSP SH7720 CPU.
344 Select SH7721 if you have a SH3-DSP SH7721 CPU.
352 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
373 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
[all …]
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| /arch/arm/mach-tegra/ |
| D | reset-handler.S | 54 @ & ext flags for CPU power mgnt
180 and r10, r10, #0x3 @ R10 = CPU number
182 mov r11, r11, lsl r10 @ R11 = CPU mask
188 bleq __die @ CPU not present (to OS)
277 wfi @ CPU should be power gated here
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| /arch/arm64/boot/dts/renesas/ |
| D | r8a779a0-falcon.dts | 3 * Device Tree Source for the Falcon CPU and BreakOut boards with R-Car V3U
14 model = "Renesas Falcon CPU and Breakout boards based on r8a779a0";
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| /arch/m68k/ |
| D | Kconfig.cpu | 5 prompt "CPU family support"
22 bool "Classic M68K CPU family support"
26 bool "Coldfire CPU family support"
50 The Freescale (was Motorola) 68000 CPU is the first generation of
51 the well known M68K family of processors. The CPU core as well as
52 being available as a stand alone CPU was also used in many
63 The Freescale (was then Motorola) CPU32 is a CPU core that is
376 This gives you access to some advanced options for the CPU. The
499 Define the CPU clock frequency in use. This is the core clock
505 specific to the exact CPU that you are using.
[all …]
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| /arch/powerpc/boot/dts/ |
| D | iss4xx-mpic.dts | 36 model = "PowerPC,4xx"; // real CPU changed in sim
50 model = "PowerPC,4xx"; // real CPU changed in sim
66 model = "PowerPC,4xx"; // real CPU changed in sim
82 model = "PowerPC,4xx"; // real CPU changed in sim
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| /arch/arm/mach-mvebu/ |
| D | pmsu_ll.S | 15 orr r1, r1, #0x8 @ SCU CPU Power Status Register
16 mrc p15, 0, r0, cr0, cr0, 5 @ get the CPU ID
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| /arch/arm/mach-sa1100/ |
| D | sleep.S | 50 @ Adjust memory timing before lowering CPU clock
53 @ delay 90us and set CPU PLL to lowest speed
137 @ about 7 ns out of the entire time that the CPU is running!
|
| /arch/mips/bmips/ |
| D | Kconfig | 18 bool "BCM93384WVG Zephyr CPU"
22 bool "BCM93384WVG Viper CPU (EXPERIMENTAL)"
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| /arch/mips/boot/dts/mti/ |
| D | sead3.dts | 64 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
227 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
242 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 */
253 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
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| /arch/ia64/ |
| D | Kconfig | 216 This enables support for systems with more than one CPU. If you have
217 a system with only one CPU, say N. If you have a system with more
218 than one CPU, say Y.
221 systems, but will use only one CPU of a multiprocessor system. If
239 only use 2 CPUs on a >2 CPU system. Setting this to a value larger
240 than 64 will cause the use of a CPU mask array, causing a small
250 Say N if you want to disable CPU hotplug.
256 Improves the CPU scheduler's decision making when dealing with
275 Tiger4 systems are capable of re-directing CPEI to any CPU other than BSP.
402 menu "CPU Frequency scaling"
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| /arch/arm/mach-vexpress/ |
| D | dcscb_setup.S | 30 2: @ Implementation-specific local CPU setup operations should go here,
|