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Searched refs:CRn (Results 1 – 5 of 5) sorted by relevance

/arch/arm64/kvm/
Dsys_regs.h18 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2)
23 u8 CRn; member
33 .CRn = ((esr) >> 10) & 0xf, \
51 u8 CRn; member
93 p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read"); in print_sys_reg_msg()
162 if (i1->CRn != i2->CRn) in cmp_sys_reg()
163 return i1->CRn - i2->CRn; in cmp_sys_reg()
213 #define CRn(_x) .CRn = _x macro
220 CRn(sys_reg_CRn(reg)), CRm(sys_reg_CRm(reg)), \
Dsys_regs.c740 if (r->CRn == 9 && r->CRm == 13) { in access_pmu_evcntr()
755 } else if (r->CRn == 0 && r->CRm == 9) { in access_pmu_evcntr()
761 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { in access_pmu_evcntr()
795 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { in access_pmu_evtyper()
799 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { in access_pmu_evtyper()
1362 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1829 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1831 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1833 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1835 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
[all …]
Dtrace_handle_exit.h170 __field(u8, CRn)
182 __entry->CRn = reg->CRn;
189 __entry->Op0, __entry->Op1, __entry->CRn,
/arch/arm/include/asm/vdso/
Dcp15.h14 #define __ACCESS_CP15(CRn, Op1, CRm, Op2) \ argument
15 "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32
/arch/arm64/kvm/hyp/nvhe/
Dsys_regs.c324 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \